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ENTITY full_adder IS

PORT ( a, b, carry_in : IN BIT;


sum, carry_out : OUT BIT
);
END full_adder;

ARCHITECTURE dataflow OF full_adder IS


BEGIN
carry_out <= (a AND b) OR (a AND carry_in) OR (b AND carry_in);
sum <= a XOR b XOR carry_in;
END dataflow;