ASIA PACIFIC INSTITUTE OF INFORMATION TECHNOLOGY

GROUP ASSIGNMENT

CSA Case Study3 Memory Architecture

Prepared By Malith Waniganayake (CB004144) Viraj De silva (CB004078) Harin Fernando (CB004134)

Module Code & Title AICT001-3-2 Computer Systems Architecture Cohort DF10A1ICT

Date of Submission 12th May 2011 Lecturer Dr.Gayan Jayakody Word count - 2978

Viraj

Malith

De Silva

Harin
Assumptions (5) Report content (10) Diagrams and/or Figures (20) Analytical and Critical Thinking (20)

Waniganayake

Fernando GROUP COMPONENT

Documentation (5) Referencing (10) Group Total (70) Presentation (20) Progress Report (5)

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INDIVIDUAL COMPONENT

Workload Matrix (5)

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Individual Total (30)

Grand Total (100)

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WORKLOAD MATRIX
Name / CB No. Work Assigned Work Completed Comments & Signature Malith RISC Architecture Viraj De Silva CB004078 Compiling the Document Frequently Asked Questions ALL COMPLETED Viraj Harin

Memory Hierarchy Harin Fernando CB004134 Introduction of the document Frequently Asked Questions ALL COMPLETED

Cache memory Meeting Minutes Malith Waniganayake CB004144 Frequently Asked Questions GANTT Chart Proofing the document

ALL COMPLETED

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ACKNOWLEDGEMENT

It had been a wonderful experience, researching this Project. It would be imperative to extend our sincere thanks to several people who have helped us in making this project a reality.

Our most sincere appreciation goes to Dr.Gayan Jayakody, our CSA lecturer for helping us on completion of this project and without whom the completion of this project would not have been a success.

We wish to thank APIIT Lanka for providing us with excellent facilities and inspiration. We also would like to thank all the lab assistance for enabling us to use the computer laboratories.

Last but not least, our friends who were doing this project with us and sharing our ideas. They were helpful that when we combined and discussed together, we had this task done.

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Contents
WORKLOAD MATRIX ................................................................................................................ 3 ACKNOWLEDGEMENT .............................................................................................................. 4 Introduction ..................................................................................................................................... 7 1.0 Memory Hierarchy .................................................................................................................... 8 1.1 Principle of Memory Hierarchy ........................................................................................ 8 1.2 Types of memory in a hierarchy ....................................................................................... 9 1.3 Accessing Speed and Capacity relation to Memory Hierarchy ...................................... 10 1.4 Benefits of Memory Hierarchy ....................................................................................... 11 Principles of Locality .................................................................................................................... 11 2.0 CACHE MEMORY ................................................................................................................ 12 2.1 What is Cache Memory? ................................................................................................. 12 2.2 Main reason for having the cache memory. .................................................................... 13 2.3 Mechanism of cache memory. ........................................................................................ 14 2.4 Level 1 and Level 2 of the Cache Memory..................................................................... 15 2.5 Strategies for cache memory........................................................................................... 16 2.5.1 Write through strategy ................................................................................................. 16 2.5.2 2.5.3 Copy Back (Write back) strategy ............................................................................ 17 Buffer write ............................................................................................................. 19

3.0 Definition of RISC .................................................................................................................. 20 3.1 History of RISC ...................................................................................................................... 21 3.2 Advantages of RISC ........................................................................................................... 22 3.3 What is pipelining ............................................................................................................... 23 3.4 How Pipelining works......................................................................................................... 23 3. 5 RISC PIPELINE stages...................................................................................................... 25 3.6 Pipelining Developments .................................................................................................... 26 APPENDIX ................................................................................................................................... 29 Registers ........................................................................................................................................ 30 FREQUENTLY ASKED QUESTIONS ON CACHE MEMORY ...................................... 32 Frequently asked questions about RISC ................................................................................... 34 CRITICAL EVALUVATION ( Harin Fernando CB004134) ...................................................... 36

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May 12, 2011 [COMPUTER SYSTEM AND ARCHITECTURE] CRITICAL EVALUVATION ( Viraj De silva CB004078) ......................................................... 37 CRITICAL APRASIAL (Malith Waniganayake cb004144) ........................................................ 38 MINUTES OF MEETINGS ......................................................................................................... 39 Referencing list ............................................................................................................................. 40 Image Referencing ........................................................................................................................ 42

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Introduction
The group selected the 3rd Case study under the topic Memory Architecture. The following assignment is a research project where the authors had to depend on various resources such as books, internet, articles and even the knowledge bestowed on us by our lecture to answer the questions as required by the assignment. The report has argued and described the principles and the benefits of a memory hierarchy; the ways in which memory hierarchies provide both fast and large capacity and the typical program behavior which coincides with the benefit of the memory hierarchy. In addition, the research paper also analyses the main reason for having cache along with the functioning methodology. Furthermore, the advantages of reduced instruction set computers (RISC) which provide a large number of general purpose registers and very few memory access instructions are also analyzed. In this project we mainly focused on 3 topics Memory hierarchy, Cache memory and RISC architecture. This topic have been divided the members so that workload is divided equally to each and every member.

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1.0 Memory Hierarchy

1.1 Principle of Memory Hierarchy

The arrangement of storage in computer architectures nowadays in a hierarchical manner is known as a memory hierarchy. The memory hierarchy is therefore a mechanism of comparing the cost and performance of the various places we can store data and instructions. These facts therefore means that memory hierarchies take advantage of both locality and cost-performance of memory technologies. The main idea of a hierarchical structure of memory is to use, not just one type of memory, but several different kinds of memory and try to achieve the best of every type.

Figure 1 : Hierarchy

As it is shown by the diagram above as you travel higher up the hierarchy the speed of the memory increases and the expense also increases. Therefore the CPU Registers will have the largest speed and the highest expense whilst the permanent storage areas have the lowest relative

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May 12, 2011 [COMPUTER SYSTEM AND ARCHITECTURE] speed and the least expense. The hierarchy for this takes an upright triangular shape as the availability of more expensive is low and because the capacity of the memory decreases as you traverse up the hierarchy.

1.2 Types of memory in a hierarchy

When looking at the types of memories in a memory hierarchy closely, the registers are at the highest. Registers are the closest to the Central Processing Unit and they are the most expensive. As shown in the memory hierarchy diagram, registers are very small in size, though they are the fastest.

The caches are the next closest to the Central Processing Unit. Cache itself can be divided into two parts known as Level 1 cache, also known as Internal Cache, and Level 2 cache, also known as External Cache. Level 2 cache however is only available in some CPUs, such as Pentium II, III, and IV CPUs. Level 1 cache is much larger and the cost-per-byte is much lower than registers. Level 2 caches are itself lower in cost and much larger than Level 1 caches.

Going down the triangular from the top levels in the memory hierarchy comes the main memory or the Random Access Memory, which is usually a low-cost and in-expensive. Main Memory, which is usually DRAM (Dynamic Random Access Memory) in this case, is larger in capacity than caches or registers.

Next comes the small size but large capacity memory such as flash or USB memory. These different types of disk storages are in the forms of hard disks, floppy disks,etc. Hard disks are however way more expensive and larger in capacity than the other forms of disk storages.

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May 12, 2011 [COMPUTER SYSTEM AND ARCHITECTURE] 1.3 Accessing Speed and Capacity relation to Memory Hierarchy

According to memory hierarchy triangle as we traverse up the triangular hierarchy the access time/speed decreases. Consequently the capacity of the devices decreases along with the access time. At the bottom of the hierarchy are devices like hard drives, removable storage and ROM BIOS. These devices are slow in relation to access but have large capacity of storage. And as we traverse up the hierarchy triangular the cost for devices rises. The base devices of the triangular are cheaper than the devices in the up.

Figure 2 :Design

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May 12, 2011 [COMPUTER SYSTEM AND ARCHITECTURE] 1.4 Benefits of Memory Hierarchy Support for multi-programming Infinite Memory Faster Access Cost Reduction

Principles of Locality
As the definition of memory hierarchy states that, memory hierarchies take advantage of both locality and cost-performance of memory technologies, the word locality has to be defined. Locality itself can be divided into two types, namely:

Temporal Locality References repeated in time. This means that if an item is referenced, it is more likely to be referenced again. Therefore temporal locality can also be referred to as locality in time. Spatial Locality References repeated in space. This means that if a particular item is referenced, it is more likely that items whose addresses are close by tend to be referenced soon.

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2.0 CACHE MEMORY

2.1 What is Cache Memory?

Cache is a high speed memory residing on or near the central processing unit (CPU) of the system. Cache memory is made of high-speed static RAM (SRAM). This memory is by far the smallest and fastest memory in the system when compared to other storing devices. This memory is directly accessed by the CPU. Cache memory supplies the processor most frequently requested data and instructions of most of the programs that was recently accessed by the CPU. Since the cache memory is near or on the CPU, CPU doesnt have to use the slow motherboard bus to get data about the program. Because of this CPUs efficiency becomes much higher and as a result the system will perform much faster. Due to the factor that the cache is a SRAM it is a volatile memory. Because of that it does not need a periodic refresh like Dynamic RAMs (DRAM). It will lose data only if the power is turned off. (Gache, 2008)

Figure 3 : Cache

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May 12, 2011 [COMPUTER SYSTEM AND ARCHITECTURE] 2.2 Main reason for having the cache memory.

Central processing unit (CPU) of the computer is made of flip-flops and gates. This makes the CPU have a very fast processing speed. So the CPU has its processing speed in GHz. Normal processor like Intel i5 has around 2.8GHz speed. The main memory or the RAM is made out of complicated circuits of Integrated circuits(ICs) These ICs does not have the speed of the processor. DDR3 SDRAM (Double Data Rate Three Synchronous Dynamic Random Access Memory) has around 1033MHz of speed. This is not at all enough for the processing speed of the processor. This is a critical problem for fetching and executing instructions because the speed of the CPU and the RAM does not match. If the CPU access the RAM and take the data and instructions for processing, the CPUs speed would be limited to the speed of the RAM. This will slow down the processing speed and the overall efficiency of the system. To overcome this bottleneck of speed of data transferring and to make a high speed machine at a lower cost the cache memory was introduced. (Tyson, 2011)

Figure 4 : connection

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May 12, 2011 [COMPUTER SYSTEM AND ARCHITECTURE] 2.3 Mechanism of cache memory.

Cache Memory is a small and special memory which is situated between the CPU and the motherboard. Cache memory also falls into the category of Random access memory (RAM). Cache memory is made of high-speed static RAM (SRAM). So the cache memory can transfer data and instructions at a around the same rate of the CPU. The cache memory only stores the recently accessed data and instruction that is most likely to be used again. These data and instructions are stored in orderly manner so that whenever the CPU needs them they can be accessed easily. According to Gache (April, 2008) The cache memory has the role of backing up the RAM. This means that before retrieving the information from the hard drive, the computer first looks for it in the cache memory. If it is present in the cache, then it is instantly relayed to the processor. This could quickly turn into a disadvantage if the requested information cannot be found in the cache, because processing time is first being lost by checking the cache, then actually retrieving the information from the hard drive. Whenever the CPU in need of instructions or data which are needed to complete a process the cache memory is examined before the main memory. If the necessary instruction or the data can be found at the cache memory it is retrieved fast and will be processed at the CPU. This is much faster than going in to the main memory and going through every memory location checking for the necessary instruction and data. Finding the necessary data and instruction in the cache needed by the CPU for the next process is called the Cache HIT. If the necessary data and instructions are not to be founded in the cache memory then the CPU refers to the main memory. This is called the Cache MISS. When this happens the necessary data and instructions that has just been accessed by the CPU is transferred or copied to the cache from the main memory so that the CPU can access those data and instructions straightforwardly from the cache faster than the main memory. If a Cache miss occurs processing time of checking the cache is lost. This is a main disadvantage of this method. (Gache, 2008)

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Figure 5 : data flow

Performance of the cache memory depends on the cache hits and cache misses. It is measured in the quantity called HIT RATIO. Hit ratio is the percentage of memory accesses satisfied by the cache. Higher the hit ratio it will be considered as the CPU access the cache more than reading from the main memory. If the hit ratio is high it means the processing speed will be high and the performance of the system will be much faster. (anon, 2011)

2.4 Level 1 and Level 2 of the Cache Memory

Anon , 2011 stated that A level 1 (L1) cache is a memory bank built into the CPU chip. A level 2 cache (L2) is a secondary staging area that feeds the L1 cache. Increasing the size of the L2 cache may speed up some applications but have no effect on others. L2 may be built into the CPU chip, reside on a separate chip in a multichip package module or be a separate bank of chips on the motherboard. Caches are typically static RAM (SRAM), while main memory is generally some variety of dynamic RAM (DRAM).

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2.5 Strategies for cache memory

There are several methods to write data and instructions to the cache memory. Apart from the read operation the write operation gets the main memory involved. When this happens there are three strategies to do the write operation. They are: Write through Copy Back(Write Back) Buffered Write

2.5.1 Write through strategy

In this Write through strategy Data is written to the main memory or to a disk through the cache memory. The cache updates its stored data as the data passes by. This write cycle will not end until the all of the data is written in to the main memory. The data is also written into the cache assuming that subsequent read operation needs the same data. Since data is written in two places at the same time makes the write strategys write performance low. But if a subsequent read operation that needs the same data then the read performance will be much higher than just taking from the main memory. It is because the data is already is in the cache and the processor only have to check in the cache for the data. (anon 2, 2011)

Figure 6 : Write through strategy

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Advantages of Write through strategy

In this strategy CPU access the main memory directly. So all the recent data and instructions are available in the in the main memory. Then all the Input/output devices (I/O) can access the main memory and are capable of receiving the most recently updated data for better performance. This is a less complex strategy and therefore it is less expensive to implement. Cache is always synced with the main memory so that data loss is minimum, also because of this the chances of cache miss will be minimum. Because of this the hit ratio gets higher and the overall performance becomes high. (anon, 2011) Disadvantages of Write through strategy

Sometimes the CPU has to wait for the main memory to accept the data given by the CPU. Because of this efficiency of the processor get lower. Since the CPU has to do numerous operation and copy the same data twice. Because of this it will be less efficient.

2.5.2 Copy Back (Write back) strategy

Anon-2, 2011 stated that A disk or memory cache that supports the caching of writing. Data normally written to memory or to disk by the CPU is first written into the cache. During idle machine cycles, the data are written from the cache into memory or onto disk. Write back caches improve performance, because a write to the high-speed cache is faster than to normal RAM or disk.

In this strategy cache acts as a buffer between the processor and the main memory. When the write cycle begins the cache takes the data from the processor stores inside and then terminates it. When the system bus is available the data is written back to the main memory. Because of this

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May 12, 2011 [COMPUTER SYSTEM AND ARCHITECTURE] system bus will be available for other processes as well. This allows the processor to do other processes as well as the current one.

Figure 7: write back

Advantages Copy Back (Write back) strategy

Updating the main memory happens later when the system bus is available. Because of this CPU can continue with its current work. This increases the efficiency of the system . Unnecessary operations are minimized because of this write operation gets sped up by the fact that the avoidable reference made to the main memory is reduced.

Disadvantages Copy Back (Write back) strategy

Writing to the main memory is controlled and the cache complexity will be increased. Because of that it will be hard to manufacture the cache. This will increase the cost of the cache, One cannot make certain that the data in the main memory are valid most of the time.

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2.5.3 Buffer write

In buffer write strategy acts as a buffer between the cache memory and the processor. The buffer is used to pass data to L1 and L2 cache memories also this buffer is used pass information and data with the I/O devices. Shown below is an example for how the buffer write cache works.

Figure 8: Buffer write

Advantages of buffer write Strategy increases the performance of the processor by reducing the waiting time. Disadvantage of buffer write The manufacturing cost of the cache memory is high because of the complex architecture in the cache.

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3.0 Definition of RISC

Reduced (or regular) instruction set computer is known as RISC, its a computer CPU philosophy which was implement to make the computer more efficient and faster. There is a another technology called CISC(complexes instruction set computer) which was introduce before RISC, compared to RISC the CISC philosophy is slower, the reason behind it is the larger number of computer instruction that has to perform in the order to perform arithmetic operations. In order to overcome these problem scientists introduce RISC technology which perform arithmetic operations in a smaller number of computer instructions.

Figure 9 : RISC

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3.1 History of RISC

The first RISC chip was developed at IBM by John Cocke in 1974. In 1978, other early-on RISC developments included the RISC-I processor in 1982, and the RISC-II in 1983. CISC, instead, was used by Motorola's 68040 computer processor and Intel's 80486 in the 1980s. The early developments of both CISC and RISC have lead to further developments of other processors, platforms and architectures. The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC

Figure 10 : history

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3.2 Advantages of RISC

Reduced Instruction Set Computers (RISCs) offer more performance per transistor than conventional Complex Instruction Set Computers (CISCs). There are now many examples of this advantage being exploited in the design of processors for high-end engineering workstations, where the RISC approach allows greater performance to be extracted from a single integrated circuit than could be obtained from a CISC processor based on the same silicon technology. RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the "MULT" command described above could be divided into three separate commands: "LOAD," which moves data from the memory bank to a register, "PROD," which finds the product of two operands located within the registers, and "STORE," which moves data from a register to the memory banks. In order to perform the exact series of steps described in the CISC approach, a programmer would need to code four lines of assembly

Cheap-RISC processors are cheaper than other processors, it uses less transistors. Less space-This processor is small comparing to the others. Therefore the size of the CPU is getting reduced and the users do not want to worry about the spaces. Less power-it consume less power, this processors are called energy saving processors. These processors even can run from car batteries. So it is a big advantage for the 3rd world countries. No noise-Comparing to the other processors this one does not have noise. It is completely silent.

RISC processors use pipelines strategy, which able to process millions of instructions without any conflicts.

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3.3 What is pipelining

Computer processors can handle millions of instructions each second. Once one instruction is processed, the next one in line is processed, and so on. A pipeline allows multiple instructions to be processed at the same time. While one stage of an instruction is being processed, other instructions may be undergoing processing at a different stage. Without a pipeline, each instruction would have to wait for the previous one to finish before it could even be accessed. To understand the benefit of a pipeline, imagine that a car manufacturing plant had to wait for each car to be fully completed before starting on the next one. That would be horribly inefficient, right? It makes much more sense to work on many cars at once, completing them one stage at a time. This is what a pipeline in a computer allows. Pipelining, as it is called, often keeps around six instructions at once in the processor at different stages of processing. Pipelines can be used for the CPU as well as for accessing memory (DRAM). (http://www.techterms.com/definition/pipeline)

3.4 How Pipelining works

The best way to understand how pipelining work is to demonstrate it in a laundry analogy, Let's say that there are four loads of dirty laundry that need to be washed, dried, and folded. We can put the first load in the washer for 30 minutes, dry it for 40 minutes, and then take 20 minutes to fold the clothes. Then pick up the second load and wash, dry, and fold, and repeat for the third and fourth loads. If we started at 6 PM and worked as efficiently as possible, we would still be doing laundry until midnight.

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But if we approach thesame problem in a different way the time is reduced. The waWe can put the second load of laundry into the washer after the first laundry is already clean and whirling in the dryer.Then, while the first load was being folded, the second load would dry, and a third load could be added to the pipeline of laundry. Using this method, the laundry would be finished by 9:30.

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3. 5 RISC PIPELINE stages

Fetch instruction Decode instruction Execute instruction Access operand Write result Above shown stages are the five most important stages in the pipeline process. If you glance back at the diagram of the laundry pipeline, you'll notice that although the washer finishes in half an hour, the dryer takes an extra ten minutes, and thus the wet clothes must wait ten minutes for the dryer to free up. Thus, the length of the pipeline is dependent on the length of the longest step. Because RISC instructions are simpler than those used in pre-RISC processors (now called CISC, or Complex Instruction Set Computer), they are more conducive to pipelining. While CISC instructions varied in length, RISC instructions are all the same length and can be fetched in a single operation. Ideally, each of the stages in a RISC processor pipeline should take 1 clock cycle so that the processor finishes an instruction each clock cycle and averages one cycle per instruction (CPI).

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3.6 Pipelining Developments

In order to make processors even faster, various methods of optimizing pipelines have been devised. There are different pipeline stages, if the stages are short then the pipeline become faster. In general a pipeline with five stages should be five times faster than a non-pipelined processor (or rather, a pipeline with one stage). The instructions are executed at the speed at which each stage is completed, and each stage takes one fifth of the amount of time that the non-pipelined instruction takes. Thus, a processor with an 8-step pipeline (the MIPS R4000) will be even faster than its 5-step counterpart

These are the five steps which are used by the pipeline system to make it even faster. 1. 2. 3. 4. 5. 6. 7. 8. Instruction Fetch (First Half) Instruction Fetch (Second Half) Register Fetch Instruction Execute Data Cache Access (First Half) Data Cache Access (Second Half) Tag Check Write Back

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Conclusion
After doing the respective research paper the authors were able to understand the benefits of a memory hierarchy, the method to provide both high and large capacity, and the typical program behavior which benefits a memory hierarchy. In addition, the author was able to understand the main reason for having a cache that regards to speed of instruction execution and fetching instructions, and hence the method in which cache works. Thus, the above research helped understand the three strategies for cache memories which are writing through with buffered write, and copy back along with their advantages and disadvantages. Furthermore; the advantages of a reduced instruction set computers (RISC) which provide a large number of general-purpose registers and very memory acces instructions were thoroughly understood.

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APPENDIX

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FAQ (Frequently Asked Questions) On Memory Hierarchy

Memory Hierarchy: 1. Describe the term memory. Memory is a region where data or instructions can be stored either temporarily or permanently. 2. What are the devices of memory? Registers, Cache, main memory, Hard, Ram 3. Which device has least access time? Registers 4. Write the devices in accending order with their access time? Registers, Cache, Main Memory, Magnetic Disk, Magnetic Tape & Optical Disk 5. Which device has the most Capacity? Magnetic Tape & Optical Disk 6. Which device is the most Expensive? Registers 7. How does memory hierarchy reduce cost? Fastest devices are expensive and are in the topmost region of the hierarchy triangle, whilst the lower cost memories are at the bottom level and have high access time. 8.Which device is working with CPU and main memory at the same time? Cache

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May 12, 2011 [COMPUTER SYSTEM AND ARCHITECTURE] 9. To provide infinite memory, what is the concept memory hierarchy has introduced? Virtual Memory 10. Discuss two benefits of hierarchy Cost reducing Fast Access

11. What is the Principle of Locality? Programs access a relatively small portion of the address space at any instant of time

12. What are the types of Localities?

Spatial Temporal

13. What is Spatial Locality? The locality in time which says if an item is referenced, it will tend to be referenced soon. 14. What is Temporal Locality? The locality in space. It says if an item is referenced, items whose addresses are close by tend to be referenced soon. 15. Write the order of the Memory Hierarchy? Register Cache Main Memory Magnetic Disk Magnetic Tape & Optical Disk again

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May 12, 2011 [COMPUTER SYSTEM AND ARCHITECTURE] FREQUENTLY ASKED QUESTIONS ON CACHE MEMORY

1. What is cache memory? Cache memory is small in size, and its faster, it stores copies of data from the most frequently used memory locations. 2. Why cache memory is used? Main purpose of having a cache memory in a computer system is to reduce the CPU access time to the data that is frequently accessed. 3. How does the cache memory work? When the CPU needs data it looks for that relevant data inside the cache memory, if that relevant data is available then the data is taken from the cache. Otherwise CPU has access that data from the RAM. 4. What is cache-hit? If the data which is required by the CPU is to be found inside cache then it is called a cache hit. 5. What is cache-miss? Cache-miss is the opposite of the cache-hit. If the data required by the CPU is not found to be inside the cache then it is called a cache-miss. 6. Why cache memory is dived into levels? Different levels of cache memory have been used to reduce latency time of various memory types when processing or transferring information. 7. What is L1, L2 cache and L3 cache? L1 cache- L1 cache is special, very fast memory integrated into the CPU to help facilitate computer performance. By loading frequently used bits of data into L1 cache, the computer can process requests faster. Most computers also have L2 and L3 cache, which are slower than L1 cache but faster than RAM. L2 cache- L2 cache holds the next most needed likely bit of data after the L1 cache. L2 cache is integrated into the mother board. L3 cache- L3 cache is specialized memory that works hand-in-nad-with L1 and L2 cache to improve computer performance. (Kayne, 2011)

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8. The difference between Snoop and Snarf? Snoop- Snooping is the process where the individual caches monitor address lines for accesses to memory locations that they have cached. When a write operation is observed to a location that a cache has a copy of, the cache controller invalidates its own copy of the snooped memory location. Scarfing- Snarfing is where a cache controller watches both address and data in an attempt to update its own copy of a memory location when a second master modifies a location in main memory. (neeraj,2011) 9. What is Dirty data and Stale data? Dirty Data This term is used when data is modified in the cache but not in the main memory. Stale Data This term is used when data is modified in the main memory but not in the cache. 10. What are cache memory strategies? Write through Write Back Buffered Write 11. What is the best strategy? Write Back, it just writes just to cache. Write memory only when a black is replaced. 12. What are the advantages and disadvantages in write back strategy? Advantages Internally consistent, since cache is never out of sync with the memory.

Disadvantages Provides much low performance for the user, as the CPU has to wait for the Main Memory to accept data.

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May 12, 2011 [COMPUTER SYSTEM AND ARCHITECTURE] 13. What is the different between RAM and Cache memory? RAM is general purpose memory, used to store programs, data, and graphics. Cache is specialized memory used by the CPU to speed up access to the RAM. It acts as a buffer, "looking ahead" and trying to anticipate the next item needed from RAM 14. Which device has least access time? Registers 15. . What are the devices of memory? Registers, Cache, main memory, I/O Devices

Frequently asked questions about RISC

1 Define what is meant by RISC? Reduce instruction set computer What is the purpose of introducing RISC technology? The main purpose is to make the computer fast and efficient than CISC What is the main difference between CISC instructions and RISC instructions? Compared to RISC, ISC instructions are more complex What is the main advantage of the RISC architecture? Small, highly optimized set of instructions Uses a load-store architecture Short execution time Pipelining Many registers What main features of RISC architecture rub it fast? Demands less decoding Uniform instruction set Identical general purpose registers used in any text Simple addressing modes Fewer data types in hardware

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May 12, 2011 [COMPUTER SYSTEM AND ARCHITECTURE] 6 What are the general instructions that can be executed using RISC architecture processors? Adding Subtracting Comparing two numbers Fetch numbers What is pipelining Technology? Pipeline technology dived the process into segments and execute each segment simultaneously What are the popular pipeline systems? Dynamic pipelines Superscalar pipelines Why the RISC processors are cheap? RISC processors have used transistors.

10 How to make pipelines faster? Divide the stages of pipelining into more stages Run multiple pipelines in parallel 11 What architecture is proposed with a combination of both CISC and RISC architecture? CRISC Architecture Complex-Reduced Instruction Set Computer 12 What is dynamic pipeline? Uses buffers to hold instruction bits in case a dependent instruction stalls 13 Why CISC Persists than RISC? Most Intel and AMD chips are CISC x86 Most PC applications are written for x86 Intel spent more money improving the performance of their chips 14 What are the five pipeline stages? Fetch instruction Decode instruction Execute instruction Access operand

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CRITICAL EVALUVATION ( Harin Fernando CB004134)

Im appointed to do about Memory Hierarchy in our group project. The section covers Case Study 3: Memory Architecture is the first question, hence the principles, characteristics and benefits of a memory hierarchy. I had to face various challenges in order to come up with my final report on memory hierarchies. To do this project I used my 1st semester knowledge on Operating Systems which is taught by Mr. Kolitha Gunarathne. It was really helpful to me to continue my work on Computer System Architecture. To do this project I referred to certain books and as well as to few magazines. The knowledge I used to this project has been based on the facts taught to us by our lecturer Dr.Gayan Jayakodi.

Memory hierarchy is an efficient way to allocate the different types of memory and take the best use of all of them. Memory hierarchy therefore leads to better Central Processing Unit (CPU) performance in order to access data and instructions in a quick manner.

Overall a memory hierarchy is very helpful and important in order to increase the data and instruction transfer speed between the CPU and the other different types of memory.

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CRITICAL EVALUVATION ( Viraj De silva CB004078)

Case study 3: Reduce instruction set computer, was completed by my self. RISC (REDUCE INSTRUCTION SET COMPUTER) architecture processors are faster than the CISC processors. RISC process reduces the complexity of the instruction and processes it. For example CISC processors use one complex instruction. In RISC processors is uses several instructions instead of one complex instruction. Therefore RISC perform faster than the CISC architecture.

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CRITICAL APRASIAL (Malith Waniganayake cb004144)

I did the second question in the case study. This question is on the general topic Cache Memory. Due to this case study I have learnt a lot about the cache. Cache memory is a device which is faster and smaller in size. Cache stores the most frequently used data. This helps the CPU to access the data with minimum time with higher frequency. The CPU will access the cache first in search of required data to complete the process. If the required data is found in the cache data will be gathered from the cache. Otherwise the CPU will have to look for the wanted data in the RAM. Cache HIT when the required data can be founded in the cache. Cache miss Required data cannot be founded in the cache. Then the CPU will have to look for the data in the main memory. Cache memory is divided in to two parts as the L1 and the L2. L1 is situated in the CPU and the L2 is situated outside of the CPU. Cache memory Strategies 1. Write through 2. Copy back(Write back) 3. Buffered Write

Write Through Data is written directly in to the memory and the cache. Copy back The data and information is stored in the cache and then written to the main memory when the system bus is available Buffered Write Mostly used when CPU is communicating with the devices

The overall intention is to learn how the cache works and how the system co-operates with the cache to build up a speedy system

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MINUTES OF MEETINGS
Date Members Present Venue Duration Topics Discussed

25th March

Malith Viraj Harin

L2-SR2

30 minutes

Case Study was Chosen that day and the work divided among the group members.

21st April

Malith Viraj Harin

L6

45 minutes

Project Progress discussion and the difficulties in making the group project.

6th May

Malith Viraj Harin

L1-CR3

30 minutes

Documentation and the Progress of the group work.

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Referencing list
1. Gache.G, April 18th, 2008, How Cache Memory Works, Available: http://news.softpedia.com/news/How-Cache-Memory-Works-83803.shtml [Accessed on 6/5/2011 ] 2. Jeff Tyson, 2007, How Computer Memory Works, Available : http://computer.howstuffworks.com/computer-memory4.htm [ Accessed on 6/5/2011] 3. Anon, 2011 cache Available ; http://www.pcmag.com/encyclopedia_term/0,2542,t=cache&i=39177,00.asp [Accessed on 6/5/2011] 4. Anon 2 ,2011 write through cache, Available ; http://www.pcmag.com/encyclopedia_term/0,2542,t=write+through+cache&i=54904,00. asp [Accessed 7/5/2011] 5. Anon 2 ,2011 write through cache, Available ; http://www.pcmag.com/encyclopedia_term/0,2542,t=write+back+cache&i=54893,00.asp [Accessed 7/5/2011] Kayne, 2011 What is cache, Available ;http://www.wisegeek.com/what-is-l1-cache.htm [Accessed 7/5/2011] 7. Neeraj, 2011 Available http://www.coolinterview.com/interview/4354/ [Accessed 7/5/2011 ] 8. http://www.sciencedirect.com/science?_ob=ArticleURL&_udi=B6TYV-4998TS76.

DH&_user=10&_coverDate=12%2F31%2F1989&_rdoc=1&_fmt=high&_orig=gateway &_origin=gateway&_sort=d&_docanchor=&view=c&_acct=C000050221&_version=1& _urlVersion=0&_userid=10&md5=4df42bffd58b9a43995b794814313174&searchtype=a 9. (http://www-cs-faculty.stanford.edu/~eroberts/courses/soco/projects/200001/risc/risccisc/) 10. http://static.howstuffworks.com/gif/computer-memory-pyramid.gif 11. http://www.cs.odu.edu/~wilson/cs270/lectures/ch7.3.ppt 12. Aletan, Samuel O. "An overview of RISC architecture." Proceedings of the 1992 ACM/SIGAPP Symposium on Applied computing: technological challenges of the 1990s.Vol. 1. Kansas City: Association for Computing Machinery, March 1-3, 1992.

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May 12, 2011 [COMPUTER SYSTEM AND ARCHITECTURE] 13. Bhandarkar, Dileep and Douglas W. Clark. "Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization." Communications of the ACM, September 1991: 310-319. 14. Goff, Leslie. "A RISC-y Proposition." Computer World, 9 August 1999: 80. 15. Hennessy, John L. Personal Interview. September 14, 2000. 16. "Introduction to RISC." http://www.inf.fhdortmund.de/person/prof/si/risc/intro_to_risc/irt0_index.html. 17. Marshall, Trevor. "Worth the RISC." Byte. 14:2 (Feb 1989): 245. 18. Miller, Michael J. "The Great Chip Race." PC Magazine, 13 (1994): 79. 19. Patterson, David A. and John L. Hennessy. Computer Organization & Design.2nd ed. Morgan Kaufmann Publishers: San Francisco, 1998. 20. Prosise, Jeff. "RISC vs. CISC: The Real Story." PC Magazine, 14 (1995): 247-249. 21. "Reduced instruction set computer." Whatis?com: 9 Aug 2000,http://whatis.techtarget.com/WhatIs_Definition_Page/0,4152,214266,00.html. 22. Stokes, Jon. "ArsTechnica: RISC vs CISC in the Post RISC Era." Oct. 1999.http://arstechnica.com/cpu/4q99/risc-cisc/rvc-1.html. 23. Wayne, Peter. "Processor Pipelines." Byte, 17 (1992): 305. 24. Weiss, Ray. "Third-generation RISC Processors." EDN, 37 (1992): 96. 25. White, Ron. How Computers Work. Ziff-Davis: Emeryville, California, 1997. 26. http://webster.cs.ucr.edu/AoA/Windows/HTML/MemoryArchitecture.html 27. http://www.yale.edu/pclt/PCHW/clockidea.htm

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Image Referencing
1. http://moodle.schoolnet.lk/mod/resource/view.php?id=1149 2. http://1.bp.blogspot.com/_WEa1Pqx1SxA/TIN3QgoppvI/AAAAAAAAAPg/thlUz3_djU/s1600/CACHEMEM.GIF 3. http://www.sqa.org.uk/e-learning/CompArch02CD/page_28.htm 4. http://www.cs.umd.edu/class/fall2001/cmsc411/proj01/cache/cache9.jpg 5. http://www.brainbell.com/tutors/A+/Hardware/images/F07XX08.JPG 6. http://www.solarisinternals.com/si/reading/sunworldonline/swol-071999/images/filesystem3_fig1.gif 7. http://archive.computerhistory.org/resources/stillimage/IBM/IBM_RISC/IBM.RISC.diagr am.102657026.lg.jpg 8. http://www.research.ibm.com/images/about/cocke.jpg 9. http://www.ece.arizona.edu/~ece462/Lec03-pipe/ 10.

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