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FEATURES Ideal xDSL Line Driver for VoDSL or Low Power Applications such as USB, PCMCIA, or PCI-Based Customer Premise Equipment (CPE) High Output Voltage and Current Drive 340 mA Output Drive Current Low Power Operation 3 V to 12 V Power Supply Range 1-Pin Logic Controlled Standby, Shutdown Low Supply Current of 19 mA (Typical) Low Distortion –82 dBc SFDR, 12 V p-p into Differential 21 ⍀ @ 100 kHz 4.5 nV/√Hz Input Voltage Noise Density, 100 kHz Out-of-Band SFDR = –72 dBc, 144 kHz to 500 kHz, ZLINE = 100 ⍀, PLINE = 13.5 dBm High Speed 40 MHz Bandwidth (–3 dB) 375 V/ s Slew Rate APPLICATIONS VoDSL Modems xDSL USB, PCI, PCMCIA Cards Line Powered or Battery Backup xDSL Modems
xDSL Line Driver 3 V to 12 V with Power-Down AD8391
PIN CONFIGURATION 8-Lead SOIC (Thermal Coastline)
؊VS ؊ ؉ VMID ؉VS ؉ ؊
IN1 1 PWDN 2 +VS 3 VOUT1
IN2 VMID –VS VOUT2
UPSTREAM POWER – 10dB/DIV
The AD8391 consists of two parallel, low cost xDSL line drive amplifiers capable of driving low distortion signals while running on both 3 V to 12 V single-supply or equivalent dual-supply rails. It is primarily intended for use in single-supply xDSL systems where low power is essential, such as line powered and battery backup systems. Each amplifier output drives more than 250 mA of current while maintaining –82 dBc of SFDR at 100 kHz on 12 V, outstanding performance for any xDSL CPE application. The AD8391 provides a flexible power-down feature consisting of a 1-pin digital control line. This allows biasing of the AD8391 to full power (Logic “1”), Standby (Logic “tri-state” maintains low amplifier output impedance), and Shutdown (Logic “0” places amplifier outputs in a high impedance state). PWDN is referenced to –VS. Fabricated on ADI’s high-speed XFCB process, the high bandwidth and fast slew rate of the AD8391 keep distortion to a minimum, while dissipating a minimum of power. The quiescent current of the AD8391 is low; 19 mA total static current draw. The AD8391 comes in a compact 8-lead SOIC “Thermal Coastline” package, and operates over the temperature range –40°C to +85°C.
EMPTY BIN 25 137.5 FREQUENCY – kHz 250
Figure 1. Upstream Transit Spectrum with Empty Bin at 45 kHz; Line Power = 12.5 dBm into 100 Ω
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
(@ 25؇C, VS = 12 V, RL = 10 ⍀, VMID = VS /2, G = –2, RF = 909 ⍀, RG = 453 ⍀, unless otherwise noted. See TPC 1 for Basic Circuit Configuration.)
Min Typ Max Unit
DYNAMIC PERFORMANCE –3 dB Bandwidth 0.1 dB Bandwidth Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time NOISE/HARMONIC PERFORMANCE Distortion, G = –5 (RG = 178 Ω) 2nd Harmonic 3rd Harmonic MTPR (In-Band) SFDR (Out-of-Band) Input Noise Voltage Input Noise Current Crosstalk DC PERFORMANCE Input Offset Voltage
G = –1, VOUT < 0.4 V p-p, RG = 909 Ω G = –2, VOUT < 0.4 V p-p VOUT < 0.4 V p-p VOUT = 4 V p-p VOUT = 4 V p-p VOUT = 4 V p-p 0.1%, VOUT = 2 V p-p
40 38 4 50 375 8 60
MHz MHz MHz MHz V/µs ns ns
VOUT = 8 V p-p (Differential) 100 kHz, RL = 21 Ω 100 kHz, RL = 21 Ω 25 kHz to 138 kHz, RL = 21 Ω 144 kHz to 500 kHz, RL = 21 Ω f = 100 kHz Differential f = 100 kHz f = 1 MHz, G = –2, Output to Output VMID = +VS/2 TMIN to TMAX VMID = “Float” TMIN to TMAX ∆VOUT = 5 V
–82 –95 –70 –72 4.5 9 64 ±2 ±3 ±2 ± 0.25 ± 0.35 10 ± 15 ± 2.6
dBc dBc dBc dBc nV/√Hz pA/√Hz dB mV mV mV mV mV MΩ Ω µA µA dB V mV kΩ pF Ω kΩ V mA mA mA mA mA mA V dB V V µA ns
Input Offset Voltage Match Transimpedance INPUT CHARACTERISTICS Input Resistance Input Bias Current Input Bias Current Match CMRR Input CM Voltage Range VMID Accuracy VMID Input Resistance VMID Input Capacitance OUTPUT CHARACTERISTICS Output Resistance Output Resistance Output Voltage Swing Linear Output Current Short Circuit Current POWER SUPPLY Supply Current STBY Supply Current SHUTDOWN Supply Current Operating Range Power Supply Rejection Ratio LOGIC INPUT (PWDN) Logic “1” Voltage Logic “0” Voltage Logic Input Bias Current Turn On Time
Specifications subject to change without notice.
In1, In2 pins In1 – In2 VMID = VIN = 5.5 V to 6.5 V, ∆VOS /∆VIN, cm VMID = “Float” Delta from +VS/2
125 2.5 10 ± 0.5 ±6 48 1.2 to 10.8 ±5 ± 30 2.5 10 0.3 3 0.1 340 1500 16 19 22 10 4 55 –VS + 2.0 21 11.9
Frequency = 100 kHz, PWDN “1” Frequency = 100 kHz, PWDN “0” RLOAD = 100 Ω SFDR < –75 dBc, f = 100 kHz, RL = 21 Ω
PWDN = “1” TMIN to TMAX PWDN = “Open or Three-State” PWDN = “0” Single Supply VMID = VS /2, ∆VS = ± 0.5 V
RL = 21 Ω, IS = 90% of Typical
± 300 200
–VS + 0.8
RL = 21 Ω PWDN = “1” TMIN to TMAX PWDN = “Open or Three-State” PWDN = “0” Single Supply VMID = VS/2. VOUT < 0.9 Frequency = 100 kHz. VOUT < 0.1%. V = V /2. SPECIFICATIONS (@ See TPC 1 for Basic Circuit Configuration.2 9 0.5 10 0.5 30 50 15 110 MHz MHz MHz MHz V/µs ns ns VOUT = 4 V p-p (Differential) 100 kHz.5 9 ±3 ±4 ±3 ± 0.” Delta from +V S /2 125 1 7 ± 0. ∆VOS /∆VIN.4 V p-p VOUT = 2 V p-p VOUT = 2 V p-p Differential.1dB Bandwidth Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time NOISE/HARMONIC PERFORMANCE Distortion 2nd Harmonic 3rd Harmonic Input Noise Voltage Input Noise Current DC PERFORMANCE Input Offset Voltage G = –1.4 V p-p G = –2.5 ±4 48 1.2 8 ± 15 ± 2.AD8391 25؇C. f = 100 kHz.1 ± 0. R = 10 ⍀. IS = 90% of Typical ± 60 200 –VS + 0.) S L MID S F G Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth 0. unless otherwise noted.5 V. VOUT = 1 V p-p 0. PWDN “1” Frequency = 100 kHz. G = –2. 0 –3– .4 V p-p VOUT < 0. RL = 21 Ω f = 100 kHz Differential f = 100 kHz VMID = +VS/2 TMIN to TMAX VMID = “Float” TMIN to TMAX ∆VOUT = 1 V –81 –97 4.0 18 2.3 V to 1. In2 pins In1 – In2 VMID = VIN = 1.8 REV. R = 453 ⍀.6 dBc dBc nV/√Hz pA/√Hz mV mV mV mV mV MΩ Ω µA µA dB V mV kΩ pF Ω kΩ V mA mA mA mA mA mA V dB V V µA ns Input Offset Voltage Match Transimpedance INPUT CHARACTERISTICS Input Resistance Input Bias Current Input Bias Current Match CMRR Input CM Voltage Range VMID Accuracy VMID Input Resistance VMID Input Capacitance OUTPUT CHARACTERISTICS Output Resistance Output Resistance Output Voltage Swing Linear Output Current Short Circuit Current POWER SUPPLY Supply Current STBY Supply Current SHUTDOWN Supply Current Operating Range Power Supply Rejection Ratio LOGIC INPUTS (PWDN [1. R = 909 ⍀.0 2 12 RL = 21 Ω. PWDN “0” RL = 100 Ω SFDR < –82 dBc. RL = 21 Ω 100 kHz.1 125 1000 13 16 19 8 1 55 –VS + 2. VOUT = 2 V p-p 37 36 3. In1. V = 3 V.0]) Logic “1” Voltage Logic “0” Voltage Logic Input Bias Current Turn On Time Specifications subject to change without notice.5 V 3. cm VMID = “Float.2 to 2. ∆VS = ± 0.1 ±5 ± 30 2.
. . . . . The maximum safe junction temperature for a plastic encapsulated device is determined by the glass transition temperature of the plastic. 12. . . . . Exposure to absolute maximum rating conditions for extended periods may affect device reliability. . . . . . . functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. it is necessary to observe the maximum power derating curve. . . . .AD8391 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . Temperature CAUTION ESD (electrostatic discharge) sensitive device. . 0 . 300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. . . 650 mW Input Voltage (Common-Mode) . . approximately 150°C. . . . . . . . . . permanent damage may occur on devices subjected to high-energy electrostatic discharges. . . . . . . . . . . . . Although the AD8391 features proprietary ESD protection circuitry. . . . To ensure proper operation. . . . . . . . . . . . .6 V Internal Power Dissipation2 Small Outline Package (R) .5 –40°C to +85°C 8-Lead Plastic SOIC –40°C to +85°C 8-Lead SOIC –40°C to +85°C 8-Lead SOIC Evaluation Board 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE – ؇C 80 90 Figure 2. . . . –65°C to +150°C Operating Temperature Range . . . . . . . . . . . . This is a stress rating only. . The maximum power that can be safely dissipated by the AD8391 is limited by the associated rise in junction temperature. .5 8-LEAD SOIC PACKAGE 1. . Observe Power Derating Curve Storage Temperature Range . . . . . proper ESD precautions are recommended to avoid performance degradation or loss of functionality. . . . . ± VS Logic Voltage. . 2 Specification is for device on a four-layer board in free air at 85°C: 8-Lead SOIC package: JA = 100°C/W. . . . . . . . Plot of Maximum Power Dissipation vs. . . . . . . . . . . . PWDN . . . . . . . .0 ORDERING GUIDE Model AD8391AR AD8391AR–REEL AD8391AR–REEL7 AD8391AR–EVAL Temperature Range Package Description Package Option SO-8 SO-8 SO-8 SO-8 0. . . . . 2. . . . . –40°C to +85°C Lead Temperature Range (Soldering 10 sec) . .0 TJ = 150؇C MAXIMUM POWER DISSIPATION – W 1. . . . Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. . . . . Therefore. . . . . . . . . . . . . WARNING! ESD SENSITIVE DEVICE –4– REV. . . Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. ± VS Output Short Circuit Duration .
5 CF = 0pF 1.004 0.1F 0.006 VIN = 1V p-p –3 –4 0 25 50 75 100 125 150 175 200 225 250 TIME – ns –0.0 1.4 0 25 50 75 100 125 150 175 200 225 250 TIME – ns TPC 1.4 CF 0.4 0.5V G = –2 RL = 10⍀ OUTPUT VOLTAGE – V 0.1 –0. Small Signal Step Response 0.2 0.2 VS = ؎6V G = –2 RL = 10⍀ 2.5 –1. Small Signal Step Response TPC 5.1 CF = 3pF 0 –0.3 CF = 0pF 0.002 0 –0.01 0 50 100 150 TIME – ns 200 250 300 TPC 3.5 0 –0.0 OUTPUT VOLTAGE – V 0.3 –0.Typical Performance Characteristics– AD8391 0.1F OUTPUT VOLTAGE – V VOUT 0.01 0. Large Signal Step Response 4 3 2 VS = ؎6V G = –2 RL = 10⍀ 0.2 –0. 0 –5– .1 0 –0. Single-Ended Test Circuit TPC 4.1 –0.3 –0.0 –1.5 –2.3 CF = 0pF VS = ؎1.0 25 50 75 100 125 150 175 200 225 250 VS = ؎1.1% Settling Time REV.008 –0.8F –VS –0.004 –0.1F 0.8F 6. 0.002 OUTPUT ERROR –0.2 VMID + + +VS 6.006 VS = ؎6V G = –2 CF = 0pF OUTPUT VOLTAGE – V 1 0 –1 –2 CF = 3pF OUTPUT ERROR – V 0.5V G = –2 RL = 10⍀ RG VIN RF RL ~ 0. Large Signal Step Response TPC 6.4 0 CF = 3pF CF = 3pF 0 25 50 75 100 125 150 175 200 225 250 TIME – ns TIME – ns TPC 2.008 0.
0 . Output Saturation Voltage vs. Output Voltage vs. Load 18 15 12 STANDBY 9 GAIN – dB 18 VS = ؎6V RL = 10⍀ G = ؊2 15 12 STANDBY 9 VS = ؎1.5V RL = 10⍀ G = ؊2 GAIN – dB 6 3 0 –3 –6 –9 0.5V RL = 10⍀ G = –2 OUTPUT VOLTAGE – dBV 3 0 –3 –6 –9 –12 –15 –18 0.AD8391 12 9 6 VS = ؎6V RL = 10⍀ G = –2 OUTPUT VOLTAGE – dBV 6 3 0 –3 –6 –9 –12 –15 –18 –21 1 10 FREQUENCY – MHz 100 1000 VS = ؎1. Output Saturation Voltage vs. Frequency 1500 VS = ؎6V 1200 VS = ؎1. Load TPC 11.5V VOH @+85؇C VOH @+25؇C VOH @ –40؇C OUTPUT SATURATION VOLTAGE – m V 1250 OUTPUT SATURATION VOLTAGE – m V 100 VOH @+85؇C VOH @+25؇C VOL@ –40؇C VOH @ –40؇C 1000 800 750 600 500 VOL @+85؇C 250 VOL @+25؇C VOL @ –40؇C 400 200 VOL@ +25؇C VOL@+85؇C 0 0 100 200 300 400 500 600 700 800 900 1000 LOAD CURRENT – mA 0 0 50 100 150 200 250 300 350 400 450 500 LOAD CURRENT – mA TPC 8. Output Voltage vs.1 FULL POWER 6 3 0 –3 –6 –9 0. Small Signal Frequency Response TPC 12.1 1 10 FREQUENCY – MHz 100 1000 TPC 7. Frequency TPC 10. Small Signal Frequency Response –6– REV.1 FULL POWER 1 10 FREQUENCY – MHz 100 1000 1 10 FREQUENCY – MHz 100 1000 TPC 9.1 –24 0.
01 0. Frequency REV. Voltage Noise vs. 0 –7– . RG = 453⍀. RG = 178⍀.1 1 10 100 1k FREQUENCY – MHz FREQUENCY – MHz TPC 14. Output Impedance vs. Current Noise vs.1 1 10 FREQUENCY – MHz 100 1k 1 10 FREQUENCY – MHz 100 1k TPC 15.5V 100 80 60 40 20 VS = ؎6V 40 30 20 VS = ؎1. Frequency (RTI) 10k VS = ؎6V 1k OUTPUT IMPEDANCE – ⍀ 10k VS = ؎1.1 0. Frequency TPC 17.5V 1k OUTPUT IMPEDANCE – ⍀ POWER-DOWN POWER-DOWN 100 100 10 10 POWER-UP 1 POWER-UP 1 0. Frequency 20 –15 –20 SIGNAL FEEDTHROUGH – dB 0 VS = ؎6V RL = 10⍀ POWER-DOWN VIN = 10dBm –20 CROSSTALK – dB –25 –30 –35 G = –5. RF = 909⍀ –120 0. Signal Feedthrough vs.5V 10 0 10 100 1k 10k 100k 1M 0 10 100 1k 10k 100k 1M FREQUENCY – Hz FREQUENCY – Hz TPC 13.01 0. Frequency (RTI) TPC 16.AD8391 60 140 120 VS = ؎6V 50 CURRENT NOISE – pA/ Hz VOLTAGE NOISE – nV/ Hz VS = ؎1. Crosstalk (Output to Output) vs. RF = 909⍀ –40 –45 –50 –55 0. Frequency TPC 18. Output Impedance vs.1 1 10 100 1k 0.1 0.1 –40 POWER-UP –60 –80 POWER-DOWN –100 VIN = 10dBm VS = ؎6V RL = 10⍀ G = –2 G = –2.
0 2.5V RL = 21⍀ G = –5.1 2.5V –100 HD3 @VS = ؎6V –110 0. (RG = 178⍀) DIFFERENTIAL DISTORTION – dBc RL = 21⍀ HD3 (FO = 500kHz) –40 –50 –60 –70 VS = ؎1. Frequency –30 –30 VS = ؎6V –40 DIFFERENTIAL DISTORTION – dBc –50 –60 –70 –80 –90 –100 –110 G = –5.AD8391 RG VIN+ VOUT– VMID CMID VOUT+ RF DIFFERENTIAL DISTORTION – dBc –30 –40 –50 –60 HD2 @VS = ؎1.8 1.1 1 10 RL = 21⍀ FOR VS = ؎6V.5dBm 2. Differential Distortion vs. Differential Output Test Setup TPC 22.01 0.5dBm 14dBm MTPR – dBc 13dBm –55 13. Output Voltage TPC 23.8 1.2 2.5dBm 14dBm SFDR – dBc 13dBm –65 –65 –70 –75 –75 12. 0 . MTPR vs. Differential Distortion vs. SFDR vs. (RG = 178⍀) HD2 (FO = 500kHz) HD2 (FO = 500kHz) HD3 (FO = 500kHz) –80 –90 –100 HD2 (FO = 100kHz) HD3 (FO = 100kHz) HD2 (FO = 100kHz) HD3 (FO = 100kHz) –110 2 6 10 14 18 22 0 1 2 3 4 5 6 OUTPUT VOLTAGE – V p-p OUTPUT VOLTAGE – V p-p TPC 20. Transformer Turns Ratio TPC 24.9 1. Output Voltage –25 VS = ؎6V RLINE = 100⍀ –50 –35 –55 VS = ؎6V RLINE = 100⍀ –45 –60 13. Differential Distortion vs.7 12. V OUT = 8V p-p FOR VS = ؎1. V OUT = 2V p-p G = –5 RL RG VIN– RF FREQUENCY – MHz TPC 19.2 2.0 2.7 12dBm –80 1.5V.1 2.3 TRANSFORMER TURNS RATIO TRANSFORMER TURNS RATIO TPC 21.5V –70 HD2 @ VS = ؎6V –80 –90 HD3 @VS = ؎1.5dBm –85 1.9 2. Transformer Turns Ratio –8– REV.3 12dBm 1.
5V VIN = 500mV/DIV VOUT = 500mV/DIV G = –5 RL = 10⍀ VIN 0V 0V VIN TIME – ns (100ns/DIV) TIME – ns (100ns/DIV) TPC 26. (RG = 178⍀) HD2 (FO = 500kHz) HD3 (FO = 500kHz) –60 –70 –80 HD2 (FO = 500kHz) –70 –80 –90 HD2 (FO = 100kHz) –90 –100 HD2 (FO = 100kHz) –100 HD3 (FO = 100kHz) –110 25 150 275 400 525 650 HD3 (FO = 100kHz) –110 25 75 125 175 225 275 PEAK OUTPUT CURRENT – mA PEAK OUTPUT CURRENT – mA TPC 25. Overload Recovery TPC 28. Single-Ended Distortion vs. (RG = 178⍀) –40 –50 VS = ؎1.AD8391 –30 –40 –50 –60 –30 VS = ؎6V HD3 (FO = 500kHz) SINGLE-ENDED DISTORTION – dBc SINGLE-ENDED DISTORTION – dBc G = –5. Peak Output Current VS = ؎6V VIN = 1V/DIV VOUT = 2V/DIV G = –5 RL = 10⍀ 0V VOUT 0V VOUT VS = ؎1. Overload Recovery REV. 0 –9– . Peak Output Current TPC 27. Single-Ended Distortion vs.5V G = –5.
VMID is accessible through Pin 7. allowing the gain of the amplifiers to be set with external resistors. RIN is inversely proportional to the transconductance of the amplifier’s input stage. bandwidth. The complementary common-emitter output provides the extended output swing. The output stage is another high-gain amplifier used as an integrator to provide frequency compensation. one can see that the amplifier’s bandwidth depends primarily on the feedback resistor.AD8391 GENERAL INFORMATION Theory of Operation The AD8391 is a dual current feedback amplifier with high output current capability. The process uses dielectrically isolated transistors to eliminate the parasitic and latch-up problems caused by junction isolation.com/technology/amplifiersLinear/ designTools/evaluationBoards/pdf/1. These features enable the construction of high-frequency. A current feedback amplifier’s bandwidth and distortion performance are relatively insensitive to its closed-loop signal gain. as the amplifier will have additional poles that will contribute excess phase shift. The optimum value for RF depends on the gain and the amount of peaking tolerable in the application. noise. see ADI’s High-Speed Design Techniques at www. Circuit analysis of the pictured follower with gain circuit yields: VOUT G × Tz( s) = VIN Tz( s) + RF + G × RIN VO VP VN BIAS Figure 3. and that the –3 dB point is set when Tz(s) = RF. See the front page for a connection diagram of the AD8391. low-distortion amplifiers. 0 . It is fabricated on Analog Devices’ proprietary eXtra Fast Complementary Bipolar Process (XFCB) that enables the construction of PNP and NPN transistors with fT’s greater than 3 GHz. The AD8391 has a unique pin out. The two inverting pins are available at Pin 1 and Pin 8. These values are only intended to be a starting point when designing for any application. which is a distinct advantage over a voltage-feedback architecture. Table I. –10– REV. Table I shows the recommended resistor values for use in a variety of gain settings for the test circuits in TPC 1 and TPC 19. There is also a 10 pF internal capacitor from VMID to –VS.analog. VP. Simplified Schematic G=1 + VIN VO RIN IIN IT = IIN CT RT + – VOUT – RF RG Figure 4.pdf. Figure 4 shows a simplified model of a current feedback amplifier. VN. The low-impedance current feedback summing junction is at the negative input. selection of the feedback and gain resistors will impact distortion. Model of Current Feedback Amplifier Feedback Resistor Selection where: G =1+ RF RG In current feedback amplifiers. gmi. For more information about current feedback amplifiers. The feedback signal is an error current that flows into the inverting node. The two noninverting inputs of the amplifier are connected to the VMID pin. Resistor Selection Guide Tz( s) = RIN = RF 1 + sCT ( RT ) 1 ≅ 125 Ω gmi Gain –1 –2 –3 –4 –5 RF (⍀) 909 909 909 909 909 RG (⍀) 909 453 303 227 178 Recognizing that G × RIN << RF . Emitter followers buffer the positive input. to provide low-input current and current noise. and gain flatness. There is a value of RF below which the amplifier will be unstable. Care should be exercised in the selection of these resistors so that the optimum performance is achieved. which is internally biased by two 5 kΩ resistors forming a voltage divider between +VS and –VS. A simplified schematic of an amplifier is shown in Figure 3.
A factor α corrects for the slight error due to the Class A/B operation of the output stage.8 V or less above –VS. Bypassing capacitors should be laid out in such a manner to keep return currents away from the inputs of the amplifiers.8 times the rms value: PTOT = 4 (0. A large ground plane will also provide a low impedance path for the return currents. This noise source is common mode and will not contribute to the output noise when the AD8391 is used differentially. This will help prevent any high frequency components from finding their way to the noninverting inputs of the amplifiers. The value of α depends on what portion of the quiescent current is in the output stage and varies from 0 to 1. The –VS pin is the logic reference for the PWDN function. a change in the power supply voltage (∆V) will result in a change of one-half ∆V at the VMID pin.AD8391 Power-Down Feature Power Dissipation A three-state power-down function is available via the PWDN pin. computing the dissipation in the output devices and adding it to the quiescent power dissipation will give a close approximation of the total power dissipation in the package. The AD8391 can also operate on dual supplies. or shutdown. It allows the user to select among three operating conditions: full on. standby. These resistors will contribute approximately 6. This will minimize any voltage drops that can develop due to ground currents flowing through the ground plane. from ± 1. High-quality capacitors with low equivalent series resistance (ESR) such as multilayer ceramic capacitors (MLCCs) should be used to minimize supply voltage ripple and power dissipation. the AD8391 operates in a standby mode with low impedance outputs and draws approximately 10 mA. this is unavoidable. or MAD. If the output current is large compared to the quiescent current.e. Design Considerations It is important to consider the total power dissipation of the AD8391 to size the heat sink area of an application properly. Second. Careful attention must be paid to decoupling the power supply. Figure 5 is a simple representation of a differential driver. If the inputs are dc-coupled. the AD8391 circuit should be powered with a well-regulated supply. RL is the total impedance seen by the differential driver. The VMID pin is internally biased by two 5 kΩ resistors forming a voltage divider between VCC and ground. If the PWDN pin floats. In a dual-supply system. large signal changes at the AD8391 outputs. Power Supply and Decoupling The AD8391 can be powered with a good quality (i. ∆V × (1 + Rf /Rg) will appear at the outputs. sometimes called the mean average deviation. A large. In addition. 0. In order to optimize the ADSL upstream drive capability of +13 dBm and maintain the best Spurious Free Dynamic Range (SFDR).8 VO rms VS – VO rms2 ) × 1 + 2 α IQ VS RL For the AD8391 operating on a single 12 V supply and delivering a total of 16 dBm (13 dBm to the line and 3 dBm to account for the matching network) into 50 Ω (100 Ω reflected back through a 1:2 transformer plus back termination). VO is the voltage at the output of one amplifier. resulting in a PSRR of –6 dB. ( 2 ) × R1 + 2 α IQ VS L In this differential driver.5 V to ± 6 V. usually tantalum. If the amplifiers’ inverting inputs are ac-coupled. The VMID pin should also be decoupled to ground by using a 0. First.3 nV/ √Hz of input-referred (RTI) noise. In shutdown the AD8391 will draw only 4 mA.1 µF MLCC decoupling capacitors should be located no more than 1 ⁄ 8 inch away from each of the power supply pins. eliminating this source of noise. With some simplifying assumptions the total power dissipated in this circuit can be estimated. The full shutdown state is maintained when the PWDN is at 0. Simplified Differential Driver Remembering that each output device only dissipates power for half the time gives a simple integral that computes the power for each device: 1 2 ∫ (V S – VO ) × 2 VO RL The total supply power can then be computed as: PTOT = 4 VS ∫|VO| − ∫ VO There are some unique considerations that must be taken into account when designing with the AD8391. 0 –11– . 10 µF capacitor is required to provide good decoupling for lower frequency signals and to supply current for fast. In a single-supply system. VMID can be connected directly to ground. REV. When VMID is left floating. +VS +VS +VO RL –VO –VS –VS Figure 5. one-half ∆V will appear at the output. the MAD value is equal to 0.72. low-noise) supply anywhere in the range from 3 V to 12 V. For the AD8391. so 2 VO is the voltage across RL.1 µF ceramic capacitor. with two observations the integrals are easily evaluated. the integral of |VO| is equal to the average rectified value of VO. Now. including any back termination. the integral of VO2 is simply the square of the rms value of VO. the dissipated power is 395 mW.. α ≅ 0. It can be shown that for a DMT signal.
There is also a place for an AD9632. Assuming that the maximum low distortion output swing available from the AD8391 line driver on a 12 V supply is 11 V. If the modem designer desires to transmit more than 13 dBm down the twisted pair. Proper RF design techniques are mandatory.5⍀ 10F 0. the traces on the PCB should be close. The sources of such capacitance can include but are not limited to EMI suppression capacitors. Table II. Distortion introduced by the transformer can severely degrade DSL performance.5 126 129 131 Thermal stitching. Operation at a junction temperature over the absolute maximum rating of 150°C should be avoided. which connects the outer layers to the internal ground planes(s). Layout Considerations As is the case with all high-speed applications. One must take care to minimize any capacitance present at the outputs of a line driver. Table II shows junction temperature versus power delivered to the line for several supply voltages while operating at an ambient temperature of 85°C. The existence of these capacitances is unavoidable and limiting both distributed and interwinding capacitance to less than 20 pF each should be sufficient for most applications. a step-up transformer with turns ratio of 1:2 is adequate for most applications. resistors R25 and R26. particularly in the area of the inverting inputs. The bill of materials included as Table III represents the components that are installed in the evaluation board when it is shipped to a customer. which can be used to convert a differential signal into a single-ended signal. + 1F 0. The total differential load for the AD8391.1 µF. Termination resistors and loads should be located as close as possible to their respective inputs and outputs. Transformer Selection VSUPPLY PLINE. ACcoupling capacitors of 0. Transformers have two kinds of parasitic capacitances: distributed or bulk capacitance.5 V peak voltage on a 100 Ω telephone line.5 Ω [1/2 (100 Ω/22 )] where 100 Ω is the approximate phone line impedance. Single-Supply Voltage Differential Drive Circuit –12– REV. 560 mW peak line power translates into a 7. Removing the ground plane on all layers from the areas near the input and output pins will reduce stray capacitance.1F VCC + Figure 6. When running differential signals over a long distance. and interwinding capacitance. It is also important that the transformer operates in its linear region throughout the entire dynamic range of the driver.AD8391 Using these calculations and a θJA of 100°C/W for the SOIC. Figure 10 shows the schematics for the evaluation board. This trade-off comes at the expense of higher power dissipation by the line driver as well as increased attenuation of the downstream signal that is received by the transceiver. including the termination resistors. each 12. C6 and C11. Line Power and Operating Voltage for SOIC at 858C Ambient Evaluation Board The AD8391 is available installed on an evaluation board. R45 and R46 are back termination or line matching resistors.5⍀ 1:2 Customer premise ADSL requires the transmission of a 13 dBm (20 mW) DMT signal. Distributed capacitance is a result of the capacitance created between each adjacent winding on a transformer. requiring the line driver to provide peak line power of 560 mW. a symmetrical layout should be provided to the extent possible to maximize balanced performance. The signal routing should be short and direct in order to minimize parasitic inductance and capacitance associated with these traces. overvoltage protection devices and the transformers used in the hybrid. In the simplified differential drive circuit shown in Figure 6 the AD8391 is coupled to the phone line through a step-up transformer with a 1:2 turns ratio. that will convert a single-ended signal into a differential signal. A transformer reflects impedance from the line side to the IC side as a value inversely proportional to the square of the turns ratio. will form a first order high-pass pole at 160 Hz.1F 8 7 6 5 453⍀ 909⍀ 12. especially when operating at long loop lengths. 0 . Junction Temperature vs. Interwinding capacitance is the capacitance that exists between the windings on the primary and secondary sides of the transformer.5 V of the power supply rails. dBm 13 14 15 12 125 127 129 12. Adherence to stripline design techniques for long signal traces (greater than about one inch) is recommended. Input and output traces should be kept as far apart as possible to minimize coupling (crosstalk) through the board. careful attention to printed circuit board layout details will prevent associated board parasitics from becoming problematic.3. Wherever there are complementary signals. There are footprints for additional components. is 50 Ω. a higher turns ratio can be used for the transformer. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low-impedance return path. +VS VIN VMID AD8391 RL –VS 1 – 1F 453⍀ 909⍀ 2 3 4 +3V + – 12. This will reduce the radiated energy and make the circuit less susceptible to RF interference. and taking into account the power lost due to the termination resistance. can help to use the thermal mass of the PCB to draw heat away from the line driver and other active components. Even under these conditions the AD8391 provides low distortion signals to within 0. such as an AD8138. in combination with 10 kΩ. The DMT signal has a crest factor of 5.
As the turns ratio increases. 4 ADSL systems rely on Discrete Multitone (DMT) modulation to carry digital data over phone lines. sometimes referred to as tones or bins. but will also produce spurs that exist outside of the frequency spectrum containing the transmitted signal. A voltage reduction or attenuation equal to the inverse of the turns ratio is realized in the receive channel of a typical bridge hybrid. two AD8021 low-noise amplifiers can be used instead.05 1. a dual amplifier with typical RTI voltage noise of only 2. Using a transformer with as low a turns ratio as possible will limit degradation of the received signal. A uniquely encoded. similar to expressing the relative difference between single-tone fundamentals and second or third harmonic distortion components. Significant degradation of MTPR will occur if the output transistors of the driver saturate. and Figure 8 for a time domain waveform.2 Figure 8. 0 POWER – dBm –13– . DMT Waveform in the Frequency Domain TPC 21 and TPC 24 depict MTPR and SFDR versus transformer turns respectively for a variety of line power ranging from 12 dBm to 14 dBm. “Out-of-band” spurious-free dynamic range (SFDR) can be defined as the relative difference in amplitude between these spurs and a tone in one of the upstream bins. Regardless of terminology. Measurements of MTPR are typically made on the line side or secondary side of the transformer. Multitone Power Ratio (MTPR) and Out-of-Band SFDR Conventional methods of expressing the output signal integrity of line drivers such as single-tone harmonic distortion or THD. The turns ratio of the transformer may also be dictated by the ability of the receive circuitry to resolve low-level signals in the noisy twisted pair telephone plant. Multitone Power Ratio (MTPR) is the relative difference between the measured power in a typical subband (at one tone or carrier) versus the power at another subband specifically selected to contain no QAM data. maintaining high out-of-band SFDR while reducing NEXT will improve the overall performance of the modems connected at either end of the twisted pair. Driving DMT signals to such extremes not only compromises “in-band” MTPR. 20 3 2 1 0 –1 VOLTS –2 –3 –0.5 nV/√Hz and a low supply current of 4 mA/amplifier is recommended for the receive channel.5 –1. While higher turns ratio transformers boost transmit signals to the appropriate level. DMT modulation appears in the frequency domain as power contained in several individual frequency subbands. DMT Signal in the Time Domain 0 –20 –40 –60 –80 0 50 100 FREQUENCY – kHz 150 Figure 7. The AD8022.25 –0.5 0. MTPR. sometimes referred to as the “empty bin test. Difficulties will exist when decoding these subbands if a QAM signal from one subband is corrupted by the QAM signal(s) from other subbands regardless of whether the corruption comes from an adjacent subband or harmonics of other subbands. If power-down is required for the receive amplifier. the driver hybrid can deliver more undistorted power to the load due to the high output current capability of the AD8391.2 –1. each of which are uniformly separated in frequency. a selected subband (or tone) remains open or void of intentional power (without a QAM signal) yielding an empty frequency bin.” is typically expressed in dBc. In other words.05 0 TIME – ms 0. twotone InterModulation Distortion (IMD) and third order intercept (IP3) become significantly less meaningful when amplifiers are required to process DMT and other heavily modulated waveforms.0 –0.0 1. A typical ADSL upstream DMT signal can contain as many as 27 carriers (subbands or tones) of QAM signals. Compromising out-of-band SFDR is the equivalent to increasing near-end crosstalk (NEXT). causing clipping at the DMT voltage peaks. See Figure 7 for an example of a DMT waveform in the frequency domain. Quadrature Amplitude Modulation (QAM) like signal occurs at the center frequency of each subband or tone. REV.AD8391 Receive Channel Considerations A transformer used at the output of the differential line driver to step up the differential output voltage to the line has the inverse effect on signals received from the line. DMT Modulation. they also effectively reduce the received signal-to-noise ratio due to the reduction in the received signal strength.
making this circuit ideal for any application where one signal needs to be sent to two different locations. a 14-bit TxDAC. As previously stated. Note that the DMT waveforms.1F 8 7 0. VEE 10F 75⍀ 6 – +VS 76.1F + 75⍀ VIN AD8391 + – +3V 3 4 75⍀ 909⍀ 909⍀ 0. buffered by an AD8002 amplifier configured as a differential driver. available on the Analog Devices website (www. See Figure 9 for an example circuit. The termination resistor should be 76. eliminating the need for ac-coupling.8⍀ VMID –VS 1 2 + 5 909⍀ 909⍀ 0. 0 . Generating DMT signals can be accomplished using a Tektronics AWG 2021 equipped with option 4. such as a video distribution system. the AD8391 can operate on split supplies in this case. DMT-modulated waveforms are not typically menuselectable items contained within arbitrary waveform generators.AD8391 Generating DMT Signals Video Driver At this time. digitally coupled to Analog Devices’ AD9754. MTPR evaluation requires a DMT signal generator capable of delivering MTPR performance better than that of the driver under evaluation. Driving Two Video Loads from the Same Source –14– REV. Even using AWG software to generate DMT signals. The AD8391 can be used as a noninverting amplifier by applying a signal at the VMID pin and grounding the gain resistors. The signal applied to the VMID pin would be present at both outputs.analog.1F + VCC 10F 75⍀ Figure 9. AWGs that are available today may not deliver DMT signals sufficient in performance with regard to MTPR due to limitations in the D/A converters and output drivers used by AWG manufacturers.com) are similar. TTL Digital Data Out).8 Ω to maintain a 75 Ω input impedance. (12-/24-bit. WFM files are needed to produce the necessary digital data required to drive the TxDAC from the optional TTL Digital Data output of the TEK AWG2021.
9 0⍀ AGND AGND VPOS AGND C28 SO8 DNI C10 1 –IN 2 V 3 MID V+ 4 +OUT R20 AD8391 R36 0⍀ 1 1 2 –IN 3 +IN 4 –VS DNI VNEG 8 8 7 +VS 6 OUT 5 5 Figure 10.REV. Evaluation Board Schematic +VOUT –VOUT –15– VPOS AD9632 R42 DNI DNI DNI 0⍀ AGND C15 DNI AGND OUT DNI TP1 +V TP2 GND C9 C26 C27 –V TP3 1F DNI AGND VNEG AGND DNI AD8391 .9 C29 1F 26 R29 AGND +VOUT VOUT2 R31 DNI R24 R1 0⍀ SHORT AGND R23 0⍀ SHORT AGND R25 DNI TP4 DNI C23 L1 +V GND L2 C24 C8 1F TP5 1F DNI C25 –V PWRBLK PB3 *DNI = DO NOT INSTALL 1F 1F C7 453 C6 R27 AGND R2 DNI PWDN VMID C5 DNI TB C13 DNI R26 453 DNI C11 R28 R30 DNI –VOUT R35 0⍀ R32 909 C14 DNI AGND TP7 R39 DNI 909 IN2 8 C3 SHORT 1F R33 DNI C12 0⍀ DNI DNI VNEG SHORT 0⍀ R22 R38 R40 DNI C22 DNI R17 DNI R41 DNI 8 +IN 7 NC 6 V– 5 –OUT 7 VMID 6 –VS 5 1 IN1 2 PWDN 3 +VS 4 VOUT1 TA R45 DNI R13 C16 DNI R14 DNI C17 TB R46 DNI DNI IN_POS IN_NEG R19 R18 49. 0 T1 1 10 8 C1 1F BI BI BI J1 [21:6] J1 [21:6] TP9 R47 DNI J1 [21:6] J1 [21:6] 9 7 DNI 3 2 4 J1 [21:6] J1 [21:6] TP8 BI BI BI TP6 TA C2 R21 49.
Silkscreen—Primary Side –16– REV. 0 . Layer 1—Primary Side Figure 12.AD8391 Figure 11.
Layer 3—Power Plane REV. Layer 2—Ground Plane Figure 14.AD8391 Figure 13. 0 –17– .
Layer 4—Secondary Side Figure 16. Layer 4—Silkscreen –18– REV. 0 .AD8391 Figure 15.
C6. R38 R25. 4 4 14 2 4 1 1 2 1 1 2 2 1 2 6 12 2 2 2 1 2 1 2 2 2 1 1 1 4 4 Description 0. R44. R26. C7–C9 C2. L2 PB1 PB3 R1. R47 R36. C11 C5. Evaluation Board Bill of Materials Qty. R33 R17 R18. TP9 Z4 Z5 Z6 ADS #4-7-24 ADS #12-1-31 D-K #A 9024 ADS #48-1-1 ADS #12-19-14 ADS #3-18-88 ADS #3-15-3 ADS #3-2-177 ADS #3-53-1 ADS #3-53-2 ADS #12-18-43 ADS #12-18-44 ADS #12-18-62 ADS #12-18-60 ADS #12-18-42 ADI #AD9632AR ADI #AD8391AR ADI #AD8138AR ADS #30-1-1 ADS #30-16-3 REV. C3. R24. R28 R29. R45. R35. R31. R23 R2. R32 T1 TP1. R20. R30. TP7 TP8. C10. R46. TP5 TP6. R22. 0 –19– . R40 R42. JACK (SHIELDED) 6 6 FERRITE CORE 1/8 inch BEAD FB43101 DNI 3 Green Terminal Block ONSHORE #EDZ250/3 0 Ω 5% 1/8 W 1206-Size Chip Resistor DNI DNI 49. R43.AD8391 Table III.1 µF 50 V 1206 Size Ceramic Chip Capacitor 0 Ω 5% 1/8 W 1206-Size Chip Resistor DNI 10 µF 16 V ‘B’-Size Tantalum Chip Capacitor SMA End Launch Jack (E F JOHNSON #142-0701-801) DNI AMP #555154-1 MOD. C12–C17 C22. TP4 TP2 TP3. R39. C25–C29 C23–C24 IN_NEG.9 Ω Metal Film Resistor 0 Ω Metal Film Resistor DNI DNI 453 Ω Metal Film Resistor 909 Ω Metal Film Resistor DNI Red Test Point Black Test Point Blue Test Point Orange Test Point White Test Point AD9632 (DNI) AD8391 AD8138 (DNI) #4-40 ϫ 1/4 inch STAINLESS Panhead Machine Screw #4-40 ϫ 3/4 inch-long Aluminum Round Stand-Off Vendor ADS #4-5-18 ADS #3-18-88 Ref Des C1. R41 R27. R21 R19. IN_POS PWDN. VMID OUT J1 L1.
25) 8؇ 0.AD8391 OUTLINE DIMENSIONS Dimensions shown in inches and (mm).0098 (0.10) SEATING PLANE 0.20) 0.A.80) 0.0500 (1.S.80) PIN 1 1 0.2284 (5.0192 (0.35) 0.1968 (5.49) 0.00) 0. 0 PRINTED IN U.0160 (0. .27) 0.25) 0؇ 0.00) 0.0500 (1.27) BSC 0.1497 (3. INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN –20– REV.0075 (0.0532 (1.0098 (0.50) ؋ 45؇ 0.80) 8 5 4 0.25) 0.1574 (4.8–10/01(0) 0.1890 (4.19) CONTROLLING DIMENSIONS ARE IN MILLIMETERS.75) 0.0688 (1.0040 (0.2440 (6.0138 (0.0099 (0.35) 0. 8-Lead SOIC (R-8) C02719–.0196 (0.41) 0.
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