Special Papers MOS Operational Amplifier Design— A Tutorial Overview


Abstract-This paper presents an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level. Primary emphasis is placed on CMOS amplifiers because of their more widespread use. Factors affecting voltage gain, input ,noise, offsets, common mode and power supply rejection, power dissipation, and transient response are considered for the traditional bipolar-derived two-stage architecture. Alternative circuit approaches for optimization of particular performance aapects are summarized, and examples are given.

In Section II, the important




objectives for operational amplifiers within a monolithic analog subsystem are summarized. In Section III, the performance of the basic two-stage CMOS operational amplifier architecture is summarized. In Section IV, alternative circuit approaches for the improvement of particular performance aspects are considered. In Section V, the particular problems associated with NMOS depletion sidered. amplifiers Finally, a summary load amplifier design are constages is considered, and in Section VI, the design of output


and discussion of the design of are presented in Section VII.
OBJECTIVES AMPLIFIERS operational subsystem stand-alone difference amplifiers are often bipolar is the fact quite that to be diffor FOR

in scaled technologies II. PERFORMANCE



HE rapid increase in chip complexity analog-digital

which has occurred cirused within ferent Perhaps many from the

over the past few years has created the need to implement subsystems on the same integrated

cuit using the same technology. For this reason, implementation of analog functions in MOS technology has become increasingly important, and great strides have been made in recent years in implementing functions such as high-speed DAC’S, sampled data analog filters, voltage references, instrumentation amplifiers, and ‘so forth in CMOS and NMOS technology [1] . These developments have been well documented in the literature. Another key technical development has been a maturing of the state of the art in the implementation of operational amplifiers (op amps) in MOS technology. These amplifiers are key elements of most analog subsystems, particularly in switched capacitor filters, and the performance of many systems is strongly influenced by op amp performance. amplifier deand in the literature, Many of the developments the intent field. within in MOS operational

The performance those most

objectives of traditional important


a monolithic



of the amplifiers

in the system, the load which the out-

put of the amplifier stand-alone

has to drive is well defined, and is often In contrast, must be deamplifiers usually

purely capacitive with values of a few picofarads. general-purpose

signed to achieve a certain level of performance independent of loading over capacitive loads up to several hundred picofarads and resistive loads down to 2 kfl or less. Within a monolithic analog subsystem, only a few of the amplifiers must drive a signal off chip where the capacitive and resistive loads are significant and variable. In this paper, these amplifiers will be termed output buffers, and the amplifiers whose outputs do not go off chip will be termed internal amplifiers. The particular problems of the design of these output buffers are considered in Section VII. A typical application of an internal operational amplifier, a switched capacitor integrator, is illustrated in Fig. 1. The basic function of the op amp is to produce an updated value of the output in response to a switching capacitor event at the input in which the source and disthe sampling is charged from

sign have not been as well documented

of this paper is to review the state of the art in this LSI systems, and the particuare

This paper is focused on the design of op amps for use single-chip analog-digital

lar problems of the design of stand-alone CMOS amplifiers not addressed.

Manuscript received August 24, 1982; This work was supported by the Joint under Contract F49620-79-c-0178 and tion under Grant ENG79-07055. The authors are with the Department Computer Sciences and the Electronics sity of California, Berkeley, CA 94720.

revised September 27, 1982. Services Electronics Program the National Science Foundaof Electrical Engineering and Research Laboratory, Univer-

charged into the summing node. The output must assume the new updated value within the required accuracy, typically on the order of 0.1 percent, within one clock period, t ypically Important on the order of 1 I.N for voiceband filters. performance

0018 -9200/82/ 1200-0969 $00.75

@ 1982 IEEE

NO. 2(a). Typical application of an internal MOS operational a switched capacitor integrator. portant in other applications. deviation CMRR CM range 5000 500 ns 100 nV/@ 90 dB 60 dB 40 dB lfF 0. focusing particularly polar case. . While the implementation of this architecture in NMOS technology requires additional circuit elements because of the lack of a complementary device. Fig. and CMRR in a simple circuit that can be compensated with a single pole-splitting capacitor. amplifier. for constant drain current decreasing either the channel length or width results in a decrease in the gain. making operational amplifier offsets less important. along with noise considerations. The expression illustrates several key aspects of MOS devices used as analog amplifiers. typically by a factor on the order of 10-40 for typically used geometries and bias currents [3] . the latter because of the fact that Vg~ increases. and the bipolar counterpart is also illustrated in Fig. Open Circuit Voltage Gain on the aspects which are different from the bi- the various performance pa- for the most widely used amplifier An important difference between MOS and bipolar technology is the fact that the maximum transistor open circuit voltage gain gm /gO is much lower for MOS transistors than for bipolar transistors. voltage gain. First. This circuit configuration provides good common mode range. In this section. III. usually be used this is the minimum high-gain size of the transistors amplifier application. 6. output ratio. Cl = 5 pF Fquiv. 1 kHz PSRR. In the following section. 50 kHz Supply capacitance Power dissipation Unity-gain frequency Die area Systematic offset Random offset std. Under certain to be simplifying assumptions.1 mV 2 mV 80 dB within 1 V of supply (c) parameters capacitive equivalent power are the power load. output swing. DECEMBER 1982 D G4 4NMO: SUB s G++ PM& SUB & Fig. we will analyze the various performance parameters of the CMOS implementation of this circuit. SC-17. and commonmode range are less important. dictates in a given This fact. 1 kHz PSRR. (a) Bipolar implementation. and die area. In this particular application the input offset voltage. (c) An example of an NMOS implementation with interstage coupling network. Currently. input noise. Two-stage operational amplifier architecture. This configuration is also widely used in bipolar technology. 1. 4pm S1 GATE CMOS) vSs (a) L!!!! OUT v- c (b) dc gain (capacitive load only) Setting time. 2(b). thermal (to be de- noise. many NMOS amplifiers commercially manufactured at the present time use a conceptually similar (1) where xd is the width of the depletion region between the end of the channel and the drain and L is the effective channel length. dc PSRR. IN IN OUT i‘H ~i TABLE I TYPICAL PERFORMANCE. voltage swing.970 IEEE JOURNAL OF SOLID-STATE CIRCUITS. CONVENTIONAL TWO-STAGE CMOS INTERNAL OPERATIONAL AMPLIFIER (+/–5 V SUPPLY. The behavior of this circuit when implemented in bipolar technology has been reviewed in an overview article published earlier [2] .5 mW 4 MHz 75 mils2 0. common-mode rejection ratio. 2. 1 V step. voltage gain can be shown BASIC TWO-STAGE CMOS OPERATIONAL the most widely AMPLIFIER used circuit approach for the im- plementation configuration of MOS operational amplifiers is the two-stage shown in Fig. (b) CMOS implementation. 2(c) where a differential composed in- supply supply capacitance level-shifting network of voltage and curthe first and second fined later). terstate as illustrated in Fig. VOL. the factors affecting rameters are evaluated architecture. maximum input allowable noise. voltage gain. The implementation of this circuit is discussed further in Section V. equivalent configuration. dc offsets can often be eliminated at the subsystem level. open-loop input flicker rejection dissipation. stages so that both stages can utilize n-channel active devices and depletion mode devices as loads. A typical set of values for the parameters given above for a conventional amplifier design in 4 pm CMOS technology are given in Table I. that must Usually. but these parameters can be imBecause of the inherent capaci- rent sources has been inserted between tive sample/hold capability in MOS technology.

5.VT) is several hundred amplifier. 5. The latter results from mismatches in supposedly identical pairs of devices.amps DEPENDS -3 -2 -1 1234 . Turning to the operational amplifier. if device size and bias current the gain is an increasing &d/dvd~ decreases with function increasing Systematic Offset Voltage In bipolar which technology. and at the same time compli- cates the design of high-speed amplifiers high current.3. since and is present even when all of the matched devices in the circuit are indeed identical. expression demonstrates Finally. ‘2 go6 +807 II For switched capacitor filter applications. and DC Power Supply Rejection The input dom offset. because of the relatively low gain per stage. 6.e SCALE /. the voltage gain is inversely proportional to the square root of the drain current since (v& . and the drain deple- Fig.\/ M41 L M6 lengths and widths are usually chosen such that the transistor (Vz= . are discussed in Section IV. the comparatively high voltage gain in per stage (on the order of 500) tends to result in a situation the input-referred is primarily amplifier of substrate doping doping. 1 M8 Ir M5 ~t M7 identical and thatlf3 andi144 are identical. each 50 mV difference . achieving the same voltage gain with smaller devices. then the quiescent output voltage at the drain of lkf4 is equal to the voltage at the drain of i143 (M3 voltage. alternatively. OF OCCURRENCE \ . A typical variation of open circuit voltage gain as a function of drain current is shown in Fig. Typical open circuit gain of anMOS bias current.GRAY AND MEYER: MOS OP AMP DESIGN–AN OVERVIEW 971 ’09al r“:~’:::~’:ooo 1 FREQ. DC Biasing. Vos. if the device geometry is kept constant. 4 has been split into two separate stages. from the quiescent output voltage of the first stage. Similarly. The gain becomes constant at a value comparable in the subthreshold of low current to bipolar devices results from the design of the circuit This fact makes use which must operate at are kept constant. Thus.. In Fig. the that open circuit gain is not degraded dc offset voltage of an operational dependent on the design of the first stage. mV Fig. the overall voltage gain required is on the order of several thousand [5]. the operational amplifier of Fig. implying a gain in each stage on the order of 50. However..7 . +V transistor asafunctionof Fig. the offset voltage of the differential to single-ended converter and second stage can play an important role. Circuit approaches to achieving more voltage gain or. For a first signal output stage gain of 50. and f144 have the same drain and hence must the value of the gate voltage current and gate-source voltage). range of current. scaling in the quasi-constant field or constant voltage sense would result in a decrease in gain.-5 .vT) is proportional to the square root of the drain current. Second. Typicdtiput { SYSTEMATIC OFFSET offset distribution. levels desirable.4 ON . millivolts. if the inputs of the first stage are grounded. 4. the systematic offset and the ran- larger than the length and width used for digital circuits in the same technology. A typical observed distribution of input offset voltages is shown in Fig. offset voltage of an operational The former amplifier is composed of two components.? Z. Third.&. MOSoperationfl mpltiier. Assuming perfectly matched devices. thesec- ond stage voltage gain is A= 6 gi?? (3) “ I (J BIAS -+ Ml M2 --J++ — V. the voltage gain of the first stage of the circuit simply gm 1 Avl = g02 + shown in Fig. However. Schematic of basic two-stage CMOS operational tio-ri region is on the order of one fifth or less of the effective channel length at the typical drain bias of several volts. transistor bias currents and channel 1 M3 ‘ . DC Offsets.L * I. In MOS op amps. 4 can be shown to be (2) and go is the small and lf2 are go4 to force the amplifier and assuming that Ml output of IW6 which is required voltage to zero maybe different in these where gm is the device transconductance conductance.:.&. In order to achieve this level of gain per stage. have the same drain-source by technology scaling in the constant field sense since all terms in the expression decrease in proportion. 3 [4]. for example. devices which have received a channel implant to increase threshold voltage would display a higher open circuit gain than an unimplanted device whose channel doping was lower.

the I/gm ratio is equal to kT/q or 0.VT)/2. NO. bias current independent. in this case assumed to be resistors. SC-17. the result is typically a somewhat larger offset voltage than in the bipolar case [2]. This circuit has been anrdyzed by many authors [2] . a differential amplifier is made up of an identical pair of unilateral active devices biased at a current 1 and displaying a transconductance gm. of Fig. has high transconductance. Two-stage ampltler illustrating interstage coupling constraints. 7. the ratio is V at room temperature. the 100-500 a bias-dependent mV range. important differences arise because of the much lower transconductance of the MOS transistor relative to bipolar devices [7]. f144. and the ratios the for channel the widths. One mismatch component present in MOS devices which is not present in bipolar transistors is the mismatch in the threshold voltage itself. v ‘i f(v) ZI df(v) dv 1 = 9rn ‘x voltages results in 1 mV of input-referred that the current the simple form (W/L)3 (W/L)6 In order variations and kf6 provided use of with M3 and systematic offset. then in order for the output voltage of the differential amplifier to be zero. This component does not obey the above rewhich is and results in a constant offset component frequency loading. dc power it is likely particularly in the rejection ratio. . capacitive stantially improved by operating at low values of V&. 6.026 For MOS transistors. of ikf3. such as area mismatches in bipolar transistors and channel length and width mismatches in MOS transistors. the I/gm ratio also directly effects the slew rate for class A input stages. Thus. Conceptual circuit for calculation elements. Compensation. 6. 8(a) if the nondominant poles due to the capacitances at the source of Ml -2. This in turn requires that the dc input difference voltage applied to bring about this difference be Vg~ = ~ A. The reason for this is perhaps best understood intuitively by means of the conceptual circuit shown in Fig. so that ofteh transient performance requirements place a lower limit on the allowable value of this parameter. and can be substantially improved by the use of common centroid geometries. DECEMBER 1982 v+ ‘“+ + 1 M7 v- . Here. (Vg. this constraint would circuit take the Fig. Threshold mismatch is a strong function of process cleanliness and uniformity. best the requirements have response later) transconductance. The circuit can be approximately represented by the smallsignal equivalent circuit of Fig. if the bias reference amplifier source is such that the bias currents are not supply independent.972 IEEE JOURNAL OF SOLID-STATE CIRCUITS. The channel low devices that and for that M6 is at odds low for noise. Frequency Response. and can be Random Input Offset Voltage Source-coupled pairs of MOS transistors inherently display somewhat higher input offset voltage than bipolar pairs for the same level of geometric mismatch or process gradient. Published data indicate that large-geometry commoncentroid structures are capable of achieving threshold match distributions with standard deviations on the order of 2 mV in a silicon gate MOS process of current vintage [6] . If the load elements. quantity which is normally in While the offset voltage can be sub- in channel usually by identical M4 must properly length. lationship. are assumed to mismatch by a percentage A. For matched I= f(v) [’*I of random offset voltage. As discussed in a later section. the capacitance at the gate of M3. and any other nondominant poles which may exist on the circuit are neglected. 7. Systematic supply to display offset voltage is closely correlated offset supply with exists. 6. Power Dissipation The compensation Slew Rate. However. that = () 1 (W/L)5 (W/L). the input of the active (5) offset in this case depends on the I/gm ratio mismatch in the devices and the fractional of the two-stage CMOS amplifier carried out much as in the case of its bipolar equivalent using a pole-splitting capacitor CC as shown in Fig. 2. VOL. and M6 must be chosen so density in these three devices are equal. If a systematic on power a dependence voltage. [8] because it occurs so fre- . “ over process-induced lengths ~ (4) this ratio be maintained the channel selves. M4. be chosen choosing lengths (discussed under to be the same. g??? Thus. the W/L ratios of M3. the absolute difference in the currents in the two devices must be equal to AI. A similar dependence is found for mis- matches in many of the parameters of the active devices them_ (W/L)4 .(l#/L). vFig. For bipolar devices.

the transconductance of the second stage is normally much higher than the first because it is o~erated at relatively high current and the transconductance of the bipolar device is proportional to current level. pz. side of the compensation of the feedthrough similar pole locations capacitor. (7) rent from the first stage must flow principally (8) Note that the pole due to the capacitive loading of the first in the second stage transistor. the transconductances of the two stages tend to be simi- R2 (LARGE) Fig. Thus. 10. For low frequencies. Fortunately. which under the assumption two effective means have evolved for eliminatzero. is degraded. this voltage of value of the appears equal to second at is 1/gm2 of Fig. _— gm2cc gm 1 C2 cdl — (9) As expected. if a resistor stage. (a) Small-signal equivalent circuit for two-stage amplifier. voltage ing on the left the cancellation Using Fig. the problem is illustrated by considering the location of the second pole Pz and the right half-plane zero z relative to the unity-gain frequency gm ~/CC. the circuit displays a gain at high frequencies which is simply gm ~/gm2. the output p2 = C2CI+’C2CC +ccc. In bipolar technology. Analytically. in turn. the compensation is called pole splitting. gives rise to volt- age variation at the gate of the second stage which is proportional to the small-signal current from the first stage and inversely stage. has been pushed down to a very low by the Miller effect in the second stage. 8(b). In MOS amplifiers. can be shown to be approximately ing the effect of the right half-plane been to insert a source follower back through the compensation (6) agation of signals forward through the capacitor [7] . presenting a load to the first stage equal to 1/gm2. The circuit displays two poles that and a right half-plane located at -1 ‘1 =(1 +gm2R2)ccR. noise reasons. has been pushed to a very high frequency For this reason. (10) “ the zero vanishes when R= is made equal to z . An even simpler approach is to insert a nulling resistor in series with the compensation In this circuit. In fact. Here we make the simplifying assumption that the internal parasitic Cl is much smaller than either the compensation capacitor Cc or the load capacitance Cz. (b) SmaU-signal equivalent c~cuitwith C1 and C2setto zero. this circuit l?ehaves like an in“o tegrator. but at high frequencies. 9 [9] .— &7m2 L?ml cdl Note that the location of the right half-plane zero relative to l/gm~. This. resulting A unique problem arises when attempting to use pole splitting in MOS amplifiers. The movement of the zero for increasing values of RZ is illustrated in Fig. ‘47m2 Cc zero. This works well. one obtains circuit. 8(b).P2 an analysis to that performed which of for the circuit 8. although it requires more devices and dc bias current. the transconductance quently in bipolar amplifiers. the circuit inversion (a) on the ratio of the capacithrough path the zero arises because the compensation to the output at high frequencies. When this occurs. The polarity of this gain is opposite to that at low frequencies. andgainof the circuit versus frequency. One approach has in the path from the output capacitor to prevent the prop- the poles are widely spaced. This gives . directly stage by the second. the second stage behaves like a diode-connected transistor. the voltage appearin of the small-signal effect.8. capacitor as shown in Fig. in series with this resistor will to the transconductance 8. . stability tor provides a path for the signal to propagate directly Since there is no The locaby con- in that signal path as there is in the inverting at low frequencies. curas drain current note that at high frequencies. as illustrated in Fig. the inserted across proportional In the circuit However. understood dominant tion of the zero can best be conceptually + VI L ‘Ta ‘J2 4 gm2v2 — sidering a case in which Cl and C2 are zero as illustrated in Fig. turning any negative feedback that might be present around the amplifier into positive feedback. while the node of the second due to the technique pole due to the capacitance at the output shunt feedback. lar. output. 1 are close to those for the original and a zero location z= (11) co —-RZ ()gm2 1“ . the compensation cancel capacitor. frequency p ~. Physically. in part because the transconductance square root of the drain current. of the first stage must be kept reasonably varies only as the high for tkrnal Also. the resistor can be further increased to move the zero into the left half-plane to improve the amplifier phase margin [10] . the compensation capacitor behaves like a short circuit.GRAY AND MEYER: MOSOPAMP DESIGN–AN OVERVIEW 973 the unity-gain frequency is dependent transconductances of the two stages.

Noise Performance Because of the fact that MOS devices display relatively 1/f noise. SC-17. O zero a certain minimum gm in transistor i146 for a given bandwidth Fig. the CMOS op amp of Fig.J’T) input voltage for the input region. and input device transconductance SR=@ol gm where it has been assumed that gm. In this application. DECEMBER 1982 sampled data systems such as switched requirement time is that the amplifier to a certain accuracy with capacitor filters. the gate-referred equivalent portional analytical the (Vg~ . Small-signal equivalent circuit of the basic amplifier with resistor added in series with the compensation capacitor. inde- or precision applications pendent of bias conditions results are based and is inversely probut it should be em- transistors are operated at very low (V& . as illustrated in Fig. the input transistors contribute to the input noise directly. — COXWL () ~ (15) “ . Power Dissipation Even for the simple circuit of Fig. 8f K ~.e. as discussed later. Thus. ferential active The equivalent cdl. the slew rate improves.. Because this range is usu- ally substantially plifiers. Considerable discrepancy exists in the published data on 1/f noise. 4 input stage of (12) 1 sideration in MOS amplifiers. and load capacitor. this implies that the use of load capacitances of the same order as the compensation capacitance will tend to degrade the unity-gain phase margin because of the encroachment of this nondominant pole. 6. Perhaps the most widely accepted model for 1/f noise is that for a given device.f . circuits whose available output current is not greater than the quiescent bias current). usually dictates a certain minimum bias current in Jkf6 for a reasonable device size. contribute a nondominant pole. devices. (14) stage is undesirable for power V:qT’OT = V:ql + ‘:q2 + () ~ (K?q3 + J’%14 ) displays a relationship among slew rate. the factors determining the minimum power dissipation tend to be the fact that there Fig. then the same comment would apply to its bias current since its gm. the location of the nondominant pole due to capacitive loading on the output the unity-gain of the load frequency capacitance is determined to the second-stage transconductance node relative to by the ratio of the capacitance. Pole-zero diagram showing movement clf the transmission for various values of R=.VT). 2 In effect. 12. Thus. From (9). VOL. higher in MOS amplifiers usually than in bipolar amgood slew where the input MOS amplifiers In micropower display relatively mean-squared voltage noise is approximately in saturation. class A sec- can be charged in the must have suffidictates cjf the settling time The latter requirement /’x x I I +LRe \Rz. = gmz and that gm ~ = gm~. the noise performance is an important high design con- A second problem in compensation involves the effects of capacitive loading. sistor is shown in Fig. 10. and the use of an output dissipation and noise reasons. while the contribution of the loads is reduced by the to that of the in1/f noise of this inl the design can be square of the ratio of their transconductance put transistors. . The significance further appreciated where gm ~ is the input transistor transconductance. 11. bandwidth. This is of considerable practical significance in switched capacitor filters where large capacitive loads must be driven. the minimum achievable power dissipation is a complex functicm of the technology used and the particular requirements of the application. this gives (13) of the input which is kept stage is the range of difstage stays in the and this range constant l/f Noise input noise spectrum of a typical MOS tran- SR = (Vg. The following be the case. The dependence of the 1/f portion of the spectrum on device geometry and l)ias conditions has been studied by many authors [12] -[1 4]. to that of the first and the ratio compensation Since the stage transconductances tend to be similar. In phasized that the actual dependence must be verified for each process technology and device type [12]. together with the load capacitance. on this model. 9. The preceding discussion is predicted on the use of class A circuitry (i. This. however. [15]. rate. If the bandwidth is increased.VT). 4. in turn. All four transistors in the input stage contribute to the equivalent input noise.. bias current of the input quency of the amplifier. indicating that it arises from a mechanism that is strongly affected by details of device fabrication. Slew Rate As in its bipolar counterpart. NO. Quiescent power dissipation can be greatly reduced through tlhe use of dynamic circuits and class B circuits. and al ID ~ is the fre- by considering the input-referred thermal noise separately. If a class A source follower output stage is added. bias current. the be able to settle i~ a certain a capacitive load of several picofarads. By simply calculating the output noise for each circuit and equating them (1 1). nulling must be enough standing current in the amplifier ond stage such that the capacitance allowed time. is the unity-gain and the input-referred Input-Referred For the MOS case. this may not to the gate capacitance of the device.974 IEEE JOURNAL OF SOLID-STATE CIRCUITS. and the fact that the amplifier cient phase margin to avoid degradation due to ringing and overshoot.

amplifier is simply the ratio of (open loop) to to the output The PSRR of an operational noise. Thus. effectively shorting the drain of J46 to its gate for ac signals. v Z/&z pling of digital noise into the analog supplies. switching regulators are used which introduce power supply noise into the supply voltage lines. (a) Device noise contributions. if the operational amplifier is connected in a follower configuration and an ac signal is superimposed on one of the power supplies. as illustrated in Fig. ID (17b) Again. The basic circuit of Fig. it is hard to avoid some couA v:. A second reason ‘. that increasing the width — improve the 1/~ noise performance. and the second term is the increase in noise due to the loads.GRAY AND MEYER: MOS OP AMP DESIGN–AN OVERVIEW 975 v’ that of the input transistors by a factor of on the order of two or more.)(3 (16) strated that for frequencies less than the unity-gain frequency. Thermal Noise Perfoirnance -2 -2 & 2 ‘eq2 u m3 2 ‘eq. Typical IK IOK equivalent IOOK input IM IOM all system signal-to-noise ratio. the gain from the negative supply to the output where Kn and Kp are the flicker noise coefficients for the nDepending on channel and p-channel devices. ‘. The term in parentheses will be small if the W/L’s are chosen so that the transconductance the loads. 13. Power Supply Rejection Power supply rejection and Supply Capacitance ratio (PSRR) is a parameter of con- siderable importance in MOS amplifier design. they can be aliased down into the frequency band where the signal resides and degrade the overFreq. 11. Even though separate analog and digital supply buses are often run on chip. (b) Equiva- of the input If this condition by devices is much larger than that of is satisfied. then the input noise is of the input the transconductance determined transistors. and the term in parentheses represents the fractional increase in noise due to the loads. this gives ‘! V:q = 4kT 4 3 <2&CoX(W/L)l [+J-). The input transistors can then be made wide enough It is interesting to note of the channel in the loads does not to achieve the desired performance. Note that the multiplying term in front is the input noise of the input transistors. the signal appearing at the output is equal to the applied signal divided by the PSRR for that supply. Utilizing noise this assumption. If these high-frequency signals couple into the signal path in a sampled data system such as a switched capacitor filter or high-speed A/D converter. by a factor of two or more. the impedence of the compensation capacitor decreases. we obtain for the equivalent the voltage gain from the input that from the supply to the output. respectively. CMOS input stage. -. The primary reason is that as the applied frequency increases. —. I is that in many systems. %4 m! m2-J% The input-referred given by [8] V:q = 4kT () _ — thermal noise of an MOS transistor is — m4 ‘o v- A 3gm af.L ‘. 12. The parameters reflecting susceptibility to this phenomenon in the operational amplifier are the high-frequency input PSRR and the supply capacitance. (17a) (a) Utilizing the same approach as for the flicker noise. lent input noise. 4 is particularly poor in terms of its high-frequency rejection from the negative power supply. One reason for this is that in complex analog-digital systems. processing details. It is clear from this second term that the load contribution can be made small by simply making the channel lengths of the loads longer than . It can be easily demon- v:/f = WIL 1COX ‘K’(%:. the first term represents the thermal noise from the input transistors. Hz 100 Fig. these may be comparable or different. simply Fig. the analog circuitry must coexist on the same chip with large amounts of digital circuitry. MOS transistor.

M2 with current which in Ml. in a variety of applications. DECEMBER 1982 L PSRR + -1o’ 1-----A. 14 for a switched is connected variations by the ratio will to ap- system layout can produce undesired supply capacitance. important supply and they are discussed at high This between A second contribution path . [17] to coupling phenomenon one or input and the signal coupling frequency capacitance as a capacitive supplies ple. ZOR capacitor the pear supply filters four Since then the op amp input supply summing at the the power output to the supply effects voltage attenuated rejection can occur on Ml. but sup- IMPROVED PERFORMANCE The bipolar-derived amplifier discussed above is widely used can be quite Supply data analog at the present time. and vice versa. is the use of a supply-independent of body bias on Ml. the input vices. unity Several alleviate power supply itself power effect negative supply frequency at the unity-gain alternative of the operational amplifier architectures have evolved in a later between this problem. The result capacitor ways. (c) Gain from negative supply to output.976 IEEE JOURNAL OF SOLID-STATE CIRCUITS. variations applications age gain involving available from One large values of closed-loop the basic circuit to Use of a bias reference with put supply devices voltage will. the voltin Fig. can usually be overcome with careful layout. transistors by the use of cascode transistors. the is termed manifests both of the The fre- PSRR The remains quency. tive into This 2) supply If the op amp inputs voltage changes. This. The usual solu- Fig. integrator poor power sampled in Fig. then as the supply voltage changes. The resulting displacement current in Cg~ flows into the summing node. which section. M2 with supply voltage of the input transistors is If the substrate terminal approaches unity and stays there out to very high frequencies. results Variations on the Basic Two-Stage Amplifier Use of Cascodes for Improved Voltage Gain: shown of the input In precision gain. and capacitance in drain important ones are given below. utilized in commercial products in order to achieve performance which is superior to that available from the basic circuit in some respect. are grounded and the negacurrent change flows in voltin then a displacement of the resulting the summing is usually Variation node because age across the drain-gate eliminated of drain series with the drains capacitance of the input transistors. node. many alternative circuit approaches have been investigated and. In this section. Supply capacitance ~in a CMOS I I amplifier. tion to this problem reference. IV. for examdevices be n-channel deuse of fully differential fully alleviate the probto a supply. 3) Variation variations. In NMOS. on the basic circuit. the positive gain with to sup- tied to a supply or supply-related voltage. However.VT of the involtage. 4 may supply voltage. although with many variations. This will cause a be inadequate. f142 onto the summing node. 13. A second the substrate so that it [17] . the substrate bias changes. we first consider variations then alternative architectures. [10] . changes the threshold. (b) Gain from positive supply to output. the circuitry is probably the only way to lem since the substrate must be tied alternative is capacitive decoupling of does not follow 4) Interconnect high-frequency supply variations and the operational is illustrated amplifier leads. In CMOS operational amplifiers. displacement current to flow through the gate-source cabias pacitance of Ml. of the capacitance and other integrator capacitance. crossovers in the amplifier of this capacitance integrator. that in a p-well process. High-frequency PSRR of bipolarderived op amp. so that increasing approximately amplifier. (d) Positive and negative PSRR. (a) Gain from input to output. SC-17. i142 with negative 1) Variation ply voltage. in many cases. This layout and in the transistors. in switched in several circuits. ALTERNATIVE ARCHITECTUFW. with cause the ~g~ .RR-= *} {$+(J)} 11 Fig. NO. without adding approach improving the voltage stage with gain its to change supply an additional common-source . which changes V&. in turn. 14. VOL. (c) I PSRR —W PSRR+= {*} {:+(w)} [1 WIJ 4 L (d) u P. 6. The same phenomenon ply the to fall positive with frequency causes the gain from as the open-loop relatively PSRR flat falls does. in bias current in turn. the usual solution to this problem is to put the input the sources of the input transistors in a well and tie the well to This dictates.

An alternative M3 +- r M8 + M6 of two common-source use a cascade of a common-source utilizing this architecture stage and a common-gate An example of an am- ~– stage. or cascode. and gives a pole frequency approximately at the ft of these devices. 17.GRAY AND MEYER: MOS OP AMP DESIGN–AN OVERVIEW 977 (2 V7+2LV) B: k:’ . comes from the gm /Cg~ time constant of the n-channel cascode devices. the compensation capacitor and load capacitor The first nondominant stage. WH ‘-+T’TV++F”U TT! ~. resistance of The demoncurrent in the amplifier. assuming that the load capacitance or part of it is not tied to a power supply. 15. and noise [16] . random offset. the can be alleviated by optimizing V. then the capacitor not have to change whenever the negative supply voltage changed in order to have the output remain constant. from the differential nondominant A second nondominant pole results to single-ended converter. 17. Common-Gate Amplifiers a cascade approach is to ~7 cc M3A M? Common-Source J The basic amplifier considered thus far is actually stages. output age gain of this circuit at dc is approximately the same as that of the basic two-stage circuit. two-stage circuit. is not present in this circuit. reasons for considering this architecture are applied to the basic two-stage in either First. [21 ]. common-source cascode that to increase in Fig.. An additional current source and current sink of equal values must be added to bias the common-gate device in the active region and so as not to contribute any systematic offset. The principal twofold. if the left end of the capacitor nected to a virtual ground. k&A MA ~ 4 M4A M4 M2A The resulting negative PSRR at high frequencies is greatly improved at the cost of a slight increase in complexity.~ ~amplifier with AV= VGS-VT @ IR~r M2 TRIODE Fig. the output swing of this circuit amplifier. This circuit amplifier The circuit stage. Because of the fact that cascode transistors are used at the output. M=HM6 ~ of basic cascode feedback compen- Fig. in the first One disad- reduction in input pole. of the cascodes. The small-signal impedance at the output node is increased by gmro relative to the output node of the two-stage circuit. pole due to the load capacitance present in the Read and Wieser [18] have recently described a technique for could be convoltage would the negative supply PSRR of the circuit Conceptually. stage (19a) gm4r04 the cascode transistor.oTH/ -& TRIODE Cascode current source. second of this mode stage. 16 illustrates vantage common the biasing the use of cascodes circuit range. or in both is a substantial but this are the same element in this circuit. However. The displacement current from the capacitor flows into the source of this transistor and out the drain into the compensation point. The volt- associated the basic strated high impedence transistor node and pole is to add a commonthe output basic 15. An important advantage of this circuit is that it does not suffer from the degradation of the high-frequency power supply rejection problem inherent in the pole-split compensated twostage architecture. of this gate. 4. and the voltage gain is simply the product of the transconductance of the input transistors and the impedance at the output mode: Au= gm go2 + &709 1 + go7 gm5r05 “ transistors is shown incremented circuit the It is easily resistance source is equal to /-0 = ro~ [1 +gm2r01] The output open circuit directly first resistance gain d +ro~. this circuit is capable of achieving higher stable closed-loop bandwidth with large capacitive load. often called a cascode amplifier. as shown in Fig. This was accomplished by inserting a cascode device in this loop with the gate connected to ground. Two-stage amplifier with cascoded fiist stage. Schematic Fig. 18. The principal application of this architecture to date has been in high-frequency switched capacitor filters [20]. plifier is shown in Fig. is increased by an amount equal (18) to the maybe the of Fig. Thus. stages. to be discussed in Section Improved improving PSRR Grounded-Gate Cascode Compensation: of Fig. is lower than the can common-source common-source This problem . 16.

Such amplifiers are fully dynamic in the sense that no dc paths and produced class Many.M1 M2 ~ –v.0 second stage. as in the case of than the quiescent the common-source common-source amplifier. MOS transistors actually display a rather indistinct transition from triode to saturation as the drain depletion region forms. DECEMBER 1982 -i T“-!? —“+-. sources M9 and Ml O contribute an However.. Thus. the equivalent input noise can be made almost equivalent to the noise of the input transistors alone by choosing the channel lengths of the input transistors to be short compared to those of M5. The most widespread application is in output buffers. A second class of amplifiers has been explored by several authors. then the philosophy of using class AB operation vation value of can be extended for doing the quiescent to the internal current with amplifiers. [25] have recently described a novel approach to the same objective.4 to 0. 19. % ~ I P !“ v+ I 1 I I T I I L 1 IA’’” L— l% I L“9 __:fiB’A’ v- Fig. the circuit does not display slew rate limiting in the usual sense. but an auxiliary circuit is used to detect the presence of large differential signals at the input.–+ J. An example of an amplifier utilizing a class A first stage and a class AB second stage is shown in Fig. if not all. The bias current in the class A circuitry is then increased when such signals are present. Upon the application of a voltage to the input. 6. SC-17. This particular used in the inverting mode only. M9. 19 [22] . 18. tively rare that the operational to change the maximum amount the edge of saturation in one clock cycle.. Dynamic Biasing utilize Dynamic Amplifiers. M6. Another aspect of this circuit is the fact that the small-signal voltage gain in the quiescent mode can be quite high because of the low current level. Degrauwe et al. the current additional term not present in (16).VT) of each supply. Assuming that transistors Lf5-lf8 current as the input can be shown to be ciple is shown in Fig. In fact. and the fact that the voltage gain falls off during transients because of the high current levels is of little consequence. value of current be minimized by modifying the bias generator such that the source are biased on This results in an availlower transistors in the cascode current (i. the of this circuit in M2 increases above its quiescent dc value. One-stage amplifier schematic.e. MOS analog circuits commercially class AB circuitry in some form. NO. and as a result. The same considerations noise. able output voltage swing within 2(Vg~ . VOL. swings positive.. Here the term AB is taken to mean a circuit which can source and sink current from a load which is larger than the dc quiescent current flowing in the circuit.— r . and the circuit. 20 [23] . In a conventional circuit.. in which the quiescent current in the absence of signals is allowed to decay to zero. the current in one side of the input stage increases monotonically with the applied voltage until the power supply is reached. A conventional class A amplifier configuration is used. Class AB Amplifiers. Example circuit illustrating class. and Ml O. while the other side of the input stage turns off. that an MOS The motidictates the is the so is that one of the factors amplifier . Vgd = VT). the bias point must actually be chosen so as to bias the lower transistor a few hundred millivolts output into saturation if the predicted value of incremental A second disadvantage contribute resistance is to be obtained. is much larger as a result. the gate of M2 would be connected to a level-shifted the current example version of the stage input voltage.8 V in voiceband filters. when the An first stage output reducing the current in Ml. apply for the thermal not follow the relationship of (12). does The amount of current available at the output current. beginning with Copeland [26] . (19b) bias voltages shown..978 IEEE JOURNAL OF SOLID-STATE CIRCUITS. but if an important objective is the minimization of chip power. quiescent current in the input devices.. required to charge the load and/or the comHowever. to the input-referred voltage and input of a single-stage amplifier age. -6’A’ M5 ‘8 F “ l. it is relaLarge amplifier outputs actually have pensation capacitance in the required time. or perhaps 0. Similar circuits have been used extensively in bipolar technology [24] . is that more devices offset voltflicker noise are biased at the same power savings can be effected if only that current is drawn which is required to charge the capacitance on that particular cycle. that operates on this princircuit can be by the With the input grounded. the input-referred transistors is determined “q=%[’+%wwl% In this case. Experimental versions of such amplifiers have yielded quiescent power dissipation of less than 10 vW. Fig.

1 -. Examples of a single-stage class . A typical implementation of a differential switched capacitor integrator is shown in Fig. -’.‘ -. An equivalent circuit for a differential op An important problem in such amplifiers is the design of a feedback loop to force the common mode output voltage to be ground or some other internal reference potential. while the magnitude of the input-referred operational amplifier noise remains the same.-. supply rejection $ “+. one-stage it can be implemented good amplifiers and two-stage relatively . Also. output operational amplifier An example of a CMOS differential is shown in Fig. -. but presents a difficult common-mode output voltage independent of thp differential mode signal voltage [21 ] . period for and is made large during fast slewing and small of the clock portion for high gain and power is generated mirror. 22. 21.4~ op amp. Example of a differential output amplifier. >. DIFFERENTIAL As has been mentioned. Switched capacitor circuitry can make use of the linearity of MOS capacitors to achieve this goal [30]. giving a 6 dB improvement in operational amplifier noise-limited dynamic range. p. -J -.’ . While difficult remain very low valproblems of ues of power settling with time dissipation and power can be obtained. with an accompanying amp is shown in Fig. [29]. 21. power approach to micropower which uti- circuit Hostica amplifier lizes nous with proaches pendent part later put for a differential amplitler. [30] ... -. -. The bias current into the inin principle. power than by discharging While the this other savings. one inevitable result scaling is a reduction in power supply voltage reduction in internal signal swings and make use of fully These two considerations Fig. This feedback path can be implemented with transistors in a continuous-time circuit capacitor circuitry. -“ ~. \ 1 I .. 23... power supply rejection is an imporfor amplifiers to be used in comp- parameter systems. for both conditions.. .. The choice between the two techniques depends on the sensitivity of the particular application to variations in common-mode voltage. . + /’ . Equivalent STANDARD SIPJ6LE -ENDED OP AMPS these amplifiers. or can be implemented with switched The continuous approach is potentially design problem in making the simpler. differential signal paths throughout the analog portions of the system attractive for some systems [29] . 22. simple results and it has demonstrated experimental [28] n. approaches with of a current more dissipates signal circuitry. .$’ BIAS M8 M7 Ml M2 h M3 M4 BIAS L BIA s MIO — M9 V.. The operational amplifier is required to produce two analog outputs which are symmetric about ground. Differential switched capacitor integrator. 23. tant performance lex analog/digital of technology dynamic range.GRAY AND MEYER : MOS OP AMP DESIGN–AN OVERVIEW 979 -Vo+ ~o IN Fig. OUTPUT AMPLIFIERS ~- cMFB L. The block labeled ClfFB serves to keep the common-mode output voltage near ground. The inherently differential nature of the circuit tends to give very high PSRR since the supply variations appear as a common mode signal. [27] design has described for switched periodic clock above. the effective output swing is doubled. output operational applications which In contrast supply current a time-varying the master described current is synchroto the apis indethe early during the { of signal amplitude. . In addition. ‘. under low waveform a capacitor technique.’ ‘ to be solved Fig. 20. in contrast to the single-ended case where only one is produced.. + exist for current to flow from the supply. the a third capacitor bias in the filter. R R nD’Fig.../ / 1= ‘/’ .> .

23. techniques tracking used level to aspects. NO. In many CMOS technologies. and such that the output of the operational amis able to supply or emitter a large follower enough voltage swing to the load with the maximum ductance. 24.VT) drop is too large for many applica- filters. 27. The key requirements on such stages is that they be sufficiently broad band with heavy capacitive loading such that they do not degrade the loop stability plifier. This provides very low output resistance and good output swing. a bipolar transistor follower is available and can be used in place of one of the output followers. 22. positive . depending on what devices are available in the particular technology shifters [9] . larly circuit for the circuit in Fig. potential latchup problems can make the use of such devices in offchip driver stages impractical because of the fact that the collector current cause voltage biased. The cific devices available in the particular simple common-source This circuit well suited capacitor filters common-gate Thus the has only one nondominant device. have an extra device type and in this case. rejection CMOS considerations amplifier. in the widespread some applications. technology for new mixed the emergence has resulted analog-digital as a key digital of CMOS VII. The combination of the error amplifier and the commonsource device mimics the behavior of a follower with high dc transconductance. many technologies very low threshold voltage. devices Assuming trated transient ply in which The makes that Fig. so that the amount of swing lost due to threshold vohage plus the (Vg~ . DECEMBER 1982 ~+ T plifier to prevent the load from degrading the voltage gain or stability. effects load are basically additional stage The key considerations conductance impedance the shunting the depletion supply and ratio. class All CMOS output stage implementations tend to vary widely. In processes with light substrate doping. sipation considerations tion of the circuit. The primary drawback of this circuit is that the output voltage swing is limited by the gate-source voltage of the output transistors. output of the transistor drops which flows in the substrate and can to be forward device in an MOS device is illustrated cause a junction level of body the 2(c). the complementary emitter follower class AB configuration is used in the vast majority of cases. will configurations rejection no doubt be a need for NMOS of CMOS designs. has resulted amplifiers amplifiers in most performance more complexity. of the incremental current of sources the output and the An example of the use of a bipolar stage together with a low threshold power sources tion NMOS variation the resulting which floating circuit match level-shifting of power design CMOS supply degradation creative nearly Nonetheless. suptwoare of and voltage rejecin It is rare that both p-channel and n-channel low thresh- supply variations old devices are available in the same technology. This circuit is shown conceptually in Fig. been used in recently reported high-Q switched clocked center frequencies [21 ] . and quasi-complementary devices can be used in any combination. with tors. this low transis- technology is a much of task than device track technology. Circuit achieve this include replica biasing for in Fig. This situation most often arises when closed-loop signals must be supplied off the chip to an external environment. noise. similar depletion to that voltage and power to the the realization of large gains per stage difficult. VOL. load con- While class A source follower circuits can be used in some applications. for example. feedback for for high power ampliadop- voltage supply While fiers VLSI tion for gain there [31 ] . pole.5-1 V range. bipolar devices. as shown in Fig. they present difficult problems in compensation of the local feedback loop in the presence of large capacitive loads. 250 kHz in a 4 pm silicon VI. the The absence threshold device can be used for one of the two output a complementary shifters plex. In amplifier applications resistive load. but since the amplifier must be broad band to prevent crossover distortion problems. However. is a cascade. 6. SC-17.IEEE JOURNAL OF SOLID-STATE CIRCUITS. [30] [29 ]. This occurs because the transistors used for logic functions on the chip have thresholds in the 0. to the implementation A configuration work yielding with at 4 MHz of the common-gate switched capacitor configuration is particu- CMOS complementary source follower class Al? output buffer stage shown in Fig. Fig. depending technology on the speused. A third alternative is the use of quasi-complementary configurations in which a common-source transistor together with an error amplifier is used in place of one or both of the follower devices. Such quasi-complementary circuits provide excellent dc performance with voltage swings approaching the supply rails. an output OUTPUT BUFFERS involving either a large capacitive or stage must be added to the basic am- . and power dissipation. always and others. implementation much of level more comload illusgain. 25 is a direct analog of its bipolar counterpart. Proper control of the quiescent current is also a key design constraint. The mance more design level difficult NMOS of in gate CMOS technology AMPLIFIERS OPERATIONAL an operational NMOS depletion in CMOS makes voltage effect amplifier load of a given perfor- tions. differential [30]. put buffers. [17] . at theft of of high-frequency this type has of In bipolar operational amplifier design. In contrast. Low threshold devices. quiescent power disto class Al? out- usually dictate a class AB implementa- This discussion is limited Another important advantage of differential output ampli- fiers is that the differential single-ended converter with its associated nondominant poles is eliminated. architecture small-signal input response and slew rate. Small-signal differential half circuit for the amplifier in Fig. The small-signal equivalent 24. 26. basic the found in most is similar properties. albeit at the cost of somewhat die area.

1974. Hodges. Gray and R. J. are important REFERENCES [1] D. Black and D. and E. IEEE Dec. pp. is the kT/C noise contributed the analog switches making dynamic range also falls as the technology is scaled. 1978. mance New Yor~: Wiley. “Low ter: IEEE J. “The monolithic Qp amp. pp.” IEEE J. 27’. “Basic MOS operational amplifier design-An view. and D. R. 1981. and the removal of 1/f noise from path in such circuits. P. R. but this does not appear to be a fundamental the signal newer in 1/f limitation on system dynamic range portion zation tinuing because [29] can always using technologies be translated like to a higher stabilicon- v+ of the spectrum .GRAY AND MEYER: MOSOP AMP DESIGN–AN OVERVIEW 981 design of MOS operational An important amplifiers in the past several years. Analysis and Design of Analog Inte- complementary class 13 emitter grated Circuits. 748-753. “An integrated NMOS operational amplifier with internrd compensation. pp. A. Tsividis and P. there appears to be no I barrier to constant-field scaling of operational amplifiers for this application. June 1978. J. G. Solid-state Cir. dc parameters for constant-field designs can be scaled as minimum crease. Jr. SC-9. In this techniques paper. and P. R. 1979. Tsividis. A. pp. vol. R. Dec. assuming that 1/f noise is removed by circuit or technological means. and since for practical clock rates and capacitor sizes this noise source is dominant Fig. fol- over op amp thermal noise. pp. D. 1980. Kramer. J. Whereas inthebipolar case thevast majority of [8] [9] stage applications has yet emerged can be satisfied follower as the standard using the traditional stage. Dec.’ IEEE J. “MOS overIEEE the signal objectives in future work. 1976. 929-938. in Analog MOS Integrated Circuits. pp. June 1978. C. The input-referred 1/f noise increases. R. “A low-voltage BiMOS OP amp. Gray. Example ofa CMOS output stage using abipolar emitter lower and a low-threshold p-channel source follower. W. 383391. no single circuit for CMOS output also O. and SUMMARY AND CONCLUSIONS to summarize have been the various applied in the [11] used. the primary limitation filters and data convertrange. cuits. and R. VIII. capacitor fiiters~ 0. J. 1977. 61-75. 314-332. 28-49. SolidMOS technologies for analog integrated circuits: State Circuits. Shade. vol. Hodges. See J. Gray. IEEE. New York: Press. Solid-State Jr. vol. “Potential of IEEE J. D. Solid-State Circuits. P. J. to de- question is the extent to which these amplifier feature sizes continue out in a recent study [32] . Thus. pp. SC-11. Dec. pp. 285-293. Meyer. Solid-State Circuits. 1978. 791-798. SC-13. Fig. Hodges. “A high-perfor- NMOS operational amplifier’ IEEE cuits. Dec. vol. “Design considerations in single-channel MOS analog circuits-A tutorial. circuits. 1/f noise has been removed. W. “BiMOS micropower integrated CYrcuits. although they are degraded for quasi-constant voltage or constant voltage scaling. Solid-State Cir- [10] W. E. P. pp. Input-referred thermal noise remains constant Fig.” IEEE J. Bertails. Jan. pp. Dec. H. 1980. 25. 661-668. Example of a complementary classll output stage using cornpound devices with imbedded common-source output transistors. Broderson. R. A tutorial studyy IEEE J. Senderowicz. for MOS am- we have attempted architectures which noise considerations . Schade.. Allstott. Perhaps the most difficult problem results from the fact that the effective dynamic range of the amplifier falls in scaled technologies. P. Solid-State Circuits. ‘In sampled data analog amplifiers. P. This occurs fundamentally because of the fact that analog signal swings fall with reductions in power supply voltage. [2] ~1 — ‘$” > V’1 [3] [4] [5] [6] I “- switched Proc. SC-13. P. Broderson. Y. Gray. techniques chopper have demonstrated reductions noise as a result of better process / control. A. vol. Solid-State Circuits. H. [7] being output approach stages. Gray. R. ers. SC-16. C. assuming that by The kT/C limited on dynamic up the filter. As pointed such as voltage gain are generally unaffected scaling. 760-768. Also. the adaptation of the circuit approaches described in this paper to lower supply voltages and scaled devices. Gray. stage basedon because of the fact that the device transconductance remains constant under constant-field scaling. 26. Complementary source follower CMOS output the traditional bipolar implementation. “Low frequency power CMOS channel filSC-15. vol. Y. Solomon.

“A precision low power PCM channel filter with on-chip power supply regnlation~’ IEEE J. June 1982. pp. . Aug. De Man. A. Rabaey. Choi. San Francisco. Feb. 1974. 188-189. pp. in 1963. 1982 Int. Philadelphia. W. 697-603. Gray (S’56-M’69-SM76 -F’8 1). He has been a consultant to Hewlett-Packard.” IEEE J. and biogra- [25] [26] [27] [28] [29] 506. M. Tech. Additional gate MOS transis[33] References on MOS Operational Amplifiers [14] [15] tor” IEEE Trans. 499D. Solid-State Circuits. K. SC-14. D. J. University of California. vol.. Tech. vol. 1979. Vittoz and J. 1070-1076. Hoefflinger. R. E. Feb. “Measurements and interpretation of low-frequency noise in FET’sj” IEEE Trans. pp. pp. Hosticka. Moore. T. pp. [20] 327. pp. Circuits Syst. pp. Guinea and D. 1979. SC-14.” Technology. shiro. A. Rahhn. pp.” in Dig. Dec.’ IEEE J. Electron Devices. H. H. Pandel. and W. Solid-State Circuits. B. S. May 1974. pp. SC-17. E. R. Papers. Tsividis and D. R. S. Hsieh. F. Dec. D. Jacobs. Schweer. 1965. CA. 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