Institute of of Energy Technology Institute Electronic Systems

Fredrik Bajers Vej 7 A1 9220 Aalborg Ø Denmark http://ies.aau.dk

Faculty of Engineering and Science

Title:

Low cost camera for CubeSats 
a feasibility study

Synopsis:

Theme:

Microcomputer systems

Project period:

E4, spring semester 2006

Project group:
418

Loss Balancing in a Three Level Active Neutral Point Clamped Converter

Group members:

Simon Just Kjeldgaard Pedersen Morten Burchard Tychsen Morten Egelund Jensen Jens Martin Oddershede

Supervisor:

Rasmus Abildgren

Number printed:
7

Number of pages:

Report: 95 Appendicies: 42 Total: 137

Finished:

This project concerns the development of a camera system for taking a picture of Earth from a CubeSat. Based on a market survey, a suitable image sensor complying with the requirements for operation in space is chosen. For testing purposes, a lens is chosen, but a comprehensive market survey should be made to select a lens suitable for operation in space. The functionality of the camera system is analyzed using UML use cases. The use cases obtained are take picture, generate thumbnail, and self test. In order to test the camera system, a test system is constructed, based on the Motorola 68000. The test system runs the TS2MON debugger/monitor and communicates with a PC over a RS232 connection. This forms a platform for designing the interfaces needed for the camera. Hardware and software design of the camera system is modulated by using the use cases and the Rugby metamodel. The hardware and software of the test system works as designed, but it has not been possible to take a picture. It is possible to communicate with the camera, but the resulting data does not resemble a picture. This is possibly due to misconguration of the camera. During software integration, faulty memory reads have occurred, which are believed to be EMC related, due to the long buses. Both of these problems are not investigated further, which should be done before the camera can be used on board a CubeSat.

29th May 2006

- 2010 -

Title: Semester: Semester theme: Project period: ECTS: Supervisor: Project group:

Loss Balancing in a Three Level Active Neutral Point Clamped Converter 8 Control in converter-fed AC drives 15.02.2010 - 26.05.2010 26 Andrzej Adamczyk 840

SYNOPSIS
An unbalanced distribution of the semiconductor power losses amongst the switches of a converter will limit its switching frequency and output power. Hence, for the Neutral Point Clamped (NPC) topology, which is widely used in medium voltage, high power drives, this issue represents a major disadvantage. In order to overcome this drawback, the NPC can be replaced by the Active Neutral Point Clamped (ANPC) topology. This report investigates different modulations strategies which can be used for controlling the ANPC converter in order to balance the power losses amongst the semiconductor devices. Several strategies, which use the active neutral point clamping switches are presented and analysed through simulations and experimental tests. The obtained results confirm that by taking advantage of the flexibility provided by ANPC topology, a major improvement in the losses distribution can be brought.

Catalin Dincan

Cam Pham

Claudia Georgiana Cojocaru

Marco Guarrera

Copies: Pages: Appendices: Supplements:

2 85 4 1 CD

By signing this document, each member of the group confirms that all participated in the project work and thereby all members are collectively liable for the content of the report.

hj effekt driver. som er anvendt i stor udstrkning i mellemspnding.26.Title: Semester: Semester theme: Project period: ECTS: Supervisor: Project group: Jvn fordeling af tab i en three-level ANPC 8 Styring af konverter til at forsyne AC driver 15. forbedring af tabene fordeling kan hentes.2010 . De opnet resultater bekrfter. ved at udnytte fleksibilitet givet af ANPC topologi. For at kunne lse denne ulempe. for Neutral Point Clamped (NPC) topologi. at alle har deltaget ligeligt i projektarbejdet og at alle er kollektivt ansvarlige for rapportens indhold.2010 26 Andrzej Adamczyk 840 SYNOPSIS En ujvn fordeling af effekt tabene imellem konverterens kontaktorer vil begrnse dens switchs frekvens og udgangseffekt. . denne problemstilling er hovedsagelig den vigtigste ulempe. Denne rapport undersges hvilken modulation principper som kan bruges til at styre ANPC konverteren med henblik i jvn fordeling af effekt tab imellem halvleder komponenter.05. Catalin Dincan Cam Pham Claudia Georgiana Cojocaru Marco Guarrera Oplag: Antal sider: Appendiks: Bilag: 2 85 4 1 CD Ved at underskrive dette dokument bekrfter hvert enkelt gruppemedlem. Flere principper som bruges af ANPC kontaktorer er fremlagt og analyseret gennem simulering og eksperimenter. NPC kan erstattes med den Aktiv Neutral Point Clamped (ANPC) topologi.02. Deraf.

.

Number and Table Chapter. The literature references are shown in square brackets by numbers. in order to ensure loss equalization amongst the semiconductor switches. Appendices are assigned with letters. setting the main objectives and limitations. In chapter three.Number. Chapter two provides information about the theoretical concepts which are used throughout the report. The aim of the project was to study different modulation strategies for a three level Active Neutral Point Clamped (ANPC) inverter. The list of the references is presented in the chapter Bibliography. The project was prepared between the 15th of February and the 26th of May 2010. The first chapter gives a brief presentation of the background an motivation for this project. The contents of the enclosed CD are listed in Appendix D. 26th of May 2010 . In chapter four experimental are performed in order verify if loss balancing is achieved. and arranged in alphabetical order at the end of the report. from the point of view of losses distribution amongst the switches. The report is structured into five chapters. Figures and tables are numbered in the following format: Figure Chapter. by the 8th semester group 840.Preface This report represents the documentation of the project entitled Loss Balancing in a Three Level Active Neutral Point Clamped Converter. Matlab Simulink simulations are performed in order to study how the ANPC inverter behaves for different modulation strategies. at Aalborg University Institute of Energy Technology. The final chapter presents the conclusions of the report and future work.

.

. . . . . . . . . . . . . .2. . . . . . . . 35 37 3 Simulations 3. . . . . . . . . . . . .1 3. . . . . . . . . . . 43 Results for validation in the laboratory . . . . . . . . . .3 Basics on three level converters . . . . . . . . . . . . . . . . . . . 18 Project limitations . . .2. . . . . . . . . . . . . .2.2 System description . . . . . . . . . . . . . . . . . . .5 3. . . . . . . . . . . . . . . . . . . . . .3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 19 2 Basics on converter losses and the ANPC topology 2. . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PWM-3 . . . . . . . . . . .2 3. . . . . . . . .2 17 Background and motivation . .2 2. . . . . . . . . . . . . . . . 24 2. . . . . . .2. . . . . . . 20 Diode losses . . . . . . . .2. . . 39 PWM-1 .2 Project objectives . . . . . . . . . . . . . . . . 39 PWM-2 . . . . 37 Simulation results 3. . . . . . . . . . . . . . . . . . . .3 IGBT conduction losses . . 21 2. .6 . . . . . . . . . . . . . . . . . . . . . .3 Summary . . . . . . . . . . . . 23 Modulation strategies . . . . . . . . . . . . . . . . . . . 44 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . .1. . .1 3. . .4 3. . . .1 IGBT and diode power losses . . . . . . . . . . . . . . . . . . . . . . . . 19 2. . . . . 21 ANPC topology . . . 42 PWM-ALD . . . . . . . . . . . . . .1. 19 IGBT switching losses . . . . . . . 46 5 .2. . . . . . . . . . . .1. . . . . . . . . . . . . . . . 18 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . . . . . . . . . . . . .1 1. . . . . . .2. . . . . . . .2 2. . . . . . . . . . .3 3. 41 PWM-DF . . . . . . . . . . . 20 . .1 2.1 2. . . . . . . . . . .2. . . .2 The Active Neutral Point Clamped topology 2. 17 Problem formulation . . . . . . . . . . . . . . .1 1. . . . .2.Contents 1 Introduction 1.

. . . . . . . 52 Experimental results . . . . . . 53 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 65 5 Conclusions 5.1 4. . . . . . . . . . .2 Review of the main tasks . . .1. 49 4. . . . 53 RL load . . . . . . . 51 Interface board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 69 71 77 79 81 Bibliography A Heat sink selection B Extension interface board C List of used laboratory instruments D Contents of the enclosed CD 6 . . . . . . . . . . . . . . . . . .1. . . . . . 51 4. . . . . . . . . .1 5. . . . . . 50 DSP board . . . . . . . . .1 49 Test setup .3 Modulation implementation on the DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4. . . . . . . . . . . . . . . . . . . . . . . .4 Summary . . .2 4. . .1 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . .1. . . . . . . . . . . . .3 ANPC converter . . . . . . . . . . . . . . . . . . . . . . .2 R load . . . . 65 Future work . . . . . . . . .3. . .4 Laboratory implementation 4. . . . . . . . . . . . . . . .2 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . .8 2. . . . . . . . Because the frequency of the carrier waves is much higher than that of the reference signal. . . . . . .1 2. . . . . . . . . . 37 The PLECS block diagram of the plant . . . . . . . . . . . . . . . .7 2. . .S4 and S6 are on. . .13 PWM generation for PWM-ALD modulation strategy for 50%-50% Stress In/Stress Out ratio . . . . . . . . . . . . . . . . . . . . . . 31 2. . . . . . . . . . . . . . (b) N . . . . .5 2. . . . during one period of the carrier wave.11 PWM generation for the PWM-DF strategy . . . . . . . . 26 The switching sequences and output voltage for the 3L-ANPC PWM-1 strategy. . . . .S4 and S5 are on. . . .6 2. . 38 7 . . . . . . . . . . . . Because the frequency of the carrier waves is much higher than that of the reference signal. . . . . . .2 The general block diagram of the simulation models . . . . . . . . . . . . . . during one period of the carrier wave. . . . .S1 and S3 are on. . . . . . 23 Switching states for the single-phase three-level ANPC converter: (a) P S1 and S3 are on. .12 The switching sequences and output voltage for the 3L-ANPC PWM-DF strategy . (c) OU . . . . . . . 26 The switching sequences and output voltage for the PWM-NPC strategy. . . . . . . . .S2 and S3 are on. . . . . . . .14 The switching sequences and output voltage for the 3L-ANPC PWM-ALD strategy . . .S4 and S6 are on. . . . . . . . . . 30 2. . . the reference can be considered to be constant. . . 31 2. .9 2. . . . . . .3 2. . . . . . . . . .1 3. . . . . . . . . . . . . . . . . . . . . . . . . .2 2. . . 28 PWM generation for the PWM-3 strategy . . . . (b) OD . . . . . . . . .1 2. . . . . . 29 2. . . . . . . . . . . . 27 The switching sequences and output voltage for the 3L-ANPC PWM-2 strategy . . . .4 Single-phase three-level NPC (a) and ANPC (b) voltage source converters . . . . . . . . the reference can be considered to be constant. . . . . . . . . . . . . . . 22 Single-phase ANPC voltage source converter . . . . . . . . . .10 Switching signals for the ANPC inverter switches with PWM-3 modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .S3 and S4 are on . . . . (c) O . . 33 2. . 21 Switching states for the single-phase three-level NPC converter: (a) P . . . . . . . . . 34 3. . . . . . . . . . . . . . . . . . . . . 24 PWM generation for the PWM-NPC strategy . 17 Single-phase two-level half bridge (HB) (a) and three-level Neutral Point Clamped (NPC) (b) voltage source converters . . . .List of Figures 1. . . . . . . (b) N . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . .24 V. . .8 The Simulink block diagram of the losses calculation block . . . . . . . . . . . .11 Thermal picture of the ANPC inverter with RL load for PWM-3 modulation strategy . . . . . . . . . . . . . . . . . . 50 Simulink model used for DSP implementation . . . . . . . . . . . . . . . .3 3. 55 Thermal picture of the ANPC inverter with R load for PWM-3 modulation strategy . . . . . . . . 59 4. . . . . . . . . . . . . . . . . . . . 41 Power losses distribution for PWM-3 modulation strategy with a 50%-50% PWM-1/PWM-2 ratio and a 10 kW load (PF = 1) . . . . . 44 Block diagram of the experimental test setup . . . . . . . . . . . . . . . . . . . . . . .5 4. . . . . (11)PC . . (9). . . . .2 4. . . . . .7 4. . . . . . . . . . . . . . .10 Thermal picture of the ANPC inverter with RL load for PWM-2 modulation strategy . . 60 4. . . . . . . . . . . . . . . 57 Thermal picture of the ANPC inverter with R load for PWM-ALD modulation strategy . . . . . . . . . . . (5)load inductor. .8 4. . . 49 Laboratory test setup: (1). . . . . . . . . .9 4. . (4). . . . . . . . . . . .85) with PWM-1 modulation strategy . . . . . . . . . . . . . .85) with PWM-2 modulation strategy . . . . . . . . . . . . . . .5 3. . 5 A DC power supply. . . . (7). . . . . . . . . . . .13 Thermal picture of the ANPC inverter with RL load for PWM-ALD modulation strategy . (6). . . . 42 Power losses distribution for PWM-DF modulation strategy with a 10 kW load (PF = 1) . . . . . . . . . . . . . (8)TMS320F28335 eZdsp board. . . . . . . . . . . . . . . . . . . . . . 62 8 . . . . . . . . . . .14 The waveform of the output voltage (measured on the resistor) for RL load (PF =0. . . . . . .6 3.single-phase power analyser. . . . . . . . . . . . . . . . . . . . . .3 4. . . . . . . . . . 60 4. .12 Thermal picture of the ANPC inverter with RL load for PWM-DF modulation strategy . . .single-phase ANPC converter. . . . 59 4. . . . .1 4. . . . . . . . .interface board. . . . .oscilloscope. . . . .7 3. . . . 3 A DC power supply. . . . . . . .85) . . . . . . . . . . . . . . . . . . .load resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power losses distribution for PWM-1 modulation strategy with a 10 kW load (PF = 1) . . . . . . . . . . . .4 4. . . . .3. . . . . . . . . . . 62 4. . 40 Power losses distribution for PWM-2 modulation strategy with a 10 kW load (PF = 1) . . . . .thermal camera. . . . . . . . . . . .6 4. . . . . . . . . 58 Thermal picture of the ANPC inverter with RL load for PWM-1 modulation strategy . . . . . . . . . . . . . . . . . . . . . . . . . .300 V. . . . . . . . . . . 52 Thermal picture of the ANPC inverter with R load for PWM-1 modulation strategy . . . . . . . . (3). . . . . . . . . . . . . . . . . (2). . . . . . . . . . . . 43 Power losses distribution for PWM-ALD modulation strategy with a 50%50% Stress In/Stress Out ratio and a 10 kW RL load (PF = 0. . . . . . . . . . 56 Thermal picture of the ANPC inverter with R load for PWM-DF modulation strategy . .15 The waveform of the output voltage (measured on the resistor) for RL load (PF =0. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3. . . . . . . . 54 Thermal picture of the ANPC inverter with R load for PWM-2 modulation strategy . . . . (10). . . . . . . 61 4. . . . . . . . . .

. . . . . . .85) with PWM-3 modulation strategy . . . . . Rha is heat sink-to-ambient resistance [o C/W ] . . . 76 B. . . . . . .case-to-heat sink resistance [o C/W ]. . . . . 77 B.5 Matlab Simulink simulation model for heat sink calculation .4 Matlab Simulink simulation model for heat sink calculation . . 73 A. . .3 Equivalent electrical model for a semiconductor device.temperature of the heat sink [o C ]. . . . . . .temperature of the case [o C ]. . . Th . . . . Tc . 75 A. 72 A.1 The circuit diagram of the extension interface board . where: Q . Rjc . . . .junctionto-case resistance [o C/W ]. . . .4. . . . . . . . . . .1 Typical switching losses versus the collector-to-emitter current . . . 78 9 . . Ta . . .16 The waveform of the output voltage (measured on the resistor) for RL load (PF =0. . . . .2 The PCB layout of the extension interface board .subsystem . . . .heat source which has a current source as an electrical correspondent [W]. . . Tj junction temperature [o C ]. . . 63 A. . . . . . . . . . . . . . . .ambient temperature [o C ]. Rch . . 73 A. . . . . .2 Device and heat sink physical model . . . . . . .

.

. . . . . . . . . 23 Switching sequences for the PWM-NPC strategy . . . . . . . . . . . . 46 4. . . . .5 2. . . . .1 3. . 39 Simulation results for PWM-2 modulation strategy with a 10 kW load (PF = 1) . . . 28 Switching sequences for the PWM-DF strategy .6 2. . . . . . . . . . . . . . .List of Tables 2. . . . . . . 79 11 . . . . . . . . . . . . . . . . . . . . . . . . . .1 Total power losses of the semiconductor devices . . . . 25 Switching sequences for the PWM-1 strategy . . . . . .7 3.1 Laboratory instruments . . . . . . . . . . . . . . . . . . . 43 Simulation results for PWM-ALD modulation strategy with a 50%-50% Stress In/Stress Out ratio and a 10 kW load (PF = 1) . . . . .10 Simulation results for PWM-ALD modulation strategy . . . . . . . . . . . .4 3. . 45 Simulation results for PWM-DF modulation strategy . . . . . . . . . . 45 Simulation results for PWM-3 modulation strategy . . . . . 33 Simulation results for PWM-1 modulation strategy with a 10 kW R load . . . . . 53 The temperatures [o C ] of the switching devices obtained for the RL load . . . . . . . . . . . . . .3 3. . . . . . .2 2. . . . 45 Simulation results for PWM-2 modulation strategy . . . . .6 3. . .2 4. . . . . . 46 3. .4 2. . . . . . . . . 41 Simulation results for PWM-3 modulation strategy with a 50%-50% PWM1/PWM-2 ratio and a 10 kW load (PF = 1) . . . 32 Switching sequences for the 3L-ANPC PWM-ALD strategy . . . . . . . . . .9 Possible switching states used for the NPC converter . 44 Simulation results for PWM-1 modulation strategy . . . . .7 3. . . . . . . . . . .3 2. . . . . . . . . . . . . . 42 Simulation results for PWM-DF modulation strategy with a 10 kW load (PF = 1) . . . . . . . . . 72 C. . . . 27 Switching sequences for the PWM-2 strategy . . . . . . . . . . . . . . . . .3 Simulation parameters .1 2. 22 Possible switching states used for the ANPC converter . . . . . . . . . . . . . . 61 The temperatures [o C ] of the switching devices obtained for the R load . . . . . . . . . . . . .1 4. . . . 64 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. .2 3.

12 .

insulated gate bipolar transistor MV .stacked cells VSC .resistive inductive S .active neutral point clamped APOD .phase disposition PF .switch SC .half bridge IGBT .voltage source inverter 13 .resistive RL .three-level ALD .pulse width modulation R .flying capacitor HB .alternative phase opposition disposition DF .power factor POD .medium voltage NPC .neutral point clamped PD .phase opposition disposition PWM .List of Acronyms 2L .two-level 3L .adjustable losses distribution ANPC .digital signal processor FC .voltage source converter VSI .double frequency DSP .

.

IGBT collector-emitter on resistance 15 .phase current iC .instantaneous current M .diode forward current IDav .switching time period for the reference wave vCE .voltage variation in time fsw .average value of the IGBT collector current ICrms .blocking (leakage) losses rC .frequency of the carrier waves Ts .rms value of the IGBT collector current iD .IGBT collector-emitter voltage at zero current vD0 .modulation index O .Nomenclature list dv dt .diode forward voltage gf e .IGBT collector current ICav .negative switching state Pcond .zero down switching state OU .IGBT collector-emitter voltage vCE 0 .diode forward voltage at zero current vD .positive switching state P N .diode rms forward current is .IGBT transconductance iph .switching losses Pb .total losses Psw .zero up switching state P .average forward current of the diode IDrms .zero switching state OD .conduction losses Ploss .

switching time period for the carrier wave vs .instantaneous voltage VAO .phase voltage Vdc . Sc2 .DC link voltage 16 .rD .reference signals Tsw . Sr ’ .diode forward resistance Sc1 .carrier waves Sr .

The goals and limitations are also stated. A very important drawback of the NPC topology is that the semiconductor losses are distributed unequally among the devices of the converter. the clamping diodes of the NPCVSC (see Figure 1. the losses in the most stressed device will limit the switching frequency and the output power. mining and traction applications [3]. As in every converter. Today.1(a)) have been replaced by active switches with anti-parallel diodes.1 Background and motivation The three-level (3L) Active Neutral Point Clamped (ANPC) topology was proposed in 2001 [1]. 17 . Hence. the NPC converter is widely used in medium voltage (MV) drives for industry. which will also lead to an unequal junction temperature distribution [3]. 1.Chapter 1 Introduction In this chapter. a short introduction on the background and motivation of this project is given. marine. some of the devices will become hotter. as an improved version of the Neutral Point Clamped (NPC) topology. The problem of the project is formulated. The NPC offered a simple solution for extending the the voltage and power ranges of the existing two-level voltage source converter (VSC) technology and a superior output voltage quality [2]. S1 ___ V dc 2 D2 D1 ___ V dc 2 S3 D3 iph S1 D1 D2 S3 D5 S4 D3 iph S2 D5 ___ dc V 2 S6 S4 D4 ___ dc V 2 S5 D4 D6 S6 D6 (a) 3L NPC-VSC (b) 3L ANPC-VSC Figure 1.1: Single-phase three-level NPC (a) and ANPC (b) voltage source converters In order to overcome the uneven loss distribution issue. while others will stay cooler. which dates back in the early 1980’s.

The main limitations of this project are: • a low voltage ANPC converter will be used in the laboratory implementation. This way.2. • the modulation strategies are going to be tested only on an R and RL load. 18 . Hence. • to investigate the distribution of the power losses amongst the ANPC switches for different modulation strategies through simulations. the additional switches will enable more switching states and commutations compared to the NPC topology. • the inverter used in the experiments was not built for the purpose of studying loss balancing.2 Problem formulation The aim of this report is to investigate the modulation strategies for the three level Active Neutral Point Clamped (ANPC) voltage source inverter in order to achieve an even distribution of the power losses amongst the inverter’s semiconductor switches.in the ANPC converter (see Figure 1. Due to the fact that the most stressed device will limit the current capability of the converter.1(b)). 1. the transferred power and switching frequency of the converter can be increased. by using the proper modulation technique. power loss balancing amongst the switches of the converter is desired. This way. not all the aspects of the considered problem have been covered.2 Project limitations Due to time constraint. • experimental validation of the simulation results. 1. without having to increase the costs by replacing the switches with higher rated ones or bringing improvements to the cooling system.1 Project objectives The main goals of this project are: • to achieve knowledge about the the existing modulation strategies used for the ANPC converter. loss balancing amongst the semiconductor devices could be achieved. • only the inverter mode of operation of the converter will be studied. Due to the increased number of possible switching states and commutations which can be achieved with the ANPC topology compared to the NPC structure. • only single phase operation is considered.2. 1. numerous modulation strategies can be implemented for controlling the ANPC inverter.

This type of losses depend on the voltage across the switch and the current through it. as an improvement to the basic Neutral Point Clamped (NPC) structure. • switching losses (Psw ). basic notions about Insulated Gate Bipolar Transistors (IGBT) and diode power losses are briefly presented. as well as power losses in any semiconductor component operating in switch-mode can de divided in three main groups [4]: • conduction losses (Pcond ).2) . the three-level converter concept is introduced. • blocking (leakage) losses (Pb ). representing the IGBT on-state zero-current collector-emitter voltage (vCE 0 ) connected in series with a resistance representing the the collector-emitter on-state resistance (rc ) [4]: vCE (iC ) = vCE 0 + rC · iC 19 [V ] (2.1. which are generally neglected. IGBT conduction losses can be calculated by approximating the semiconductor device with a DC voltage source. 2.1) 2. the conduction losses are represented by the energy lost in the switch during the on-state. The Active Neutral Point Clamped (ANPC) topology is then described. the total losses in a semiconductor device (Ploss ) are given by Equation 2. Therefore. At the beginning. with focus on how the power losses are distributed amongst the switches.1 IGBT and diode power losses IGBT and diode power losses. Ploss = Pcond + Psw + Pb ≈ Pcond + Psw [W ] (2.1 [4].Chapter 2 Basics on converter losses and the ANPC topology This chapter introduces the main theoretical concepts which are used throughout the report.1 IGBT conduction losses If the energy associated with the small amount of leakage current during the off-state of the switch is neglected. Several modulation strategies used for controlling the ANPC converter are presented. Afterwards.

during on-state. is is the instantaneous current through the IGBT and vs is the instantaneous voltage across the switch. the current through it and the switching time. can be expressed as [4]: t1 +tswon Psw = fsw · t1 is · vs dt + t2 +tswoff t2 is · vs dt [W ] (2. 2.3) 2 (vCE 0 · iC (t) + rC · iC (t)2 )dt = vCE 0 · ICav + rC · IC rms [W ] 1 is the switching period.5) where vD is the voltage across the diode and iD is the current through the diode. representing the forward voltage drop at zero current (vD0 ) connected in series with a resistance representing the forward resistance of the diode (rD ) [4]: vD (iD ) = vD0 + rD · iD [V ] (2. IDav is the average where fsw is the switching frequency. The switching losses depend on the voltage across the switch. Tsw = fsw current and ICrms is the rms value of the current through the IGBT. and based on the instantaneous waveforms of the voltage and current. The average conduction losses of the IGBT can be computed as [4]: Pcond = Pcond = 1 · Tsw Tsw 0 1 · Tsw Tsw (vCE · iC (t))dt 0 [W ] (2. 20 . t2 represents the time moment when the switch starts to turn off. The average conduction losses of the diode can be computed as [4]: Pcond = Pcond = 1 · Tsw Tsw 0 1 · Tsw Tsw (vD · iD (t))dt 0 [W ] (2.1. ICav is the average where fsw is the switching frequency. and can therefore be neglected. tswon and represents the time needed for the switch to turn on.6) 2 (vD0 · iD (t) + rD · iD (t)2 )dt = vD0 · IDav + rD · ID rms [W ] 1 is the switching period. Tsw = fsw current and IDrms is the rms value of the current through the diode. tswoff represents the time needed for the switch to turn off.4) where fsw is the switching frequency. Diode switching losses are generally small. 2. as the operating state of the switch is changed from on (off) to off (on).where vCE is the collector-emitter voltage and iC is the current through the IGBT. during on-state. The conduction losses can be calculated by approximating the semiconductor device with a DC voltage source. the diode has both conduction and switching losses.2 IGBT switching losses The IGBT switching losses represent the energy losses which occur during the switching transient. t1 represents the moment when the IGBT starts to turn on.3 Diode losses Similar to the IGBT.1.

With this topology. each of the switching device has to withstand full DC link voltage. • Negative (N) .1(b). and can be seen in Figure 2. The NPC inverter. Compared with the two-level topology. 21 .when the two upper switches S1 and S3 are turned on. The output voltage obtained with this topology is a d square wave whose amplitude swings between + V2d and − V 2 . A standard single-phase two-level inverter is composed of two complementary switches. S1 S1 Vdc D1 iph D1 D2 S3 ___ V dc 2 D3 iph D5 S4 D4 S2 D2 ___ dc V 2 S6 D6 (a) 2L HB converter (b) 3L NPC converter Figure 2. Nowadays.2. − V2d is applied to the output (see Figure 2. this type of converters are successfully used in high power.2. and they have been developed as an improvement to the existing two-level (2L) topologies. Flying Capacitor (FC) and Neutral Point Clamped (NPC). + V2d is applied to the output (see Figure 2.2 2. an additional zero level is introduced in the waveform of the output voltage. hence the name of three-level converter. as well as all any three-level topology. can take one of the following three switching states [5]: • Positive (P) .1(a). two extra switches with anti-parallel diode are added and so. the multilevel topologies can reduce the dv dt and if the number of levels is sufficiently high. A single-phase three-level NPC converter is presented in Figure 2. harmonic distortion will be small enough that output filter can be omitted [6]. multilevel topologies can be used instead.when the two lower switches S4 and S6 are turned on.2(b)).1(a). With an appropriate switching strategy. The three main multilevel inverter topologies are Stacked Cells (SC). due to the advance in technology. where NPC has found wide application in high power medium voltage drives [5]. fast switching applications [1]. hence the name of two-level.2(a)).1 The Active Neutral Point Clamped topology Basics on three level converters Three-level (3L) converters are relatively new.1: Single-phase two-level half bridge (HB) (a) and three-level Neutral Point Clamped (NPC) (b) voltage source converters In order reduce the problems of the classical two-level inverters. Other disadvantages of the two-level converters are high harmonic distortion and high dv dt [5]. medium voltage. shown in Figure 2.

the current will flow through D5 (see Figure 2.when the two inner switches S3 and S4 are turned on.S1 and S3 are on. depending on the direction of the load current: if iph is positive. and so they can be used for applications which require high power transfer. and if iph is negative. S1 ___ V dc 2 D2 D1 ___ V dc 2 S3 D3 iph S1 D1 D2 S3 D3 iph D5 ___ dc V 2 S6 S4 D4 ___ dc V 2 D5 S4 D4 D6 S6 D6 (a) Positive switching state (P) (b) Negative switching state (N) S1 ___ V dc 2 D2 D1 S3 D3 iph D5 ___ dc V 2 S6 S4 D4 D6 (c) Zero switching state (O) Figure 2.S4 and S6 are on.1: Possible switching states used for the NPC converter An advantage of the 3L NPC converter is that each of the switches will have to withstand only half of the DC link voltage. the current will flow through D2 . (b) N .1.2(c)). Switching state P 0 N Device state S1 S3 S4 S6 On Off Off On On Off Off On On Off Off On Inverter terminal voltage dc + V2 0 dc − V2 Table 2. which will yield an unequal junction 22 . The drawback of this topology is represented by the unequal distribution of the power losses among the semiconductor devices. (c) O .• Zero (O) .S3 and S4 are on The switching states which can be used for the NPC topology are summarized in Table 2. the output is connected to the neutral point of the converter through one of the clamping diodes ( D2 or D5 ).2: Switching states for the single-phase three-level NPC converter: (a) P .

meaning that with this topology. Switching state P1 P2 OU 1 OU 2 OD1 OD2 N1 N2 S1 On On Off Off On Off On Off S2 Off Off On On Off On Off On Device S3 On On On On Off Off Off Off state S4 Off Off Off Off On On On On Inverter terminal voltage S5 Off On Off On On On Off Off S6 On Off On Off Off Off On On dc + V2 V dc + 2 0 0 0 0 V dc − 2 dc − V2 Table 2. The additional active switches in the ANPC converter will introduce more possible switching states (see Table 2. the paths of the current through the switches remain the same as for the NPC topology. in the ANPC converter (see Figure 2. independent from the direction of the load current [7]. the additional switches will enable more switching states and commutations compared to the NPC topology. The most thermally stressed device will limit the switching frequency and the output power transfer of the converter [3]. This way. In order to achieve this. S1 ___ V dc 2 S2 D1 D2 S3 D5 S4 D3 iph S5 ___ dc V 2 D4 S6 D6 Figure 2.temperature distribution.2: Possible switching states used for the ANPC converter 23 .3: Single-phase ANPC voltage source converter With the ANPC converter.3). For the positive and negative switching states.2.2 ANPC topology The Active Neutral point Clamped (ANPC) topology was developed in order to overcome the uneven loss distribution issue of the NPC converter [1]. In the case of the zero switching state.1(b)) have been replaced by active switches with anti-parallel diodes. the same output state can be obtained with more than one switching state. the active clamping devices allow the selection of different current paths. the clamping diodes of the NPC-VSC (see Figure 2.2). 2. the same switching states can be achieved as with the NPC topology.

or the switching frequency can be increased. neither improve the cooling system [7]. S1 ___ V dc 2 S2 D1 D2 S3 D3 iph ___ V dc 2 S1 D1 D2 S3 D5 S4 D3 iph S2 S5 ___ dc V 2 D5 S4 D4 ___ dc V 2 S5 D4 S6 D6 S6 D6 (a) Positive switching state (P) (b) Negative switching state (N) S1 ___ V dc 2 S2 D1 ___ V dc 2 D2 S3 D3 iph S1 D1 S2 D2 S3 D3 iph S5 ___ dc V 2 D5 S4 D4 ___ dc V 2 S5 D5 S4 D4 S6 D6 S6 D6 (c) Zero (up) switching state (OU ) (d) Zero (down) switching state (OD ) Figure 2. its current capability.4: Switching states for the single-phase three-level ANPC converter: (a) P . without changing the switching devices for higher rated ones. In general. This can be achieved by applying a specific modulation strategy.S2 and S3 are on.3 Modulation strategies The main function of a voltage source inverter (VSI) is to convert a fixed DC voltage to an AC voltage with variable magnitude and frequency.The switching states which can be used for the ANPC topology are presented in Figure 2.S1 and S3 are on. they can be classified into two main categories [8]: • carrier-based methods. 2. The additional switching states of the ANPC topology will allow an improvement in what concerns the uneven distribution of the losses amongst the semiconductor devices.S4 and S6 are on. and hence control the switching sequence of the inverter’s switches [5]. (b) OD . 24 .S4 and S5 are on. compared to the NPC converter.4. Hence. the lifetime of the inverter can be extended. There are various control techniques that have been proposed for the multilevel inverters. (c) OU . This can be achieved by using an appropriate switching sequence which can redistribute the power loses of the switches in a way that loss balancing is achieved.2. (b) N .

3: Switching sequences for the PWM-NPC strategy 25 .3). Through the comparison process. three switching states are obtained: P (Vdc /2). N (−Vdc /2) and O (see table 2. more zero conduction paths can be achieved. i. various PWM modulation strategies can be obtained for the ANPC topology. For three-level inverters.6 (on the next page) present how the switching signals are obtained for the PWM-NPC strategy. Compared to the classical NPC structure. NPC modulation strategy The control strategy of the NPC converter can also be used on the ANPC topology. a more even distribution of the losses in the semiconductor devices can be achieved with the ANPC topology [10]. the ANPC topology has more degrees of freedom. In this report. centred in the middle of the carrier set [9]. In the case of carrier-based strategies. where all carriers are in phase. The three-level ANPC inverter is derived from the NPC topology. In this case. the ANPC converter offers more than one possibility of clamping the midpoint [10]. • phase opposition disposition (POD).e. By using different zero states and conduction paths. This way. there are three common carrierbased strategies [9]: • alternative phase opposition disposition (APOD). where the carriers above the reference zero point are out of phase with those below the zero point by 180o .1). the two additional active switches of the ANPC converter are not used. Output Voltage dc + V2 0 dc − V2 Switching State P O N Switching Sequence S1 S3 S4 S6 1 1 0 0 0 1 1 0 0 0 1 1 Table 2. the APOD and POD strategies are equivalent [9].• space vector modulation methods. where the clamping diodes are replaced by two active switches with anti-parallel diodes (see Figure 1. Figures 2. with a sinusoidal reference. • phase disposition (PD). in contrast to the conventional NPC topology. Depending on the phase relationship between the carriers. where each carrier is phase shifted by 180o from its adjacent carriers. Due to the fact that the commutations to or from the zero states determine the distribution of the switching losses and that the distribution of conduction losses during the zero states can be controlled by the selection of different current paths. only carries based modulation strategies are going to be presented. by comparing the reference signal (Sr ) with two carrier waves (Sc1 and Sc2 ).5 and 2. the switching states for the switches of a n-level inverter are obtained by comparing n-1 triangular carrier waves having the same frequency and amplitude.

018 0.2 -0. during one period of the carrier wave.014 0.6 0. The N state is obtained by turning on the switches S4 and S6 .002 0. 26 .016 0.6 -0.1 0.4 -0.008 0.2 0 -0. In order to obtain the P state.6: The switching sequences and output voltage for the PWM-NPC strategy.02 Time[s] Figure 2. The zero voltage level is obtained when the switches S3 and S4 are turned on [11].4 0.012 0.01 0.5: PWM generation for the PWM-NPC strategy Vdc/2 Sr Sc1 0 O N Sc2 0 Ts O O 0 0 P O Ts Sr -Vdc/2 S1 S3 S4 S6 S1 S3 S4 S6 VAO Vdc/2 (a) VAO Vdc/2 (b) Figure 2. the switches S1 and S3 must be turned on.006 0.004 0.8 0.8 -1 0 Sc1 Sc2 Sr 0. Because the frequency of the carrier waves is much higher than that of the reference signal. the reference can be considered to be constant.

In the case of PWM-1 strategy. Output Voltage dc + V2 Switching State P O1 + O1 − N S1 1 0 0 0 0 dc − V2 Switching S2 S3 0 1 1 1 0 0 0 0 Sequence S4 S5 0 0 0 0 1 1 1 0 S6 0 0 0 1 Table 2. In this case. Through the comparison process. The state O1− is obtained when the reference voltage is negative. the reference can be considered to be constant. equal to the frequency of the reference voltage [12]. the switches S1 and S3 must be turned on.7: The switching sequences and output voltage for the 3L-ANPC PWM-1 strategy.Classical PWM strategies For the ANPC topology there are two well known classical carrier-based PWM modulation strategies. For these two commutation sequences. S2 and S5 . Because the frequency of the carrier waves is much higher than that of the reference signal. O1+ and O1− (see Table 2.7 present how the switching signals are obtained for the PWM-1 strategy. by comparing the reference signal (Sr ) with two carrier waves (Sc1 and Sc2 ). four switching states are obtained: P (Vdc /2).5 (on the previous page) and 2. while S3 and S4 switch at a low frequency.4: Switching sequences for the PWM-1 strategy In order to obtain the P state. N (−Vdc /2). The N state is obtained by turning on the switches S4 and S6 . Vdc/2 Sr Sr Ts -Vdc/2 S1 S2 S3 S4 S5 S6 Vdc/2 (a) VAO Vdc/2 (b) 0 0 O1O1+ 0 S1 S2 S3 S4 S5 S6 VAO 0 P O1+ N Sc2 Ts O1- Sc1 Figure 2. Figures 2. S6 switch alternatively at a high frequency (fsw /2). the switches S1 . during one period of the carrier wave.4). S4 and S5 must be 27 . The zero voltage level is obtained with two switching states: O1− and O1+ . called PWM-1 and PWM-2. the paths of the load current through the switches are the same as for the NPC topology.

28 . while the rest of the switches switch at a low frequency(the frequency of the reference voltage) [12]. the inner switches of the inverter (S3 and S4 ) have only conduction losses. S5 and S6 must be turned off [12]. The state O1+ is obtained when the reference voltage is positive. With the PWM-1 strategy. S3 and S5 must be turned on. S2 and S3 must be turned on. four switching states are obtained: P (Vdc /2).8: The switching sequences and output voltage for the 3L-ANPC PWM-2 strategy Output Voltage dc + V2 Switching State P O2 + O2 − N S1 1 1 0 0 0 dc − V2 Switching S2 S3 0 1 0 0 1 1 1 0 Sequence S4 S5 0 1 1 1 0 0 1 0 S6 0 0 1 1 Table 2. In this case. S2 . The state O2− is obtained when the reference voltage is negative. by comparing the reference signal (Sr ) with two carrier waves (Sc1 and Sc2 ). S3 and S6 must be turned on. the paths of the load current through the switches are the same as for the ANPC PWM-1 strategy. S4 and S6 .8 present how the switching signals are obtained for the PWM-2 strategy. N (−Vdc /2). The zero voltage level is obtained with two switching states: O2− and O2+ . Figures 2. while S1 . In the case of these two commutation sequences. S2 . S3 and S6 must be turned off. In the case of PWM-2 strategy. Vdc/2 Sr O2O2+ 0 S1 S2 S3 S4 S5 S6 VAO Vdc/2 (a) 0 P O2+ Ts Sr -Vdc/2 S1 S2 S3 S4 S5 S6 VAO Vdc/2 (b) 0 N Sc2 O2Sc1 0 Ts Figure 2. In this case. the switches S1 . while S1 . S4 .5 (on page 25) and 2.5: Switching sequences for the PWM-2 strategy In order to obtain the P state.5).turned on. O2+ and O2− (see table 2. The state N is obtained by turning on the switches S2 . Through the comparison process. S4 and S5 must be turned off. while the switching losses mainly stress the outer IGBTs (S1 and S6 ) [10]. the switches S3 and S4 switch at a high frequency. while S1 .

4 -0. to a limitation in the output power of the ANPC inverter.8 0. For the remaining 25% of the negative cycle. the switches are controlled with PWM-1. a new strategy was obtained. the transistors S3 and S4 switch during the entire cycle. this means that the inner switches have only conduction losses and the switching losses mainly stress the outer IGBTs.9: PWM generation for the PWM-3 strategy The switching states for the PWM-3 modulation strategy are obtained by applying for 50% of the period of the reference signal Sr .006 0. For the rest of the positive cycle and the first 25% of the negative cycle PWM-2 strategy is applied. the switching losses stress the inner switches. For O2− and O2+ states.012 0.01 0. and named PWM-3.The state O2+ is obtained when the reference voltage is positive.2 -0.004 0.8 -1 0 0. PWM-1 strategy is applied again.S3 and S6 must be turned off.6 -0.7 on page 27). PWM-1 1 0. 29 .002 0. Hence. With the PWM-2 modulation strategy.008 0. the switching sequences of PWM-1 strategy (see Figure 2. Figure 2. which leads to an unequal distribution of junction temperatures and so. the main drawback of the conventional NPC topology is not overcome by the ANPC structure.2 0 -0. and for the rest of the period. For the first 25% of the positive cycle of the reference signal.8 on page 28).4 0.016 0.6 0. the switching sequences of PWM-2 strategy (see Figure 2.018 0.014 0.02 Sc1 Sc2 Sr PWM-2 PWM-1 Time[s] Figure 2.9 shows the reference and carrier signals which are used for obtaining the switching sequences for the switches with PWM-3 modulation strategy. S1 . S4 and S5 must be turned on and S2 . by using the two classical PWM modulation strategies. Classical strategies combined By combining the two classical modulation strategies. the load current can pass in both directions through S2 and S3 or through S5 and S4 [12]. and so they are the most stressed semiconductor devices in the inverter. The disadvantage of the PWM-1 and PWM-2 methods is given by an unequal distribution of the losses in the semiconductor devices. while the outer have only conduction losses. Therefore. For a resistive load.

002 0.02 15 10 S4 5 0 0 15 10 5 0 0 0.008 0.002 0.01 0.008 0.012 0. 15 10 S1 5 0 0 0. the switching losses can be equally distributed amongst the inner and outer switches.10: Switching signals for the ANPC inverter switches with PWM-3 modulation strategy 30 .01 0.006 0.01 Time [s] 0.02 S5 0.02 15 10 S2 5 0 0 15 10 0.012 0.01 0.008 0.006 0.012 0.012 0. The switching signals for the six switches with the PWM-3 strategy can be seen in Figure 2.014 0.02 Figure 2.012 0.014 0.018 Time [s] 0.016 0.006 0.016 0.006 0.004 0.018 Time [s] 0.10.016 0.018 Time [s] 0.01 0.02 S3 5 0 0 0.004 0.016 0. in order to balance the overall power losses.008 0.008 0.014 0.002 0.018 Time [s] 0.004 0.004 0.014 0.002 0.016 0.004 0.02 15 10 S6 5 0 0 0.012 0.002 0.018 Time [s] 0.014 0.014 0.008 0.By using this PWM modulation strategy.002 0.006 0.016 0.006 0.018 0.004 0.01 0.

Double frequency PWM strategy Figures 2. O2− .008 0. O2+ . O1− (see table 2.6 0. Through the comparison process. 1 0.016 0.2 -0. O1+ . N (−Vdc /2).4 0.01 0.11: PWM generation for the PWM-DF strategy Vdc/2 Sr 0 O1+ P O2+ Sc1 -Vdc/2 S1 S2 S3 S4 S5 S6 VAO Vdc/2 (a) 0 Ts P O1+ Vdc/2 Sc2 0 Sr -Vdc/2 S1 S2 S3 S4 S5 S6 VAO Vdc/2 (b) O1N 0 O2N Ts O1- Figure 2.6 -0. by comparing the reference signal (Sr ) with two carrier waves (Sc1 and Sc2 ).004 0.11 and 2.12: The switching sequences and output voltage for the 3L-ANPC PWM-DF strategy 31 . six switching states are obtained: P (Vdc /2).2 0 -0.8 0.014 0.8 -1 0 0.002 0.12 present how the switching signals are obtained for the PWM-DF strategy [12].018 0.012 0.6 on the next page).4 -0.02 Sr Sc1 Sc2 Time[s] Figure 2.006 0.

For the zero voltage level. O− the outer switches (S1 and S6 ) make zero current switching. In this case. the switches S1 . O+ . OIn− . the paths of the load current are similar to those of the state O2− . Due to the fact that during the switching sequences O+ . N . The state O2+ is obtained when S1 .Output Voltage dc + V2 Switching State P O1+ O2+ O2− O1− N S1 1 0 1 0 0 0 0 dc − V2 Switching S2 S3 0 1 1 1 0 0 1 1 0 0 1 0 Sequence S4 S5 0 1 0 0 1 1 0 0 1 1 1 0 S6 0 0 0 1 0 1 Table 2. OOut+ . OIn− . PWM-DF determines a more uniform distribution of the switching losses between the inner (S3 and S4 ) and the outer (S1 and S6 ) switches .14 (on the next pages) present how the switching signals are obtained for the PWM-ALD strategy. Through the comparison process. The state O1+ is obtained when the switches S2 and S3 are turned on.13 and 2. by using two reference signals (Sr and Sr ) which have the same phase angle and frequency. whereas the outer switches (S1 and S6 ) make hard switching. OOut− . O2− when the reference voltage is negative. while the state N is obtained by turning on the switches S2 . and O1− . O− and OIn− (see Table 2. In comparison with the modulation strategies PWM-1 and PWM-2. but different amplitudes and two carrier waves (Sc1 and Sc2 ). O+ and O− . N (−Vdc /2). OOut− . S3 and S5 must be turned on. meaning that each IGBT works at a switching frequency fs . Figures 2. while the state O2− is obtained when S2 . Adjustable losses distribution strategy The adjustable losses distribution modulation (PWM-ALD) [10] is a combination of the classical and PWM-DF strategies. OIn+ . 32 . whereas the inner switches (S3 and S4 ) make hard switching. OOut+ . four different control sequences are used: O1+ . The state O1− is obtained when the switches S4 and S5 are turned. OOut+ . S4 and S6 . eight switching states are obtained: P (Vdc /2).7 on the next page). O2+ when the reference voltage is positive. the paths of the load current are the same as for the PWM-1 and PWM2 strategies. while the output voltage has a switching frequency equal to 2fs [12]. OIn+ . OOut− . S4 and S5 are turned on. O+ and O− . P . S3 and S6 are on. causing them to be more stressed.6: Switching sequences for the PWM-DF strategy In order to obtain the switching state P . P . OIn+ . O− the inner switches (S3 and S4 ) make zero current switching. causing them to be more stressed. For both these sequences. N . these two switching sequences are named Stress Out mode [10]. The commutation sequences of the PWM-DF modulation strategy lead to a doubling of the apparent switching frequency. Due to the fact that during the switching sequences O+ . and the paths of the load current are similar to the state O1− [12]. these two switching sequences are named Stress In mode.

1 0.5 S1/S2 0 -0.5 -1 0 1 0.5 S3/S4 0 -0.5 -1 0
1 0.5

Sr Sr' Sc1 Sc2

0.005

0.01

0.015

0.02

0.005

0.01

0.015 Stress Out

0.02

S5/S6 0
-0.5 -1 0

Stress Out

Stress In
0.01 0.012 0.014 0.016 0.018 0.02

0.002 0.004 0.006 0.008

Figure 2.13: PWM generation for PWM-ALD modulation strategy for 50%-50% Stress In/Stress Out ratio

Output Voltage
dc + V2

Switching State P OIn+ OOut+ O+ O− OOut− OIn− N S1 1 1 0 0 0 0 0 0

0

dc − V2

Switching S2 S3 0 1 0 0 0 1 0 0 1 1 1 1 1 1 1 0

Sequence S4 S5 0 1 1 1 1 1 1 1 0 0 1 0 0 0 1 0

S6 0 0 0 0 0 0 1 1

Table 2.7: Switching sequences for the 3L-ANPC PWM-ALD strategy

33

Vdc/2 Sr’ Sr O+ 0 S1 S2 S3 S4 S5 S6 VAO

Sc1

Vdc/2 Sr’ Sr P O+ OIn+ Ts 0 S1 S2 S3 S4 S5 S6 Vdc/2 (a) VAO Vdc/2 (b) 0 O+ OOut+ P OOut+ Ts O+

OIn+ 0

0

0

Sc2

Sr Sr’ OOIn-Vdc/2 S1 S2 S3 S4 S5 S6 VAO 0

N

OOInTs

Sr Sr’ -Vdc/2 S1 S2 S3 S4 S5 S6

O0

N OOut- OOut-

OTs

Vdc/2 (c)

VAO

Vdc/2 (d)

Figure 2.14: The switching sequences and output voltage for the 3L-ANPC PWM-ALD strategy With this strategy, during a given cycle, different working time rates of Stress In mode and Stress Out mode can be chosen, in order to modify the distribution of the switching losses (see Figure 2.13). When Stress In mode is used, during the positive half cycle, S1 uses signal Sr’ instead Sr, whereas during the negative half cycle, S4 uses Sr’ instead of Sr. When Stress Out mode is used, during the positive half cycle, S2 uses Sr, whereas during the negative half cycle, S3 uses Sr instead of Sr. If the conduction losses mainly stress the inner IGBTs (the conduction losses distribution depends on the modulation index M and power factor PF), then the PWM-ALD control could give more switching losses to the outer IGBTs, by increasing the rate of Stress Out mode. Otherwise, if the conduction 34

losses mainly stress the outer IGBTs, then, by increasing the rate of Stress In mode, more switching losses could be put on the inner IGBTs. Thereby, the total losses of inner and outer switches can be balanced [10].

2.3

Summary

In this chapter, the main theoretical concepts which are used throughout the entire report have been presented. The chapter starts with a brief presentation of the types of power losses which can occur in semiconductor devices. Formulas for calculating the total power losses (Ploss ) of the IGBT and diode, as the sum of the conduction (Pcond ) and switching losses (Psw ), are given. Afterwards, the three-level converter concept is introduced, as an improvement brought to the two-level structure. The additional zero level of the output voltage (voltage levels of dc dc the output voltage for the three level case are: + V2 , 0 and − V2 ) will determine a lower dv harmonic distortion and a lower dt , hence making this topology well suited for high power medium voltage applications. The Active Neutral Point Clamped (ANPC) topology is then described. Compared to the basic Neutral Point Clamped (NPC) converter, this structure allows, by the use of an adequate modulation strategy, to achieve a more balanced distribution of the power losses between the semiconductor devices on the converter, and therefore overcome the main drawback of the NPC. This advantage of the ANPC is due to the two additional active switches, which replace the clamping diodes in the NPC topology. These extra switching devices will enable the ANPC to achieve the same switching states as the NPC, but with different switching sequences and so, the losses amongst the devices can be distributed in a more even way. Several modulation strategies used for controlling the ANPC converter are presented, with focus on how the power losses are distributed amongst the switches. The two classical modulation strategies (PWM-1 and PWM-2) do not take advantage of the multiple possibilities of the ANPC topology to obtain the zero state. By using these two modulations, there will always be an uneven distribution of losses between the inner and outer switches of the converter. A new modulation strategy, called PWM-3 has been investigated. This strategy represents a combination of the two classical methods. The switching sequences of PWM-3 are obtained by using for 50% of the reference signal’s period, the switching sequences of PWM-1 strategy and for the other 50%, the switching sequences of PWM-2 strategy. This way, the switching losses are redistributed amongst the inner and outer switches, hence bringing an improvement to the loss balancing issue. Other two modulation strategies are presented, namely PWM-DF [12] and PWM-ALD [10]. These two strategies also bring improvements to the loss unbalancing issue, by using more and different switching sequences in order to achieve the zero state. Due to the fact that the most stressed device will limit the current capability of the converter, power loss balancing amongst the switches of the converter is desired. This way, the transferred power and switching frequency of the converter can be increased, without having to increase the costs by replacing the switches with higher rated ones or bringing improvements to the cooling system.

35

powered from two DC voltage sources.1: The general block diagram of the simulation models 37 . 3. The aim of this chapter is to study the distribution of the power losses amongst the six switches in the ANPC inverter. PLECS Toolbox was used.Chapter 3 Simulations The different modulation strategies which have been presented in Chapter 2 are going to be simulated using Matlab Simulink. load).1 Sr Vload Sr Sc1 Gate signals Gate signals Sc1 Iload Sc2 Sc2 Modulator Plant Losses calculation (a) General block diagram S1 S1 Sr Sr S1 S1 Sr S2 S3 S2 S2 S3 S4 S5 S6 Iload S2 S3 PLECS Circuit S4 S5 S6 Iload Sr Sc1 3 Iload S3 3 Iload PWM_1 Sc1 PWM_1 S4 S5 Sc1 Sc1 Sc2 Sc2 1 1 Gate signals2 Gate signals 1 1 Gate signals Gate signals9 S4 S5 S6 PLECS Circuit Vload S6 Vload 2 Vload 2 Vload Sc2 Sc2 (b) Modulator block (c) Plant block Figure 3. For modelling the plant (DC sources.1 System description The modulation techniques presented in Chapter 2 have been tested on a single-phase ANPC converter working in inverter mode of operation. ANPC converter. The general block diagram of the simulation models is presented in Figure 3. The simulations have been performed in Matlab Simulink environment.

The plant block was modelled using PLECS Toolbox. the switching states of the inverter’s switches are obtained. The outputs of the modulator block represent the gate signals of the IGBTs. 38 .IRG4PC40FD [14]. • RL load. The inputs of the block are the reference signal (Sr ) and the two carriers (Sc1 and Sc2 ). a thermal description needs to be added to the semiconductor components. these have been introduced in the thermal model merged. The structure of the plant block can be seen in Figure 3. The semiconductor devices which have been implemented in the simulation models are IGBTs with incorporated anti-parallel diode. Also. because this is how this information is provided in the datasheet [14]. the conduction losses have been introduced in the thermal model of the device separately.The modulator block implements each of the five modulation strategies which have been previously discussed.2. the conduction and switching losses of the semiconductor devices can be determined. for the diode and the IGBT. By using PLECS Thermal Toolbox. The selection of the heat sink is presented in Appendix A. is a very well suited tool for modelling power electronics systems that contain both electrical circuits and controllers. This is achieved by adding a heat sink to the simulation model. based on whose comparison. and it consists of: • two DC supplies. Figure 3. This decision was taken in order for the behaviour of the semiconductor switches in the simulations to be similar to the behaviour of the semiconductor switches which have been used in the laboratory tests (IGBT with incorporated ultra fast soft recovery diode . using the information provided in the datasheet of the IRG4PC40FD device [14].2: The PLECS block diagram of the plant By using PLECS Thermal Modelling Toolbox. which in combination with Simulink. • single-phase ANPC converter. In what concerns the switching losses.

2 Simulation results In order for the results to be more clear.33 50. The DC link voltage was considered 600 V and the frequency of the carrier waves 15 kHz. Switch S1 S2 S3 S4 S5 S6 Pcond [W] 50.1 PWM-1 The simulation results obtained with a load of 10 kW (PF = 1) using PWM-1 modulation strategy are presented in Table 3.1 0 0 0 0 45. the results of the simulations that had the same load like in the laboratory experiments are shown. 6). The distribution of the losses amongst the converter switches has been tested on both an R (PF = 1) and an RL (PF = 0. The conduction (Pcond ).2.36 0 50. where i = 1.1 Ploss [W] 95. 3. The outputs the Conduction Switching Cond_Loss Sw_Loss thermal conduction losses and thermal switching losses of the selected IGBT with antiAverage Discrete parallel device (Si .3.3: The Simulink block diagram of the losses calculation block mean is presented Out1 signal In1PLECS probe 1 in Figure 2 2 The losses1 calculation block 3. switching (Psw ) and Mean Value total (Ploss ) power losses are calculated for one cycle of the reference signal (20 ms) and then displayed.1. large currents will pass through the switches and loss balancing can be seen more easily.41 0 95.46 0 50. the behaviour of the switches from the simulations can be compared with the results obtained in the laboratory.5 kHz.33 50.44 Psw [W] 45. 3.54 Table 3.85) load for a modulation index M = 1.1: Simulation results for PWM-1 modulation strategy with a 10 kW R load 39 . In this way. The obtained results are presented and discussed in the following subsections. the power of the load was considered to be 10 kW in the simulations.41 0 50. where the IGBT and diode are mounted in the same case. This is because at this level. except for the PWM-DF strategy. In the last part of this section. together.Cond_Loss Conduction Switching Pcond Si PLECS Probe Si Sw_Loss Ploss Si Psw Si Losses calculation Si Figure 3. The values which are displayed represent the power losses of the IGBT and diode together. where the frequency is 7.

33 50. It can be concluded then.4. The difference in losses between the two groups of IGBTs is due to the fact that S1 and S6 switch at a higher frequency (15 kHz) compared to S3 and S4 . the distribution of the losses amongst the semiconductor switches remaining unbalanced.1 Figure 3. For the resistive case the recovery diodes are not used. Similar to the PWM-1 case. and therefore have more switching losses.2.44 Psw Pcond 45. the results represent the power losses of the IGBT and anti-parallel diode summed.1 and Figure 3. the inner switches (S3 and S4 ) having higher losses than the outer switches (S1 and S6 ). where the outer switches have almost two times more power losses than the inner pair of switches.1 represent the power losses of the IGBT and anti-parallel diode summed. The disadvantage of the PWM-1 modulation strategy can be easily seen from Figure 3. the values which are presented represent only the losses of the IGBTs. For the resistive case the recovery diodes are not used.41 50. The switches S2 and S5 do not have any power losses due to the fact that with a resistive load. which switch at 50 Hz.4: Power losses distribution for PWM-1 modulation strategy with a 10 kW load (PF = 1) As it can be seen from Table 3.1 45.2 and Figure 3.4. there is no current passing through them. As it can be seen from Table 3. with PWM-2 modulation strategy the total power losses are unevenly distributed amongst the inverter’s switches.5 (on the next page). 100 90 80 Power losses [W] 70 60 50 40 30 50. the outer switches (S1 and S6 ) having higher losses than the inner switches (S3 and S4 ). that with this strategy.2 PWM-2 The simulation results obtained with a load of 10 kW (PF = 1) using PWM-2 modulation strategy are presented in Table 3. The difference in losses between the two groups of IGBTs is due to the fact that 40 . and so. with PWM-1 modulation strategy the total power losses are unevenly distributed amongst the inverter’s switches. the main drawback of the NPC topology is not overcome by the ANPC. the values which are presented represent only the losses of the IGBTs.2 (on the next page). 3. and so.The results presented in Table 3.36 20 10 0 S1 S3 S4 S6 50.

8 0 94.3 PWM-3 The simulation results obtained with a load of 10 kW (PF = 1) using PWM-3 modulation strategy are presented in Table 3. which switch at 50 Hz.2: Simulation results for PWM-2 modulation strategy with a 10 kW load (PF = 1) Similar to the PWM-1 case.7 Table 3. there is no current passing through them.5 42. the switches S2 and S5 do not have any power losses due to the fact that with a resistive load.9 0 0 Ploss [W] 50.8 50.3. the distribution of the losses amongst the semiconductor switches remaining unbalanced.9 Figure 3.8 50.5 42.5: Power losses distribution for PWM-2 modulation strategy with a 10 kW load (PF = 1) The disadvantage of the PWM-2 modulation strategy can be easily seen from Figure 3. Similar to the previous cases. 100 90 80 Power losses [W] 70 60 50 40 30 50. and therefore have more switching losses. 3.75 50.2. For the resistive case the recovery diodes are not used. where the inner switches have almost two times more power losses than the outer pair of switches.8 0 50.5. the main drawback of the NPC topology is not overcome by the ANPC. the values which are presented represent only the losses of the IGBTs. It can be concluded then.65 0 50.S3 and S4 switch at a higher frequency (15 kHz) compared to S1 and S6 .3 93. 41 . the results represent the power losses of the IGBT and anti-parallel diode summed. and so.7 Psw Pcond 43.7 Psw [W] 0 0 43. that with this strategy.8 20 10 0 S1 S3 S4 S6 50.75 0 50. Switch S1 S2 S3 S4 S5 S6 Pcond [W] 50.

83 20 10 0 S1 S3 S4 S6 50.6: Power losses distribution for PWM-3 modulation strategy with a 50%-50% PWM-1/PWM-2 ratio and a 10 kW load (PF = 1) As it can be seen from Table 3.7 21. the results represent the power losses of the IGBT and anti-parallel diode summed. and so.Switch S1 S2 S3 S4 S5 S6 Pcond [W] 50. loss balancing is obtained.8 20.7 0 21. 100 90 80 Power losses [W] 70 60 50 40 30 50.65 71.3 and Figure 3. 3.4 PWM-DF The simulation results obtained with a load of 10 kW (PF = 1) using PWM-DF modulation strategy are presented in Table 3.53 0 72. the switches S2 and S5 do not have any power losses due to the fact that with a resistive load.53 Psw Pcond Figure 3. with PWM-DF modulation strategy the total power losses are uniformly distributed amongst the inverter’s switches.75 50.73 21.3: Simulation results for PWM-3 modulation strategy with a 50%-50% PWM1/PWM-2 ratio and a 10 kW load (PF = 1) Similar to the previous cases. With this PWM modulation technique the switching losses are redistributed amongst the switches and so.83 0 50. 42 . with PWM-3 modulation strategy the total power losses are uniformly distributed amongst the inverter’s switches.2.7 (on the next page).81 50.75 0 50. For the resistive case the recovery diodes are not used.4 and Figure 3.81 50.7 0 21. the values which are presented represent only the losses of the IGBTs.73 Psw [W] 21.45 0 72. Similar to the previous cases.4 (on the next page).8 20.7 21.53 Ploss [W] 72. there is no current passing through them.26 Table 3.6. As it can be seen from Table 3.

59 50.4: Simulation results for PWM-DF modulation strategy with a 10 kW load (PF = 1) Similar to the previous cases. the results represent the power losses of the IGBT and anti-parallel diode summed.59 0 50.58 Psw [W] 20.1 71.8 (on the next page).59 20 10 0 S1 S3 S4 S6 50.79 21.3 21. 43 .51 21. Similar to the previous cases.2.5 and Figure 3. For the resistive case the recovery diodes are not used.Switch S1 S2 S3 S4 S5 S6 Pcond [W] 50.61 Ploss [W] 71.61 Psw Pcond Figure 3.68 50.68 20. with PWM-ALD modulation strategy the total power losses are uniformly distributed amongst the inverter’s switches.5 PWM-ALD The simulation results obtained with a load of 10 kW (PF = 1) using PWM-ALD modulation strategy are presented in Table 3.98 0 72. As it can be seen from Table 3.7: Power losses distribution for PWM-DF modulation strategy with a 10 kW load (PF = 1) 3.5 (on the next page).59 50. the values which are presented represent only the losses of the IGBTs.79 0 21. there is no current passing through them.51 21. the switches S2 and S5 do not have any power losses due to the fact that with a resistive load.38 0 72. 100 90 80 Power losses [W] 70 60 50 40 30 50. and so.3 0 21.29 Table 3.68 0 50.

45 22.42 45.56 23. This apparent reduction is due to the fact that the modulation index used for obtaining the switching states for the PWM-ALD strategy is smaller1 then the value used for the other strategies.4 45.8: Power losses distribution for PWM-ALD modulation strategy with a 50%-50% Stress In/Stress Out ratio and a 10 kW RL load (PF = 0. This downscaling is due to the current limitation (5 A) of the available DC sources. with an amplitude of 1.5 45. there is no current passing through them.93 Psw Pcond Figure 3. from 10 kW to approximately 650 W.48 22.6 Results for validation in the laboratory Due to the fact that not all the simulation conditions could be reproduced in the laboratory. two carrier waves with different amplitudes are used: Sr .85) From Figure 3.5 0 45.98 0 68.07 0 23.41 Table 3.07 23.57 0 69. This set of simulations have been performed in order to verify if even with such a small load power there are still loss balancing issues.5: Simulation results for PWM-ALD modulation strategy with a 50%-50% Stress In/Stress Out ratio and a 10 kW load (PF = 1) Similar to the previous cases. The only parameter which changes is the load power. where M = 1.42 0 45.48 Psw [W] 22. 3. 100 90 80 Power losses [W] 70 60 50 40 30 20 10 0 S1 S3 S4 S6 45.56 0 23. and hence the losses obtained in this case are smaller. the switches S2 and S5 do not have any power losses due to the fact that with a resistive load. with an amplitude of 0.8 it can be seen that the total power losses of the semiconductor devices are smaller when compared to the previous strategies.45 22.4 45.85 67.93 Ploss [W] 67. 1 44 . even though the same load has been used.9 and Sr ’. another set of simulations have been done.2. For the PWM-ALD strategy.Switch S1 S2 S3 S4 S5 S6 Pcond [W] 45.

41 1.87 0.83 0 0.29 0.55 0.66 0 0 0 0 1.28 0 0.9 0.59 0 0.82 0.8: Simulation results for PWM-3 modulation strategy 45 .59 0.59 0 0.39 0.59 0 0.7: Simulation results for PWM-2 modulation strategy Switch S1 S2 S3 S4 S5 S6 Pcond [W] 0.46 1.17 0.18 0.17 a) PF =1 b) PF = 0.59 Switch S1 S2 S3 S4 S5 S6 Pcond [W] 0.18 1 0.32 2.66 0 0 Ploss [W] 0.15 0.01 1.26 0.6: Simulation results for PWM-1 modulation strategy Switch S1 S2 S3 S4 S5 S6 Pcond [W] 0.6 0 0 0.Switch S1 S2 S3 S4 S5 S6 Pcond [W] 0.18 2.59 0 2.28 a) PF =1 b) PF = 0.59 0.59 Psw [W] 0.46 0.41 0.50 0 0.66 0.89 a) PF =1 b) PF = 0.28 Psw [W] 0.34 0.25 0 0.59 0.25 0 0.59 0 2.28 Psw [W] 0.72 0.66 1.28 Psw [W] 0 0 1.83 Ploss [W] 1.29 0.59 0.59 0 0.59 Psw [W] 0 0 1.73 0 0.33 1.42 0 1.55 0 0 Ploss [W] 0.66 Ploss [W] 2.41 0.85 Table 3.41 0 1.85 Table 3.46 0.61 Ploss [W] 0.85 Table 3.9 Ploss [W] 1.6 1.82 0 0.39 0.4 0.39 0.75 0.25 2.25 Switch S1 S2 S3 S4 S5 S6 Pcond [W] 0.29 0.6 0.59 0 0.16 1.59 Psw [W] 1.42 Switch S1 S2 S3 S4 S5 S6 Pcond [W] 0.29 0.82 0.

10: Simulation results for PWM-ALD modulation strategy 3.38 0 1. the modulator block and the losses calculation block. the same configuration of the semiconductor devices was used in the simulations.28 0.31 0.53 0 0.48 0. where the frequency of the carriers was set to 7. the structure of the simulation models is described.86 0.6 0 0.88 Ploss [W] 1.74 0.71 0 0.85 Table 3. with a frequency of the carrier waves equal to 15 kHz (except the PWM-DF strategy.Switch S1 S2 S3 S4 S5 S6 Pcond [W] 0.53 0 0.3 Summary This chapter treats the simulation part of this report.71 a) PF =1 b) PF = 0.59 0.29 0.9: Simulation results for PWM-DF modulation strategy Switch S1 S2 S3 S4 S5 S6 Pcond [W] 0.59 0 0.43 Ploss [W] 0.21 0. All the modulation strategies which have been presented in the previous chapter have been simulated for a 10 kW resistive load. composed of the DC sources.34 0 1.53 0.9).39 1.54 0 0. and a unity modulation index (except from PWM-ALD strategy. while the other has M = 0. The general system is divided into three main blocks: the plant.59 1.2 Psw [W] 0.25 0.76 0 0.39 Switch S1 S2 S3 S4 S5 S6 Pcond [W] 0.71 0.68 0.55 0. Because in the inverter from the laboratory setup.38 1. where two reference signals are used. the single-phase ANPC converter and the load.3 0. 46 .21 0. In order to be able to calculate the power losses of the inverters’ switches.27 0 1.35 0 1.89 1. one having M = 1. In this way.83 0 0. The losses of the converter are presented as the power losses of the IGBT and anti-parallel diode summed for each of the devices.3 0. the IGBTs and the anti-parallel diode are mounted in the same case.42 0.6 Ploss [W] 0.8 a) PF =1 b) PF = 0.29 Psw [W] 0.5 kHz).55 0.36 0 1.78 0 0.83 0 0. their thermal model was implemented using PLECS Thermal Toolbox.53 Psw [W] 0.41 Switch S1 S2 S3 S4 S5 S6 Pcond [W] 0.85 Table 3. the behaviour of the semiconductor switches in the simulations is similar to the behaviour of the semiconductor switches which have been used in the laboratory tests (IRG4PC40FD).79 Ploss [W] 1.17 1.79 0.71 0.17 0.81 0 0.29 1.6 Psw [W] 0.59 0. In the beginning of the chapter.

From the simulation results it can be seen that as expected.85). hence loss balancing amongst the switches of the inverter is not achieved. With PWM-3. in order to check if for this low power level. the maximum load which could be used with the available equipment was of 650 W. 47 . the issue of loss balancing is still valid. for both R and and RL load (PF = 0. PWM-DF and PWM-ALD it can be seen that the total power losses are evenly distributed between the switches. with PWM-1 and PWM2. the simulations have been repeated for this new situation. the main drawback of the NPC topology is not overcome by the ANPC. Due to the fact that in the laboratory tests.

.

1.1: Block diagram of the experimental test setup The laboratory setup can be seen in Figure 4. The obtained results are presented and discussed.2. • 2 x 24 V. • load resistor. in order to validate the simulation results presented in Chapter 3. 3 A DC power supply. and is composed of: • 2 x 300 V.1 Test setup The block diagram of the experimental test setup is presented in Figure 4. 4. • single-phase ANPC converter.Chapter 4 Laboratory implementation The different modulation strategies which have been described in Chapter 2 are going to be experimentally tested. 49 . A description of the laboratory setup which has been used for the experimental tests is given. T1 D1 Power Analyzer Load D2 Differential probe T5 D5 T2 D6 T3 A T6 D3 V V T4 D4 PC DSP + Interface Board Dc Power Supply Figure 4. 5 A DC power supply.

(7). To avoid short circuits caused by an incorrect modulation. in order to insure a constant delay between the two switches in each of the three pairs [7].2: Laboratory test setup: (1). (2). • TMS320F28335 eZdsp board. Initially.PC 4. Details about the extension board are given in Appendix B. (6). (3). (5). (10) (7) (2) (5) (4) (1) (3) (6) (9) (8) (11) Figure 4.TMS320F28335 eZdsp board. The inverter board is divided into a high-power part mainly containing the power switches. using only three signals. • interface board.interface board.load resistor.24 V. 5 A DC power supply. • single-phase power analyser.300 V. The detailed list of laboratory instruments which have been used is given in Appendix C.• load inductor. 50 . the inverter switches needed to be driven using six independent gate signals. • power analyser. (11). For safety and noise reasons. the ANPC inverter’s six switches were driven as three complementary pairs. (9). (10). • oscilloscope. 3 A DC power supply.oscilloscope. both parts are electrically insulated from each other [7]. and a low-power part which transfers the command signals form the control unit.single-phase ANPC converter.single-phase power analyser. In order to achieve this. a hardware dead time was used. (4). developed by Andrzej Adamczyk and Maciej Swierczynski [7]. and replaced by an extension interface board.thermal camera. • PC. (8).load inductor. the dead time generator was removed. • differential probe.1 ANPC converter The inverter used in the experiments was a single-phase 3L-ANPC VSI platform. In order to implement PWM-DF and PWM-ALD modulation strategies.1.

• 68K bytes on-chip RAM. • 2 general purpose digital inputs are provided as optic fiber receivers. • 12 ePWM modules (6 modules with 2 ePWM outputs each).1. which has the following main features [13]: • TMS320F28335 Digital Signal Controller. • 12 bit analog to digital (A/D) converter with 16 input channels.The communication with the control unit is achieved through a fiber optic bus. • 10 PWM outputs available for optic fiber transmission. The inverter board also provides protection for a safe operation of the power switches. • 32-bit floating point unit.3 Interface board The communication between the DSP and the inverter is assured through an interface compatible with the TI TMS320F28335 eZdsp board. • 150 Mhz operating speed. • short circuit protection . • over voltage limiting circuitry. like [7]: • gate protection. 4.1. • under voltage lock-out. • over temperature protection. 51 .2 DSP board The control of the inverter was implemented on a DSP board from Texas Instruments. The features of this interface board are listed below: • 24 V DC supply voltage. • 3 voltage sensors scaled for measuring 400 V. • 6 current hall-sensors scaled for measuring 35 A. • 512K bytes on-chip Flash memory. 4. • 2 voltage sensors scaled for measuring 700 V.

ePWM2 and ePWM3 blocks are used for generating the switching signals for the switches S1 and S2 . in order to prevent the heating of the fiber optic transmitters from the interface board. in order to do the necessary configurations before generating the code.3. and set to 3.3: Simulink model used for DSP implementation The Simulink model of the control structure used to generate the code for the DSP board is presented in Figure 4. and it was selected in order to safely switch these on and off. was implemented software using the ePWM blocks. The Digital Output block configures the GPIO11 pin to operate as a digital output pin. The ePWM blocks configure the corresponding ePWM modules of the DSP board. 52 . and then loaded into the TMS320F28335 eZdsp board using Code Composer Studio v3. The ePWM1. S1 WA WB S2 C280x/C28x3x F28335 eZdsp ePWM ePWM1 S3 WA Sr C280x/C28x3x 1 GPIOx C28x3x WB Sr S4 ePWM ePWM2 Enable GPIO DO Digital Output S5 WA WB S6 C280x/C28x3x C280x/C28x3x ePWM ePWM3 ePWM ePWM4 Modulator Figure 4.4. and S5 and S6 .3. Also. These were added to the model from the Target Support Package TC2 Toolbox. in order to enable the PWM outputs on the interface board. S3 and S4 . the model of the control structure was implemented in discrete time domain. provides access to the processor’s hardware settings. The choice of dead time depends on the turn-on and turn-off characteristics of the IGBT’s. The code was automatically generated from the simulation model. without short circuiting the DC sources. The dead time that was used for generating the switching signals for the IGBTs belonging to the same leg.2 Modulation implementation on the DSP The software implementation of the control structure was developed using Matlab 2009b Simulink environment. in order to obtain the switching signals for the inverter. The ePWM4 block is used for disabling the corresponding channels. for the F28335 eZdsp target board. respectively (see Figure 4. In order to generate the code by using Matlab.4 µs.1). The Target Preferences block that was added to the model. like Digital Output and ePWM blocks. This pin is set to 1. some dedicated blocks were used.

In order to study the distribution of the losses amongst the inverter switches. only the outer IGBTs (S1 and S6 ) switch.5 kHz. 4.99). except from the double frequency modulation strategy. for both R and an RL load (PF = 0. the frequency of the carriers have been set to 15 kHz.4.1: Simulation parameters For all the modulation strategies. using the experimental setup from Figure 4.4 (on the next page). The thermal picture presented in Figure 4. Parameter DC-link voltage Switching frequency Load resistance Load inductance Modulation index Vdc fsw Rload Lload M Value 600 V 15 kHz 65 Ω 128 mH 1 Table 4. Another reason for their increased temperature compared to the ambient temperature is due to the presence of the nearby hotter switches (the switches are mounted on the inverter leg close one next to the other).1.3 Experimental results All five modulation strategies which have been simulated in Chapter 3.1 R load PWM-1 The experimental results which have been obtained for a resistive load using the PWM-1 modulation strategy are presented in Figure 4. the temperature is lower. manifested as heat. with approximately 10o C. the temperatures of S1 and S6 are the highest.1. due to the parasitic inductance of the load (the power factor read from the power analyser was PF = 0. also temperature measurements have been performed. 53 . All the tests have been performed only for the inverter mode of operation of the ANPC converter. Because in the semiconductor devices of the inverter which has been used in the laboratory tests. Because the inverter supplies a resistive load. while the inner pair (S3 and S4 ) suffers only conduction losses. It can be seen that due to higher power losses. both the IGBT and the diode are incorporated in the same case. where the carrier wave frequency was set to 7. The parameters used in the experimental tests are given in Table 4.4 confirms this uneven distribution in the power losses amongst the outer and inner switches. But. while for S3 and S4 . have also been tested experimentally. With the help of the thermal camera. caused by the current which passes through them during zero state. the two switches will suffer small losses.3. thermal pictures have been taken for each case. the switches S2 and S5 should not have any power losses. With the PWM-1 strategy.85). the temperatures measured with the thermal camera will represent the the sum of the power losses for both devices. and therefore should remain at room temperature. which have only conduction losses. The obtained experimental results are presented and discussed in the following sections.

pwm-1-r.Figure 4.5 (on the next page).5 confirms this uneven distribution in the power losses of the outer and inner switches. which have only conduction losses.4: Thermal picture of the ANPC inverter with R load for PWM-1 modulation strategy PWM-2 The experimental results which have been obtained for a resistive load using the PWM-2 modulation strategy are presented in Figure 4.jpg 54 . The thermal picture presented in Figure 4. while for S1 and S6 . With the PWM-2 strategy. while the outer pair (S1 and S6 ) suffers only conduction losses. the temperature is approximately 25o C lower. only the inner IGBTs (S3 and S4 ) switch. The increased temperature of S2 and S5 compared to the ambient temperature is due to the same reasons which are stated in the comments of the experimental results obtained for the PWM-1 modulation strategy. the temperatures of S3 and S4 are the highest. It can be seen that due to higher power losses.

that the values obtained for the temperatures of the switches are lower than those obtained with the classical modulations.5: Thermal picture of the ANPC inverter with R load for PWM-2 modulation strategy PWM-3 The experimental results which have been obtained for a resistive load using the PWM-3 modulation strategy are presented in Figure 4. It can be seen from Figure 4.Figure 4. the switching frequency and the modulation index were the same. pwm-2-r. because the distribution of the power losses between the semiconductor devices was of interest.6 (on the next page).6. This difference is due to the fact that the measurement of the temperature was performed for a shorter working time of the inverter (half. when compared to the measurements for the other strategies). especially since the tests have been performed for the same conditions. even if the load. A ratio of 50%-50% for the PWM-1 and PWM-2 working times determines a more balanced distribution of the power losses between the inner and outer switches. The thermal picture of the inverter leg controlled with the PWM-3 strategy presented in Figure 4.jpg This measurement is still valid. as the differences between the temperatures of the outer and inner switches are not as big as with the PWM-1 or PWM-2 modulations. 55 .6 confirms this improvement. The increased temperature of S2 and S5 compared to the ambient temperature is due to the same reasons which are stated in the comments of the experimental results obtained for the PWM-1 modulation strategy. compared to the classical strategies. and not the exact value of the losses.

The thermal picture of the inverter leg controlled with the PWM-DF strategy presented in Figure 4. the power losses of the switches would increase. If the frequency of the carrier waves in the PWM-DF modulation strategy would be double (equal to 15 kHz.7 confirms that this modulation brings an improvement to the loss balancing issue. S3 .7 (on the next page). With PWM-DF modulation strategy. pwm-3-r.jpg 56 . the difference between the temperatures of the inner and outer switches being reduced.6: Thermal picture of the ANPC inverter with R load for PWM-3 modulation strategy Double frequency PWM strategy The experimental results which have been obtained for a resistive load using the PWM-DF modulation strategy are presented in Figure 4. as for the cases of PWM-1 and PWM-2 strategies). S4 and S6 should be more balanced when compared to the classical strategies.Figure 4. when compared to PWM-1 or PWM-2 strategies. The increased temperature of S2 and S5 compared to the ambient temperature is due to the same reasons which are stated in the comments of the experimental results obtained for the PWM-1 modulation strategy. the distribution of the power losses between switches S1 .

which has an amplitude of 0.8.7: Thermal picture of the ANPC inverter with R load for PWM-DF modulation strategy Adjustable loss distribution PWM strategy The experimental results which have been obtained for a resistive load using the PWMALD modulation strategy are presented in Figure 4. where this difference is almost double. in comparison with PWM-1 or PWM-2 modulation strategies. Still.9 instead of using both reference signals and applying a 50%-50% Stress In/Stress Out ratio. shows that the difference between the temperatures of switches S1 and S3 is very small. The issue arises for the negative cycle of the reference signal. instead of being similar. the PWM-ALD strategy determines a more even distribution of the power losses amongst the switches. it can be concluded that this method brings an improvement to the loss balancing issue. With the PWM-ALD modulation strategy. it would be expected that the power losses of the inner and outer switches should be similar. where there is a bigger difference between the temperatures of switches S4 and S6 . This unsymmetry of the reference signals (unsymmetry of the modulation index) explains why the temperature of S6 lower than the temperature of Spwm-df-r. but only for the positive cycle of the reference signal.Figure 4. The thermal picture of the inverter leg which is presented in Figure 4. 57 . if the Stress In/Stress Out ratio would have been correctly implemented.jpg 1 .8 (on the next page). A detailed reinvestigation of the code implemented on the DSP shows that S6 uses only the reference signal from Stress In. So.

4.for PWM-2.13 .8: Thermal picture of the ANPC inverter with R load for PWM-ALD modulation strategy 4. 4. are presented in Figures 4.12 .10 .jpg 58 .85) for all the five strategies which have been presented in Chapter 2.3.for PWM-1.Figure 4.for PWM-3. pwm-ald-r.for PWM-DF and 4.2 RL load The experimental results which have been obtained with an RL load (PF = 0.11 .for PWM ALD (on the next pages). 4.9 .

jpg Figure 4.Figure 4.10: Thermal picture of the ANPC inverter with RL load for PWM-2 modulation strategy 59 .9: Thermal picture of the ANPC inverter with RL load for PWM-1 modulation strategy pwm-1-rl.

jpg Figure 4.Figure 4.12: Thermal picture of the ANPC inverter with RL load for PWM-DF modulation strategy 60 .11: Thermal picture of the ANPC inverter with RL load for PWM-3 modulation strategy pwm-3-rl.

5 59.8 49. the zero switches (S2 and S5 ) are expected to have more losses then compared to the R load case.7 58.2 40.4 42.5 55. because they carry a higher current during zero state.9 Table 4. The thermal pictures of the inverter for all the modulation strategies confirm this. the temperature measured with the thermal camera represents the the sum of both the IGBT and diode power losses.8 38.3 42. With an RL load.Figure 4.5 37. due to the stored energy in the inductance.4 38. In order to explain the uneven temperature distribution amongst the complementary switches.2. Because the diode is incorporated in the same case with the IGBT.2 Modulation strategy PWM-2 PWM-3 PEM-DF 34. PWM-2 and PWM-3 modulation 61 . with RL load also the diodes will conduct.6 45.3 40.6 65.7 39.9 38.5 43.4 41.8 51.6 66.8 47. manifested as pwm-ald-rl. Based on the the waveforms of the output voltages for PWM-1.8 37. Switch S1 S2 S3 S4 S5 S6 PWM-1 46 34.1 57.1 40.3 50.13: Thermal picture of the ANPC inverter with RL load for PWM-ALD modulation strategy The measured temperatures of the switches which have been obtained for all the discussed modulation strategies are summarized in Table 4.1 53.1 59 PWM-ALD 44. a more thorough investigation in the laboratory would be needed.jpg heat.2: The temperatures [o C ] of the switching devices obtained for the RL load Unlike the R load case.

14.14: The waveform of the output voltage (measured on the resistor) for RL load (PF =0. 4.04 0.01 0. The switches which conduct during the negative cycle are hotter than the switches which conduct on the positive cycle. so the switch S5 is hotter than S2 and the switch S4 is hotter than S3 .03 0.01 0. This unbalancing of the output voltage is also reflected in the temperature distribution amongst the switches.03 0.02 0.85) with PWM-1 modulation strategy 200 150 100 50 Amplitude [V] 0 -50 -100 -150 -200 -250 0 0.02 0.06 Time [s] Figure 4.06 Time [s] Figure 4.strategies1 .05 0.04 0.85) with PWM-2 modulation strategy The waveforms for the PWM-DF and PWM-ALD strategies are missing due to the limited amount of time for access in the laboratory 1 62 .15 and 4. 250 200 150 100 Amplitude [V] 50 0 -50 -100 -150 -200 -250 0 0. it can be seen that the amplitude of the voltage during the negative cycle of the reference signal is higher than the amplitude during positive cycle of the reference signal.16.15: The waveform of the output voltage (measured on the resistor) for RL load (PF =0.05 0. which are presented in Figures 4.

the temperatures measured with the thermal camera represent the the sum of the power losses for both devices. With the help of a thermal camera.04 0. The code for the control strategies which have been implemented on the DSP was generated using Matlab Simulink.03 0. have also been tested experimentally.85). both the IGBT and the diode are incorporated in the same case. an extension board for the control part of the inverter leg was developed.05 0. The inverter used in the experimental tests was a low voltage single-phase ANPC inverter developed by [7]. the laboratory setup is described. Because in the semiconductor devices of the inverter. In order be able to drive the switches with six independent signals. for both R and an RL load (PF = 0.3 (on the next page). due to the fact that in this case also the anti-parallel diodes will conduct.85) with PWM-3 modulation strategy 4. In the beginning of the chapter. manifested as heat. temperature measurements have been performed on the inverter. The communication between the DSP and the semiconductor switches is achieved through an interface which is compatible with this DSP board. the loss balancing is not as evident as for the resistive load. All the tests have been performed only for the inverter mode of operation of the ANPC converter.06 Time [s] Figure 4. In the case of the resistive load.01 0.250 200 150 100 Amplitude [V] 50 0 -50 -100 -150 -200 -250 0 0. The temperatures [o C ] of the switching devices obtained for the resistive load are summarized in Table 4. the experimental results confirm the simulation results obtained in the previous chapter in what concerns the distribution of the power losses (expressed as temperatures) amongst the switches of the inverter. The control of the inverter has been implemented on a TMS320F28335 eZdsp. In the case of the RL load (PF = 0.02 0. 63 .16: The waveform of the output voltage (measured on the resistor) for RL load (PF =0.4 Summary This chapter treats the laboratory implementation part of this report. and therefore their losses will add to the losses of the IGBTs.85). All five modulation strategies which have been simulated in Chapter 3.

3 78. This unbalancing of the output voltage is also reflected in the temperature distribution amongst the switches.9 42.7 57.1 57. So.5 Table 4.1 36.6 66.2 77.4 33.1 45 62.9 37. The waveforms of the output voltages have been measured.5 65.5 31.Switch S1 S2 S3 S4 S5 S6 PWM-1 70.3 68.3: The temperatures [o C ] of the switching devices obtained for the R load An uneven distribution of the temperatures amongst the complementary switches is obtained. and it can be seen that the amplitude during the negative cycle of the reference signal is higher than the amplitude during positive cycle of the reference signal.9 PWM-ALD 68.2 46.3 33.2 64.4 53.3 Modulation strategy PWM-2 PWM-3 PWM-DF 53.4 35.4 36.2 55.8 35. the switches which conduct during the negative cycle are hotter than the switches which conduct on the positive cycle. 64 .7 65.9 34.5 50.5 61.9 33.

this strategy allow by the use of an adequate modulation strategy. the switching sequences of PWM-2 strategy. the switching losses are redistributed amongst the inner and outer switches. By using these two modulations. the transferred power and switching frequency of the converter can be increased. Other two modulation strategies were presented. The general system was divided into three main blocks: the plant. This way. After a brief presentation of the types of power losses which can occur in semiconductor devices. by using more and different switching sequences in order to achieve the zero state. without having to increase the costs by replacing the switches with higher rated ones or bringing improvements to the cooling system. to achieve a more balanced distribution of the power losses between the semiconductor devices on the converter. power loss balancing is desired. there will always be an uneven distribution of losses between the inner and outer switches of the converter. the three-level converter concept was introduced. These two strategies also bring improvements to the loss unbalancing issue. hence bringing an improvement to the loss balancing issue. The two classical modulation strategies (PWM-1 and PWM-2) do not take advantage of the multiple possibilities of the ANPC topology to obtain the zero state. After the background an motivation of this project have been briefly presented. The third chapter contains the simulation part of the report.Chapter 5 Conclusions 5. the main goals and limitations were established. the structure of the simulation models was described. This way. in order to achieve an even distribution of the power losses amongst the switches of the converter. Several modulation strategies used for controlling the ANPC converter were presented. the single-phase 65 . In the beginning of the chapter. The switching sequences of PWM-3 are obtained by using for 50% of the reference signal’s period. Compared to the basic Neutral Point Clamped (NPC) converter. composed of the DC sources. the switching sequences of PWM-1 strategy and for the other 50%.1 Review of the main tasks The goal of this project was to investigate different modulation strategies for the Active Neutral Point Clamped (ANPC) topology. The main theoretical concepts which have been used throughout the entire report have been presented in the beginning of chapter 2. with focus on how the power losses are distributed amongst the switches. called PWM-3 has been investigated. as an improvement brought to the two-level structure. This strategy represents a combination of the two classical methods. namely PWM-DF [12] and PWM-ALD [10]. and therefore overcome the main drawback of the NPC. The Active Neutral Point Clamped (ANPC) topology was then described. A new modulation strategy. Due to the fact that the most stressed device will limit the current capability of the converter.

manifested as heat. Because in the inverter from the laboratory setup. Only power losses (total for the IGBT and anti-parallel diode) are provided by the implemented simulations. Because in the semiconductor devices of the inverter.85). the simulations have been repeated for this new situation. in order to check if for this low power level. for both R and an RL load (PF = 0. in order to study how the power losses are distributed amongst the semiconductor device of the converter and to discover the source of the unbalanced output voltage. Due to the fact that in the laboratory tests. the loss balancing is not as evident as for the resistive load. the IGBTs and the anti-parallel diodes are mounted in the same case. due to the fact that in this case also the anti-parallel diodes will conduct. their thermal model was implemented using PLECS Thermal Toolbox. where two reference signals are used. the same configuration of the semiconductor devices was used in the simulations. with a frequency of the carrier waves equal to 15 kHz (except the PWM-DF strategy. the maximum load which could be used with the available equipment was of 650 W. and a unity modulation index (except from PWM-ALD strategy. both the IGBT and the diode are incorporated in the same case. The code for the control strategies which have been implemented on the DSP was generated using Matlab Simulink. PWM-DF and PWM-ALD it can be seen that the total power losses are evenly distributed between the switches. In this case.ANPC converter and the load.2 Future work Because the experimental results which have been obtained for the RL load are not so clear. temperature measurements have been performed on the inverter.85). and therefore their losses will add to the losses of the IGBTs. From the simulation results it can be seen that as expected. All five modulation strategies which have been simulated in Chapter 3. With the help of a thermal camera. the experimental results confirm the simulation results obtained in the previous chapter in what concerns the distribution of the power losses (expressed as temperatures) amongst the switches of the inverter. the laboratory setup was described. the behaviour of the semiconductor switches in the simulations is similar to the behaviour of the semiconductor switches which have been used in the laboratory tests (IRG4PC40FD). the modulator block and the losses calculation block. 5. The losses of the converter are presented as the power losses of the IGBT and anti-parallel diode summed for each of the devices. hence loss balancing amongst the switches of the inverter was not achieved. In the case of the resistive load. it could be of interest to perform more tests for this type of load. In the case of the RL load (PF = 0. In the beginning of the chapter. while the other has M = 0. with PWM-1 and PWM-2. the issue of loss balancing is still valid. The fourth chapter presents the laboratory part of this report.5 kHz). In this way. the main drawback of the NPC topology is not overcome by the ANPC. All the tests have been performed only for the inverter mode of operation of the ANPC converter. This information is enough if the purpose of the analysis is to 66 . This unsymmetry was also reflected in the temperature distribution amongst the switches. In order to be able to calculate the power losses of the inverters’ switches. an unbalancing of the output voltages has been observed on the oscilloscope. With PWM-3. have also been tested experimentally. the temperatures measured with the thermal camera represent the the sum of the power losses for both devices. The final chapter of the report contains the conclusions and ideas for future work. for both R and and RL load (PF = 0. where the frequency of the carriers was set to 7. one having M = 1. All the modulation strategies which have been presented in the previous chapter have been simulated for a 10 kW resistive load.85).9).

simulations and experiments could be performed for different Stress In/Stress Out ratios. like: • semiconductor switch modelled by separate IGBT and diode. By building a new converter leg.study the way that the losses are distributed amongst the switches of the inverter for a resistive load. which has the IGBT and diode mounted separately could allow a more detailed analysis of the power distribution. Due to the fact that the converter which has been used for the laboratory test was not build for loss balancing analysis purposes. The ANPC converter is used for high power medium voltage drives for industry. 67 . In this case it is impossible to analyse only the IGBT power losses. for example. In order to study better the advantages of PWM-ALD strategy. In order to perform a more thorough investigation. and for loads with different power factors. the switches which have been used have the IGBT and the anti-parallel diode mounted in the same case. some improvements could be brought to the simulations. and so it would be of interest to study the loss balancing modulation strategies on a machine load. especially for RL loads. • evaluation of the temperature in the simulation.

.

John Wiley & Sons Inc. Issue 3. H. Inhrent Correlation Between Multilevel Carrier-Based PWM and Space Space Vector PWM:Principle and Application. [5] Bin Wu. Application Note v 1. [9] B. Bruckner. Power Electronics Handbook. Modulation of Three Level Inverter with Common Mode Voltage Elimination and DC Link Balancing. Aalborg University. ISBN 0-7803-7233-6. 20-24 September 2009. 2001 [7] Maciej Swierczynski. Pages 674 . Natural Doubling of the Apparent Switching Frequency using Three-Level ANPC Converter. Volume IA-17. Marco Purschel. D. Takahashi. IGBT Power losses Calculation Using the Data-Sheet Parameters. A Comparison of Multicarrier PWM Strategies for Cascaded and Neutral Point Clamped Multilevel Inverters. ISBN 13-978-0-471-73171-9. June 2005. Floricau. Pages 855-868. pages 1-6.281. [11] Ionut Trintis. McGrath. Bernet.679. Issue 5. S. [4] Graovac Dusan. 2008. M. ISBN 978-1-4244-2893-9. Xiangning He. Andrzej Adamczyk. ISBN 978-1-4244-2129-9. [13] eZdspT M F38335 Technical Reference. ISBN 0-7803-5692-6. Pages 1135-1140. H. First Edition. Bernet. Nabel. Acadamic Press. IEEE Transactions on Industry Applications. IEEE Energy Conversion Congress and Exposition. Holmes. [3] T. Aalborg University.G. Akagi. I. Volume 2. Proceedings. 2001. 2009. [12] D. Bruckner. Marco Liserre. pages 920 . E.. High-Power Converters and AC Drives. Pages 518-523.1. The Active NPC Converter and Its Loss-Balancing Control. S. Guldner. IEEE 31st Annual Power Electronics Specialists Conference. A New Neutral-Point-Clamped PWM Inverter. January 2009. 10-13 June 2008. First Edition. [6] Muhammad H. Floricau. 2006. 69 . Remus Teodorescu. September 1981. Rashid. 22-25 October 2001. Tamas Kerekes. IEEE Transactions on Industrial Electronics. [10] Lin Ma. pages 276 . Infineon Automotive Power. Xinmin Jin. 18-23 June 2000. Volume 52 . [8] Hongyang Wu. [2] A. International School on Nonsinusoidal Currents and Compensation. Pedro Rodriguez.Bibliography [1] T. 4th IEEE International Conference on Power Electronics and Drive Systems. Loss Balancing in Three-Level Voltage Source Inverters Applying Active NPC Switches. Active Neutral Point Clamped Converter. volume 1.927. Dumitrescu. Volume 2. IEEE 32nd Annual Power Electronics Specialists Conference. The PWM Strategies of Grid-connected Distributed Generation Active NPC Inverters.P.

htm [cited on 16 April 2010].Technical Info. 70 .uk/technical technical 01.hsmarston. [16] PLECS User manual. Available from http://www.2.co.[14] International Rectifier. Insulated Gate Bipolar Transistor with ultra fast soft recovery diode IRG4PC40FD . 2009. [15] HS Marston Aerospace. Version 2.Datasheet.Heat Sinks for Electronics Cooling .

The switching frequency is 15 kHz and the load is a 3 kW R load (PF = 1). For this calculation. as presented in Equation A. preventing them from becoming too hot.2 [4].Appendix A Heat sink selection A very important aspect in converter design is the selection of the cooling system for the semiconductor devices. 2 S The forward resistance can be calculated from the transconductance as: rC = 1 = 0.1. Iavg is the average current through the device [A]. the total power losses of the semiconductor device need to be calculated.1) The conduction losses can be calculated from Equation A. the inverter is considered to be controlled with the PWM2 modulation strategy. In order to better observe the temperature of each switch.3) 71 . which stresses the most the semiconductor devices. The losses in the semiconductor device are represented by conduction and switching losses for both the transistor and the antiparallel diode.2) where Vf is the forward voltage drop at zero current [V]. The purpose of the heat sink is to dissipate the heat generated by Joule effect due to the current which passes through the devices. Ploss = Pcond + Psw [W ] (A. individual heat sinks are going to be mounted. The forward voltage drop Vf and the forward transconductance are provided in the datasheet of the selected semiconductor device (IRG4PC40FD) [14]: VCE 0 = 0. 2 Pcond = VCE 0 · ICav + rC · IC rms [W ] (A. especially the inner switches. The most handy solution is to passively cool the switches by mounting them on a heat sink. rf is the forward resistance [Ω] and Irms is the rms value of the current through the device [A]. which would lead to their destruction. 11 Ω gC The switching losses can be calculated from Equation A.3 [4]: Psw = 1 fsw T Tsw e(i)dt 0 [W] (A. For choosing the heat sink. 9 V gC = 9.

5 4. The losses in these devices will be considered for sizing the heat sink.1: Typical switching losses versus the collector-to-emitter current In order to analytically calculate the power losses.2 and A. switching frequency.5 0 0 5 10 15 Total switching energy losses [mJ] y = 0.5 4 3.1 Table A. e(i) is the total switching energy losses for the IGBT together with the reverse recovery diode [J]. T is fundamental voltage period [s].181x + 0. with PWM-2 modulation strategy the inner switches (S3 and S4 ) are the most stressed. a Matlab Simulink simulation model has been developed (see Figure A. the current through the device is approximately 4 A.5 1 0.1: Total power losses of the semiconductor devices As it can be seen from Table A.5). as presented in Figure A. the calculation can also be performed also for other operating conditions of the inverter (different load. This way. the given graph has been extended. for currents above 13 A. etc. In order to size the heat sink the equivalent electrical model of thermal behaviour for the selected switch is considered (see Figures A. Tsw is the switching period [s]. In the IRG4PC40FD datasheet [14] it is provided a chart for the total switching losses versus the collector-to-emitter current.1.) The values of the total inverter losses for each semiconductor device are given in Table A.5 3 2.1.1 S2 0 S3 25 S4 25 S5 0 S6 6.where fsw is the switching frequency [Hz].1.5 2 1.3 on the next page) [15].11 R² = 0. Switch Total power losses [W ] S1 6. 72 .4 and Figure A. Due to the fact that in the considered operating conditions. modulation technique. The other heat sinks are going to be selected to be identical.9997 20 25 30 Collector‐to‐emitter current [A]   Figure A.

Tc .  Figure A. power resistors. Th . but can be neglected in a first approximation. • the presence of any other heat source nearby (like other sinks. • the calculations do not take into account that there are other paths of heat (between the device and the ambient). The aim of the calculations is to assess the maximum junction temperature of the semiconductor. which should be represented in the scheme by additional resistances. Tj . The model and the resulting equations are approximate. Rch . The temperature difference between the nodes is treated as a voltage drop on the equivalent thermal impedance. convection and radiation.case-to-heat sink resistance [o C/W ]. the temperatures are seen as node potentials. 73 .temperature of the case [o C ]. etc.temperature of the heat sink [o C ].2: Device and heat sink physical model Tj Rjc P Tc Rch Th Rha Ta Figure A. Ta ambient temperature [o C ]. mainly because [15]: • the heat transfer process is static or slowly varying over time (order of magnitude of seconds). where: Q . due to the carried losses [15]. • the event of heat transfer (especially between the heat sink and the ambient) is nonlinear because it involves simultaneously heat transfer by conduction.junction-to-case resistance [o C/W ].junction temperature [o C ]. Rha is heat sink-to-ambient resistance [o C/W ] In the equivalent electrical model.) reduces the cooling efficiency.3: Equivalent electrical model for a semiconductor device. • it is a model that has been simplified to one-dimension.heat source which has a current source as an electrical correspondent [W]. Rjc .

4 [15].5 [15].The junction-to-case resistance Rjc and the case-to-heat sink resistance Rch are given in the datasheet of the semiconductor device IRG4PC40FD [14]: Rjc = 0. 77 o C/W Rch = 0. The heat sink-to-ambient resistance. Tjmax − Ta = P · (Rjc + Rch + Rha ) [o C ] (A.4) The required minimum thermal resistance for the heat sink can be determined from Equation A. Rha = Tjmax − Ta − (Rjc + Rch ) P [o C/W ] (A. Rha can be evaluated using Equation A.5) The value which is obtained for the thermal resistance of the heat sink is Rha = 5 o C/W 74 . 24 o C/W The maximum working temperature of the junction is Tj = 150 o C and the ambient temperature is considered Ta = 25 o C .

02 PsS1 Cond_Losses S2 PsS3 0.03 PsS4 Total_Losses S4 Cond_Losses S4 Rthjc Tj Rthcs Ta PcS3 Figure A.158 PsS5 Total_Losses S5 0.06312 Swit_Losses S5 18.93 Swit_Losses S3 0 PsS3 Total_Losses S3 0.094 Cond_Losses S1 PcS1 PcS1 6.0055 Swit_Losses S6 PcS4 25.0055 PsS2 PsS5 0.0631 PcS5 Swit_Losses S1 PcS3 PcS1 Is1 Is1 PcS2 PcS2 PcS3 Is2 Is2 PcS4 PcS4 PcS5 Is3 Is3 PcS6 PcS6 PsS1 Is4 Is4 PsS2 PsS2 PsS3 Is5 Is5 PsS4 PsS4 PsS5 Is6 Is6 PsS6 PsS6 0 Cond_Losses S6 PcS6 0.4: Matlab Simulink simulation model for heat sink calculation PsS3 .094 Cond_Losses S3 PcS3 25.6.995 Rth [°C/W] 6.157 PsS1 Total_Losses S1 6.94 Swit_Losses S4 0.095 4.095 Cond_Losses S5 PcS5 6.0055 Swit_Losses S2 Total_Losses S2 PcS2 18.0055 PsS6 Total_Losses S6 6.

subsystem 76 .5: Matlab Simulink simulation model for heat sink calculation .001 f_switching 7 PsS1 Imean fcn e 8 PsS2 9 PsS3 10 PsS4 11 PsS5 12 PsS6 fref Figure A.1 Is1 2 Is2 3 Is3 4 Is4 5 Is5 6 Is6 0 In Mean signal rms 1 PcS1 1/gfe 2 PcS2 sqrt 3 PcS3 4 PcS4 Uce0 5 PcS5 6 PcS6 0.

and all the drive signals are routed to it. like in the case of PWM-DF and PWM-ALD modulation strategies.32k R4 15k HFBR 2521z VCC U3 5 8 A 9 R1 CON6A 4. In order not to perform any hardware modifications on the inverter leg. 2010 2 HFBR 2521z A Rev 1. This feature became a limitation in some situations.1. To overcome this limitation.12k J2 1 3 5 NC NC RL VCC GND Vo 4 3 2 1 C3 100n C10 100p PED2-840. another three opto receivers have been added. an extension board containing the extra opto receivers has been built.12k 2 4 6 CON6A R3 7. May 21. while the remaining three complementary signals were generated hardware by using a dead time generator. 5 4 3 2 1 VCC C4 100u 18 U5 D C5 100n U4 R ENAR 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 con18 VCC UU UL NU NL BU BL OSC RC IN 18 17 16 15 14 13 12 11 10 18 17 16 15 14 13 12 11 10 D R S T RC IN ENAR ENAS ENAT RESET OUTPUT ENA 1 3 5 10 2 4 6 8 7 VCC R S T RU RL SU SL TU TL GND OSCOUT 17 16 15 14 13 12 11 UU NU S ENAS T RCIN ENAR ENAS ENAT RST OUTEN IXDP630 BU OSC ENAT OUTPUT ENA RESET GND C 9 C VCC U1 5 8 NC NC RL VCC GND Vo 4 3 2 1 VCC VCC C8 100n U9 1 3 5 6 9 8 4 3 2 1 1A 2A 3A 3Y 4A 4Y 14 2 13 12 4 11 10 18 U6 1 3 5 10 ENAR ENAS ENAT RESET OUTPUT ENA 2 4 6 8 7 R S T C6 100u C7 100n C1 100n HFBR 2521z VCC U2 B VCC 1Y 6A 6Y 2Y 5A 5Y VCC GND RU RL SU SL TU TL GND OSCOUT 17 16 15 14 13 12 11 1 3 5 UL NL B NC NC 8 RL VCC GND Vo 7 5 74HC04 C2 100n RCIN ENAR ENAS ENAT RST OUTEN IXDP630 J1 BL 2 4 6 R2 4. where the switches needed to be controlled individually. and then re-routed to the inverter leg through the pins where the dead time generator was.Appendix B Extension interface board The ANPC converter [7] was build to be driven with three optical signals. Spring 2010 Title Extension interface for A/NPC Size A Date: Document Number Friday.1 Sheet 1 1 of 1 5 4 3 Figure B. The diagram and the PCB layout o the extension board can be seen in Figure B. therefore requiring six independent switching signals.1: The circuit diagram of the extension interface board 77 .

Figure B.2: The PCB layout of the extension interface board 78 .

Instrument 300 V.PERES 79059 56061 29511 29512 35596 Table C. 3 A DC Power Supply Load Resistor Load Inductor Single-Phase Power Analyser Type Delta Elektronika GW-INSTEK GPS-4303 4 ASEA Education AB-5514 152-B ASEA Education Voltech PM 100 AAU inventory code GPL . 5 A DC Power Supply 24 V.1.Appendix C List of used laboratory instruments The instruments which have been used for the laboratory test setup are given in Table C.1: Laboratory instruments 79 .

.

this folder contains the articles used as reference in the report. the Code Composer projects and the thermal pictures of the inverter 81 .this folder contains the Simulink models used for generating the code for DSP implementation. when available in electronic format • Simulations .Appendix D Contents of the enclosed CD The enclosed CD contains: • Report .this folder contains the the report in PDF format • References .this folder contains the simulation files • Laboratory implementation .

Sign up to vote on this title
UsefulNot useful