INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS Int. J. Circ. Theor. Appl.

2011; 39:783–790 Published online 29 April 2010 in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.659

A fully-integrated CMOS UWB transceiver for ultra-low-power short-range application
Mengmeng Liu∗, † , Sheng Zhang, Shuo Wang and Runde Zhou
Institute of Microelectronics, Tsinghua University, Beijing 100084, People’s Republic of China

SUMMARY In short-range UWB communication systems, the low-power design is the most important issue to make UWB technology attractive. A novel trigger receiving algorithm for UWB signals is proposed, which can reduce the system power significantly at the cost of slight performance degrade. A UWB transceiver based on the trigger receiving algorithm is designed and fabricated in HJTC 0.18 m CMOS process with a total size of 0.45 mm2 . The experimental results show that the total power consumption of the transceiver is only 12 mW at 100 Mb/s data rate from a 1.8 V supply, making it suitable for low-power short-range communication. Copyright ᭧ 2010 John Wiley & Sons, Ltd.
Received 6 July 2009; Revised 24 September 2009; Accepted 10 October 2009 KEY WORDS:

UWB transceiver; low power; short range

1. INTRODUCTION UWB is recognized as a high-speed, low-power communication technology that can coexist with other wireless systems, £which attracts much interest of researchers [1, 2]. Owing to its strictly limited transmitted power, UWB has no advantages in long-range communication, while in the short range, UWB becomes an attractive choice. However, even if in short range, some nonideal factors, such as multipath and narrow band interference, make UWB costly to realize high-speed data transmission, resulting in high-power dissipation and large chip area [3–5]. Whereas, in shortrange systems especially portable systems, low-power and little chip area are more important than the ultra-high data speed, UWB technology seems competent in these systems: first, since UWB has huge capacity margin in short range due to its wide bandwidth, the performance degrade brought by structures with low power, low complexity is negligible and can be easily compensated; second, in short-range moderate speed application, multipath is not a thorny problem any more; third, the characteristic of UWB pulses makes some low-complexity processing method and architecture practicable, bringing low power and low cost. Thus, UWB technology is very attractive in low-power short-range application; moreover, the IEEE 802.15.4a has greatly encouraged the development of UWB applications in such field [6]. This paper aims at low-power short-range UWB systems, proposes a transceiver based on a novel trigger receiving algorithm, which can be implemented and integrated much easily with ultra-low power. The trigger receiving algorithm is discussed in Section 2, its characteristic of ultra-low power is analyzed and demonstrated by simulation. Based on the algorithm, a UWB transceiver
∗ Correspondence

to: Mengmeng Liu, Institute of Microelectronics, Tsinghua University, Beijing 100084, People’s Republic of China. † E-mail: liumm06@mails.tsinghua.edu.cn Copyright ᭧ 2010 John Wiley & Sons, Ltd.

thus. the high level.1002/cta . especially for ultra-low-power case: v ≈ max {s (t )} ≈ max {s (n )} 0 t <Tb 0 n < Nb (2) Equation (2) corresponds to the receiver depicted in Figure 1. Hence. What’s more. E b increases about 1 dB if the number of samples Nb increases 10 times by trigger receiver. 39:783–790 DOI: 10. the receiver sample rate f s is much higher than the data rate Rb . This receiving method is called trigger receiving algorithm. in UWB systems. in UWB systems. 2. with the Nb increased by 10 dB. the trigger receiving algorithm. Luckily. However. the trigger receiver has a power consumption proportional to Tb . is much lower than the signal bandwidth. f s = 2 GHz. the conventional correlation receiving algorithm is widely used for receiving UWB signals [3–5]. whereas E b is not relevant to Nb by the traditional correlation receiver. Theor. Int. respectively. the whole systems can achieve same performance but much lower power dissipation using trigger receiver in short-range moderate speed UWB systems. Since short-range moderate speed UWB systems have low Spectrum utilization and wide bandwidth. As long as the received signal s (t ) surpasses the threshold of the comparator (CMP) at any moment during the data period Tb .18 m CMOS technology. Ts is the sampling period. in short-range moderate speed UWB systems. Nb 1 is always satisfied. Block diagram of trigger receiver. J. however. the trigger one has a 20 dB lower power consumption. using trigger receiver and correlation receiver. Nb = Tb / Ts denotes the number of samples in each data period. TRIGGER RECEIVING ALGORITHM In most UWB systems. the transmitted power is quite low. i. where Rb = 1/ Tb . which can be expressed as v= 0 Tb T (t )s (t ) dt ≈ T (n )s (n ) 0 n < Nb (1) where Tb is the period of receiving data. is designed and fabricated in 0. it is observed that the sample rate or working frequency of the digital correlation receiver is f s = 1/ Ts even if there are no signals at that moment. the data rate.g. which means in most of the time. The design and the measurement of the transceiver are presented in Sections 3 and 4. e. As a consequence. whereas the performance is only decreased by only 1 dB. LIU ET AL. From Equation (1).e. as depicted below in Equation (2). the receiver has no input but is still operating. signal bandwidth BW = 1 GHz. Ltd. respectively.g. is very suitable for such systems. 20 Mbps. Figure 2 shows the performance of pulse UWB system under the binary symmetric AWGN channel and OOK modulation. Circ. compared with the correlation receiver. The trigger receiver works at the frequency of the data rate Rb . or Tb = 50 ns.784 M. which is much lower than the sample rate of the correlation receiver f s mentioned above. As a result. e. value 1. 1 GHz. it is obvious that the trigger receiving algorithm is much simpler to implement than the correlation receiving algorithm. which is reduced Nb times compared with the correlation receiver. we can get Nb = 100. The simulation results indicate that when Nb = 1. 1 dB of which is negligible considering 10 dB of power consumption of the receiver. wasting much power with little significance. In other words. s(t) CMP trigger Y Figure 1. From Figure 1. can be triggered to output Y . the performance of trigger receiver and correlation receiver are the same. T (·) and s (·) are local template and received signal. Copyright ᭧ 2010 John Wiley & Sons. Suppose Rb = 20 Mbps. the power consumption of the trigger receiver is reduced by 10 dB. Appl. resulting a power consumption proportional to Ts . 2011. when the bit-error-rate Pb is below 10−2 .

1. The regulated controlling voltage can set the transistor current I D . whereas the core of the receiver is trigger receiver and the rest include auto-gain-control (AGC) loop and demodulator. 2011. Appl. Phase-lock-loop (PLL) generates the multiple frequency clock from the baseband clock clk for receiver digital baseband process. leading to low power and low cost. D in Figure 5) are set by a charge pump regulated by the digital back-end. Theor. high-resolution ADC and the complicated synchronization process in the baseband. the block diagram of which is described in Figure 3. Int. TRANSCEIVER ARCHITECTURE AND CIRCUIT DESIGN Based on the trigger receiving algorithm discussed before. VGA uses gate-controlled MOS channel resistance to obtain variable gain. Considering baseband data TXD lags the rising edge of the baseband clock clk. 3. consequently. 3. The frequency of receiver clock clk3 is triple the baseband clock clk only to make the digital baseband algorithm.1002/cta . preventing unexpected glitches generated by the gate-controlled clock. the first register will be set to high level asynchronously. Trigger receiver Figure 5 depicts the schematic of the VGA and the trigger receiver. aiming at ultra-low-power short-range moderate speed communication. When a negative-phase pulse arrives at node opl or oph in Figure 5. 3. whose dynamic range is designed as 40 dB. the output of the nor-gate is not influenced by the transition of baseband data. the pulse width. mulipath remove etc. J. Pulse generator UWB pulse generator is shown in Figure 4. and the gain control signals (U .A FULLY-INTEGRATED CMOS UWB TRANSCEIVER 785 Figure 2. avoiding frequent unwanted overturn. The transmitter is mainly comprised of pulse generator. whose delay is verse-proportional to the transistor current from the relationship t p = C L VDD /2 I D . Compared with correlation receivers. When the rising Copyright ᭧ 2010 John Wiley & Sons. Ltd. Performance of trigger receiver and correlation receiver.2. such as phase-offset correct. CMP utilizes hysteresis structure to suppress the noise. 39:783–790 DOI: 10. A narrow pulse is created at every rising edge of gate-controlled clock. which will be discussed later. Circ. efficient. which is not indispensable to the analog parts of the transceiver. the proposed trigger receiver does not need high-speed. the baseband working frequency is quite lower. what is more. as described on the top of Figure 5. The transceiver integrated the whole circuits from digital baseband blocks to UWB antenna. a pulse UWB transceiver is designed. The controllable delay unit is implemented by current-starved inverters.

Appl. Block diagram of UWB transceiver. realizing the synchronous receiving of asynchronous data. this register will be synchronously reset. edge of clk3 arrives. Ltd. Theor. and at the same time data propagate to the second register. Schematic of pulse generator. Schematic of the VGA and trigger receiver. 2011. LIU ET AL. RFI VGA Trigger receiver Gain control Demodulator RXD PLL Receiver CLK RFO Pulse generator Transmitter TXD Figure 3.786 M. Circ. U Vbm D Vbl + CMP + Vbh CMP CP vga + opl in Vbn out ip rfip oph rfin VGA CMP Vbh Vbm vga Vbl D Vbcn Vbn Vbn in ip vga U Vbcp out CP oph opl bias psyn Q VGA 0 L D SET Q D SET CLR Q CLR Q clk3 clk3 pulse-detector Figure 5. Int. enabling the operation of the following digital process parts. TXD clk RFOn CL Vctrl gated clk RFOp Figure 4. Copyright ᭧ 2010 John Wiley & Sons.1002/cta . J. 39:783–790 DOI: 10.

and voltage-controlled ring oscillator comprised of current-starved inverter chain [7]. including gain control module and demodulator. Phase-lock-loop PLL uses baseband clock clk to generate triple frequency clock clk3 as the main working clock for the receiver. The die photograph is shown in Figure 8. The experimental results show that the whole transceiver consumes 4 mW from 1. digital back-end of the system is also full-custom designed with low-complexity baseband algorithm.45 mm2 . leading to additional cost. 2011.4.3. The receiver was tested with UWB pulses of peak voltage of 10 mV.5 and 10 ns. phase frequency detector (PFD). Schematic of PLL. The core block is mainly comprised of transmitter and receiver. Theor. The low-pass filter comprised of resistor and capacitance in series is put outside the chip. 39:783–790 DOI: 10. PLL is comprised of 3-divider. Appl. the gain control module generates the control signals U . The gain control module and the demodulator are pure digital circuit designed for baseband process. Int.18 m CMOS process. 3. including 20 pads. current pump (CP). The demodulator corrects the phase-offset between the clock of transmitter and the receiver.8 V supply at the data rate of 40 Mb/s whereas 12 mW at the data rate of 100 Mb/s. More tests show that the width of the pulse can be adjusted between 0. All the circuits are designed only by CMOS active devices. as shown in Figure 6. The measured output of receiver corresponding to input data pattern is shown in Figure 11. whereas receiver can be divided into two parts: RF front-end and digital back-end (here we consider PLL as a part of the digital back-end). the absence of inductor and capacitor makes chip area as small as only 0. Digital back-end of receiver In order to achieve ultra-low-power consumption of the transceiver. The tested dynamic range of Copyright ᭧ 2010 John Wiley & Sons. 3. EXPERIMENTAL RESULTS The UWB transceiver aiming at ultra-low-power short-range moderate speed communication is implemented in HJTC 0. the spectrum can be compliant with the mask allowed for UWB communication. and then obtains the final data rxd. D according to the occurrence probability of data Y = 1. The measured PN sequence of UWB pulse at the load of 50 and the pulse details are shown in Figures 9 and 10.1002/cta . As shown in Figure 7. Ltd. respectively. J. targeting at the occurrence probability of 1 and 0 are both 50%. With an off-chip filter or band-pass antenna.A FULLY-INTEGRATED CMOS UWB TRANSCEIVER 787 clk 0 Q Vbcp D Q vco 0 D Q Vbcn Q Vbcn PFD CP VC O clk1 Q D Q D Q Q clk3 3-divider Figure 6. the bandwidth is about 200 MHz–4 GHz. 4. Circ.

In Figure 12. The measurement also shows that when BER is about 0. 2011. Die photograph for pulse UWB transceiver. J. Schematic of gain control module and demodulator.1%. which accords with Figure 12 generally. The comparison between the proposed transceiver and other works in [3–5. Figure 7. 39:783–790 DOI: 10. LIU ET AL. the BER at 40 Mbps data rate is depicted. 8] are listed in Table I. Appl. the communication distance can be even further. the communication distance can be extended to 1 m at the data rate of 40 Mbps.1002/cta . Ltd. Figure 8. where the signal power is regulated by controllable attenuator. Int. It is obvious that the proposed UWB transceiver has lower bit-power dissipation per Copyright ᭧ 2010 John Wiley & Sons.788 M. Theor. Circ. the receiver is 30 dB. When the data rate declines.

Circ. Theor. Copyright ᭧ 2010 John Wiley & Sons.A FULLY-INTEGRATED CMOS UWB TRANSCEIVER 789 Figure 9. unit voltage and smaller size. which makes it suitable for short-distance low-power wireless applications. Figure 11.18 m CMOS process. and implemented only by CMOS active devices. Figure 10. The proposed transceiver with a size of only 0. Transmitted pulse details.1002/cta . CONCLUSION In this paper a novel low-power UWB transceiver for short-range communication based on the trigger receiving algorithm are presented. Int. Measured output at the receiver (data out is delayed). Appl. J.45 mm2 is full-custom designed in 0. whereas the data speed is moderate. Ltd. 39:783–790 DOI: 10. Measured PN sequence of UWB pulses. 5. 2011.

Lacy C.790 M.4a UWB transceiver for communication and localization. Table I. 39:783–790 DOI: 10.5 Power supply (V D D ) (V) Data rate ( Rb ) 100 Mb/s 1 Gb/s 16. CA. Ltd. Kaltiokallio M. Recent system applications of short-pulse ultra-wideband (UWB) technology.1002/cta . Theor. San Francisco. Zheng Y. A 2. Fontana RJ. 4.65V 3-to-5 GHz subbanded UWB receiver in 90 nm CMOS. Carnevali S.4a Task Group. IEEE 802. A 0. Int. 214–216.18 0.1 to 5 GHz CMOS DSSS UWB transceiver for WPANs.7 GHz WiMedia UWB RF/analog front-end in 130 nm CMOS. 7. making it a good choice for short-range low-power communication. Appl. UWB transceiver This work [3] [4] [5] [8] Process ( m) 0.html. IEEE ISSCC.1–4. Lee FS. IEEE ISSCC. Analysis and design of common-gate low-noise amplifier for wideband applications.4 nJ/V2 3. Low power UWB pulse radio transceiver frontend. 52(9):2087–2104. 2007. REFERENCES 1.15. Munich. LIU ET AL. 0. IEEE RFIC. Griffiths B et al.8 V supply at the data rate of 100 Mb/s. Chandrakasan AP.45 5 2.7 Mb/s 62. IEEE Transactions on Microwave Theory and Techniques 2004. 118–120. 8. Annamalai Arasu M. Belabbes N. Yu M et al. 3. 2005.4 Mb/s 8 Mb/s Power consumption ( P ) (mW) 12 385 38 728 2. Copyright ᭧ 2010 John Wiley & Sons. Demirdag C. 2007. Available from: http://www. Ryynanen J. Anis M. ESSCIRC.15. 6.8 0.6 2 ) 37 pJ/V2 120 pJ/V2 5. Shoji N. CA. Lynch MW. Yoshikawa N. 2011.1 (active area) The overall power consumption of the transceiver is 12 mW from a 1.09 0. A 3. Iida S. International Journal of Circuit Theory and Applications 2009.1 BER 0. Comparison among UWB transceivers. Suzuki H.18 0. Wong K-W.18 1. 131–134. 37(2):257–281. Kaukovuori J.18 0. Circ. IEEE ISSCC.8 1. ieee802. Average BER at 40 Mbps. 2.65 1.01 1E-3 0 5 10 15 20 25 Eb/n0 Figure 12. Tielert R. 207–210. Tanaka K. 116–118.5nJ/b 0. Honolulu.18 m CMOS 802. Hawaii. 2007.2 4. 2008.8 1.6 nJ/V2 144 pJ/V2 Bit-power dissipation per unit voltage ( E d / VDD Chip area (mm2 ) 0. 5.org/15/pub/TG4a. 2007. 3. J. San Francisco.5 3.

Sign up to vote on this title
UsefulNot useful