3.

Boolean Algebra and Logic Gates

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Chapter 3 Boolean Algebra and Logic Gates
Algebraic Properties  A set is a collection of objects with a common property.  A binary operator on set Ë is a rule that assigns to each pair of elements in Ë another unique element in Ë .  The axioms (postulates) of an algebra are the basic assumptions from which all theorems of the algebra can be proved.  It is assumed that there is an equivalence relation (=), which satisfies the principle of substitution.  It is reflexive, symmetric, and transitive.  Most common axioms used to formulate an algebra structure (e.g., field): 6 Closure: a set Ë is closed with respect to ¯ if and only if Ü Ý ¾ Ë ´Ü ¯ Ý µ ¾ Ë .

6 Associativity: a binary operator ¯ on Ë is associative if and only if Ü Ý Þ ¾ Ë ´Ü ¯ Ý µ ¯ Þ Ü ¯ ´Ý ¯ Þ µ .

6 Identity element: a set Ë has an identity element with respect to ¯ if and only if ¾ Ë such that Ü ¾ Ë ¯ Ü Ü ¯ Ü . 6 Commutativity: a binary operator ¯ defined on Ë is commutative if and only if Ü Ý ¾ Ë Ü ¯ Ý Ý ¯ Ü .

6 Inverse element: a set Ë having the identity element with respect to ¯ has an inverse if and only if Ü ¾ Ë Ý ¾ Ë such that Ü ¯ Ý . 6 Distributivity: if ¯ and ¾ are binary operators on Ë , ¯ is distributive over ¾ if and only if Ü Ý Þ ¾ Ë Ü ¯ ´Ý¾Þµ ´Ü ¯ ݵ¾´Ü ¯ Þµ .

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c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005

3. Boolean Algebra and Logic Gates

3-2

Axiomatic Definition of Boolean Algebra  Boolean algebra: an algebraic system of logic introduced by George Boole in 1854.  An Investigation of Laws of Thought on which are Founded the Mathematical Theories of Logic and Probabilities, Macmillan (Dover, 1958)  Switching algebra: a 2-valued Boolean algebra introduced by Claude Shannon in 1938.  A Symbolic Analysis of Relay and Switching Circuits, MS Thesis, MIT  Huntington postulates for Boolean algebra: defined on a set with binary operators + & ¡, and the equivalence relation = (Edward Huntington, 1904): x (a) Closure with respect to +. (b) Closure with respect to ¡. y (a) Identity element 0 with respect to +. (b) Identity element 1 with respect to ¡. { (a) ¡ is distributive over +. (b) + is distributive over ¡. and (b) Ü ¡ Ü
Ü

z (a) Commutative with respect to +. (b) Commutative with respect to ¡. |

¾

Ü
¼

¼

¾

(called the complement of Ü) such that (a) Ü · Ü .

¼

½

¼.

} There are at least 2 distinct elements in 

The axioms are independent; none can be proved from the others.  Associativity is not included, since it can be derived (for both operators) from the given axioms.  In ordinary algebra, + is not distributive over ¡.  No additive or multiplicative inverses; no subtraction or division operations.  Complement is not available in ordinary algebra.  is as yet undefined. It is to be defined as the set 0,1 (two-valued Boolean algebra). 

In ordinary algebra, the set Ë can contain an infinite number of elements (e.g., all integers).
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c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU

2005

a unary operation NOT (complement) is also included when we define the basic operations. (b) Ü ¡ Ü Ü. For convenience. NTHU 2005 . ­ c Cheng-Wen Wu. (b) ´Ý · ÜµÜ Theorem 4 (Involution) ´Ü µ Ü. B Two-valued Boolean algebra (switching algebra) 6 The binary operations are defined as the logical AND (¡) and OR (+). 6 Unless otherwise noted. of at least 2 elements (not variables). EE. Lab for Reliable Computing (LaRC).3. we will use the term Boolean algebra for 2valued Boolean algebra. Boolean Algebra and Logic Gates 3-3 ´ · µ· Exercise 1 Prove the associative law: B Boolean algebra 6 Set ·´ · µ and ´ µ ´ µ . Theorem 2 (a) Ü · ½ ½. Theorem 5 (Associativity) (a) Ü · ´Ý · Þ µ ´Ü · Ý µ · Þ . and vice versa. Theorem 3 (Absorption) (a) ÝÜ · Ü Ü. 6 ¼ ½ . 6 Huntington postulates satisfied by the elements of and the operators. 1(b) is the dual of Thm.  Thm. Basic Theorems of Boolean Algebra Theorem 1 (Idempotency) (a) Ü · Ü Ü. (b) Ü ¡ ¼ ¼. 6 The Huntington postulates can be shown valid (read pp. ¼ ¼ Ü . ¾ 6 Rules of operation for the 2 binary operators (+ & ¡). (b) Ü´ÝÞ µ ´ÜÝ µÞ . 1(a). 66-68).

Lab for Reliable Computing (LaRC).  Duality principle: every algebraic expression deducible from the axioms of Boolean algebra remains valid if · ° ¡ and ½ ° ¼ Theorem 7 If ´Ü½ ܾ ÜÒ µ is a Boolean expression of Ò variables. by transformations based on axioms and theorems) or by truth table.e. and (4) OR. (2) NOT. ¾ Boolean Functions A boolean function is an algebraic expression formed with boolean variables. and NOT. then ¼ ´Ü½ ܾ Ü Òµ ´Ü½ ܾ Ü Òµ ´Ü½ ¼ ܾ ¼ Ü ¼ Òµ Theorem 8 (De Morgan (generalized)) ´Ü½ · ܾ · ´Ü½Ü¾ ¡¡¡ ¡¡¡ · ¼ Ü ¼ Òµ ¼ ܽ ܾ ¼ Ü Òµ ܽ · ܾ ¡¡¡ ·¡¡¡ · ¼ ¼ Ü Ü ¼ Ò ¼ Ò  The theorems usually are proved algebraically (i. and is its dual expression. and NOT gates. we must follow a specific order of computation: (1) parenthesis. Exercise 2 Show that the set theory is an example of (multi-element) Boolean algebra. The number of rows in the table is ¾Ò. NTHU 2005 .  When evaluating a boolean function. It is important to find the simplest one. EE. where Ò is the number of variables in the function. AND. OR.3. Boolean Algebra and Logic Gates 3-4 ¼ Theorem 6 (De Morgan) (a) ´Ü · Ý µ Ü ¡ Ý . and an equal sign.  There are infinitely many algebraic expressions that specify a given boolean function. (3) AND. (b) ´ÜÝ µ ¼ ¼ ¼ ¼ Ü · ݼ. parentheses.  Any boolean function can be represented by a truth table. ­ c Cheng-Wen Wu. the operators OR..  Any boolean function can be transformed in a straightforward manner from an algebraic expression into a logic diagram composed only of AND.

and 3 AND terms (product terms).3. ¼ ½ has  The complement of any function is . e. Boolean Algebra and Logic Gates 3-5 Example 1 ½ ÜÝ · ÜÝ Ü ¼ Þ · Ü ÝÞ Þ ½ ½ ¼ ¼ Row number 0 1 2 3 4 5 6 7 Ý 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0 ¾  A literal is a variable or its complement in a boolean expression.g. 8 literals. EE. and 2) complement each literal in .. 1 OR term (sum term). ­ c Cheng-Wen Wu. which can be obtained by De Morgan’s theorem: 1) take the dual of . Example 2 ¼ ½ ´ÜÝ · ÜÝ ¼ Þ · Ü ÝÞ µ ¼ ¼ ´Ü · Ý µ´Ü · Ý · Þ µ´Ü · Ý · Þ µ ¼ ¼ ¼ ¼ ¼ ¼ ¾ x y z x y z F F (a) AND−OR expression F (b) OR−AND expression Figure 1: Graphic representation of two expressions for ½ [Gajski]. NTHU 2005 . Lab for Reliable Computing (LaRC).

there are no specific rules to follow that will guarantee the optimal result. ¾ ­ c Cheng-Wen Wu.  The number of literals can be minimized by algebraic manipulation.3. Lab for Reliable Computing (LaRC). Unfortunately. how many different boolean functions can we define? ¾ Algebraic Manipulation  Minimization of the number of literals and the number of terms usually results in a simpler circuit (less expensive). Boolean Algebra and Logic Gates 3-6 Exercise 3 Given Ò variables. EE. Some useful rules: x y z { Ü · ܼ Ý ¼ Ü ·Ý ÜÝ Ü´Ü · ݵ ÜÝ · ÝÞ · ܼ Þ ÜÝ · ܼ Þ (the Consensus Theorem I) (the Consensus Theorem II) ´Ü · Ý µ´Ý · Þ µ´Ü¼ · Þ µ ´Ü · Ý µ´Ü¼ · Þ µ Example 3 · ÜÝ ¼ ÜÝ Þ · Ü ÝÞ ¼ Ü´Ý Ü´Ý ÜÝ · Ý Þ µ · Ü ÝÞ · Þ µ · Ü ÝÞ ¼ ¼ ¼ ¼ · ÜÞ · Ü ÝÞ · Ü Þ µ · ÜÞ · Þ µ · ÜÞ ¼ Ý ´Ü Ý ´Ü ÜÝ · ÜÞ · ÝÞ The literal count is reduced from 8 to 6. NTHU 2005 .  CAD tools for logic minimization are commonly used today.

denoted as Ñ . Their complements are called the maxterms (or standard sums).  Canonical forms: 6 Sum-of-minterms (som) 6 Product-of-maxterms (pom)  Each maxterm is the complement of its corresponding minterm: Ü Ý Þ Ñ ¼ Å . ¼ ¾Ò   ½. and ܾܽ). ¼ ¼ ¼ ¼  Ò variables µ ¾Ò combinations. ¾ ¾ ¼ Ü Þ ½ ½ ¼ 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0 ­ c Cheng-Wen Wu. ܾܽ . Boolean Algebra and Logic Gates 3-7 Canonical Forms  2 variables µ 4 combinations (ܾܽ.3. ¼ ¾Ò   ½. Minterms Notation Ü Ý Þ ¼ ¼ ¼ ¼ ¼ ¼ Maxterms Ü Ü Ü Ü Ü Ü Ü Ü Notation ż Ž ž Å¿ Å Å Å Å 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Ѽ ѽ Ѿ Ñ¿ Ñ Ñ Ñ Ñ ·Ý·Þ ·Ý·Þ ¼ ¼ ¼ ÜÝ Þ Ü ÝÞ ¼ ¼ ·Ý ·Þ ·Ý ·Þ ¼ Ü ÝÞ ÜÝ Þ ¼ ¼ ¼ ¼ ·Ý·Þ ·Ý·Þ ¼ ¼ ¼ ÜÝ Þ ÜÝÞ ¼ ¼ ¼ ·Ý ·Þ ·Ý ·Þ ¼ ÜÝÞ ¼ Example 4 Consider the two functions ¾ and Ý ½ as shown in the following table. each is called a minterm (or a standard product). Lab for Reliable Computing (LaRC). denoted as Å . NTHU 2005 . ܽ ܾ. EE.

.   ½ ½ ¼ ¾ È and É.  How do we convert.g. into the canonical forms?  By expanding the missing variables in each term. ­ c Cheng-Wen Wu. which can have fewer literals than the minterms. · ÝÞ . interchange the numbers that were excluded from the original form. using ½ ¼ Ü ¡Ü . NTHU 2005 .  To convert from one canonical form to another.3. e.  By truth table. Boolean Algebra and Logic Gates 3-8 Sum-of-minterms: ¾ ½ Ü Ý Þ Ü ÝÞ ¼ ¼ ¼ · ÜÝ · ÜÝ ¼ ¼ Þ ¼ · ÜÝÞ ¼ ѽ ·Ñ ·Ñ Ñ¿ ´½ µ ´¿ µ Þ · ÜÝÞ · ÜÝÞ ·Ñ ·Ñ ·Ñ Product-of-maxterms: ¾ ´Ü · Ý · Þ µ´Ü · Ý · Þ µ´Ü · Ý · Þ µ´Ü · Ý · Þ µ´Ü · Ý · Þ µ ż ¼ ¼ ¼ ¼ ¼ ¼ ¼ ¡ ¡ ž ¡ ¡ Å¿ ¡ ¡ Å ¡ Å ¼ ´¼ ¾ ¿ ¼ ¼ µ ½ ´Ü · Ý · Þ µ´Ü · Ý · Þ µ´Ü · Ý · Þ µ´Ü · Ý · Þ µ ż Ž ž Å ´¼ ½ ¾ µ Any function can be represented by either of these 2 canonical forms. ¾ Standard Forms  Standard forms: 6 Sum-of-products (sop) 6 Product-of-sums (pos)  Product terms (or implicants) are the AND terms. ¼ Ü · Ü ¼ and Exercise 4 Convert Ü Ý ¼ ¼ · ÜÞ to its canonical (som & pom) forms. Lab for Reliable Computing (LaRC). and list È´¿ È´¼ µ is ½ ¾ µ is the sum of 1-minterms for the sum of 0-minterms for Ü ½ ½ . EE.

3. EE. terms with distance 1. i. Example 6 (a) ÜÝ · ÜÝ Þ · ÜÝ Û ¼ ¼ Ü´Ý ÜÝ · Ý ¼ Þ · Ý ¼ Ûµ · ´Ü · Ý µÞ Ü´Ý Ü´Ý · Ý ¼ ´Þ · Û µµ ÜÞ (b) ½ ÜÝ · ÜÞ · ÝÞ · Þ µ · ÝÞ · Ý ´Ü · Þ µ ¾ ­ c Cheng-Wen Wu. NTHU 2005 . Lab for Reliable Computing (LaRC).  Standard forms are not unique!  Standard forms can be derived from canonical forms by combining terms that differ in one variable.  Each 1-minterm can be included in several prime implicants. which can have fewer literals than the maxterms..  If there is a 1-minterm included in only 1 prime implicant.  Each sum term in the reduced pos form is called a prime implicate.e.  Each prime implicant represents 1 or more 1-minterms. ¾  Nonstandard forms can have fewer literals than standard forms. ¼ ¼ ¼ ½ ´Ü¼ · Ý ¼ µ´Ü¼ · Ý · Þ ¼ µ´Ü · Ý ¼ · Þ ¼ µ (b) Consider the boolean function form. and is in pos form. no more reduction is possible) is called a prime implicant (PI).  Each product term in the reduced sop form (i. Example 5 (a) ½ ÜÝ · ÜÝ Þ · Ü ÝÞ is in sop form. B Sop form: B Pos form: Û Ü ÝÞ ¼ ¼ ´ÛÜ · ÝÞ µ´Û Ü ¼ ¼ · Ý Þ ¼ ¼ µ in nonstandard · ÛÜÝ ¼ Þ ¼ . ´Û · ܼ µ´Û ¼ · Ý ¼ µ´Ý · Þ ¼ µ´Þ · ܵ.. Boolean Algebra and Logic Gates 3-9  Sum terms are the OR terms.e. then the prime implicant is an essential prime implicant (EPI).

 There are 16 different boolean functions if Ò ¾. NTHU 2005 . Name Zero AND Inhibition Transfer Inhibition Transfer XOR OR NOR Equivalence Complement Implication Complement Implication NAND One Operator Symbol Ü¡Ý Ü Ý Ý Ü Ü¨Ý Ü·Ý Ü Ý Ü¬Ý Ý Ü Ý Ü Ü Ý Ü Ý ¼ ¼ 00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Values ÜÝ 01 10 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Algebraic 11 Expression 0 ¼ ¼ 1 ÜÝ ½ 0 ÜÝ ¾ 1 Ü ¿ 0 ÜÝ 1 Ý 0 ÜÝ · Ü Ý 1 Ü·Ý 0 ´Ü · Ý µ 1 ÜÝ · Ü Ý 0 Ý ½¼ 1 Ü ·Ý ½½ 0 Ü ½¾ 1 Ü ·Ý ½¿ 0 ´ÜÝ µ ½ 1 ½ ½ ¼ ¼ ¼ ¼ ¼ ¼ ¼ ¼ ¼ ¼ ¼ ¼ Comment Binary constant 0 Ü and Ý Ü but not Ý Ü Ý but not Ü Ý Ü or Ý but not both Ü or Ý Not-OR Ü equals Ý Not Ý If Ý then Ü Not Ü If Ü then Ý Not-AND Binary constant 1  There are 2 functions that generate constants. NOR. Boolean Algebra and Logic Gates 3-10 Other Logic Operations  There are ¾¾ different boolean functions for Ò binary variables. & Transfer. and NOT (complement). Ò Table 1: Boolean functions of two variables. Implication and NAND. OR. NOR. Equivalence. XOR (exclusive-OR). Inhibition. Lab for Reliable Computing (LaRC). i.e. or equivalence).  There are 4 functions of one variable which indicate Complement and Transfer operations.3. the Zero and One functions.  There are 10 functions that define 8 specific binary operations: AND. XNOR (exclusive-NOR. EE. OR.. ­ c Cheng-Wen Wu. the following functions also are frequently used: NAND. XOR.  Apart from AND.

The numbers in this table are based on the typical complementary metal-oxide semiconductor (CMOS) implementation.  We would like to maximize the performance and minimize the cost. Name Inverter Driver AND OR NAND NOR XOR XNOR Graphic symbol Function Ü ¼ No. Boolean Algebra and Logic Gates 3-11 Exercise 5 Show that Inhibition and Implication are neither commutative nor associative.3. transistors Gate delay (ns) 2 4 6 6 4 4 14 12 1 2 2. NTHU 2005 . The numbers in this table are also based on the typical CMOS implementation. EE. ­ c Cheng-Wen Wu.4 1. Are XOR and XNOR commutative? Are they associative? ¾ Digital Logic Gates Table 2: Basic logic library in CMOS technology [Gajski].4 4.4 1. and NAND and NOR are commutative but not associative.  The number of transistors represent the hardware cost.4 2. Lab for Reliable Computing (LaRC).2 x x x y F F F Ü ÜÝ Ü·Ý ´ÜÝ µ¼ ´Ü · Ý µ¼ x y x y F F x y x y x y F F F Ü¨Ý Ü¬Ý  You have to memorize the graphic symbols.  The gate delay represents the performance.2 3.

· Ý ´Ü · Ý µ ¼ ¼ ´´Ü ´Ü ´Ü Ý µ ´ ´Ü · Ý µµ µ µ µ ¼ × We can implement Ü ¬ ¨ ¬ Ý Ý ¬ · ´Ü ¬ Ý µ with NAND and NOR gates. Boolean Algebra and Logic Gates 3-12 Example 7 Consider the full adder as defined in the following truth table. Ü Ý ·½ × 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 We first derive expressions for the two output functions that contain a minimum number of operators.3. NTHU . EE. 2. Ü ¬ Ý Ü Ý ·Ü Ý ¼ ¼ Ý ¼ ¼ ´´Ü µ ´Ü · Ý µµ The gate-level implementations for the full adder are shown in Fig. ­ ¾ 2005 c Cheng-Wen Wu. ¼ ·½ Ü Ý Ü Ý Ü Ý ·Ü Ý ¼ ·Ü ¼ Ý ¼ ·Ü Ý ¼ · · ¼ ´Ü ´Ü ¼ Ý ¨ ¼ ·Ü Ý Ý µ µ ¼ ¼ ¼ × Ü Ý ¼ ·Ü ·Ü Ý Ý ¼ ·Ü Ý ¼ ·Ü ·Ü Ý Ý ´Ü ´Ü ¼ Ý ¨ µ ¨ ¼ Ý µ ¼ · ´Ü Ý µ Note that the carry function ·½ ·½ could be reduced to Ü Ý Ü Ý · ´Ü · Ý µ. Lab for Reliable Computing (LaRC).

4 x . Boolean Algebra and Logic Gates 3-13 x y i i 2. y to s i i si (c) Design with NANDs and ORs (d) Input−output delays for the design in (c) Figure 2: Full adder design [Gajski].4 c i to c i+1 2.y i i x .y i i s i to c i+1 to si (b) Input−output delays for the design in (a) 1.8 ns 3.2 ns 9. ­ c Cheng-Wen Wu.2 i si (a) Design with minimum number of operators x y i i c to i x .3. Lab for Reliable Computing (LaRC).0 ns 8.4 c i to ci+1 c i to s i 2. y to c i+1 i i x i . NTHU 2005 .4 4.4 c i+1 1.8 ns 5.2 ns 7.4 c 1.4 2.8 ns 4. EE.2 c i+1 2.4 2.4 i 1.4 ns c 4.4 4.4 1.2 ns 1.

8 F 10 3.8 4-input AND w x y z F 10 3.3.2-inOAI Û · ܵ´Ý · Þ µµ ¼ 8 2. EE. NTHU 2005 .2 F ´ ¼ 2-wide. Boolean Algebra and Logic Gates Name Graphic symbol x y F z Function No.0 F ´´ 3-wide.8 F ´ 4-input NOR Ü · Ý · Þ · Ûµ ÛÜ · ÝÞ µ ¼ 10 2.2 3-input NOR x y z w x y z w x y z u v w x y z F ´ Ü · Ý · Þµ ¼ 8 1.2 F ´´ 2-wide.2-inOAI Ù · Úµ´Û · ܵ´Ý · Þ µµ ¼ 12 2.0 F ´ 3-wide.2-inAOI ÙÚ · ÛÜ · ÝÞ µ ¼ 12 2.4 ­ c Cheng-Wen Wu.8 F ´ 4-input NAND ÜÝÞÛµ ¼ 10 2.2 4-input OR F ´ 3-input NAND ÜÝÞ µ ¼ 8 1. trs Delay (ns) 3-14 3-input AND ÜÝÞ ÜÝÞÛ 8 2.2-inAOI 8 2.4 2-wide.3-inAOI u v w x y z w x y z u v w x y z F ´ ÙÚÛ · ÜÝÞ µ ¼ 12 2.2 3-input OR x y z w x y z x y z w x y z F Ü·Ý·Þ Ü·Ý·Þ·Û 8 2.3-inOAI u v w x y z F ´´ Ù · Ú · Ûµ´Ü · Ý · Þ µµ ¼ 12 2.2 2-wide. Lab for Reliable Computing (LaRC).

8 c i to c i+1 c i to si xi . y i to si 3.8 1.4 2.4 ns 2.2 c i+1 si (b) Input−output delays for the design in (a) (a) Design with multiple−input gates xi yi c i c i to c i+1 c i to si x i .0 ns i 1.2 ns 5.4 ns 3. Boolean Algebra and Logic Gates 3-15 xi yi c 1.4 1.8 1.0 ns 3.0 2.0 c i+1 1. ­ c Cheng-Wen Wu.8 1.3.4 ns 4.4 1. Lab for Reliable Computing (LaRC).4 1.4 ns 4.8 2.4 si (a) Design with multiple−operator gates (b) Input−output delays for the design in (a) Figure 3: Full adder design using multiple-input and multiple-operator gates [Gajski].2 ns 5. EE. y to c i+1 i x i . y to s i i 3. NTHU 2005 . y i to c i+1 xi .

3V) Low (0V) Positive logic 1 0 Negative logic 0 1 A B . N · Y ·¡¡¡·Æ OR 0 1 A B Y A V(1) V(0) B t Y t t 0 0 1 1 1 1 A V B Y 0 0 1 1 0 1 0 1 0 1 1 1 Figure 5: OR gate. Boolean Algebra and Logic Gates 3-16 Gate Implementations +5V Î Î ÎÓ S (Î ) V (Ë closed) µ ÎÓ ¼V (Ë open) µ ÎÓ ¼V V Figure 4: Inverter and binary logic. . Positive and negative logic: Logic type High (3.3. Lab for Reliable Computing (LaRC). ­ c Cheng-Wen Wu. EE. NTHU 2005 .

NTHU 2005 . EE. Lab for Reliable Computing (LaRC). ­ c Cheng-Wen Wu. (c) XOR gate. Boolean Algebra and Logic Gates A B . (d) NOR and NAND gates. .3. N ¡¡¡ 3-17 A B Y A V(1) V(0) B t Y t t Y Æ AND 0 1 0 0 0 1 0 1 Y 0 0 1 1 0 1 0 1 0 0 0 1 A V B A ¼ Y A Y 0 1 1 0 A B ¨ Y XOR 0 1 A B Y A V(1) V(0) B t Y t t 0 0 1 1 1 0 0 0 1 1 0 1 0 1 0 1 1 0 A B ´ · µ¼ Y A B Y A B ´ µ¼ 0 0 1 1 0 1 0 1 1 0 0 0 Y A B Y 0 0 1 1 0 1 0 1 1 1 1 0 Figure 6: (a) AND gate. (b) NOT gate (Inverter).

positive-logic OR.0 1. ­ c Cheng-Wen Wu.0 Ouput voltage VO 2. EE. Table 3: Examples of positive and negative logic symbols [Gajski]. NTHU 2005 .5 3.5 1. Boolean Algebra and Logic Gates 3-18  Negative-logic OR  Negative-logic AND positive-logic AND. B Noise margin: the maximum noise voltage level that can be tolerated by the gate.3.5 3. Lab for Reliable Computing (LaRC).0 Input voltage VI 3.0 0.0 Figure 7: Typical I/O characteristics for an inverter [Gajski].0 3.5 2.5 4. 4.0 1.5 2. Positive logic Negative logic B Noise: undesirable voltage variations that are superimposed on the normal voltage levels.5 1.5 0.0 2.

B Fan-out (standard load): the number of gates that each gate can drive. ­ c Cheng-Wen Wu. Lab for Reliable Computing (LaRC).4) L GND (0) Output voltage range Low noise margin L VIL (0.0) 3-19 VIH (2.0) VOL (0. IIH IIL IOH IIH IOL IIL IIH IIL to other gates (a) Gate as a current source to other gates (b) Gate as a current sink Figure 9: Current flow in a typical logic circuit [Gajski].8) GND (0) Input voltage range Figure 8: High and low noise margins [Gajski]. while providing voltage levels in the guaranteed range. B The fan-out depends on the amount of current a gate can source or sink while driving other gates. EE. Boolean Algebra and Logic Gates VCC (5) H VOH (2. NTHU 2005 .4) High noise margin H VCC (5.3.

 Rise time: delay for a signal to switch from 10% to 90% of its nominal value.  Heat removal is the major issue for high power dissipation.  ØÈ ÀÄ (ØÈ ÄÀ ): delay for the output signal to reach 50% of its nominal value on the H-to-L (L-to-H) transition after the input signal reached 50% of its nominal value. EE. Lab for Reliable Computing (LaRC).  Rise time and fall time may not be equal.  Propagation delay: ØÈ Rise time ´ØÈ ÀÄ · ØÈ ÄÀ µ ¾ . Fall time 90% Input 50% 10% 90% Output 50% 10% tPHL tPLH Figure 10: Propagation delay [Gajski].3.  In standard CMOS technology. ­ c Cheng-Wen Wu.  Fall time: delay for a signal to switch from 90% to 10% of its nominal value. the power dissipation increases linearly with respect to the input transition rate. NTHU 2005 . Boolean Algebra and Logic Gates 3-20 *Power Dissipation and Propagation Delay  The average power dissipation is the product of average current and power supply voltage (È Á Î ).

Lab for Reliable Computing (LaRC). EE. NTHU 2005 .3. Boolean Algebra and Logic Gates 3-21 Integrated Circuits and VLSI Technology  What is an integrated circuit (IC)? Levels of integration Acronym Number of gates Small-scale integration SSI 10 Medium-scale integration MSI 10–100 Large-scale integration LSI Hundreds–Thousands Very large-scale integration VLSI Tens of Thousands System-on-Chip SOC Millions Exercise 6 What are the popular digital logic families commonly used today? ¾ ­ c Cheng-Wen Wu.

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