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A

Page Index
===============
P01-Cover Page
P02-Block Diagram
P03-Notes List
P04-Dothan(1/2)
P05-Dothan(2/2)
1

P06-Alviso HOST(1/5)
P07-Alviso DDR(2/5)
P08-Alviso PCI-E(3/5)
P09-Alviso POWER(4/5)
P10-Alviso POWER(5/5)
P11-DDRI-SODIMM0
P12-DDRI-SODIMM1
P13-DDR Decoupling
P14-Clock Generator
P15-CRT Conn.
P16-VGA / LCD Conn.

Dunlin LA-2601 Schematics Document

P17-ICH6(1/4)_HUB,PCI,HOST
P18-ICH6(2/4)_CPU,AC97,IDE,LPC
P19-ICH6(3/4)_USB,PM,LAN,GPIO

P20-ICH6(4/4)_POWER&GND
P21-HDD/CDROM

Intel Dothan / Alviso GM(PM) / DDR-2 / ICH6-M

P22-DVI / TV_Out

Conn

P23-PCMCIA ENE CB1410 & CB714


P24-PCMCIA SOCKET

(NV43/44M)

P25-TI 1394A TSB43AB21A


P26-LAN BCM5788M
P27-LAN Magnetic & RJ45/RJ11
P28-Mimi-PCI Slot

2005 / 03 / 14

P29-AC97 Codec_ALC250D
P30-Audio Line in Switch
P31-AMP & Audio Jack

Rev:1.0

P32-Super IO SMC217
P33-ENE-KB910
P34-MDC / BT / KBD / TP Conn.

P35-BIOS & I/O Port & SATA HDD


P36-RJ11/LID Switch / Fan / FIR
P37-USB2.0 Conn
P38-Docking Conn.
P39-PWR_OK / RTC
P40-DC INTERFACE
P41-Screws
P42-PWR-DCIN / Precharge
P43-PWR-Charger
P44-PWR-Battery Select
P45-PWR-3V/5V/12V
P46-PWR-GMCH_CORE/1.8V/0.9V
P47-PWR-1.5V/2.5V
P48-PWR-CPU_CORE
4

P49-PWR-OTP
P50-PWR-PIR

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

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Document Number

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401336
D ate:

P , 17, 2005

Sheet
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of

51

Compal confidential
File Name : LA-2601

page 4,5

CRT/TV-OUT

page 4

page 15

Clock Generator
ICS954226AGT

Thermal Sensor
ADM1032ARM

Intel Dothan CPU


FSB

H_A#(3..31)

MV43 / MV44
VGA Board

400 / 533 Mhz

Intel Alviso GM(PM)

page 16

page 14

H_D#(0..63)

DDR-2

DDR-SO-DIMM X2
BANK 0, 1, 2, 3page 11,12,13

PCBGA 1257
LCD CONN

page 6,7,8,9,10

page 16

Signal Channel DDR-1


Two Channel DDR-2

DMI
PCI-E BUS

USB 2.0

USB conn x 4

RJ11 CONN

page 37

Intel ICH6-M

USB 2.0

BT Conn

Audio CKT
ALC250-D

AC-LINK

BROADCOM
BC M5788M
BCM4401

page 28

page 26

page 17,18,19,20

ENE Controller
CB714

RJ45 CONN
page 27

page 31

1394 Controller
TSB43AB21
page 25

page 23,24

Slot 0

AMP & Audio Jack

page 29

PATA HDD
conn
SATA HDD

SATA
3

page 34

mBGA-609

PCI BUS

Mini PCI
socket

5in1 CardReader
page 24
Slot

page 24

13 94
Conn.

page 21

LPC BUS

page 25

MODULE
Connector

PATA

Docking CONN.

page 21

*RJ-11 / 45(LED*2)
*COMPOSITE Video Out
*TVOUT
*LINE IN / OUT
*PS/2
*Print port
*1394
*USB
*DC JACK

Power On/Off CKT.


page 39

SMsC LPC47N217

DC/DC Interface CKT.

RTC CKT.

page 40

page 39

ENE KB910/910L

page 32

page 33

Int. KBD
Power Circuit DC/DC
4

page 42~49

Parellel Port

Power OK CKT.

DOCKING CONN

page 39

page 36

page 38

Serial Port
DOCKING CONN
page 38

page 34

Touch Pad
CONN. page

page 39

34

BIOS
page 35

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Size

Document Number

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401336
D ate:

P , 17, 2005

Sheet
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of

51

SIGNAL

STATE

Voltage Rails

Full ON

Power Plane

Description

S1

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3

S5

S1(Power On Suspend)
S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+1.05VS

1.05V switched power rail

ON

OFF

OFF

+DDRVTT

1.25V switched power rail for DDR terminator

ON

OFF

OFF

+1.5VALW

1.5V always on power rail

ON

ON

ON*

+1.5VS

1.5V switched power rail

ON

OFF

OFF

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+DDRVCC

2.5V power rail for DDR

ON

ON

OFF

Vcc
Ra / Rc

+2.5VS

2.5V switched power rail

ON

OFF

OFF

Board ID

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V

3.3V power rail

ON

ON

OFF

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

0
1
2
3
4
5
6
7

+5VMOD

5V switched power rail for Module Bay

ON

OFF

OFF

+12VALW

12V always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

Board ID / SKU ID Table for AD channel

Board ID
0
1
2
3
4
5
6
7

External PCI Devices


Device

IDSEL#

C ardB us

AD20

PIRQA/PIRQB

1 3 94

AD16

PI RQE

SD

AD20

PIRQA/PIRQB

Mini-PCI

AD18

PIRQG/PIRQH

LAN

AD17

PIRQF

3.3V +/- 5%
100K +/- 5%
Rb / Rd
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

BOARD ID Table

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

REQ#/GNT#

Interrupts

PCB Revision
0.1

EC SM Bus1 address

EC SM Bus2 address

Device

Address

Device

Address

Smart Battery

0001 011X b

ADM1032

1001 110X b

EEPROM(24C16/02)

1010 000X b

2'nd Battery

1001 011X b

(24C04)

1011 000Xb

ICH6M SM Bus address


4

Device

Address

Clock Generator
( ICS 952623)

1101 001Xb

DDR DIMM0

1010 000Xb

DDR DIMM2

1010 010Xb

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
E

of

51

H_D#[0..63]

H_D#[0..63] <6>

+3VS

JP7A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

<6> H_REQ#[0..4]

H_REQ #[0..4]

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

<14> CLK_CPU_BCLK
<14> CLK_CPU_BCLK#

<6> H_LOCK#
<6> H_CPURST#
<6> H_RS#[0..2]

H_RS# [0..2]

H_IER R#
H_CPURST#
H_RS#0
H_RS#1
H_RS#2

R2
P3
T2
P1
T1
U3
AE5

<6> H_ADSTB#0
<6> H_ADSTB#1

<6> H_ADS#
<6> H_BNR#
<6> H_BPRI#
<6> H_BR0#
<6> H_DEFER#
<6> H _ D R DY#
<6> H_HIT#
<6> H_HITM#

P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1

<6> H_TRDY#

<18> H_PW RGOOD


<6,18> H_CPUSLP#

Dothan

ADDR GROUP

ADSTB0#
ADSTB1#
ITP_CLK0
ITP_CLK1

B15
B14

BCLK0
BCLK1

N2
L1
J3
N4
L4
H2
K3
K4
A4
J2
B11
H1
K1
L2
M3

ITP_DBRRESET# A7
M2
B7
G1
C19
A10
B10
PRO_CHOT#
B17

HOST CLK

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

CONTROL GROUP

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

MISC

H_PW RGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

E4
A6
A13
C12
A12
C5
F23
C11
B13

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMDA
THERMDC

B18
A18
C17

THERMDA DIODE
THERMDC
THERMTRIP#

<6,18> H_THERMTRIP#

DATA GROUP

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

A16
A15

C8
B8
A9
C9

<6> H_DBSY#
<18> H_DPSLP#
<18> H_DPRSTP#
<6> H_DPW R#

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#

THERMAL

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

H _D#0
H _D#1
H _D#2
H _D#3
H _D#4
H _D#5
H _D#6
H _D#7
H _D#8
H _D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

C17

H_A #[3..31]

C12
0.1U_0402_16V4Z

R20
@ 10K_0402_5%

U3
THERMDA

D+

VDD1

THERMDC

D-

ALERT#

<33,44> EC_SMB_CK2

SCLK

THERM#

<33,44> EC_SMB_DA2

SDATA

GND

2200P_0402_50V7K

<6> H_A#[3..31]

ADM1032ARM_RM8

+1.05VS
C

ITP_TDI

R508

ITP_TDO

R29

1 @ 54.9_0402_1%

150_0402_5%

H_CPURST#

R28

1 @ 54.9_0402_1%

ITP_TMS

R27

40.2_0402_1%

PRO_CHOT#

R31

56_0402_5%

H_PW RGOOD

R24

200_0402_5%

H_IER R#

R23

56_0402_5%

+3VS

DINV0#
DINV1#
DINV2#
DINV3#

D25
J26
T24
AD20

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

C23
K24
W25
AE24
C22
L24
W24
AE25

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1

C2
D3
A3
B5
D1
D4

H_A20M# <18>
H_FERR# <18>
H_IGNNE# <18>
H_INIT# <18>
H_INTR <18>
H_NMI <18>

STPCLK#
SMI#

C6
B4

H_STPCLK# <18>
H_SMI# <18>

LEGACY CPU

<6>
<6>
<6>
<6>

ITP_DBRRESET#

R26

150_0402_5%

ITP_TRST#

R509

680_0402_5%

ITP_TCK

R30

27.4_0402_1%

TEST1

R25

1 @ 1K_0402_5%

TEST2

R46

1 @ 1K_0402_5%

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

Compal Electronics, Inc.

TYCO_1612365-1_Dothan
Title

SCHEMATIC, M/B LA-2601


THERMDA & THERMDC Trace / Space = 10 / 10 mil
5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

of

51

+CPU_CORE

+CPU_CORE

JP7B

1
1

@ 54.9_0402_1%
@ 54.9_0402_1%

2
2

V CCSENSE
VSSSENSE

+VCCA

+1.05VS

1.8V FOR DOTHAN-A


+1.8VS

1
R63

2
@ 0_1206_5%

1
R56

F26
B1
N1
AC26

VCCA0
VCCA1
VCCA2
VCCA3

P23
W4

VCCQ0
VCCQ1
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

D6
D8
D18
D20
D22
E5
E7
E9
E17
E19
E21
F6
F8
F18

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

<48> PSI#

E1

PSI#

<48>
<48>
<48>
<48>
<48>
<48>

E2
F2
F3
G3
G4
H4

VID0
VID1
VID2
VID3
VID4
VID5

2
0_1206_5%

C26

C25
2
2
0.01U_0402_16V7K
10U_0805_10V4Z

+CPU_CORE

+1.05VS

R75
1K_0402_1%

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5

1
R78

GTL_REF0

2
2K_0402_1%

AD26

<14> CPU_BSEL0
<14> CPU_BSEL1
COMP0
COMP1
COMP2
COMP3

JP7C

VCCSENSE
VSSSENSE

D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L5
L21
M6
M22
N5
N21
P6
P22
R5
R21
T6
T22
U21

1.5V FOR DOTHAN-B


+1.5VS

AE7
AF6

Dothan
POWER, GROUNG, RESERVED SIGNALS AND NC

R85
R84

GTLREF

C16
C14

BSEL0
BSEL1

P25
P26
AB2
AB1

COMP0
COMP1
COMP2
COMP3

B2
C3
E26
AF7
AC1

RSVD
RSVD
RSVD
RSVD
RSVD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

1
+

2
2
10U_0805_10V4Z

27.4_0402_1%

COMP0

54.9_0402_1%

COMP1

R83

27.4_0402_1%

COMP2

R82

54.9_0402_1%

COMP3

+ C460

C427
2
220U_D2_4VM_R12

2
2
10U_0805_10V4Z

2
2
10U_0805_10V4Z

2
10U_0805_10V4Z

+CPU_CORE

10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1
1
1
1
1
1
C42
C40
C41
C39
C444
C443

C33

2
10U_0805_10V4Z

2
2
10U_0805_10V4Z

2
2
10U_0805_10V4Z

2
10U_0805_10V4Z

+CPU_CORE

10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1
1
1
1
1
1
C455
C64
C65
C66
C67
C68

C454

2
10U_0805_10V4Z

2
2
10U_0805_10V4Z

2
2
10U_0805_10V4Z

2
10U_0805_10V4Z

+CPU_CORE

10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1
1
1
1
1
1
C70
C429
C470
C430
C471
C516

C69

2
10U_0805_10V4Z

2
2
10U_0805_10V4Z

2
2
10U_0805_10V4Z

2
10U_0805_10V4Z

+CPU_CORE

10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1
1
1
1
1
1
C510
C511
C512
C513
C514
C515

C509

2
10U_0805_10V4Z

2
2
10U_0805_10V4Z

2
2
10U_0805_10V4Z

Vcc-core
Decoupling
SPCAP,Polymer

C,uF

ESR, mohm

3X330uF

9m ohm/3

3.5nH/4

MLCC 0805 X5R

35X10uF

5m ohm/35

0.6nH/35

0.1U_0402_16V4Z

ESL,nH

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
1
C435

1
C445

1
C16

1
C458

0.1U_0402_16V4Z

1
C13

1
C15

0.1U_0402_16V4Z

1
C14

1
C461

0.1U_0402_16V4Z

F20
F22
G5
G21
H6
H22
J5
J21
K22
U5
V6
V22
W5
W21
Y6
Y22
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC9
AC11
AC13
AC15
AC17
AC19
AD8
AD10
AD12
AD14
AD16
AD18
AE9
AE11
AE13
AE15
AE17
AE19
AF8
AF10
AF12
AF14
AF16
AF18

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Dothan

POWER, GROUND

2
10U_0805_10V4Z

+1.05VS

150U_D2_6.3VM

10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1
1
1
1
1
1
1
C47
C46
C45
C48
C30
C31
C32

R70

220U_D2_4VM_R12
1

+CPU_CORE

TYCO_1612365-1_Dothan

R69

+ C472

C441
2
220U_D2_4VM_R12

220U_D2_4VM_R12
1

C453

C448

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

TYCO_1612365-1_Dothan

C442

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Compal Electronics, Inc.


Title

TRACE CLOSELY CPU < 0.5'


COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils
5

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

of

51

H_RS# [0..2]

+1.5VS

H_RS#[0..2] <4>

H_A #[3..31]

<4> H_A#[3..31]

H_REQ #[0..4]

<4> H_REQ#[0..4]

H_D#[0..63]

H_D#[0..63] <4>

CL K_DREF_SSC

R51

2 PM@ 0_0402_5%

C LK_DREF_SSC#

R52

2 PM@ 0_0402_5%

U5A

G4
K1
R3
V3
G5
K2
R2
W4
H8
K3
T7
U5

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

<4> H_CPURST#
<4> H_ADS#
<4> H_TRDY#
<4> H_DPW R#
<4> H _ D R DY#
<4> H_DEFER#

<4>
<4>
<4>
<4>
<4>
<4>
<4>

H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#

CPU_SLP#
H_RS#0
H_RS#1
H_RS#2

H10

HCPURST#

F8
B5
G6
F7
E6
F6
D6
D4
B3
E7
A5
D5
C6
G8
A4
C5
B4

HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HEDRDY#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#
HRS0#
HRS1#
HRS2#

R54

<19>
<19>
<19>
<19>

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

0_0402_5%

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

Y31
AA35
AB31
AC35

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

AA33
AB37
AC33
AD37

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

Y33
AA37
AB33
AC37

DMITXP0
DMITXP1
DMITXP2
DMITXP3

AM33
AL1
AE11
AJ34
AF6
AC10

<11> M_CLK_DDR0
<11> M_CLK_DDR1
<12> M_CLK_DDR3
<12> M_CLK_DDR4

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

AP21
AM21
AH21
AK21

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

AN16
AM14
AH15
AG16

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

M_OCDCOMP0
M_OCDCOMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3

AF22
AF16
AP14
AL15
AM11
AN10

SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

M_RCOMPN
M_RCOMPP
SMVREF

AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

<12> M_CLK_DDR#3
<12> M_CLK_DDR#4
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

<11>
<11>
<12>
<12>

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

R426 1
R427 1

2 40.2_0402_1%
2 40.2_0402_1%
<11>
<11>
<12>
<12>

R429 1
R430 1

+DDRVCC

M_ODT0
M_ODT1
M_ODT2
M_ODT3

2 80.6_0402_1%
2 80.6_0402_1%

SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5

AN33
AK1
AE10
AJ33
AF5
AD10

<11> M_CLK_DDR#0
<11> M_CLK_DDR#1

<11>
<11>
<12>
<12>

CFG/RSVD

H_ VREF
H_XRCOMP
H_XSCOMP
H_YRCO MP
H_YSCOMP
H_XSW ING
H _YSW ING

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

M_XSLEW
M_YSLEW

+1.05VS
R50 2
R47 1
R72 2
R68 1

24.9_0402_1%
54.9_0402_1%
24.9_0402_1%
54.9_0402_1%

1
2
1
2

(10mil:20mil)

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

CF G0
MCH_CLKSEL1
MCH_CLKSEL0

MCH_CLKSEL1 <14>
MCH_CLKSEL0 <14>

+1.05VS

CF G9

CF G0

R40

C FG12
C FG13

CF G5

R413 1

2 @ 1K_0402_5%

C FG16

CF G6

R407 1

2 1K_0402_5%

C FG18
C FG19

CF G7

R408 1

2 @ 1K_0402_5%

CF G9

R404 1

2 @ 1K_0402_5%

C FG12 R409 1

2 @ 1K_0402_5%

C FG13 R412 1

2 @ 1K_0402_5%

C FG16 R417 1

2 @ 1K_0402_5%

+2.5VS
C

BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#

DREF_CLKN
DREF_CLKP
DREF_SSCLKP
DREF_SSCLKN
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11

R423

J23
J21
H22
F5
AD30
AE29

R421
+1.05VS

+1.05VS

C488

1K_0402_1%

SMVREF

R387

H _YSW ING

0.1U_0402_16V4Z

200_0603_1%

A24
A23
D37
C37

2 @ 1K_0402_5%

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

H_THERMTRIP# <4,18>
VGATE <14,19,48>
PLT_RST# <17,19,21,32,33>

CLK_DREF_96M#
CLK_DREF_96M
CL K_DREF_SSC
C LK_DREF_SSC#

CLK_DREF_96M# <14>
CLK_DREF_96M <14>
CLK_DREF_SSC <14>
CLK_DREF_SSC# <14>

(12mil:10mil)

+2.5VS

EXT_TS#0 R416 1

2 10K_0402_5%

EXT_TS#1 R411 1

2 10K_0402_5%

CFG5

Refer to sheet 6 for FSB


frequency select
Low = DMI x 2
High = DMI x 4

CFG6

Low = DDR-II
High = DDR-I

CFG7

Low = DT/Transportable CPU


High = Mobile CPU

CFG9

Low = Reverse Lane


High = Normal Operation

CFG[13:12]

00
01
10
11

CFG16
(FSB Dynamic
ODT)

Low = Disabled
High = Enabled

CFG[2:0]

*
*

= Reserved
= XOR Mode Enabled
= All Z Mode Enabled
= Normal Operation (Default)

CFG18
(VCC Select)

Low = 1.05V (Default)


High = 1.5V

CFG19
(VTT Select)

Low = 1.05V (Default)


High = 1.2V

R405

0.1U_0402_16V4Z

100_0603_1%

C459
0.1U_0402_16V4Z

*
A

Compal Electronics, Inc.

R419
100_0603_1%

Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C FG19 R42

C423

C436

R420
221_0603_1%

H_XSW ING

H_ VREF

C489
0.1U_0402_16V4Z

(12mil:10mil)

2 @ 1K_0402_5%

(5mil:15mil)

R406
221_0603_1%

R388
100_0603_1%

+1.05VS

PM_BMBUSY# <19>

EXT_TS#0
EXT_TS#1
H_THERMTRIP#

1K_0402_1%
0.1U_0402_16V4Z

C FG18 R41

CFG[19:18]: internal pull-down

ALVISO_BGA1257

CPU_SLP#

2 10K_0402_5%

CFG[17:3]: internal pull-up

+DDRVCC

H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil

CF G5
CF G6
CF G7

J11
C1
C2
T1
L1
D1
P1

<19>
<19>
<19>
<19>

ALVISO_BGA1257

Un-pop for Dothan-A


<4,18> H_CPUSLP#

HVREF
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HDINV#0
HDINV#1
HDINV#2
HDINV#3

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

AA31
AB35
AC31
AD35

NC

<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>

HCLKN
HCLKP

<19>
<19>
<19>
<19>

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

DDR MUXING

AB1
AB2

<14> CLK_MCH_BCLK#
<14> CLK_MCH_BCLK

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

CLK PM

<4> H_ADSTB#0
<4> H_ADSTB#1

HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HADSTB#0
HADSTB#1

<19>
<19>
<19>
<19>

A11
A7
D7
B8
C7
A8
B9
E13

E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

Alviso

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HOST

G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13

H _D#0
H _D#1
H _D#2
H _D#3
H _D#4
H _D#5
H _D#6
H _D#7
H _D#8
H _D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

DMI

U5B
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

of

51

<11> DDR_A_DQS#[0..7]
C

<11> DDR_A_MA[0..13]

<11> DDR_A_CAS#
<11> DDR_A_RAS#
<11> DDR_A_W E#
B

SA_BS0#
SA_BS1#
SA_BS2#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

D DR_A_DQS0
D DR_A_DQS1
D DR_A_DQS2
D DR_A_DQS3
D DR_A_DQS4
D DR_A_DQS5
D DR_A_DQS6
D DR_A_DQS7

AK36
AP33
AN29
AP23
AM8
AM4
AJ1
AE5

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

AN15
AP16
AF29
AF28
AP15

SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#

DDR MEMORY SYSTEM A

<11> DDR_A_DQS[0..7]

AK15
AK16
AL21

AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

DDR _A_D0
DDR _A_D1
DDR _A_D2
DDR _A_D3
DDR _A_D4
DDR _A_D5
DDR _A_D6
DDR _A_D7
DDR _A_D8
DDR _A_D9
DD R_A_D10
DD R_A_D11
DD R_A_D12
DD R_A_D13
DD R_A_D14
DD R_A_D15
DD R_A_D16
DD R_A_D17
DD R_A_D18
DD R_A_D19
DD R_A_D20
DD R_A_D21
DD R_A_D22
DD R_A_D23
DD R_A_D24
DD R_A_D25
DD R_A_D26
DD R_A_D27
DD R_A_D28
DD R_A_D29
DD R_A_D30
DD R_A_D31
DD R_A_D32
DD R_A_D33
DD R_A_D34
DD R_A_D35
DD R_A_D36
DD R_A_D37
DD R_A_D38
DD R_A_D39
DD R_A_D40
DD R_A_D41
DD R_A_D42
DD R_A_D43
DD R_A_D44
DD R_A_D45
DD R_A_D46
DD R_A_D47
DD R_A_D48
DD R_A_D49
DD R_A_D50
DD R_A_D51
DD R_A_D52
DD R_A_D53
DD R_A_D54
DD R_A_D55
DD R_A_D56
DD R_A_D57
DD R_A_D58
DD R_A_D59
DD R_A_D60
DD R_A_D61
DD R_A_D62
DD R_A_D63

U 5D

DDR_A_D[0..63] <11>
<12> DDR_B_BS#0
<12> DDR_B_BS#1
<12> DDR_B_BS#2
<12> DDR_B_DM[0..7]

<12> DDR_B_DQS[0..7]

<12> DDR_B_DQS#[0..7]

<12> DDR_B_MA[0..13]

<12> DDR_B_CAS#
<12> DDR_B_RAS#
<12> DDR_B_W E#

AJ15
AG17
AG21

SB_BS0#
SB_BS1#
SB_BS2#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

D DR_B_DQS0
D DR_B_DQS1
D DR_B_DQS2
D DR_B_DQS3
D DR_B_DQS4
D DR_B_DQS5
D DR_B_DQS6
D DR_B_DQS7

AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

AH14
AK14
AF15
AF14
AH16

SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#

DDR SYSTEM MEMORY B

U 5C
<11> DDR_A_BS#0
<11> DDR_A_BS#1
<11> DDR_A_BS#2
<11> DDR_A_DM[0..7]

ALVISO_BGA1257

SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AJ9
AK9
AJ7
AK6
AJ4
AH5
AK8
AJ8
AJ5
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5

DDR_B_D[0..63] <12>

DDR _B_D0
DDR _B_D1
DDR _B_D2
DDR _B_D3
DDR _B_D4
DDR _B_D5
DDR _B_D6
DDR _B_D7
DDR _B_D8
DDR _B_D9
DD R_B_D10
DD R_B_D11
DD R_B_D12
DD R_B_D13
DD R_B_D14
DD R_B_D15
DD R_B_D16
DD R_B_D17
DD R_B_D18
DD R_B_D19
DD R_B_D20
DD R_B_D21
DD R_B_D22
DD R_B_D23
DD R_B_D24
DD R_B_D25
DD R_B_D26
DD R_B_D27
DD R_B_D28
DD R_B_D29
DD R_B_D30
DD R_B_D31
DD R_B_D32
DD R_B_D33
DD R_B_D34
DD R_B_D35
DD R_B_D36
DD R_B_D37
DD R_B_D38
DD R_B_D39
DD R_B_D40
DD R_B_D41
DD R_B_D42
DD R_B_D43
DD R_B_D44
DD R_B_D45
DD R_B_D46
DD R_B_D47
DD R_B_D48
DD R_B_D49
DD R_B_D50
DD R_B_D51
DD R_B_D52
DD R_B_D53
DD R_B_D54
DD R_B_D55
DD R_B_D56
DD R_B_D57
DD R_B_D58
DD R_B_D59
DD R_B_D60
DD R_B_D61
DD R_B_D62
DD R_B_D63

ALVISO_BGA1257

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

of

51

+3VS

+2.5VS
PCIE_MTX_C_GRX_N[0..15]

<16> PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]

<16> PCIE_MTX_C_GRX_P[0..15]

2
D

PCEI_GTX_C_MRX_P[0..15]

<16> PCEI_GTX_C_MRX_P[0..15]

LBKLT_EN

<16,33> GMCH_ENBKL

PCEI_GTX_C_MRX_N[0..15]

<16> PCEI_GTX_C_MRX_N[0..15]

2
G

R402
GM@ 2.2K_0402_5%

Q44
GM@ BSS138_SOT23

U5G

R418

2
R384
2
R385
2
R386

<15> GMCH_CRT_G
<15> GMCH_CRT_R
<15> GMCH_CRT_VSYNC
<15> GMCH_CRT_HSYNC

R382

1
R414

R400
R39

4.7K_0402_5%

GMCH_CRT_CLK

4.7K_0402_5%

GMCH_CRT_DATA

2.2K_0402_5%

LCTLB_DATA

2.2K_0402_5%

<16> GMCH_ENVDD

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

GMCH_TXCLKGMCH_TXCLK+
GMCH_TZCLKGMCH_TZCLK+

B30
B29
C25
C24

LACLKN
LACLKP
LBCLKN
LBCLKP

GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-

B34
B33
B32

LADATAN0
LADATAN1
LADATAN2

2 REFSET
255_0402_1%

LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDD C_CLK
LDDC_DATA
GM CH_ENVDD
L IBG

LCTLA_CLK
<16>
<16>
<16>
<16>

R398

100K_0402_5%

LBKLT_EN

R403

1.5K_0402_1%

L IBG

R44

150_0402_5%

GMCH_TV_COMPS

R515

150_0402_5%

GMCH_TV_LUMA

R516

150_0402_5%

GMCH_TV_CRMA

GMCH_TXCLKGMCH_TXCLK+
GMCH_TZCLKGMCH_TZCLK+

<16> GMCH_TXOUT0<16> GMCH_TXOUT1<16> GMCH_TXOUT2<16> GMCH_TXOUT0+


<16> GMCH_TXOUT1+
<16> GMCH_TXOUT2+

<16> GMCH_TZOUT0<16> GMCH_TZOUT1<16> GMCH_TZOUT2-

MISC

E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20

1
150_0402_5%
1
150_0402_5%
1
150_0402_5%

+2.5VS
R381

2
R399

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

TV_REFSET
1
0_0402_5%

GMCH_CRT_CLK
GMCH_CRT_DATA

<15> GMCH_CRT_CLK
<15> GMCH_CRT_DATA
<15> GMCH_CRT_B

4.99K_0603_1%

A15
C16
A17
J18
B15
B16
B17

GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+

GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-

A34
A33
B31

C29
D28
C27

PCI - EXPRESS GRAPHICS

EXP_COMPI
EXP_ICOMPO

TV

GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA

<22> GMCH_TV_COMPS
<22> GMCH_TV_LUMA
<22> GMCH_TV_CRMA

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

VGA

SDVO_SDAT
SDVO_SCLK
CLK_MCH_3GPLL#
CLK_MCH_3GPLL

H24
H25
AB29
AC29

LVDS

<16>
<16>
<14>
<14>

SDVO_SDAT
SDVO_SCLK

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

+2.5VS

+3VS

C28
D27
C26

LBDATAP0
LBDATAP1
LBDATAP2

PEG_COMP

R48

EXP_RXN0/SDVO_TVCLKIN# E30
EXP_RXN1/SDVO_INT# F34
EXP_RXN2/SDVO_FLDSTALL# G30
EXP_RXN3 H34
EXP_RXN4 J30
EXP_RXN5 K34
EXP_RXN6 L30
EXP_RXN7 M34
EXP_RXN8 N30
EXP_RXN9 P34
EXP_RXN10 R30
EXP_RXN11 T34
EXP_RXN12 U30
EXP_RXN13 V34
EXP_RXN14 W30
EXP_RXN15 Y34

PCEI_GTX_C_MRX_N0
PCEI_GTX_C_MRX_N1
PCEI_GTX_C_MRX_N2
PCEI_GTX_C_MRX_N3
PCEI_GTX_C_MRX_N4
PCEI_GTX_C_MRX_N5
PCEI_GTX_C_MRX_N6
PCEI_GTX_C_MRX_N7
PCEI_GTX_C_MRX_N8
PCEI_GTX_C_MRX_N9
PCEI_GTX_C_MRX_N10
PCEI_GTX_C_MRX_N11
PCEI_GTX_C_MRX_N12
PCEI_GTX_C_MRX_N13
PCEI_GTX_C_MRX_N14
PCEI_GTX_C_MRX_N15

EXP_RXP0/SDVO_TVCLKIN
EXP_RXP1/SDVO_INT
EXP_RXP2/SDVO_FLDSTALL
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_P15

EXP_TXN0/SDVOB_RED#
EXP_TXN1/SDVOB_GREEN#
EXP_TXN2/SDVOB_BLUE#
EXP_TXN3/SDVOB_CLKN
EXP_TXN4/SDVOC_RED#
EXP_TXN5/SDVOC_GREEN#
EXP_TXN6/SDVOC_BLUE#
EXP_TXN7/SDVOC_CLKN
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

EXP_TXP0/SDVOB_RED
EXP_TXP1/SDVOB_GREEN
EXP_TXP2/SDVOB_BLUE
EXP_TXP3/SDVOB_CLKP
EXP_TXP4/SDVOC_RED
EXP_TXP5/SDVOC_GREEN
EXP_TXP6/SDVOC_BLUE
EXP_TXP7/SDVOC_CLKP
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

24.9_0402_1%

+1.5VS

C59

C71

C76

C80

C91

C100 1
C109 1
C116 1

C58

C63

C75

C79

C89

C98

C105 1
C115 1

C57
2 DVI@ 0.1U_0402_16V4Z
C62
2 DVI@ 0.1U_0402_16V4Z
C74
2 DVI@ 0.1U_0402_16V4Z
C78
2 DVI@ 0.1U_0402_16V4Z
C87
2 DVI@ 0.1U_0402_16V4Z
C97
2 DVI@ 0.1U_0402_16V4Z
C104
2 DVI@ 0.1U_0402_16V4Z
C114
2 DVI@ 0.1U_0402_16V4Z

C56
2 DVI@ 0.1U_0402_16V4Z
C60
2 DVI@ 0.1U_0402_16V4Z
C73
2 DVI@ 0.1U_0402_16V4Z
C77
DVI@
0.1U_0402_16V4Z
2
C83
2 DVI@ 0.1U_0402_16V4Z
C92
DVI@
0.1U_0402_16V4Z
2
C101
2 DVI@ 0.1U_0402_16V4Z
C110
DVI@
0.1U_0402_16V4Z
2

1
1
1
1
1
1
1

1
1
1
1
1
1
1

2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N0


PCIE_MTX_C_GRX_N1
2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
DVI@
0.1U_0402_16V4Z
PCIE_MTX_C_GRX_N10
2
PCIE_MTX_C_GRX_N11
2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
DVI@
0.1U_0402_16V4Z
PCIE_MTX_C_GRX_N14
2
PCIE_MTX_C_GRX_N15
B

2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P0


PCIE_MTX_C_GRX_P1
2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
2 DVI@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

GMCH_LCD_CLK

ALVISO_BGA1257

LDD C_CLK

R49
GM@ 4.7K_0402_5%

R45
4.7K_0402_5%

<16> GMCH_TZOUT0+
<16> GMCH_TZOUT1+
<16> GMCH_TZOUT2+

GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+

D36
D34

GMCH_LCD_CLK <16>

Q6
GM@ 2N7002_SOT23

+2.5VS

+3VS

Compal Electronics, Inc.

1
D

GMCH_LCD_DATA

SCHEMATIC, M/B LA-2601

Title

LDDC_DATA

R401
GM@ 4.7K_0402_5%

R397
4.7K_0402_5%

GMCH_LCD_DATA <16>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Q43
GM@ 2N7002_SOT23
5

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

of

51

+1.05VS
U 5F
U5E

T29
R29
N29
M29
K29
J29
V28
U28
T28
R28
P28
N28
M28
L28
K28
J28
H28
G28
V27
U27
T27
R27
P27
N27
M27
L27
K27
J27
H27
K26
H26
K25
J25
K24
K23
K22
K21
W20
U20
T20
K20
V19
U19
K19
W18
V18
T18
K18
K17

+1.05VS

+1.5VS
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL
+1.5VS_MPLL

AC1
AC2
B23
C35
AA1
AA2

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

F17
E17
D18
C18
F18
E18

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

1
+
C871
TV@ 2 150U_D2_6.3VM

H18
G18

VCCD_TVDAC
VCCDQ_TVDAC

D19
H17

24mA

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

B26
B25
A25

60mA

VCCA_LVDS

A35

VCCHV0
VCCHV1
VCCHV2

B22
B21
A21

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

B28
A28
A27

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

AF20
AP19
AF19
AF18

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

AE37
W37
U37
R37
N37
L37
J37

+1.5VS

10mA

+2.5VS

2mA
60mA
+1.5VS_DDRDLL

+1.5VS_PEG

1500mA
C23
0.47U_0603_16V4Z

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

Y29
Y28
Y27

VCCA_3GBG
VSSA_3GBG

F37
G37

VCC_SYNC

H20

+1.5VS_3GPLL

0.15mA

+2.5VS_3GBG

70mA

1
+2.5VS
C24
0.47U_0603_16V4Z

F19
E19
G19

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC

K13
J13
K12
W11
V11
U11
T11
R11
P11
N11
M11
L11
K11
W10
V10
U10
T10
R10
P10
N10
M10
K10
J10
Y9
W9
U9
R9
P9
N9
M9
L9
J9
N8
M8
N7
M7
N6
M6
A6
N5
M5
N4
M4
N3
M3
N2
M2
B2
V1
N1
M1
G1

+1.05VS
+3VS_TVDAC

VCCA_TVBG
VSSA_TVBG

POWER

VCCD_HMPLL1
VCCD_HMPLL2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

120mA

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51

POWER

2
1

ALVISO_BGA1257

C49
0.22U_0402_10V4Z

+
C872
150U_D2_6.3VM

1
2

C34
0.22U_0402_10V4Z

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

C519
0.1U_0402_16V4Z
V 1.8_DDR_CAP1
2
1
V 1.8_DDR_CAP2
2
V 1.8_DDR_CAP5

4000mA

C505
0.1U_0402_16V4Z
1
2
1
C520
0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.1U_0402_16V4Z
AM37
AH37
1
1
1
1
1
1
C457
C451
C452
AP29
AD28
+DDRVCC
C450
C456
C447
AD27
2
2
2
2
2
2
AC27
22U_1206_16V4Z_V1
AP26
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
AN26
D
AM26
+DDRVCC
AL26
2200mA
AK26
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AJ26
AH26
1
AG26
1
1
1
1
1
1
1
1
+
C494
C86
C81
C483
AF26
AE26
C88
C487
C498
C481
C486
AP25
2
2
2
2
2
2
2
2
330U_D2E_2.5VM 2
AN25
AM25
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AL25
AK25
AJ25
AH25
AG25
+2.5VS
AF25
VCCHV(Ball A21,B21,B22)
AE25
AE24
AE23
AE22
1
1
1
1
1
1
C417
C419
C413
C416
C21
C414
AE21
AE20
AE19
2 0.1U_0402_16V4Z 2 0.01U_0402_16V7K 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z
AE18
AE17
AE16
AE15
AE14
VCCA_LVDS (Ball A35)
VCCTX_LVDS(Ball A27,A28,B28) C
AP13
AN13
+2.5VS
AM13
VCCA_CRTDAC(Ball F19,E19)
AL13
AK13
AJ13
AH13
1
1
1
1
C22
C434
C424
C431
AG13
AF13
AE13
2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z 2 0.022U_0402_16V7K
AP12
AN12
AM12
AL12
AK12
VCC_SYNC(Ball H20)
AJ12
AH12
AG12
VCCD_TVDAC (Ball D19)
+1.5VS
AF12
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AE12
AD11
AC11
AB11
1
1
1
1
1
1
C82
C20
C415
C421
C425
C440
C437
AB10
0.1U_0402_16V4Z C517
AB9
0.1U_0402_16V4Z
AP8 V 1.8_DDR_CAP6 2
1
2
2
2
2
2
4.7U_0805_10V4Z 2
AM1 V 1.8_DDR_CAP4
2
1
AE1 V 1.8_DDR_CAP3
2
1
B
C490
0.1U_0402_16V4Z
0.022U_0402_16V7K
0.022U_0402_16V7K
0.1U_0402_16V4Z

ALVISO_BGA1257

2.2U_0603_6.3V6K

VCCD_LVDS(Ball A25,B25,B26)

VCCDQ_TVDAC (Ball H17)

+1.05VS
+1.5VS_PEG
R415

1
+1.5VS_DPLLA

+1.5VS_DPLLB
L6
CHB1608U301_0603
1
2
+1.5VS

60mA
1

C412

C418

2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z

+1.5VS_DDRDLL
L25
CHB1608U301_0603
1
2
+1.5VS

60mA
1

C426

C420

2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z

R86
0_0603_5%
1
2

C84

2 22U_1206_16V4Z_V1

C446

C449

0_0805_5%

+1.5VS

C439

2 4.7U_0805_10V4Z

2 4.7U_0805_10V4Z

2 2.2U_0603_6.3V6K

60mA
A

C50

C478

C52

+1.5VS_3GPLL
L8
CHB1608U301_0603
1
2
+1.5VS

60mA
1

C482

C55

R79
L9
0.5_0603_1%
CHB1608U301_0603
1
2+3GPLL 1
2
+1.5VS

L49
CHB1608U301_0603
1
2

+2.5VS_3GBG

2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z

2 2.2U_0603_6.3V6K

2 2.2U_0603_6.3V6K

C469

2 2.2U_0603_6.3V6K

+3VS

1
R410

2
0_0603_5%

VCCA_TVDAC

C432

2 0.1U_0402_16V4Z

+2.5VS

VCCA_TVBG (Ball H18)

C422

C433

2 0.022U_0402_16V7K 2 0.1U_0402_16V4Z

C438

2 0.022U_0402_16V7K

1
C475

2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z

C474

2 0.1U_0402_16V4Z

1
+1.5VS_MPLL
L7
CHB1608U301_0603
1
2
+1.5VS

C463

C496

+3VS_TVDAC

+1.5VS_HPLL

C462

C53

+1.5VS

2 22U_1206_16V4Z_V1

950mA

470U_D2_2.5VM

2 10U_1206_16V4Z 2 0.1U_0402_16V4Z

C428
0.1U_0402_16V4Z

120mA

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

of

51

U 5H
U5I

+1.05VS

L12
M12
N12
P12
R12
T12
U12
V12
W12
L13
M13
N13
P13
R13
T13
U13
V13
W13

VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0

Y12
AA12
Y13
AA13
L14
M14
N14
P14
R14
T14
U14
V14
W14
Y14
AA14
AB14
L15
M15
N15
P15
R15
T15
U15
V15
W15
Y15
AA15
AB15
L16
M16
N16
P16
R16
T16
U16
V16
W16
Y16
AA16
AB16
R17
Y17
AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20
R21
Y21
AA21
AB21
Y22
AA22
AB22
Y23
AA23
AB23
Y24
AA24
AB24
Y25
AA25
AB25
Y26
AA26
AB26

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0

V25
W25
L26
M26
N26
P26
R26
T26
U26
V26
W26

VCC_NCTF10
VCC_NCTF9
VCC_NCTF8
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF1
VCC_NCTF0

VCCSM_NCTF31
VCCSM_NCTF30
VCCSM_NCTF29
VCCSM_NCTF28
VCCSM_NCTF27
VCCSM_NCTF26
VCCSM_NCTF25
VCCSM_NCTF24
VCCSM_NCTF23
VCCSM_NCTF22
VCCSM_NCTF21
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
VCCSM_NCTF16
VCCSM_NCTF15
VCCSM_NCTF14
VCCSM_NCTF13
VCCSM_NCTF12
VCCSM_NCTF11
VCCSM_NCTF10
VCCSM_NCTF9
VCCSM_NCTF8
VCCSM_NCTF7
VCCSM_NCTF6
VCCSM_NCTF5
VCCSM_NCTF4
VCCSM_NCTF3
VCCSM_NCTF2
VCCSM_NCTF1
VCCSM_NCTF0

NCTF

+1.05VS

VCC_NCTF78
VCC_NCTF77
VCC_NCTF76
VCC_NCTF75
VCC_NCTF74
VCC_NCTF73
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF63
VCC_NCTF62
VCC_NCTF61
VCC_NCTF60
VCC_NCTF59
VCC_NCTF58
VCC_NCTF57
VCC_NCTF56
VCC_NCTF55
VCC_NCTF54
VCC_NCTF53
VCC_NCTF52
VCC_NCTF51
VCC_NCTF50
VCC_NCTF49
VCC_NCTF48
VCC_NCTF47
VCC_NCTF46
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF42
VCC_NCTF41
VCC_NCTF40
VCC_NCTF39
VCC_NCTF38
VCC_NCTF37
VCC_NCTF36
VCC_NCTF35
VCC_NCTF34
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF19
VCC_NCTF18
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF14
VCC_NCTF13
VCC_NCTF12
VCC_NCTF11

AB12
AC12
AD12
AB13
AC13
AD13
AC14
AD14
AC15
AD15
AC16
AD16
AC17
AD17
AC18
AD18
AC19
AD19
AC20
AD20
AC21
AD21
AC22
AD22
AC23
AD23
AC24
AD24
AC25
AD25
AC26
AD26

+DDRVCC

L17
M17
N17
P17
T17
U17
V17
W17
L18
M18
N18
P18
R18
Y18
L19
M19
N19
P19
R19
Y19
L20
M20
N20
P20
R20
Y20
L21
M21
N21
P21
T21
U21
V21
W21
L22
M22
N22
P22
R22
T22
U22
V22
W22
L23
M23
N23
P23
R23
T23
U23
V23
W23
L24
M24
N24
P24
R24
T24
U24
V24
W24
L25
M25
N25
P25
R25
T25
U25

+1.05VS

U5J

VSS271
VSS270
VSS269
VSS268
VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196

VSSALVDS

VSS

VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130

AL24
AN24
A26
E26
G26
J26
B27
E27
G27
W27
AA27
AB27
AF27
AG27
AJ27
AL27
AN27
E28
W28
AA28
AB28
AC28
A29
D29
E29
F29
G29
H29
L29
P29
U29
V29
W29
AA29
AD29
AG29
AJ29
AM29
C30
Y30
AA30
AB30
AC30
AE30
AP30
D31
E31
F31
G31
H31
J31
K31
L31
M31
N31
P31
R31
T31
U31
V31
W31
AD31
AG31
AL31
A32
C32
Y32
AA32
AB32

B36
AA11
AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23
B24
D24
F24
J24
AG24
AJ24

ALVISO_BGA1257

VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68

AC32
AD32
AJ32
AN32
D33
E33
F33
G33
H33
J33
K33
L33
M33
N33
P33
R33
T33
U33
V33
W33
AD33
AF33
AL33
C34
AA34
AB34
AC34
AD34
AH34
AN34
B35
D35
E35
F35
G35
H35
J35
K35
L35
M35
N35
P35
R35
T35
U35
V35
W35
Y35
AE35
C36
AA36
AB36
AC36
AD36
AE36
AF36
AJ36
AL36
AN36
E37
H37
K37
M37
P37
T37
V37
Y37
AG37

VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0

VSS

ALVISO_BGA1257

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601

ALVISO_BGA1257

Y1
D2
G2
J2
L2
P2
T2
V2
AD2
AE2
AH2
AL2
AN2
A3
C3
AA3
AB3
AC3
AJ3
C4
H4
L4
P4
U4
Y4
AF4
AN4
E5
W5
AL5
AP5
B6
J6
L6
P6
T6
AA6
AC6
AE6
AJ6
G7
V7
AA7
AG7
AK7
AN7
C8
E8
L8
P8
Y8
AL8
A9
H9
K9
T9
V9
AA9
AC9
AE9
AH9
AN9
D10
L10
Y10
AA10
F11
H11
Y11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

10

of

51

+DDRVCC

+DIMM_VREF

+DDRVCC
DDR_A_D [0..63]

DD R_A_D16
DD R_A_D17

2
C816

C815

0.1U_0402_16V4Z

C814

JAE_MM50-200B1-1R~D

0.1U_0402_16V4Z

1
2
C857
0.1U_0402_16V4Z

C803

+3VS

C813

D_CK_SDATA
D_CK_SCLK

0.1U_0402_16V4Z

<12,14,38> D_CK_SDATA
<12,14,38> D_CK_SCLK

C802

DD R_A_D58
DD R_A_D59

C812

DDR_A_DM7

0.1U_0402_16V4Z

DD R_A_D56
DD R_A_D57

C811

DD R_A_D50
DD R_A_D51

0.1U_0402_16V4Z

DDR_A_DQS#6
D DR_A_DQS6

M_ODT0
DDR_A_MA13

DDR_A_BS#1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA# <6>

C810

DD R_A_D48
DD R_A_D49

DDR_A_BS#1
D DR_A_RAS#
DDR_CS0_DIMMA#

0.1U_0402_16V4Z

DD R_A_D42
DD R_A_D43

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

C809

DDR_A_DM5

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

0.1U_0402_16V4Z

DD R_A_D40
DD R_A_D41

DDR_CKE1_DIMMA <6>

C808

DD R_A_D34
DD R_A_D35

DDR_CKE1_DIMMA

0.1U_0402_16V4Z

DDR_A_DQS#4
D DR_A_DQS4

C799

+0.9V_DDR_VTT

C807

DD R_A_D32
DD R_A_D33
B

C798

DD R_A_D30
DD R_A_D31

0.1U_0402_16V4Z

M_ODT1

C797

DDR_A_DQS#3
D DR_A_DQS3

C806

<6> M_ODT1

D DR_A_CAS#
DDR_CS1_DIMMA#

DD R_A_D28
DD R_A_D29

0.1U_0402_16V4Z

<7> DDR_A_CAS#
<6> DDR_CS1_DIMMA#

DDR_A_MA10
DDR_A_BS#0
DDR_A_W E#

DDR_A_DM2

C796

DD R_A_D22
DD R_A_D23

C805

<7> DDR_A_BS#0
<7> DDR_A_W E#

DD R_A_D20
DD R_A_D21

C804

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

C795

DD R_A_D14
DD R_A_D15

0.1U_0402_16V4Z

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

Layout Note:
Place near DIMM

M_CLK_DDR0 <6>
M_CLK_DDR#0 <6>

0.1U_0402_16V4Z

DDR_A_BS#2

DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0

0.1U_0402_16V4Z

<7> DDR_A_BS#2

DDR_CKE0_DIMMA

+DDRVCC
1K_0402_1%

0.1U_0402_16V4Z

<6> DDR_CKE0_DIMMA

R91

0.1U_0402_16V4Z

DD R_A_D26
DD R_A_D27

DDR_A_ DQS#[0..7]

C801

DDR_A_DM3
C

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DD R_A_MA[0..13]

<7> DDR_A_DQS#[0..7]

C800

DD R_A_D24
DD R_A_D25

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

DD R_A_D12
DD R_A_D13

DDR_A_D QS[0..7]

<7> DDR_A_MA[0..13]

0.1U_0402_16V4Z

DD R_A_D18
DD R_A_D19

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DDR _A_D6
DDR _A_D7

1K_0402_1%

0.1U_0402_16V4Z

DDR_A_DQS#2
D DR_A_DQS2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_A_DM0

4.7U_0805_10V4Z

DD R_A_D10
DD R_A_D11

DDR_A_ DM[0..7]

<7> DDR_A_DQS[0..7]

4.7U_0805_10V4Z

DDR_A_DQS#1
D DR_A_DQS1

DDR _A_D4
DDR _A_D5

R92

4.7U_0805_10V4Z

DDR _A_D8
DDR _A_D9

C840

DDR _A_D2
DDR _A_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

4.7U_0805_10V4Z

DDR_A_DQS#0
D DR_A_DQS0

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

C121

DDR _A_D0
DDR _A_D1

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

0.1U_0402_16V4Z

JP24

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

<7> DDR_A_D[0..63]
<7> DDR_A_DM[0..7]

4.7U_0805_10V4Z

+DDRVCC

4.7U_0805_10V4Z

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

M_ODT0 <6>

DD R_A_D36
DD R_A_D37

+0.9V_DDR_VTT
RP30

DDR_A_DM4

DDR_A_MA8
1
DDR_A_MA5
2
56_0404_4P2R_5%

DD R_A_D38
DD R_A_D39

RP59

4
3

4
3

4
3

4
3

4
3

4
3

RP29
DDR_A_MA3
1
DDR_A_MA1
2
56_0404_4P2R_5%

DD R_A_D44
DD R_A_D45

D DR_A_RAS#
1
DDR_CS0_DIMMA# 2
56_0404_4P2R_5%

DD R_A_D46
DD R_A_D47

DDR_A_MA10
DDR_A_BS#0
56_0404_4P2R_5%

1
2

M_CLK_DDR1 <6>
M_CLK_DDR#1 <6>

DDR_A_W E#
D DR_A_CAS#
56_0404_4P2R_5%

1
2

DDR_A_MA7
DDR_A_MA6
56_0404_4P2R_5%

1
2

DDR_A_MA12
DDR_A_MA9
56_0404_4P2R_5%

1
2

DDR_A_MA4
DDR_A_MA2
56_0404_4P2R_5%

1
2

DDR_A_MA0
DDR_A_BS#1
56_0404_4P2R_5%

1
2

M_ODT0
DDR_A_MA13
56_0404_4P2R_5%

1
2

DDR_CKE1_DIMMA
DDR_A_MA11
56_0404_4P2R_5%

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

RP35

4
3

4
3

4
3

4
3

RP26

M_CLK_DDR1
M_CLK_DDR#1

1
2

RP57

RP27

DD R_A_D52
DD R_A_D53

DDR_CKE0_DIMMA
DDR_A_BS#2
56_0404_4P2R_5%

RP58

RP28
DDR_A_DQS#5
D DR_A_DQS5

1
2

RP34

RP33

DDR_A_DM6

4
3

DD R_A_D54
DD R_A_D55
RP31
DD R_A_D60
DD R_A_D61

M_ODT1
2
DDR_CS1_DIMMA# 1
56_0404_4P2R_5%

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

RP32

3
4

4
3

DDR_A_DQS#7
D DR_A_DQS7

DD R_A_D62
DD R_A_D63
R692 1
R693 1

2 10K_0402_5%
2 10K_0402_5%

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

11

of

51

+DDRVCC

+DDRVCC

+DIMM_VREF

DD R_B_D10
DD R_B_D11

2
C839

C838

0.1U_0402_16V4Z

C837

JAE_MM50-200B1-1~D

0.1U_0402_16V4Z

C836

1
C858
0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VS

C835

D_CK_SDATA
D_CK_SCLK

0.1U_0402_16V4Z

<11,14,38> D_CK_SDATA
<11,14,38> D_CK_SCLK

C826

DD R_B_D58
DD R_B_D59

C834

DDR_B_DM7

0.1U_0402_16V4Z

C825

DD R_B_D56
DD R_B_D57

0.1U_0402_16V4Z

DD R_B_D50
DD R_B_D51

C833

DDR_B_DQS#6
D DR_B_DQS6

M_ODT2
DDR_B_MA13

0.1U_0402_16V4Z

DD R_B_D48
DD R_B_D49

C824

DDR_B_DM5
DD R_B_D42
DD R_B_D43

DDR_B_BS#1
D DR_B_RAS#
DDR_CS2_DIMMB#

C832

DD R_B_D40
DD R_B_D41

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

0.1U_0402_16V4Z

DD R_B_D34
DD R_B_D35

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

C831

DDR_B_DQS#4
D DR_B_DQS4

DDR_CKE3_DIMMB <6>

0.1U_0402_16V4Z

DD R_B_D32
DD R_B_D33

DDR_CKE3_DIMMB

C830

M_ODT3

Layout Note:
Place near DIMM

0.1U_0402_16V4Z

<6> M_ODT3

D DR_B_CAS#
DDR_CS3_DIMMB#

+0.9V_DDR_VTT

C829

<7> DDR_B_CAS#
<6> DDR_CS3_DIMMB#

DDR_B_MA10
DDR_B_BS#0
DDR_B_W E#

C821

DD R_B_D30
DD R_B_D31

C828

<7> DDR_B_BS#0
<7> DDR_B_W E#

C820

DDR_B_DQS#3
D DR_B_DQS3

C827

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

C819

DD R_B_D28
DD R_B_D29

0.1U_0402_16V4Z

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DD R_B_D22
DD R_B_D23

0.1U_0402_16V4Z

DDR_B_BS#2

DDR_B_DM2

0.1U_0402_16V4Z

<7> DDR_B_BS#2

DDR_CKE2_DIMMB

DD R_B_D20
DD R_B_D21

0.1U_0402_16V4Z

<6> DDR_CKE2_DIMMB

DD R_B_D14
DD R_B_D15

C818

0.1U_0402_16V4Z

DD R_B_D26
DD R_B_D27

C817

M_CLK_DDR3 <6>
M_CLK_DDR#3 <6>

0.1U_0402_16V4Z

DDR_B_DM3
2

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

C823

DD R_B_D24
DD R_B_D25

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

DDR_B_ DQS#[0..7]

+DDRVCC

0.1U_0402_16V4Z

DD R_B_D18
DD R_B_D19

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3

<7> DDR_B_DQS#[0..7]

C822

DDR_B_DQS#2
D DR_B_DQS2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DD R_B_D12
DD R_B_D13

DD R_B_MA[0..13]

<7> DDR_B_MA[0..13]

0.1U_0402_16V4Z

DD R_B_D16
DD R_B_D17

DDR _B_D6
DDR _B_D7

DDR_B_D QS[0..7]

4.7U_0805_10V4Z

DDR_B_DQS#1
D DR_B_DQS1

DDR_B_DM0

4.7U_0805_10V4Z

DDR _B_D8
DDR _B_D9

C841

<7> DDR_B_DQS[0..7]

4.7U_0805_10V4Z

DDR _B_D2
DDR _B_D3

DDR _B_D4
DDR _B_D5
4.7U_0805_10V4Z

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

C843

DDR_B_DQS#0
D DR_B_DQS0

DDR_B_ DM[0..7]

<7> DDR_B_DM[0..7]

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

0.1U_0402_16V4Z

DDR _B_D0
DDR _B_D1

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

DDR_B_D [0..63]

<7> DDR_B_D[0..63]

JP25

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

4.7U_0805_10V4Z

4.7U_0805_10V4Z

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

DDR_B_BS#1 <7>
DDR_B_RAS# <7>
DDR_CS2_DIMMB# <6>
M_ODT2 <6>

DD R_B_D36
DD R_B_D37

+0.9V_DDR_VTT
RP71

DDR_B_DM4
DD R_B_D38
DD R_B_D39

DDR_B_MA3
DDR_B_MA1
56_0404_4P2R_5%

1
2

DDR_B_MA10
DDR_B_BS#0
56_0404_4P2R_5%

1
2

DDR_B_MA0
DDR_B_BS#1
56_0404_4P2R_5%

1
2

4
3

4
3

4
3

4
3

4
3

4
3

4
3

4
3

4
3

RP70

DD R_B_D44
DD R_B_D45

DD R_B_D46
DD R_B_D47

DDR_B_W E#
D DR_B_CAS#
56_0404_4P2R_5%

M_CLK_DDR4 <6>
M_CLK_DDR#4 <6>

1
2

1
2

DDR_CKE3_DIMMB
DDR_B_MA11
56_0404_4P2R_5%

1
2

DDR_B_MA8
DDR_B_MA5
56_0404_4P2R_5%

1
2

DDR_B_MA7
DDR_B_MA6
56_0404_4P2R_5%

1
2

DDR_B_MA4
DDR_B_MA2
56_0404_4P2R_5%

1
2

M_ODT2
DDR_B_MA13

Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil

RP63

RP67

M_CLK_DDR4
M_CLK_DDR#4

DDR_B_MA12
DDR_B_MA9
56_0404_4P2R_5%

RP64

RP68
D DR_B_RAS#
1
DDR_CS2_DIMMB# 2
56_0404_4P2R_5%

DD R_B_D52
DD R_B_D53

1
2
RP65

RP69
DDR_B_DQS#5
D DR_B_DQS5

RP66

4
3

RP62

RP61

DDR_B_DM6

4
3

DD R_B_D54
DD R_B_D55

56_0404_4P2R_5%

DD R_B_D60
DD R_B_D61

RP56
M_ODT3
2
DDR_CS3_DIMMB# 1
56_0404_4P2R_5%

DDR_B_DQS#7
D DR_B_DQS7

Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"

RP60

3
4

4
3

1
2

DDR_CKE2_DIMMB
DDR_B_BS#2

56_0404_4P2R_5%

DD R_B_D62
DD R_B_D63
R695 1
R694 1

2 10K_0402_5%
2 10K_0402_5%

Compal Electronics, Inc.


Title

+3VS

SCHEMATIC, M/B LA-2601

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
E

12

of

51

Layout note :
Distrib ute as close as possible
to DDR-SODIMM.

+DDRVCC
1

1
C117
0.1U_0402_16V4Z

1
C103
0.1U_0402_16V4Z

1
C122
0.1U_0402_16V4Z

1
C102
0.1U_0402_16V4Z

+DDRVCC

1
C118
0.1U_0402_16V4Z

1
C136
0.1U_0402_16V4Z

1
C119
0.1U_0402_16V4Z

C138
0.1U_0402_16V4Z

+DDRVCC

1
C99
0.1U_0402_16V4Z

1
C137
0.1U_0402_16V4Z

1
C135
0.1U_0402_16V4Z

1
C124
0.1U_0402_16V4Z

1
C123
0.1U_0402_16V4Z

C85
150U_D2_6.3VM

C139
150U_D2_6.3VM

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-2601

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
E

13

of

51

+CLK_VDD48

FSC

FSB

FSA

CLKSEL0

CLKSEL1

CLKSEL2

CPU SRC PCI


MHz MHz MHz

2 2.2U_0603_6.3V6K

100

100

33.3

133

100

33.3

166

100

33.3

200

100

33.3

+ CLK_VDDREF

C555

+3VS

C157

2 0.047U_0402_16V7K

Clock Generator

+CLK_VDD1

L10
KC FBM-L11-201209-221LMAT_0805
1
2
1

C156
0.047U_0402_16V7K

40mil
1

C144
2.2U_0603_6.3V6K

1
C149
0.047U_0402_16V7K

1
C145
0.047U_0402_16V7K

1
C147
0.047U_0402_16V7K

C152
0.047U_0402_16V7K

+CLK_VCCA

+CLK_VDD1
U8

21
28
34

Table : ICS 954206B

+3VS

1
7

CL K_PCI2
2
10K_0402_5%

1
R153

CL K_PCI0
2
10K_0402_5%

CL K_PCI1
2
10K_0402_5%

R145

1
R135

42
48
2 + CLK_VDDREF
1_0402_5%
15mil

VDDCPU
VDDREF

1
R455

11
2 +CLK_VDD48
2.2_0402_5%
15mil

VDD48

C161
33P_0402_50V8J
1
2
CLK_ICH_48M R143 1

2 12_0402_5%

CLK_SD_48M
R147 1
CLK_14M_CODEC
2
R151

2 12_0402_5%
1
12_0402_5%

R141

C162
Y1
33P_0402_50V8J 14.318MHZ_16PF_DSX840GA
1
2

<19> CLK_ICH_48M
2

<23> CLK_SD_48M
<29> CLK_14M_CODEC

CLK_PCI0 = 0, Pin 35,36


are PCIe CLK pair
R77

<23> CLK_PCI_PCM

CLK_PCI1 = 0, Pin 17,18


are 96Mhz

C LK_PCI_LAN

<26> CLK_PCI_LAN

CLK_PC I_MINI

<28> CLK_PCI_MINI

CLK _PCI_SIO

<32> CLK_PCI_SIO

CLK_PCI_1394

<25> CLK_PCI_1394

C LK_PCI_LPC

<33> CLK_PCI_LPC

CLK_PCI_ICH

<17> CLK_PCI_ICH

1
R146

50

XTALOUT

49

CLKSEL2
CLKSEL0

12
53

FS_A/USB_48MHz
REF1/FSLC/TEST_SEL

CLKSEL1

16

FSLB/TEST_MODE

2
G
1

2
G
3

41

C LK_CPU1

R124 1

2 33_0402_5%

CLK_MCH_BCLK

40

CLK_CPU1# R120 1

2 33_0402_5%

CLK_MCH_BCLK#

CPUCLKT0

44

C LK_CPU0

R134 1

2 33_0402_5%

CLK_CPU_BCLK

X2

CPUCLKC0

43

CLK_CPU0# R128 1

2 33_0402_5%

CLK_CPU_BCLK#

CPUCLKT2_ITP/PCIEXT6

36

C LK_SRC3

R106 1

2 33_0402_5%

CLK_MCH_3GPLL

CPUCLKC2_ITP/PCIEXC6

35

CLK_SRC3# R102 1

2 33_0402_5%

CLK_MCH_3GPLL#

PCICLK4

PEREQ1#/PCIEXT5

33

PEREQ1#

R684 1

2 0_0402_5%

PE_REQ1#

PCICLK3

PEREQ2#/PCIEXC5

32

PEREQ2#

R685 1

2 0_0402_5%

PE_REQ2#

CL K_PCI2

56

CL K_PCI1

2
33_0402_5%

CL K_PCI0

47
39
2 CLKIR EF
475_0402_1% 15mil

PCICLK2/REQ_SEL
PCIEXT4

31

C LK_SRC2

R114 1

2 33_0402_5%

CLK_PCIE_VGA

PCIEXC4

30

CLK_SRC2# R110 1

2 33_0402_5%

CLK_PCIE_VGA#

ITP_EN/PCICLK_F0

SATACLKT

26

C LK_SRC4

2 33_0402_5%

CLK_PCIE_SATA

SCLK

SATACLKC

27

CLK_SRC4# R96

2 33_0402_5%

CLK_PCIE_SATA#

R678 1

2 33_0402_5%

CLK_EZ_CLK2

SELPCIEX_LCDCLK#/PCICLK_F1

SDATA

13

+3VS

C165
2 2.2U_0603_6.3V6K

C159
C163
2 0.047U_0402_16V7K 2 0.047U_0402_16V7K

CLK_MCH_BCLK# <6>

R100 1

PCIEXT3

24

C LK_SRC6

PCIEXC3

25

CLK_SRC6# R679 1

2 33_0402_5%

CLK_EZ_CLK2#

PCIEXT2

22

C LK_SRC7

R113 1

2 33_0402_5%

CLK_EZ_CLK1

PCIEXC2

23

CLK_SRC7# R109 1

2 33_0402_5%

CLK_EZ_CLK1#

PCIEXT1

19

C LK_SRC1

R121 1

2 33_0402_5%

CLK_PC IE_ICH

PCIEXC1

20

CLK_SRC1# R117 1

2 33_0402_5%

CLK_P CIE_ICH#

R129 1

2 33_0402_5%

CL K_DREF_SSC

29

GND_1

LCDCLK_SS/PCIEX0T

17

C LK_SRC0

GND_2

LCDCLK_SS/PCIEX0C

18

CLK_SRC0# R125 1

2 33_0402_5%

C LK_DREF_SSC#

45

GND_3
DOTT_96MHz
DOTC_96MHz

14
15

CLK_DOT
CLK_DOT#

2 33_0402_5%
2 33_0402_5%

CLK_DREF_96M
CLK_DREF_96M#

51

GND_4

GND_5

R136 1
R131 1

+3VS

+1.05VS

R456
@ 1K_0402_5%
R457
0_0402_5%
1
2

2
R459
0_0402_5%

MCH_CLKSEL0 <6>
CPU_BSEL0 <5>

R453
4.7K_0402_5%
CLKSEL1 1
2

1
R451
@ 0_0402_5%

2
1
R458
@ 0_0402_5%

R460
4.7K_0402_5%
CLKSEL0 1
2

CLK_CPU_BCLK# <4>

CLK_MCH_3GPLL <8>

CLK_PCIE_SATA

2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%

1
R101
1
R97
CLK_MCH_3GPLL 1
R107
CLK_MCH_3GPLL# 1
R103
CLK_PCIE_VGA
1
R115
CLK_PCIE_VGA# 1
R111
CLK_PC IE_ICH
1
R122
CLK_P CIE_ICH#
1
R118
CL K_DREF_SSC 1
R130
C LK_DREF_SSC# 1
R126
CLK_DREF_96M
1
R137
CLK_DREF_96M# 1
R132
CLK_EZ_CLK2
1
R680
CLK_EZ_CLK2#
1
R681

PE_REQ1# <33>

CLK_PCIE_SATA#

PE_REQ2# <33>
CLK_PCIE_VGA <16>
CLK_PCIE_VGA# <16>
CLK_PCIE_SATA <18>
CLK_PCIE_SATA# <18>
CLK_EZ_CLK2 <38>
CLK_EZ_CLK2# <38>
CLK_EZ_CLK1 <38>
CLK_EZ_CLK1# <38>
CLK_PCIE_ICH <19>
CLK_PCIE_ICH# <19>

1
R138

CLK_DREF_SSC <6>
CLK_DREF_SSC# <6>
CLK_DREF_96M <6>
CLK_DREF_96M# <6>

2
10K_0402_5%

VGATE <6,19,48>

52

VTT_POWERGD#
C LK_REF

1
R144

CLK_14M_SIO
2
12_0402_5%

CLK_14M_SIO <32>

1
R148

CLK_ICH_14M
2
12_0402_5%

CLK_ICH_14M <19>

3
S

10

REF0

R454
@ 1K_0402_5%

2
R448
0_0402_5%

2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%

CLK_MCH_3GPLL# <8>

VTT_PWRGD#/PD

ICS954226AGT_TSSOP56

R450
0_0402_5%
1
2

1
R123
1
R119
CLK_CPU_BCLK
1
R133
CLK_CPU_BCLK# 1
R127
CLK_EZ_CLK1
1
R112
CLK_EZ_CLK1#
1
R108

GND_0

D_CK_SDATA

+1.05VS

CLK_MCH_BCLK

CLK_CPU_BCLK <4>

Q17
2N7002_SOT23

CLK_MCH_BCLK <6>

IREF

+3VS

+3VS

CPUCLKT1
CPUCLKC1

PM_STP_CPU# <19,48>

CL K_PCI3

Q16
2N7002_SOT23

<19> CK_SDATA

54

PM_STP_PCI# <19>

CL K_PCI4

D_CK_SCLK

R461
4.7K_0402_5%
1
2

CPU_STOP#

STP_CPU#

40mil

CLK_MCH_BCLK#

+3VS

<19> CK_SCLK

STP_PCI#

2
33_0402_5%
2
33_0402_5%
2
33_0402_5%
2
33_0402_5%

1
R452

R462
4.7K_0402_5%
1
2

55

PCICLK5

46

PCI/SRC_STOP#

12_0402_5%

D_CK_SDATA

<11,12,38> D_CK_SDATA

GNDA

+CLK_VDD2

L11
KC FBM-L11-201209-221LMAT_0805
1
2

+3VS

C150
2 0.047U_0402_16V7K

CL K_PCI5

D_CK_SCLK

<11,12,38> D_CK_SCLK

37
38

+CLK_VDD1

X1

2 12_0402_5%

1
1
R71
1
R150
1
R149
1
R154
1
R142

XTALIN

C553
2 2.2U_0603_6.3V6K

VDDA

VDDPCI_0
VDDPCI_1

+CLK_VDD1

CLK_PCI2 = 1, Pin 32,33


are PEREQ# pin

CLKSEL2
2
10K_0402_5%

1
R139

VDDPCIEX_0
VDDPCIEX_1
VDDPCIEX_2

40mil

2
G

+CLK_VDD2

1
2
R449
2.2_0402_5%

Q14
2N7002_SOT23

Compal Electronics, Inc.


Title

MCH_CLKSEL1 <6>
CPU_BSEL1 <5>

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005
G

Sheet

of

14
H

51

CRT Connector

+5VS

+R_CRT_VCC

+5VS

R18

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

0_0402_5%

1A
2A
3A
4A

1B2
2B2
3B2
4B2

3
6
10
13

CRT_B

GND

R2

R3

150_0402_5%

C9

C8

150_0402_5% 2 8P_0402_50V8K 2 8P_0402_50V8K 2

C7
C1
8P_0402_50V8K

P
OE#

C RT_HSYNC 2

2
PM@ 0_0402_5%
2
GM@ 39_0402_5%

1
L2

2 2@0_0402_5%

C RT_R

CRT_G_1 R713 1

2 2@0_0402_5%

CRT_G

CRT_B_1

2 2@0_0402_5%

CRT_B

C6
10P_0402_50V8J

C409 2
68P_0402_50V8K

DSUB_15

C407
68P_0402_50V8K

D_CRT_HSYNC <38>

5
1
P
OE#

CRT_VS YNC

33P for GMCH

D_CRT_V SYNC

D_CRT_VSYNC <38>

U35
SN74AHCT1G125GW_SOT353-5

+CRT_VCC

R714 1

2
PM@ 0_0402_5%
2
GM@ 39_0402_5%

R4
4.7K_0402_5%

2 PM@ 0_0402_5%

+3VS

R10

2 GM@ 0_0402_5%

+2.5VS

R11
2

2
4.7K_0402_5%
1
D

DSUB_12

R5

2
<38> D_DDC_DATA

R9

CRT_R_1 R712 1

1
R377
1
R378

2
0.1U_0402_16V4Z

<8> GMCH_CRT_VSYNC

C5
10P_0402_50V8J

+CRT_VCC

<16> VGA_CRT_VSYNC

D_CRT_HSYNC

(CL55)

VSYNC_L

2
FCM1608C-121T_0603

U1
SN74AHCT1G125GW_SOT353-5

1
C410

H S YNC_L

2
FCM1608C-121T_0603

DSUB_12

1
10K_0402_5%

5
1

C10

2
R6

C408
100P_0402_25V8K

1
L1

2
0.1U_0402_16V4Z

C3
8P_0402_50V8K

2
8P_0402_50V8K

8P_0402_50V8K

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

DDC_MD2

1
1

C2

10P for GMCH

1
R8
1
R7

1
2 CRT_R_L
L3
FCM2012C-800_0805
1
2 CRT_G_L
L4
FCM2012C-800_0805
1
2 CRT_B_L
L5
FCM2012C-800_0805

+CRT_VCC

<8> GMCH_CRT_HSYNC

JP1
CRT-15P

CRT_G

150_0402_5%

D_CRT_R <38>
D_CRT_G <38>
D_CRT_B <38>
C RT_R

FSAV330MTC_TSSOP16

<16> VGA_CRT_HSYNC

2
+3VS

D_ CRT_R
D_CRT_G
D_CRT_B

R1

C4
0.1U_0402_16V4Z

DSUB_15

VGA_DDC_DATA

Q1
BSS138_SOT23
<38> D_DDC_CLK

GM@ 0_0402_5%
1

GMCH_CRT_DATA <8>

VGA_DDC_DATA <16>

2
G

1
1

0_0402_5%

2
5
11
14

D21
@ DAN217_SC59

2
G

1
1

2 PM@
2
GM@
2 PM@
2
GM@
2 PM@
2
GM@

16

1B1
2B1
3B1
4B1

POLYSW ITCH_1A

R21
R19

1
1

VCC

<16> VGA_CRT_B
<8> GMCH_CRT_B

R33
R32

4
7
9
12

SEL
OE#

<16> VGA_CRT_G
<8> GMCH_CRT_G

R34

CRT_R_1
CRT_G_1
CRT_B_1

1
15

<16> VGA_CRT_R
<8> GMCH_CRT_R

DOCKIN#

<22,27,33,38> DOCKIN#

2 0.1U_0402_16V4Z

1
C18

W=40mils

F1

RB411D_SOT23

U4

+CRT_VCC

W=40mils

D1

D23
D22
@ DAN217_SC59 @ DAN217_SC59

V GA_DDC_CLK

VGA_DDC_CLK <16>

Q2
BSS138_SOT23

2
1
R12
GM@ 0_0402_5%

GMCH_CRT_CLK <8>

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
E

15

of

51

LCD POWER CIRCUIT

B+

P
OE#

5
1

+3VALW

GM@ 0.01U_0402_16V7K

1
C868

1
C869

PCIE_MTX_C_GRX_P[0..15]

<8> PCIE_MTX_C_GRX_P[0..15]

C870

@ 0.1U_0402_25V4K

VGA BOARD Conn.

R62

JP11

Bypass CAP under B+ trace(+25V)

+3VS

R53

B+

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159

1 2

GM@ 100_0402_5%

2
G

GM@ 100K_0402_5%

+LCDVDD

<15> VGA_CRT_R

VGA_CRT_R

<15> VGA_CRT_G

VGA_CRT_G

<15> VGA_CRT_B

VGA_CRT_B

1
R55

DAC_B RIG
DISP OFF#
INVT_PWM

Q9
GM@ SI2301DS_SOT23

C27
GM@ 0.047U_0402_16V7K

C28
GM@ 4.7U_0805_10V4Z

C29

+3VALW

GM@ 0.1U_0402_16V4Z

+2.5VS
<22> DVI_TXC+
<22> DVI_TXC<22> DVI_TXD0+
<22> DVI_TXD0-

<22> DVI_TXD1+
<22> DVI_TXD1-

+3VS

<22> DVI_TXD2+
<22> DVI_TXD2-

C19
@ 0.1U_0402_16V4Z

R510 1

DVI@ 2 0_0402_5%
GMCH_ENBKL
<8,33> GMCH_ENBKL

<19> PLTRST_VGA#

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1

+3VS

PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
R477

PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3

4.7K_0402_5%
<33> BKOFF#

BKOFF#

D32
2 RB751V_SOD323

PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4

DISP OFF#

PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6

PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8

LCD/PANEL BD. Conn.

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9

JP6
B+
+3VS
<8> GMCH_LCD_CLK
<8> GMCH_LCD_DATA

GMCH_LCD_CLK
GMCH_LCD_DATA

<8> GMCH_TZOUT0<8> GMCH_TZOUT0+


<8>
<8>
<8>
<8>

GMCH_TZOUT1+
GMCH_TZOUT1GMCH_TZOUT2+
GMCH_TZOUT2-

GMCH_TZOUT0GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT1GMCH_TZOUT2+
GMCH_TZOUT2GMCH_TZCLKGMCH_TZCLK+

<8> GMCH_TZCLK<8> GMCH_TZCLK+


A

GM@ 301_0402_1%

Q8
GM@ 2N7002_SOT23

1
C867

@ 0.1U_0402_25V4K

C860

1
C866

PCIE_MTX_C_GRX_N[0..15]

<8> PCIE_MTX_C_GRX_N[0..15]

+LCDVDD

U33
GM@ SN74AHCT1G125GW_SOT353-5

PCEI_GTX_C_MRX_P[0..15]

<8> PCEI_GTX_C_MRX_P[0..15]

@ 0.1U_0402_25V4K @ 0.1U_0402_25V4K @ 0.1U_0402_25V4K

PCEI_GTX_C_MRX_N[0..15]

<8> PCEI_GTX_C_MRX_N[0..15]

GM CH_ENVDD

<8> GMCH_ENVDD

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DAC_B RIG
INVT_PWM
DISP OFF#

PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10

DAC_BRIG <33>
INVT_PWM <33>

PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11

+LCDVDD
GMCH_TXOUT0GMCH_TXOUT0+
GMCH_TXOUT1GMCH_TXOUT1+
GMCH_TXOUT2+
GMCH_TXOUT2GMCH_TXCLKGMCH_TXCLK+

PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12

GMCH_TXOUT0- <8>
GMCH_TXOUT0+ <8>
GMCH_TXOUT1GMCH_TXOUT1+
GMCH_TXOUT2+
GMCH_TXOUT2-

PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13

<8>
<8>
<8>
<8>

PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

GMCH_TXCLK- <8>
GMCH_TXCLK+ <8>

B+

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160

V GA_DDC_CLK
VGA_DDC_DATA

VGA_DDC_CLK <15>
VGA_DDC_DATA <15>

VGA_TV_LUMA

VGA_TV_LUMA <22>

VGA_TV_CRMA

VGA_TV_CRMA

VGA_TV_COMPS
VGA_C RT_HSYNC
SUSP#
VGA _CRT_VSYNC

VGA_TV_COMPS <22>
VGA_CRT_HSYNC <15>
SUSP# <33,35,40,47>
VGA_CRT_VSYNC <15>

<22>

+1.5VS
DVI_DET <22>
DVI_SCLK <22>
DVI_SDATA <22>
+3VS
+5VS

+5VALW
SDVO_SCLK
SDVO_SDAT

SDVO_SCLK <8>
SDVO_SDAT <8>
CLK_PCIE_VGA <14>
CLK_PCIE_VGA# <14>

PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_N0
PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_N1
PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_N2
PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_N3
PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_N4
PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_N5
PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_N6

PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_N7
PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_N8
PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_N9
PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_N10
PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_N11
PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_N12
PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_N13
PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_N14
PCEI_GTX_C_MRX_P15
PCEI_GTX_C_MRX_N15

DVI@ ACES_88081-1600

GM@ ACES_87216-4012

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

SCHEMATIC, M/B LA-2601


Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

16

of

51

RP89

RP88

1
2
3
4

+3VS

8
7
6
5

PCI_PLOCK#
P C I_ I RDY#
PCI_PERR#
PCI_DEVSEL#

8.2K_0804_8P4R_5%

RP91

1
2
3
4

+3VS

8
7
6
5

PCI_PIRQD#
PCI_ PIRQB#
PCI_PIRQC#
PCI_ PIRQA#

8.2K_0804_8P4R_5%
RP92

1
2
3
4

+3VS
C

8
7
6
5

PCI_ PIRQE#
PCI_PIRQF#
D_USB_SMI#2
PCI_ PIRQG#

8.2K_0804_8P4R_5%

U17B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PC I_AD10
PC I_AD11
PC I_AD12
PC I_AD13
PC I_AD14
PC I_AD15
PC I_AD16
PC I_AD17
PC I_AD18
PC I_AD19
PC I_AD20
PC I_AD21
PC I_AD22
PC I_AD23
PC I_AD24
PC I_AD25
PC I_AD26
PC I_AD27
PC I_AD28
PC I_AD29
PC I_AD30
PC I_AD31

E2
E5
C2
F5
F3
E9
F2
D6
E6
D3
A2
D2
D5
H3
B4
J5
K2
K5
D4
L6
G3
H4
H2
H5
B3
M6
B2
K6
K3
A5
L1
K4

AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]

REQ[0]#
GNT[0]#
REQ[1]#
GNT[1]#
REQ[2]#
GNT[2]#
REQ[3]#
GNT[3]#
REQ[4]#/GPI[40]
GNT[4]#/GPO[48]
REQ[5]#/GPI[1]
GNT[5]#/GPO[17]
REQ[6]#/GPI[0]
GNT[6]#/GPO[16]

L5
C1
B5
B6
M5
F1
B8
C8
F7
E7
E8
F6
B7
D8

P CI_REQ#0
PCI_GNT#0
P CI_REQ#1
PCI_GNT#1
P CI_REQ#2
PCI_GNT#2
P CI_REQ#3
PCI_GNT#3
P CI_REQ#4

C/BE[0]#
C/BE[1]#
C/BE[2]#
C/BE[3]#

J6
H6
G4
G2

P CI_CBE#0
P CI_CBE#1
P CI_CBE#2
P CI_CBE#3

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#

A3
E1
R2
C3
E3
C5
G5
J1
J2

P C I_ I RDY#
PCI_PAR
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRD Y#

PLTRST#
PCICLK
PME#

R5
G6
P6

PLT_RST#
CLK_ICH _PCI

D9
C7
C6
M3

PCI_ PIRQE#
PCI_PIRQF#
PCI_ PIRQG#
PCI_PIRQH#

PCI

RP87

1
2
3
4

+3VS

8
7
6
5

P CI_REQ#3
D_USB_SMI#1
P CI_REQ#4
P CI_REQ#1

8.2K_0804_8P4R_5%

<23,25,26,28> PCI_FRAME#
<23> PCI_PIRQA#
<23> PCI_PIRQB#

RP90

1
2
3
4

+3VS

8
7
6
5

P CI_FRAME#

J3

FRAME#

PCI_ PIRQA#
PCI_ PIRQB#
PCI_PIRQC#
PCI_PIRQD#

N2
L2
M1
L3

PIRQ[A]#
PIRQ[B]#
PIRQ[C]#
PIRQ[D]#

Interrupt

AC5
AD5
AF4
AG4
AC9
AD9
AF8
AG8
U3

P CI_REQ#0
P CI_REQ#2
PCI_PIRQH#

8.2K_0804_8P4R_5%

I/F

PIRQ[E]#/GPI[2]
PIRQ[F]#/GPI[3]
PIRQ[G]#GPI[4]
PIRQ[H]#/GPI[5]

D_USB_SMI#1
PCI_GNT#5
D_USB_SMI#2

PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
PCI_GNT#1
PCI_REQ#2
PCI_GNT#2
PCI_REQ#3
PCI_GNT#3

Internal Pull-up.
Sample high destination is LPC.

<25>
<25>
<28>
<28>
<23>
<23>
<26>
<26>

PCI_GNT#5

<23,25,26,28> PCI_AD[0..31]

8.2K_0804_8P4R_5%

R231
@ 0_0402_5%

D_USB_SMI#1 <38>

PCI_SERR#
PCI_TRD Y#
P CI_FRAME#
PCI_STOP#

D_USB_SMI#2 <38>
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

<23,25,26,28>
<23,25,26,28>
<23,25,26,28>
<23,25,26,28>

P C I_ IRDY# <23,25,26,28>
PCI_PAR <23,25,26,28>
PCI_RST# <23,25,26,28,32,33>
PCI_DEVSEL# <23,25,26,28>
PCI_PERR# <23,25,26,28>
PCI_SERR# <23,25,26,28>
PCI_STOP# <23,25,26,28>
PCI_TRDY# <23,25,26,28>

PLT_RST# <6,19,21,32,33>
CLK_PCI_ICH <14>

CLK_PCI_ICH

8
7
6
5

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

<25>
<26>
<28>
<28>

R177
@ 10_0402_5%

1
2
3
4

+3VS

RESERVED

SATA[1]RXN/RSVD[1]
SATA[1]RXP/RSVD[2]
SATA[1]TXN/RSVD[3]
SATA[1]TXP/RSVD[4]
SATA[3]RXN/RSVD[5]
SATA[3]RXP/RSVD[6]
SATA[3]TXN/RSVD[7]
SATA[3]TXP/RSVD[8]
TP[3]/RSVD[9]

C192
@ 10P_0402_50V8J

ICH6_BGA609

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-2601


Size

R ev
C

401336
D ate:

Document Number
P , 17, 2005

Sheet
1

17

of

51

C269
12P_0402_50V8J
2
1

IN

U17A
+1.05VS

Y1
Y2

ICH_RTCX2

INTRUD ER#

1
R439
20K_0402_5%

+RTCVCC

IC H_RTCRST#

INTRUD ER#

close to RAM door

+3VS

1
JOPEN

J1

1
R706

RTCRST#

AA3
AA5

INTRUDER#
INTVRMEN

D12
B12
D11
F13

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

PH DD_LED#

C224
@ 10P_0402_50V8J
1
2

R210

<29,34> ICH_AC_SDOUT

PH DD_LED#

2 4.7K_0402_5%

ID E _ D I ORDY

R203 1

2 8.2K_0402_5%

I DE_IRQ

SATA[0]RXN
SATA[0]RXP
SATA[0]TXN
SATA[0]TXP

SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
SATA_ITX_DRX_N2
SATA_ITX_DRX_P2

AD7
AC7
AF6
AG6

SATA[2]RXN
SATA[2]RXP
SATA[2]TXN
SATA[2]TXP

CLK_PCIE_SATA# AC2
CLK_PCIE_SATA AC1

SATA_CLKN
SATA_CLKP

AG11
SATARBIAS AF11

ID E _ D I ORDY
I DE_IRQ
IDE_D DACK#
IDE_ DIOW #
IDE_DIO R#

AF16
AB16
AB15
AC14
AE16

SATARBIAS#
SATARBIAS

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

2 10K_0402_5%

+3VS

EC_GA20 <33>
H_A20M# <4>
0_0402_5%

H_CPUSLP#

2 @ 0_0402_5%
H_DPSLP# <4>

H_DPRSTP#

H_DPRSTP# <4>

FERR#

AF24

R696 1

H_FE RR#

H_FERR# <4>

CPUPWRGD/GPO[49]

AG25

H_PW RGOOD

H_PW RGOOD <4>

IGNNE#
INIT3_3V#
INIT#
INTR

AG26
AE22
AF27
AG24

H_IG NNE#

H_IGNNE# <4>

RCIN#

AD23

KB_RST#

NMI
SMI#

AF25
AG27

H_N MI
H_SMI#

H_NMI <4>
H_SMI# <4>

STPCLK#

AE26

H_STPCLK#

H_STPCLK# <4>

THRMTRIP#

AE23

THRMTRIP#

DA[0]
DA[1]
DA[2]

AC16
AB17
AC17

IDE _DA0
IDE _DA1
IDE _DA2

DCS1#
DCS3#

AD16
AE17

IDE _DCS1#
IDE _DCS3#

DD[0]
DD[1]
DD[2]
DD[3]
DD[4]
DD[5]
DD[6]
DD[7]
DD[8]
DD[9]
DD[10]
DD[11]
DD[12]
DD[13]
DD[14]
DD[15]

AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13

IDE_D D0
IDE_D D1
IDE_D D2
IDE_D D3
IDE_D D4
IDE_D D5
IDE_D D6
IDE_D D7
IDE_D D8
IDE_D D9
IDE_ DD10
IDE_ DD11
IDE_ DD12
IDE_ DD13
IDE_ DD14
IDE_ DD15

DDREQ

AB14

IDE_DD REQ

SATALED#

AE3
AD3
AG2
AF2

2 24.9_0402_1%

<21> ID E _ D IORDY
<21> IDE_IRQ
<21> IDE_DDACK#
<21> IDE_DIOW #
<21> IDE_DIOR#

AC19

ACZ_SDO

LPC_FRAME# <32,33>

SATA

R209

C9

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

<14> CLK_PCIE_SATA#
<14> CLK_PCIE_SATA

R201 1

ACZ_SDIN[0]
ACZ_SDIN[1]
ACZ_SDIN[2]

33_0402_5%

<21> SATA_DTX_C_IRX_N2
<21> SATA_DTX_C_IRX_P2

+3VS

F11
F10
B10

AC97_SDOUT_R

R206

<33> PHDD_LED#

AC_S DIN0

EC_GA20
H_A20M#

R180 1

ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#

LPC_FRAME#

H_IN IT#
H_IN TR

1
R176

R520 1

LANTXD[0]
LANTXD[1]
LANTXD[2]

A10

P3
AF22
AF23

2
56_0402_5%
2
@ 56_0402_5%

R186
H_DPRSTP#

AE27

LANRXD[0]
LANRXD[1]
LANRXD[2]

LPC_DRQ#1 <32>

AE24
AD27

E12
E11
C13

AC97_RST_R#

H_FE RR#

CPUSLP#

LAN_RSTSYNC

33_0402_5%

<29> ICH_AC_SDIN0
<34> ICH_AC_SDIN1

LPC_DRQ#1

<32,33>
<32,33>
<32,33>
<32,33>

DPRSLP#/TP[4]
DPSLP#/TP[2]

LAN_CLK

C10
B9

N6
P4

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

R190 1

F12

33_0402_5%

<29,34> ICH_AC_RST#

AC97_BITCLK
AC97_S YNC_R

R215

LDRQ[0]#
LDRQ[1]#/GPI[41]

AC-97/AZALIA

<29,34> ICH_AC_BITCLK
<29,34> IC H _AC_SYNC

R207
@ 10_0402_5%
2
1

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

A20GATE
A20M#

B11

C12
C11
E13

P2
N3
N5
N4

LFRAME#/FWH[4]

10K_0402_5%

AA2

LAD[0]/FWH[0]
LAD[1]/FWH[1]
LAD[2]/FWH[2]
LAD[3]/FWH[3]

LAN

C271
1U_0402_6.3V4Z
1
2

RTCX1
RTCX2

RTC

C270
12P_0402_50V8J
2
1

56_0402_5%

H_INIT# <4>
H_INTR <4>

H_CPUSLP# <4,6>

MAINPW ON <42,45,49>

+1.05VS

R188
10K_0402_5%
1
2

R181
@ 330_0402_5%
1
2

OUT

NC

1M_0402_1%
D

Q22
@ 2SC2411K_SC59

2
B
E

NC

PIDE

LPC

32.768KHZ_12.5P_1TJS125DJ2A073

R244

ICH_RTCX1

Y3

CPU

+RTCVCC

R246
10M_0402_5%
2
1

+3VS

EC_KBRST# <33>
+1.05VS

1
R182

2
75_0402_1%

THRMTRIP#

R187
56_0402_5%
H_THERMTRIP#

H_THERMTRIP# <4,6>

IDE_DA[0..2] <21>

IDE_DCS1# <21>
IDE_DCS3# <21>
IDE_DD[0..15] <21>

IDE_DDREQ <21>

ICH6_BGA609

Place near ICH6 side.


SATA_DTX_IRX_N0

2
C845

SATA_DTX_C_IRX_N0
1
@ 0.01U_0402_16V7K

SATA_DTX_C_IRX_N0

<36>

2
C846

SATA_DTX_C_IRX_P0
1
@ 0.01U_0402_16V7K

SATA_DTX_C_IRX_P0

<36>

SATA_ITX_C_DRX_N0
1
@ 0.01U_0402_16V7K

SATA_ITX_C_DRX_N0

<36>

SATA_ITX_C_DRX_P0
1
@ 0.01U_0402_16V7K

SATA_ITX_C_DRX_P0

<36>

SATA_DTX_IRX_P0

SATA_ITX_DRX_N0
C256
SATA_ITX_DRX_P0
C257
A

SATA_ITX_DRX_N2

SATA_ITX_C_DRX_N2
0.01U_0402_16V7K

SATA_ITX_C_DRX_N2

<21>

SATA_ITX_C_DRX_P2
0.01U_0402_16V7K

SATA_ITX_C_DRX_P2

<21>

C847
SATA_ITX_DRX_P2
C848

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-2601


Size

R ev
C

401336
D ate:

Document Number
P , 17, 2005

Sheet
1

18

of

51

+3VALW
U17C

SATA[0]GP/GPI[26]
SATA[1]GP/GPI[29]
SATA[2]GP/GPI[30]
SATA[3]GP/GPI[31]

CK_SCLK
CK_SDATA
LINKALERT#
ICH _SMLINK0
ICH _SMLINK1
MCH_SYN C#
SB_SPKR

Y4
W5
Y5
W4
U6
AG21
F8

SMBCLK
SMBDATA
LINKALERT#
SMLINK[0]
SMLINK[1]
MCH_SYNC#
SPKR

<35> SUS_STAT#
S YSRST#
<6> PM_BMBUSY#

<33,38> EZ_PE_REQ2#

D39
1
RB751V_SOD323

2
<33> EC_SMI#

RB751V_SOD323
<33> EC_SCI#

R711 2

1 @ 0_0402_5%

<14> PM_STP_PCI#

<16> PLTRST_VGA#

1
R197
1
R196
1
R193
1
R195
1
R198
1
R60

ICH_GP I7
EC_SMI#

AE19
R1

GPI[7]
GPI[8]

A C IN

W6

SMBALERT#/GPI[11]

LID_OUT#
EC_ SCI#

M2
R6

GPI[12]
GPI[13]

PM_STP_PCI#

AC21

STP_PCI#/GPO[18]

AB21

GPO[19]

PM_STP_CPU#

AD22

STP_CPU#/GPO[20]

PLTRST_VGA#

AD20
AD21

GPO[21]
GPO[23]

IDE_HRESET#

V3

GPIO[24]

SATA_DET#
EC_FLASH#
PM_CLKRUN#
CD_ DK_ON
SIDE_RSET#

P5
R3
T3
AF19
AF20
AC18

<21> IDE_HRESET#

ICH_GP I7
2
10K_0402_5%
PM_CLKRUN#
2
8.2K_0402_5%
ICH_VGATE
2
10K_0402_5%
MCH_SYN C#
2
10K_0402_5%
SERIRQ
2
10K_0402_5%
LID_OUT#
2
10K_0402_5%

<36> SATA_DET#
<35> EC_FLASH#
<25,26,28,32,33> PM_CLKRUN#
<21> CD_DK_ON
<21> SIDE_RSET#
PE_WAKE#

R676 2

<23,32,33> SERIRQ
<33> EC_THERM#

1
R248
1
R262

SYS_PW ROK
2
10K_0402_5%
EC_RSMRST#
2
10K_0402_5%

<6,14,48> VGATE

SYS_RESET#
BM_BUSY#/GPI[6]

+3VS

SUS_STAT#/LPCPD#

U2
AD19

<35> SB_INT_FLASH_SEL#
<14,48> PM_STP_CPU#

W3

PM_BMBUSY#

<33,42,45> A C IN
D35

<33> EC_LID_OUT#

0_0402_5%

U5
AB20

SERIRQ

AC20

THRM#

AF21

CLK14

A27

CLK48

GPI29
GPI28
GPI27
GPI26

<33> RTC_CLK
<33> PM_SLP_S3#

RTC_CLK

V6

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

T4
T5
T6

SLP_S3#
SLP_S4#
SLP_S5#

100_1206_8P4R_5%

1
R705

<39> SYS_PW ROK

PM_DPRSLPVR
2
100K_0402_5%

<48> PM_DPRSLPVR

<33> PBTN_OUT#
<6,17,21,32,33> PLT_RST#
<33> EC_RSMRST#

SYS_PW ROK

AA1

PM_DPRSLPVR

AE20

PWROK
DPRSLPVR/TP[1]

PM_BATLOW#

V2

BATLOW#/TP[0]

PBTN_OUT#

U1

PWRBTN#

PLT_RST#

V5

LAN_RST#

EC_RSMRST#

Y3

RSMRST#

PERn[1]
PERp[1]
PETn[1]
PETp[1]

H25
H24
G27
G26

EZ_PCIE_RXN1
EZ_PCIE_RXP1
EZ_PCIE_C_TXN1
EZ_PCIE_C_TXP1

PERn[2]
PERp[2]
PETn[2]
PETp[2]

K25
K24
J27
J26

EZ_PCIE_RXN2
EZ_PCIE_RXP2
EZ_PCIE_C_TXN2
EZ_PCIE_C_TXP2

PERn[3]
PERp[3]
PETn[3]
PETp[3]

M25
M24
L27
L26

PERn[4]
PERp[4]
PETn[4]
PETp[4]

P24
P23
N27
N26

DMI[0]RXN
DMI[0]RXP
DMI[0]TXN
DMI[0]TXP

T25
T24
R27
R26

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0

DMI[1]RXN
DMI[1]RXP
DMI[1]TXN
DMI[1]TXP

V25
V24
U27
U26

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1

DMI[2]RXN
DMI[2]RXP
DMI[2]TXN
DMI[2]TXP

Y25
Y24
W27
W26

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2

DMI[3]RXN
DMI[3]RXP
DMI[3]TXN
DMI[3]TXP

AB24
AB23
AA27
AA26

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3

DMI_CLKN
DMI_CLKP

AD25
AC25

CLK_P CIE_ICH#
CLK_PC IE_ICH

C791 1

2 1@ 0.1U_0402_16V4Z EZ_PCIE_TXN1
EZ_PCIE_TXP1
1
2
C792
1@ 0.1U_0402_16V4Z

C793 1

2 1@ 0.1U_0402_16V4Z EZ_PCIE_TXN2
EZ_PCIE_TXP2
1
2
C794
1@ 0.1U_0402_16V4Z

EZ_PCIE_RXN1
EZ_PCIE_RXP1
EZ_PCIE_TXN1
EZ_PCIE_TXP1

<38>
<38>
<38>
<38>

EZ_PCIE_RXN2
EZ_PCIE_RXP2
EZ_PCIE_TXN2
EZ_PCIE_TXP2

<38>
<38>
<38>
<38>

+3VALW

DMI_ZCOMP

F24

DMI_IRCOMP

F23

DMI_IRCOMP

OC[4]#/GPI[9]
OC[5]#/GPI[10]
OC[6]#/GPI[14]
OC[7]#/GPI[15]

C23
D23
C25
C24

USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

OC[0]#
OC[1]#
OC[2]#
OC[3]#

C27
B27
B26
C26

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3

USBP[0]N
USBP[0]P
USBP[1]N
USBP[1]P
USBP[2]N
USBP[2]P
USBP[3]N
USBP[3]P
USBP[4]N
USBP[4]P
USBP[5]N
USBP[5]P
USBP[6]N
USBP[6]P
USBP[7]N
USBP[7]P

C21
D21
A20
B20
D19
C19
A18
B18
E17
D17
B16
A16
C15
D15
A14
B14

USB20_N0
USB20_P0

USBRBIAS#
USBRBIAS

A22
B22

VRMPWRGD

E10

RP85

5
6
7
8

WAKE#

EC_THERM#

CLK_48M_ICH

4
3
2
1

GPIO[25]
GPIO[27]
GPIO[28]
CLKRUN#/GPIO[32]
GPIO[33]
GPIO[34]

SERIRQ

2
1 ICH_VGATE
R194
0_0402_5%
CLK_14M_ICH

PCI-EXPRESS

AF17
AE18
AF18
AG18

DIRECT MEDIA INTERFACE

<29> SB_SPKR

RI#

GPI26
GPI27
GPI28
GPI29

GPIO

<14> CK_SCLK
<14> CK_SDATA

T2

USB

EC_SW I#

<33> EC_SW I#

CLOCK

ICH _SMLINK0
2
10K_0402_5%
ICH _SMLINK1
2
10K_0402_5%
CK_SCLK
2
2.2K_0402_5%
CK_SDATA
2
2.2K_0402_5%
LINKALERT#
2
10K_0402_5%
EC_LID_OUT#
2
10K_0402_5%
EC_SW I#
2
10K_0402_5%
PM_BATLOW#
2
8.2K_0402_5%
PE_WAKE#
2
1K_0402_5%
S YSRST#
2
10K_0402_5%

POWER MGT

1
R259
1
R257
1
R464
1
R465
1
R260
1
R255
1
R256
1
R249
1
R258
1
R261

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0

<6>
<6>
<6>
<6>

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1

<6>
<6>
<6>
<6>

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2

<6>
<6>
<6>
<6>

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3

<6>
<6>
<6>
<6>

RP83
USB_OC#5
USB_OC#4
USB_OC#6
USB_OC#7

4
3
2
1

5
6
7
8

10K_1206_8P4R_5%

RP82
USB_OC#3
USB_OC#0
USB_OC#1
USB_OC#2

4
3
2
1

5
6
7
8

10K_1206_8P4R_5%

CLK_PCIE_ICH# <14>
CLK_PCIE_ICH <14>

R472 1

2 24.9_0402_1%

+1.5VS

USB_OC#4 <37>
USB_OC#6 <37>
USB_OC#0 <37>
USB_OC#2 <37>
USB20_N0 <37>
USB20_P0 <37>

USB20_N2
USB20_P2

USB20_N2 <37>
USB20_P2 <37>
B

USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6

US BRBIAS

USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6

1
R189

<37>
<37>
<34>
<34>
<37>
<37>

2
22.6_0402_1%

ICH6_BGA609

+3VALW

IN1

SLP_S4#

IN2

SLP_S5#

U21
CLK_14M_ICH

<14> CLK_ICH_14M

<33> PM_SLP_S5#

R218
@ 10_0402_5%

SN74AHC1G08DCKR_SC70

R470
@ 10_0402_5%

CLK_48M_ICH

<14> CLK_ICH_48M

C275
0.1U_0402_16V4Z
2

1
1

C559
@ 10P_0402_50V8J

C235
@ 10P_0402_50V8J

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate:

Document Number

R ev
C

401336
P , 17, 2005

Sheet
1

19

of

51

+1.5VS

+1.5VS

C232
0.1U_0402_16V4Z

2
+5VALW +3VALW

Near PIN AG9

C234
0.1U_0402_16V4Z

1
R191

D9
ICH6 _VCCPLL

RB751V_SOD323

10_0402_5%

+3VS

ICH_ V5REF_SUS

C213
1U_0603_10V4Z

C568
0.1U_0402_16V4Z

C560
0.1U_0402_16V4Z 1

Near PIN
E26, E27

C195
0.1U_0402_16V4Z 1

VCCDMIPLL
VCC3_3[1]

+3VS

A13
F14
G13
G14

C229
0.1U_0402_16V4Z

ICH6 _VCCPLL

C221
0.1U_0402_16V4Z

+1.5VS
A

AC27
E26

+1.5VS
+3VS

+3VALW
L15
R179
CHB1608U301_0603
0.5_0603_1%
1
2 ICH6_ VCCDMIPLL1
2

VCC1_5[56]
VCC1_5[57]
VCC1_5[58]
VCC1_5[59]
VCC1_5[60]
VCC1_5[61]
VCC1_5[62]
VCC1_5[63]
VCC1_5[64]
VCC1_5[65]

AE1
AG10

+3VALW

AA7
AA8
AA9
AB8
AC8
AD8
AE8
AE9
AF9
AG9

A11
U4
V1
V7
W2
Y7
A17
B17
C17
F18
G17
G18

U7
R7

VCCSUS1_5[1]

G19

VCC1_5[78]
VCC1_5[77]
VCC1_5[76]
VCC1_5[75]
VCC1_5[74]
VCC1_5[73]
VCC1_5[72]
VCC1_5[71]
VCC1_5[70]
VCC1_5[69]
VCC1_5[68]

G20
F20
E24
E23
E22
E21
E20
D27
D26
D25
D24

VCC1_5[67]

G8

CORE
SATA

+1.5VS

VCCSUS1_5[3]
VCCSUS1_5[2]

C226
C2231

Near PIN
AG13, AG16

C563
0.01U_0402_16V7K
1
2

Near PIN
A2-A6, D1-H1

Near PIN A25


C566
0.01U_0402_16V7K
1
2

+1.5VALW

Near PIN AA19

+3VALW
C574
0.1U_0402_16V4Z
1
2
+1.5VS

C573
0.1U_0402_16V4Z
1
2

+2.5VS

V5REF[2]
V5REF[1]

AA18
A8

ICH_V5REF _RUN

V5REF_SUS

F21

ICH_ V5REF_SUS

VCCUSBPLL
VCCLAN3_3/VCCSUS3_3[1]
VCCSUS3_3[20]
VCCLAN3_3/VCCSUS3_3[2]
VCCLAN3_3/VCCSUS3_3[3]
VCCRTC
VCCLAN3_3/VCCSUS3_3[4]
VCCLAN1_5/VCCSUS1_5[2]
VCCSUS3_3[1]
VCCLAN1_5/VCCSUS1_5[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
V_CPU_IO[3]
VCCSUS3_3[4]
V_CPU_IO[2]
VCCSUS3_3[5]
V_CPU_IO[1]
VCCSUS3_3[6]
VCCSUS3_3[19]
VCCSUS3_3[7]
VCCSUS3_3[18]
VCCSUS3_3[8]
VCCSUS3_3[17]
VCCSUS3_3[9]
VCCSUS3_3[16]
VCCSUS3_3[10]
VCCSUS3_3[15]
VCCSUS3_3[11]
VCCSUS3_3[14]
VCCSUS3_3[12]
VCCSUS3_3[13]

A25
A24

+1.5VS
+3VALW

AB3

+RTCVCC

G11
G10

+1.5VS

AG23
AD26
AB22
G16
G15
F16
F15
E16
D16
C16

C565
0.1U_0402_16V4Z
1
2

+3VS

AB18
P7

VCCSATAPLL
VCC3_3[22]

C567
0.1U_0402_16V4Z
1
2

0.1U_0402_16V4Z

VCC2_5[4]
VCC2_5[2]

PCI/IDE RBP

C202
0.1U_0402_16V4Z
1
2

C571
0.1U_0402_16V4Z

Near PIN AG5

VCC1_5[46]
VCC1_5[47]
VCC1_5[48]
VCC1_5[49]
VCC1_5[50]
VCC1_5[51]
VCC1_5[52]
VCC1_5[53]
VCC1_5[54]
VCC1_5[55]

P1
M7
L7
L4
J7
H7
H1
E4
B1
A6

C203
0.1U_0402_16V4Z
1
2

0.1U_0402_16V4Z +3VS

0.1U_0402_16V4Z

AA6
AB4
AB5
AB6
AC4
AD4
AE4
AE5
AF5
AG5

VCC3_3[11]
VCC3_3[10]
VCC3_3[9]
VCC3_3[8]
VCC3_3[7]
VCC3_3[6]
VCC3_3[5]
VCC3_3[4]
VCC3_3[3]
VCC3_3[2]

C200
0.1U_0402_16V4Z
1
2

C267
0.1U_0402_16V4Z
1
2
C210
0.1U_0402_16V4Z
1
2

Near PIN A24

Near PIN AB18

+3VS

+1.05VS

C228
0.1U_0402_16V4Z
1
2

U17D

E27
Y6
Y27
Y26
Y23
W7
W25
W24
W23
W1
V4
V27
V26
V23
U25
U24
U23
U15
U13
T7
T27
T26
T23
T16
T15
T14
T13
T12
T1
R4
R25
R24
R23
R17
R16
R15
R14
R13
R12
R11
P22
P16
P15
P14
P13
P12
N7
N17
N16
N15
N14
N13
N12
N11
N1
M4
M27
M26
M23
M16
M15
M14
M13
M12
L25
L24
L23
L15
L13
K7
K27
K26
K23
K1
J4
J25
J24
J23
H27
H26
H23
G9
G7
G21
G12
G1

Near PIN AG23

VSS[172]
VSS[171]
VSS[170]
VSS[169]
VSS[168]
VSS[167]
VSS[166]
VSS[165]
VSS[164]
VSS[163]
VSS[162]
VSS[161]
VSS[160]
VSS[159]
VSS[158]
VSS[157]
VSS[156]
VSS[155]
VSS[154]
VSS[153]
VSS[152]
VSS[151]
VSS[150]
VSS[149]
VSS[148]
VSS[147]
VSS[146]
VSS[145]
VSS[144]
VSS[143]
VSS[142]
VSS[141]
VSS[140]
VSS[139]
VSS[138]
VSS[137]
VSS[136]
VSS[135]
VSS[134]
VSS[133]
VSS[132]
VSS[131]
VSS[130]
VSS[129]
VSS[128]
VSS[127]
VSS[126]
VSS[125]
VSS[124]
VSS[123]
VSS[122]
VSS[121]
VSS[120]
VSS[119]
VSS[118]
VSS[117]
VSS[116]
VSS[115]
VSS[114]
VSS[113]
VSS[112]
VSS[111]
VSS[110]
VSS[109]
VSS[108]
VSS[107]
VSS[106]
VSS[105]
VSS[104]
VSS[103]
VSS[102]
VSS[101]
VSS[100]
VSS[99]
VSS[98]
VSS[97]
VSS[96]
VSS[95]
VSS[94]
VSS[93]
VSS[92]
VSS[91]
VSS[90]
VSS[89]
VSS[88]
VSS[87]

GROUND

C233
0.1U_0402_16V4Z

C201
0.1U_0402_16V4Z
1
2

C570
0.1U_0402_16V4Z

C564
0.1U_0402_16V4Z
1
2

0.1U_0402_16V4Z

C265
0.1U_0402_16V4Z

1
0.1U_0402_16V4Z

C199
0.1U_0402_16V4Z
1
2

C572
0.1U_0402_16V4Z

C237

C266
0.1U_0402_16V4Z

AA10
AG19
AG16
AG13
AD17
AC15
AA17
AA15
AA14
AA12

C278

C2771

C240
0.1U_0402_16V4Z

2
C243
1U_0603_10V4Z

VCC3_3[21]
VCC3_3[20]
VCC3_3[19]
VCC3_3[18]
VCC3_3[17]
VCC3_3[16]
VCC3_3[15]
VCC3_3[14]
VCC3_3[13]
VCC3_3[12]

C569

ICH_V5REF _RUN
2

C562
0.1U_0402_16V4Z
1
2

0.1U_0402_16V4Z

C212
0.1U_0402_16V4Z

RB751V_SOD323

F9
U17
U16
U14
U12
U11
T17
T11
P17
P11
M17
M11
L17
L16
L14
L12
L11
AA21
AA20
AA19

PCIE

10_0402_5%

VCC1_5[98]
VCC1_5[97]
VCC1_5[96]
VCC1_5[95]
VCC1_5[94]
VCC1_5[93]
VCC1_5[92]
VCC1_5[91]
VCC1_5[90]
VCC1_5[89]
VCC1_5[88]
VCC1_5[87]
VCC1_5[86]
VCC1_5[85]
VCC1_5[84]
VCC1_5[83]
VCC1_5[82]
VCC1_5[81]
VCC1_5[80]
VCC1_5[79]

IDE

D10

VCC1_5[1]
VCC1_5[2]
VCC1_5[3]
VCC1_5[4]
VCC1_5[5]
VCC1_5[6]
VCC1_5[7]
VCC1_5[8]
VCC1_5[9]
VCC1_5[10]
VCC1_5[11]
VCC1_5[12]
VCC1_5[13]
VCC1_5[14]
VCC1_5[15]
VCC1_5[16]
VCC1_5[17]
VCC1_5[18]
VCC1_5[19]
VCC1_5[20]
VCC1_5[21]
VCC1_5[22]
VCC1_5[23]
VCC1_5[24]
VCC1_5[25]
VCC1_5[26]
VCC1_5[27]
VCC1_5[28]
VCC1_5[29]
VCC1_5[30]
VCC1_5[31]
VCC1_5[32]
VCC1_5[33]
VCC1_5[34]
VCC1_5[35]
VCC1_5[36]
VCC1_5[37]
VCC1_5[38]
VCC1_5[39]
VCC1_5[40]
VCC1_5[41]
VCC1_5[42]
VCC1_5[43]
VCC1_5[44]
VCC1_5[45]

PCI

R214

AA22
AA23
AA24
AA25
AB25
AB26
AB27
F25
F26
F27
G22
G23
G24
G25
H21
H22
J21
J22
K21
K22
L21
L22
M21
M22
N21
N22
N23
N24
N25
P21
P25
P26
P27
R21
R22
T21
T22
U21
U22
V21
V22
W21
W22
Y21
Y22

C204
0.1U_0402_16V4Z
1
2

+RTCVCC

U17E

USB

+3VS

+1.5VS

USB CORE

+5VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C561

0.1U_0402_16V4Z
C194

C242

C193

+1.5VS

220U_D2_4VM_R12

Near PIN F27(C155),


P27(C154), AB27(C157)

VSS[86]
VSS[85]
VSS[84]
VSS[83]
VSS[82]
VSS[81]
VSS[80]
VSS[79]
VSS[78]
VSS[77]
VSS[76]
VSS[75]
VSS[74]
VSS[73]
VSS[72]
VSS[71]
VSS[70]
VSS[69]
VSS[68]
VSS[67]
VSS[66]
VSS[65]
VSS[64]
VSS[63]
VSS[62]
VSS[61]
VSS[60]
VSS[59]
VSS[58]
VSS[57]
VSS[56]
VSS[55]
VSS[54]
VSS[53]
VSS[52]
VSS[51]
VSS[50]
VSS[49]
VSS[48]
VSS[47]
VSS[46]
VSS[45]
VSS[44]
VSS[43]
VSS[42]
VSS[41]
VSS[40]
VSS[39]
VSS[38]
VSS[37]
VSS[36]
VSS[35]
VSS[34]
VSS[33]
VSS[32]
VSS[31]
VSS[30]
VSS[29]
VSS[28]
VSS[27]
VSS[26]
VSS[25]
VSS[24]
VSS[23]
VSS[22]
VSS[21]
VSS[20]
VSS[19]
VSS[18]
VSS[17]
VSS[16]
VSS[15]
VSS[14]
VSS[13]
VSS[12]
VSS[11]
VSS[10]
VSS[9]
VSS[8]
VSS[7]
VSS[6]
VSS[5]
VSS[4]
VSS[3]
VSS[2]
VSS[1]

F4
F22
F19
F17
E25
E19
E18
E15
E14
D7
D22
D20
D18
D14
D13
D10
D1
C4
C22
C20
C18
C14
B25
B24
B23
B21
B19
B15
B13
AG7
AG3
AG22
AG20
AG17
AG14
AG12
AG1
AF7
AF3
AF26
AF12
AF10
AF1
AE7
AE6
AE25
AE21
AE2
AE12
AE11
AE10
AD6
AD24
AD2
AD18
AD15
AD10
AD1
AC6
AC3
AC26
AC24
AC23
AC22
AC12
AC10
AB9
AB7
AB2
AB19
AB10
AB1
AA4
AA16
AA13
AA11
A9
A7
A4
A26
A23
A21
A19
A15
A12
A1

ICH6_BGA609
C230
0.1U_0402_16V4Z
1
2

ICH6_BGA609

Near PIN AG10

Near PIN A17


C205 2
0.01U_0402_16V7K

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601

Near PIN
AC27
5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

20

of

51

HDD CONN
+5VS

HOT CDROM CONN(DCL55)


+5VMOD

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

+3VMOD
+1.8VMOD

CD _DK#
CD_RESET#

<33> CD_DK#

SATA_DTX_C_IRX_P2
SATA_DTX_C_IRX_N2

<18> SATA_DTX_C_IRX_P2
<18> SATA_DTX_C_IRX_N2

SATA_ITX_C_DRX_P2
SATA_ITX_C_DRX_N2

<18> SATA_ITX_C_DRX_P2
<18> SATA_ITX_C_DRX_N2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

JP36

80mils

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

+5VS
IDE _DCS3#
IDE _DA2
PD IAG#

<18> IDE_DCS3#

2
R637

1 ID E_CSEL
470_0402_5%

IDE_ DD15
IDE_ DD14
IDE_ DD13
IDE_ DD12
IDE_ DD11
IDE_ DD10
IDE_D D9
IDE_D D8

+5VS
R638
100K_0402_5%

+5VS

0.1U_0402_16V4Z

10U_0805_10V4Z

IDE_DA[0 ..2]

<18> IDE_DA[0..2]

JP49

IDE_DD[0..15]

<18> IDE_DD[0..15]

80mils

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

ID E_LED#
IDE _DCS1#
IDE _DA0
IDE _DA1
I DE_IRQ
IDE_D DACK#
ID E _ D I ORDY
IDE_DIO R#
IDE_ DIOW #
IDE_DD REQ

1
C748

C747

C746

IDE_LED# <33>
IDE_DCS1# <18>

2
1000P_0402_50V7K

1U_0603_10V4Z

IDE_IRQ <18>
IDE_DDACK# <18>
ID E _ D IORDY <18>
IDE_DIOR# <18>
IDE_DIOW # <18>
IDE_DDREQ <18>

C749

IDE_D D0
IDE_D D1
IDE_D D2
IDE_D D3
IDE_D D4
IDE_D D5
IDE_D D6
IDE_D D7
IDE_RESET#

1@ FOXCONNQL11253-A606
SUYIN_200138FR044G272ZU_44P
C

Q63
1@ AOS 3401_SOT23

2
1@ 240K_0402_5%

R688
1@ 200K_0402_5%

U64

C851

CD_RESET#

+3VS

1@ TC7SH08FU_SSOP5

1@ 0.1U_0402_16V4Z
<19> IDE_HRESET#

<19> CD_DK_ON

22K
<6,17,19,32,33> PLT_RST#

IDE_HRESET#

PLT_RST#

U56

Y
3

22K

IDE_RESET#

TC7SH08FU_SSOP5

CDROM CONN

Q64
1@ DTC124EK_SOT23

C750
2 0.1U_0402_16V4Z

2
5

R687

1 CDR_ PSW ITCH


1@ 10K_0402_5%

<19> SIDE_RSET#

1
1@ 1U_0805_25V4Z

2
C849

+3VMOD
C865
1@ 0.1U_0402_16V4Z

2
1
R686

1
C850
@ 10U_1206_16V4Z

1
2

+5VALW

+3VS

+5VS

+5VMOD

JP4
+3VS
B

1@ 0.1U_0402_16V4Z
2
G
C861 1
D

2
G

Q65

C862
1@ 0.1U_0402_16V4Z

1@ SI2302DS_SOT23

1@ 100K_0402_5%

R702

CDR_ PSW ITCH

CDROM_L
CD_A GND
IDE_RESET#
IDE_D D7
IDE_D D6
IDE_D D5
IDE_D D4
IDE_D D3
IDE_D D2
IDE_D D1
IDE_D D0

<29> INT_CD_L
<29> CD_AGND

+12VALW

+3VMOD

R703
Q56

IDE_ DIOW #
ID E _ D I ORDY
I DE_IRQ
IDE _DA1
IDE _DA0
IDE _DCS1#
ID E_LED#

1@ 200K_0402_5%2
C852

C853
@ 4.7U_0805_10V4Z

1@ 0.1U_0402_16V4Z

1@ 2N7002_SOT23

+5VS
+1.8VS
+5VS

2
R639

SD_CSEL
1
@ @470_0402_5%

2
G

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

2@ OCTEK_CDR-50DC1

CD ROM_R

INT_CD_R <29>

IDE_D D8
IDE_D D9
IDE_ DD10
IDE_ DD11
IDE_ DD12
IDE_ DD13
IDE_ DD14
IDE_ DD15
IDE_DD REQ
IDE_DIO R#

+5VS

10U_0805_10V4Z

IDE_D DACK#

C751

PD IAG#
IDE _DA2
IDE _DCS3#

C752

80mils

C753

C754

0.1U_0402_16V4Z

+5VS

1000P_0402_50V7K

<BOM Structure>

1
2
R640
@ @100K_0402_5%

+5VS

C863
1@ 0.1U_0402_16V4Z
2

Q66

+1.8VMOD

C854
1@ 0.1U_0402_16V4Z

Compal Electronics, Inc.

C855
@ 4.7U_0805_10V4Z

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z

1@ SI2302DS_SOT23

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

SCHEMATIC, M/B LA-2601


Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

21

of

51

P I_PW R

R531 1

2 @ 0_1206_5%

R532 1

+3VALW

1@ 0_1206_5%
+3VS
+DVI_VCC

4B1
5B1

37
36

D_DVI_TXD0D_DVI_TXD0+

32
31

D_DVI_TXC+
D_DVI_TXC-

22
23
52

D _DVI_DET
D_DVI_SDATA
D_ DVI_SCLK
M_DVI_TXD2M_DVI_TXD2+

12

A5

DVI_TXC+

14

A6

0B2
1B2

46
45

A7

2B2
3B2

41
40

M_DVI_TXD1M_DVI_TXD1+

SEL

4B2
5B2

35
34

M_DVI_TXD0M_DVI_TXD0+

LED0
LED1
LED2

6B2
7B2

30
29

M_DVI_TXC+
M_DVI_TXC-

0LED2
1LED2
2LED2

25
26
51

M_DVI_DET
M_DVI_SDATA
M_DVI_SCLK

D VI_DET
DVI_SDATA
DV I_SCLK

15
17
19
20
54

A4

6B1
7B1

DVI_TXD0+

DOCKIN#

<16> DVI_DET
<16> DVI_SDATA
<16> DVI_SCLK

A3

R650
DVI@ 4.7K_0402_5%

12
13

TMDS_DATA3TMDS_DATA3+

DDC_DATA

I2 CB_SDA

4
5

TMDS_DATA4TMDS_DATA4+

D_DVI_TXC+ <38>
D_DVI_TXC- <38>

20
21

TMDS_DATA5TMDS_DATA5+

23
24

TMDS_Clock+
TMDS_Clock-

C1

Analog Red

C2

Analog Green

C3

Analog Blue

C4

Analog HSYNC

Analog VSYNC

R651

R653
2

DVI@ 4.7K_0402_5%
I2 CB_SDA
1

D_DVI_DET <38>
D_DVI_SDATA <38>
D_DVI_SCLK <38>

DVI@ 6.8K_0402_5%
1
+3VS

M_DVI_SDATA

Q10
DVI@ BSS138_SOT23
I2 CB_SLC

M_DVI_TXC+
M_DVI_TXC-

M_DVI_SCLK

Q11
DVI@ BSS138_SOT23

2
1
+3VS
R654
DVI@ 6.8K_0402_5%

Hot Plug Detect

16

TMDS_DATA2/4 shield
TMDS_DATA1/3 shield
TMDS_DATA0/5 shield
TMDS_Clock shield

3
11
19
22

Analog GND
Analog GND(C5)

C5
C6

GND

15

+5VS

DVI@ TYCO_1470881-1

NC

2
D37
D VI@ RB411D_SOT23
+DVI_VCC

1@ PI3L500E_TQFN56~D

R648
M_DVI_DET

1
6
9
13
16
21
24
28
33
39
44
49
53
55

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13

D_DVI_TXD0- <38>
D_DVI_TXD0+ <38>

A2

0LED1
1LED1
2LED1

DVI_TXC-

<16> DVI_TXC-

I2 CB_SLC

DVI@ 20K_0603_5%

11

2
G

DVI_TXD0-

DDC_CLOCK

R652
D VI@ 0_0402_5%

+5V

<16> DVI_TXC+

DVI_TXD1+

TMDS_DATA2TMDS_DATA2+

D_DVI_TXD1- <38>
D_DVI_TXD1+ <38>

2
G

D_DVI_TXD1D_DVI_TXD1+

43
42

A1

2B1
3B1

<16> DVI_TXD0+

1
2

14

<16> DVI_TXD0-

DVI_TXD1-

TMDS_DATA1TMDS_DATA1+

M_DVI_TXD2M_DVI_TXD2+

<16> DVI_TXD1+

+DVI_VCC

D_DVI_TXD2- <38>
D_DVI_TXD2+ <38>

<16> DVI_TXD1-

DVI_TXD2+

+3VS

9
10

48
47

A0

<16> DVI_TXD2+

D_DVI_TXD2D_DVI_TXD2+

0B1
1B1

DVI_TXD2-

TMDS_DATA0TMDS_DATA0+

M_DVI_TXD1M_DVI_TXD1+

56
50
38
27
18
10
4
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0

U61

<16> DVI_TXD2-

17
18

JP41
M_DVI_TXD0M_DVI_TXD0+

R649
D38
@ SKS10-04AT_TSMA

DVI@ 100K_0603_5%

C758
DVI@ 0.1U_0402_16V4Z

RP120
DVI_TXD2+
DVI_TXD2-

1
2

4
3

M_DVI_TXD2+
M_DVI_TXD2B

2@ 0_0404_4P2R_5%
+5VS

<8> GMCH_TV_COMPS

1
R644
1
R645

0_0402_5%

4
7
9
12

1A
2A
3A
4A

0_0402_5%
0_0402_5%

D36
@ @DAN217_SOT23

3
6
10
13

1
2

TV@

L27 1
2
FBM-11-160808-121T_0603

TV@

L28 1
2
FBM-11-160808-121T_0603

CRMA

GND

R432

LUMA_L

DVI_TXD0+
DVI_TXD0-

1
2

1
2

1
C518

1
C495

1
C506

1
C485

2 TV@270P_0402_50V7K 2

(CL55)

1
C44

4
3

M_DVI_TXCM_DVI_TXC+

2@ 0_0404_4P2R_5%

C54

1 M_DVI_DET
2@ 0_0402_5%

2
R682

TV@S C O NN._SUYIN

M_DVI_TXD0+
M_DVI_TXD0-

RP123
DVI_TXCDVI_TXC+

D VI_DET

R428

4
3

2@ 0_0404_4P2R_5%

1
2
3
4
5
6
7

CRMA_L
COMPS_L

L41 1
2
FBM-11-160808-121T_0603

TV@

R643

M_DVI_TXD1+
M_DVI_TXD1-

RP122

LUMA

TV@FSAV330MTC_TSSOP16

4
3

2@ 0_0404_4P2R_5%

D_TV_LUMA <38>
D_TV_CRMA <38>
D_TV_COMPS <38>
JP10

1B2
2B2
3B2
4B2

DVI_TXD1+
DVI_TXD1-

+3VS

D_TV_LUMA
D_TV_CRMA
D_TV_COMPS

COMPS

2
PM@ 0_0402_5%
2
GM@ 0_0402_5%

D2
@ @DAN217_SOT23

<16> VGA_TV_COMPS

LUMA_1
CRMA_1
COMPS_1

2
5
11
14

<8> GMCH_TV_CRMA

0_0402_5%

1B1
2B1
3B1
4B1

D25
@ @DAN217_SOT23

<16> VGA_TV_CRMA

2
PM@
2
GM@
2
PM@
2
GM@

16

<8> GMCH_TV_LUMA

1
R422
1
R424
1
R434
1
R433

SEL
OE#

VCC

<16> VGA_TV_LUMA

1
15

U58
DOCKIN#

<15,27,33,38> DOCKIN#

RP121

RP124
DVI_SDATA
DV I_SCLK

1
2

4
3

M_DVI_SDATA
M_DVI_SCLK

2@ 0_0404_4P2R_5%

LUMA_1

R715 1

2 2@0_0402_5%

CRMA_1

R716 1

2 2@0_0402_5%

CRMA

COMPS_1

R717 1

2 2@0_0402_5%

COMPS

TV@150_0402_5% TV@150_0402_5% TV@270P_0402_50V7K


TV@270P_0402_50V7K
TV@150_0402_5%

LUMA

TV@330P_0402_50V7K
TV@330P_0402_50V7K
TV@330P_0402_50V7K

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

22

of

51

SD_PULLHIGH
2
51@ 0_0603_5%
SDCM_XDALE
2
51@ 43K_0402_5%
SDDA0_XDD7
2
51@ 43K_0402_5%
SDDA1_XDD0
2
51@ 43K_0402_5%
SDDA2_XDCL
2
51@ 43K_0402_5%
SDDA3_XDD4
2
51@ 43K_0402_5%

<17,25,26,28>
<17,25,26,28>
<17,25,26,28>
<17,25,26,28>

PCI_RST#

<17,25,26,28,32,33> PCI_RST#
<17,25,26,28> PCI_FRAME#
<17,25,26,28> PC I_IRDY#
<17,25,26,28> PCI_TRDY#
<17,25,26,28> PCI_DEVSEL#
<17,25,26,28> PCI_STOP#
<17,25,26,28> PCI_PERR#
<17,25,26,28> PCI_SERR#
<17,25,26,28> PCI_PAR
<17> PCI_REQ#2
<17> PCI_GNT#2
<14> CLK_PCI_PCM

+3VS
1
R604
1
R605
1
R606

PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0

SDCD#
2
@ 43K_0402_5%
SDWP
2
@ 43K_0402_5%
MSINS#
2
@ 43K_0402_5%

R587
51@ 43K_0402_5%

<24> SM_CD#
<33> CARD_LED#

23V_PCM_SUSP
10K_0402_5%
2 PCM_ID
100_0402_5%
PCI_PIRQA#
SD_PULLHIGH
PCI_PIRQB#

1
R585
PCI_AD20 1
R586

<17> PCI_PIRQA#
1

R588
1

+3VS

+3VS

+3VS

CLK_PCI_PCM

<17> PCI_PIRQB#
<19,32,33> SERIRQ

51@ 10K_0402_5%
SDOC#

<24> SDOC#

SDCD#
SDWP
SDPW REN#

<24> SDCD#
<24> SDWP
<24> SDPW REN#
<14> CLK_SD_48M
<24> SDCK
<24> XDWE1#

R595 1

2 51@ 22_0402_5%

R200 1

51@ 22_0402_5%

<24>
<24>
<24>
<24>
<24>

SDCM_XDALE
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4

SDCM_XDALE
SDDA0_XDD7
SDDA1_XDD0
SDDA2_XDCL
SDDA3_XDD4

G4
J4
K1
K3
L1
L2
L3
M1
M2
A1
B1
H1

PCIRST#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
PCIREQ#
PCIGNT#
PCICLK

L8
L11

RIOUT#_PME#
SUSPEND#

F4
K8
N9
K9
N10
L10
N11
M11
J9

B4
C8
D12
H11
L9
L6
N4
K2
G1
F3
VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1

A7
G13
VCCA2
VCCA1

2
C694
0.1U_0402_16V4Z

C695
0.1U_0402_16V4Z
D

S1_D[0..15]

S1_D[0..15] <24>

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3

B2
C3
B3
A3
C4
A6
D7
C7
A8
D8
A9
C9
A10
B10
D10
E12
F10
E13
F13
F11
G10
G11
G12
H12
H10
J11
J12
K13
J10
K10
K12
L13

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOW R#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

CCBE3#/REG#
CCBE2#/A12
CCBE1#/A8
CCBE0#/CE1#

B7
A11
E11
H13

S1_REG#
S1_A12
S1_A8
S1_CE1#

CRST#/RESET
CFRAME#/A23
CIRDY#/A15
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20
CPERR#/A14
CSERR#/WAIT#
CPAR/A13
CREQ#/INPACK#
CGNT#/WE#
CCLK/A16

B9
B11
A12
A13
B13
C12
C13
A5
D13
B8
C11
B12
C5
D5

S1_RST
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WE#
A16_CLK 1
R584
S1_BVD1
S1_WP

D11

S1_A19

CINT#/READY_IREQ#

D6

S1_RDY#

SPKROUT
CAUDIO/BVD2_SPKR#

M9
B5

PCM_SPK#
S1_BVD2

A4
L12
D9
C6
A2
E10
J13

S1_CD2#
S1_CD1#
S1_VS2
S1_VS1
S1_D2
S1_A18
S1_D14

CSTSCHG/BVD1_STSCHG#
CCLKRUN#/WP_IOIS16#

IDSEL

CBLOCK#/A19

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
MFUNC7

CCD2#/CD2#
CCD1#/CD1#
CVS2/VS2#
CVS1/VS1
CRSV3/D2
CRSV2/A18
CRSV1/D14

GRST#

SD/MMC/MS/SM

E7

VCC_SD

E8
F8
G7

SDCD#
SDWP/SMWPD#
SDPWREN33#

H5

SDCLKI

F6
E5
E6
F7
F5
G6

SDCLK/SMWE#
SDCMD/SMALE
SDDAT0/SMDATA7
SDDAT1/SMDATA0
SDDAT2/SMCLE
SDDAT3/SMDATA4

G5

GND_SD

IDSEL:
PCI_AD20

M12
N12

CBE3#
CBE2#
CBE1#
CBE0#

PCI_RST# M10

+VCC_5IN1

VPPD1
VPPD0

E1
J3
N1
N5

S1_A[0..25] <24>

1
C693
0.1U_0402_16V4Z

MSINS#
MSPWREN#/SMPWREN#
MSBS/SMDATA1
MSCLK/SMRE#
MSDATA0/SMDATA2
MSDATA1/SMDATA6
MSDATA2/SMDATA5
MSDATA3/SMDATA3

H7
J8
H8
E9
G9
H9
G8
F9

SMBSY#
SMCD#
SMWP#
SMCE#

H6
J7
J6
J5

1
C696
0.1U_0402_16V4Z

1
C697
0.1U_0402_16V4Z

1
C698
0.1U_0402_16V4Z

C699
0.1U_0402_16V4Z

S1_IOW R# <24>
S1_IORD# <24>
S1_OE# <24>
S1_CE2# <24>

S1_REG# <24>
S1_CE1# <24>
S1_RST <24>

S1_WAIT# <24>
S1_INPACK# <24>
S1_WE# <24>
S1_A16
2
33_0402_5%
S1_BVD1 <24>
S1_WP <24>

S1_CD1#

S1_RDY# <24>
PCM_SPK# <29>
S1_BVD2 <24>
S1_CD2# <24>
S1_CD1# <24>
S1_VS2 <24>
S1_VS1 <24>

XD_MS_PWREN#
MSBS_XDD1
1
2
MSD0_XDD2
R590 51@ 33_0402_5%
MSD1_XDD6
MSD2_XDD5
MSD3_XDD3

S1_CD2#

C705
10P_0402_50V8J

C706
10P_0402_50V8J

Closed to Pin L12

MSINS# <24>
XD_MS_PWREN# <24>
MSBS_XDD1 <24>
MSCLK_XDRE# <24>
MSD0_XDD2 <24>
MSD1_XDD6 <24>
MSD2_XDD5 <24>
MSD3_XDD3 <24>

MSD0_XDD2
MSD1_XDD6
MSD2_XDD5

XDBSY# <24>
XDCD# <24>
XDWP# <24>
XDCE# <24>

Closed to Pin A4

Close chip termenal

MSD3_XDD3
MSBS_XDD1

1
R591
1
R592
1
R594
1
R597
1
R599
1
R601

1
C692
0.1U_0402_16V4Z

1
R593
1
R596
1
R598
1
R600
1
R602

2
@ 43K_0402_5%
2
43K_0402_5%
@
2
@ 43K_0402_5%
2
@ 43K_0402_5%
2
@ 43K_0402_5%

R603
51@ 2.2K_0402_5%

CB714_LFBGA169

R589
@ 0_0805_5%

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

CARDBUS

Close chip termenal

+VCC_5IN1

C2
C1
D4
D2
D1
E4
E3
E2
F2
F1
G2
G3
H3
H4
J1
J2
N2
M3
N3
K4
M4
K5
L5
M5
K6
M6
N6
M7
N7
L7
K7
N8

S1_A[0..25]

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

C704
18P_0402_50V8K

D3
H2
L4
M8
K11
F12
C10
B6

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

+3VS

+3VS

PCI Interface

PCI_AD[0..31]

<17,25,26,28> PCI_AD[0..31]

VCCD1#
VCCD0#

U52
R583
10_0402_5%

CLK_PCI_PCM

+S1_VCC
+3VS

<24> VPPD0
<24> VPPD1
<24> VCCD0#
<24> VCCD1#

M13
N13

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

SCHEMATIC, M/B LA-2601


Size
Document Number
Custom
Date:

R ev
C

401336

, 17, 2005

Sheet
1

23

of

51

PCMCIA Power Controller


CardBus Socket
JP33
S1_A[0..25]

<23> S1_A[0..25]
+5VS

9
0.1U_0402_16V4Z

+S1_VCC

U53

C709

VCC
VCC
VCC

12V

13
12
11

40mil

+S1_VPP
+5VS
0.1U_0402_16V4Z

C713

4.7U_0805_10V4Z

C714

VPP
5
6

VCCD0
VCCD1
VPPD0
VPPD1

R607
10K_0402_5%

OC

SHDN

3.3V
3.3V

GND

3
4

16

C718

Close to
CardBus Conn.

C715
10U_0805_10V4Z

C717

4.7U_0805_10V4Z

20mil

C708 0.1U_0402_16V4Z
1
2
C710 10U_0805_10V4Z
1
2
C711 0.01U_0402_16V7K
1
2
C712
1U_0603_10V4Z

1
2
15
14

S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#

S1_D[0..15]

<23> S1_D[0..15]

5V
5V

+3VS
0.1U_0402_16V4Z

10

1
2
C707 0.1U_0402_16V4Z

VCCD0# <23>
VCCD1# <23>
VPPD0 <23>
VPPD1 <23>

<23> S1_CE1#
+S1_VCC

C716
0.1U_0402_16V4Z
2

<23> S1_OE#

<23> S1_WE#
<23> S1_RDY#
+S1_VCC
+S1_VPP

S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP

+S1_VPP

C719

CP-2211_SSOP16

4.7U_0805_10V4Z

C720

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

0.01U_0402_16V7K
2

<23> S1_WP

GND
GND
D3
CD1#
D4
D11
D5
D12
D6
D13
D7
D14
CE1#
D15
A10
CE2#
OE#
VS1#
A11
IORD#
A9
IOWR#
A8
A17
A13
A18
A14
A19
WE#
A20
IREQ#
A21
VCC
VCC
VPP1
VPP2
A16
A22
A15
A23
A12
A24
A7
A25
A6
VS2#
A5
RESET
A4
WAIT#
A3
INPACK#
A2
REG#
A1
SPKR#
A0
STSCHG#
D0
D8
D1
D9
D2
D10
IOIS16# CD2#
GND
GND

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOW R#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10
S1_CD2#

S1_CD1# <23>

S1_CE2# <23>
S1_VS1 <23>
S1_IORD# <23>
S1_IOW R# <23>

+S1_VCC
+S1_VPP

S1_VS2 <23>
S1_RST <23>
S1_WAIT# <23>
S1_INPACK# <23>
S1_REG# <23>
S1_BVD2 <23>
S1_BVD1 <23>

S1_CD2# <23>

SUPER_AC4-3000-250-3_RT

+3VS
1
R608

XDCD#
2
@ 43K_0402_5%

XDCD# <23>

+VCC_5IN1

SD CLK

SM_CD#

+VCC_5IN1

XDBSY#
MSCLK_XDRE#
XDCE#
XDCD#
SDDA2_XDCL

25
3
29
26
27
28
30
2
38

SDDA3_XDD4 <23>
SDDA2_XDCL <23>
SDDA1_XDD0 <23>
SDDA0_XDD7 <23>
SDWP <23>
SDCM_XDALE <23>

MSD0_XDD2
MSD1_XDD6
MSD2_XDD5
MSD3_XDD3
MSCLK_XDRE#
MSINS#
MSBS_XDD1

15
14
16
18
19
17
13
20

C721
@ 10P_0402_50V8K

SDCD# <23>
MSD0_XDD2 <23>
MSD1_XDD6 <23>
MSD2_XDD5 <23>
MSD3_XDD3 <23>
MSCLK_XDRE# <23>
MSINS# <23>
MSBS_XDD1 <23>

+VCC_5IN1

40
39
1
44

XDBSY#
1
2
R613 51@ 43K_0402_5%

MSCLK_XDRE#

<23> MSCLK_XDRE#

S1_WP
2
43K_0402_5%
S1_OE#
2
47K_0402_5%
S1_RST
2
47K_0402_5%
S1_CE1#
2
47K_0402_5%
S1_CE2#
2
47K_0402_5%

C722
@ 10P_0402_50V8K

XDBSY# <23>

1
R614
1
R617
1
R618
1
R619
1
R620

XDCE# <23>

+S1_VCC

Reserve for Debug.

R615
@ 0_0402_5%

R710
51@ 100K_0402_5%

51@ TAITN _R007-N3P-15-S

MS CLK

+VCC_5IN1

XDCD#

1
2 MSCLK_XDRE#
R609 51@ 43K_0402_5%
1
2 XDWE1#
R611 51@ 2.2K_0402_5%
1
2
R612 51@ 43K_0402_5%

R610
@ 0_0402_5%

+VCC_5IN1
SDCD#

xD PU and PD. Close to Socket

SDDA3_XDD4
SDDA2_XDCL
SDDA1_XDD0
SDDA0_XDD7
SDWP
SDCM_XDALE
SDCK

11
12
6
7
5
10
8
9
4
42
41

35
43
36
37

SD-DAT3
SD-DAT2
SD-DAT1
5 IN 1 CONN SD-DAT0
SD-WP-SW
SD-CMD
SD_CLK
SD-VCC
NC
SM_WP-IN / XD_WP-IN
SD-CD-SW
SM-WP-SW
SD-CD-COM
#SM_-WE / XD_-WE
#SM-ALE / XD-ALE
MS-DATA0
MS-DATA1
SM-LVD
MS-DATA2
SM-CD-SW
MS-DATA3
SM_-VCC / XD_-VCC
MS-SCLK
#SM_R/-B / XD_R/-B
MS-INS
#SM_-RE / XD_-RE
MS-BS
#SM_-CE / XD_-CE
MS-VCC
#SM_-CD
SM-CD-COM
XD-VCC
SM-CLE / XD-CLE
XD-CD
GND
GND

<23> SM_CD#

XDWP#
SDWP
XDWE1#
SDCM_XDALE

SM-D0
SM-D1 / XD-D1
SM-D2 / XD-D2
SM-D3 / XD-D3
SM-D4 / XD-D4
SM-D5 / XD-D5
SM-D6 / XD-D6
SM-D7 / XD-D7

<23> XDWE1#

34
33
32
31
21
22
23
24

<23> XDWP#

SDDA1_XDD0
MSBS_XDD1
MSD0_XDD2
MSD3_XDD3
SDDA3_XDD4
MSD2_XDD5
MSD1_XDD6
SDDA0_XDD7

SDCK

<23> SDCK

JP34

51@ 10U_0805_10V4Z 51@ 0.1U_0402_16V4Z


1
C723

C724

<23> XD_MS_PWREN#
C725

C726

U54
R622

1
<23> SDPW REN#

51@ 0.1U_0402_16V4Z

+3VS

+VCC_5IN1

+3VS
1
2
3
4

GND
IN
IN
EN#

OUT
OUT
OUT
OC#

8
7
6
5

51@ 10K_0402_5%

R621
51@ 10K_0402_5%

+VCC_5IN1

SD PWR Control

+3VS

SDOC# <23>

51@ TPS2041ADR_SO8

C727

2
51@ 0.1U_0402_16V4Z
51@ 0.1U_0402_16V4Z

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-2601


Size
Document Number
Custom

R ev
C

401336

Date:

, 17, 2005

Sheet

24

of

51

+3VS
+3VS

1
R623
1
R624
1
R625
1
R626
2
R627

+3VS

CYCLEOUT/CARDBUS
CNA
TEST17
TEST16

CYCLEIN

20
35
48
62
78

86
96
10
11

2
1394@ 4.7U_0805_10V4Z

CPS

106

NC/(TPBIAS1)
NC/(TPA1+)
NC/(TPA1-)
NC/(TPB1+)
NC/(TPB1-)

125
124
123
122
121

BIAS CURRENT

OSCILLATOR

R0

1
R628

2
1394@ 1K_0402_5%

118

1
2
R629
1394@ 6.34K_0402_1%

R1

119

X0

X1

FILTER0

C740 1

1394@ 0.1U_0402_16V4Z

C738 1

2 1394@ 22P_0402_50V8J

X5
1394@ 24.576MHz_16P_3XG-24576-43E1

EEPROM 2 WIRE BUS SDA

92

1394_SDA

SCL

91

1394_SCL

PC0
PC1
PC2

99
98
97

POWER CLASS

PHY PORT 1

TPBIAS0
TPA0+
TPA0TPB0 +
TPB0 -

2
1394@ 22P_0402_50V8J

R631
R632
C741
1394@ 56.2_0402_1% 1394@ 56.2_0402_1% 1394@ 0.33U_0603_16V4Z
2
TPBIAS0
TPA0+
TPA0TPB0+
TPB0-

116
115
114
113
112

RP119

4
3
2
1

4
3
2
1

1394_GPIO3
1394_GPIO2
1394_SCL
1394_SDA

TEST3
TEST2
TEST1
TEST0

101
102
104
105

5
6

1394@ SUYIN8004A-04G5T

R633
R634
1394@ 56.2_0402_1% 1394@ 56.2_0402_1%

1
1394@

8
9
109
110
111
117
126
127
128
17
23
30
33
44
55
64
68
75
83
93
103

5
6
7
8

94
95

JP35

(CL56)

GPIO3
GPIO2

TEST9
TEST8

FILTER1

C739 1

FILTER

G_RST

C735

2
1394@ 1000P_0402_50V7K

L39
+1394_PLLVDD 1394@ 0.01U_0402_16V7K 1
2
+3VS
1394@ BLM21A601SPT_0805
1
1
+3VS
C736
C737

14
89
90

PCI BUS INTERFACE

PLLGND1
REG_EN
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DGND
DGND
REG18
DGND
DGND
DGND
DGND
DGND
DGND
DGND
REG18
DGND

1394_GPIO3
1394_GPIO2

2
1394@ 1000P_0402_50V7K

PCI_RST#

<17,23,26,28> PCI_FRAME#
<17,23,26,28> P C I_ IRDY#
<17,23,26,28> PCI_TRDY#
<17,23,26,28> PCI_DEVSEL#
<17,23,26,28> PCI_STOP#
<17,23,26,28> PCI_PERR#
<17> PCI_PIRQE#
<26,28,32,33> 1394_PME#
<17,23,26,28> PCI_SERR#
<17,23,26,28> PCI_PAR
<19,26,28,32,33> PM_CLKRUN#
<17,23,26,28,32,33> PCI_RST#

+3VS

1394@ 1000P_0402_50V7K
1
C734

C742

R635
1394@ 5.11K_0402_1%

220P_0402_50V7K

<17,23,26,28> PCI_C/BE#3
<17,23,26,28> PCI_C/BE#2
<17,23,26,28> PCI_C/BE#1
<17,23,26,28> PCI_C/BE#0
<14> CLK_PCI_1394
<17> PCI_GNT#0
<17> PCI_REQ#0

TSB43AB21
/(TSB43AB22)

C731

2
1394@ 0.1U_0402_16V4Z

2 1394_IDSEL
1394@ 100_0402_5%

1
R630

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE3
PCI_C/BE2
PCI_C/BE1
PCI_C/BE0
PCI_CLK
PCI_GNT
PCI_REQ
PCI_IDSEL
PCI_FRAME
PCI_IRDY
PCI_TRDY
PCI_DEVSEL
PCI_STOP
PCI_PERR
PCI_INTA/CINT
PCI_PME/CSTSCHG
PCI_SERR
PCI_PAR
PCI_CLKRUN
PCI_RST

DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
PLLVDD
AVDD
AVDD
AVDD
AVDD
AVDD

+3VS

PC I_AD16

84
82
81
80
79
77
76
74
71
70
69
67
66
65
63
61
46
45
43
42
41
40
38
37
32
31
29
28
26
25
24
22
34
47
60
73
16
18
19
36
49
50
52
53
54
56
13
21
57
58
12
85

2
2
1394@ 0.1U_0402_16V4Z

1394@ 1000P_0402_50V7K
1
1
C732
C733

15
27
39
51
59
72
88
100
7
1
2
107
108
120

1394@ 0.1U_0402_16V4Z
1
C730

IDSEL:PCI_AD16

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PC I_AD10
PC I_AD11
PC I_AD12
PC I_AD13
PC I_AD14
PC I_AD15
PC I_AD16
PC I_AD17
PC I_AD18
PC I_AD19
PC I_AD20
PC I_AD21
PC I_AD22
PC I_AD23
PC I_AD24
PC I_AD25
PC I_AD26
PC I_AD27
PC I_AD28
PC I_AD29
PC I_AD30
PC I_AD31
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0
CLK_PCI_1394
PCI_GNT#0
P CI_REQ#0
1394_IDSEL
P CI_FRAME#
P C I_ I RDY#
PCI_TRD Y#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_ PIRQE#
1394_PME#
PCI_SERR#
PCI_PAR

PCI_AD[0..31]

VDDP
VDDP
VDDP
VDDP
VDDP

<17,23,26,28> PCI_AD[0..31]

U55
TSB43AB21_PQFP128

87

1394@ 0.1U_0402_16V4Z
1
1
C728
C729

2
1394@ 4.7K_0402_5%
2
1394@ 10K_0402_5%
2
1394@ 4.7K_0402_5%
2
1394@ 4.7K_0402_5%
1
1394@ 4.7K_0402_5%

1394@ 220_1206_8P4R_5%
1394@

1
CLK_PCI_1394

C743

R636
10_0402_5%

C744

2 1394@ 0.1U_0402_16V4Z

1394@ 0.1U_0402_16V4Z

Compal Electronics, Inc.

C745
Title

10P_0402_50V8K

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
Document Number
C ustom

R ev
C

401336

D ate:

P , 17, 2005

Sheet
1

25

of

51

+3VALW

Q62
SI2301DS_SOT23

VGS(th) = -0.45V
IDmax = 2.3A

R551
0_1206_5%

80mils

10U_0805_10V4Z
0.1U_0402_16V4Z
1
1
1
1
C642
C643
C644

3
G

<33> EN_WOL#

+3VS for BCM5788


+3V_LAN for BCM4401

+3VS

1
L33

2
2@ 0_0603_5%

1
L34

2
1@ 0_0603_5%

0.1U_0402_16V4Z
1

C645

C647

C646

+3V_LAN

2
4

C648

2
0.1U_0402_16V4Z

2
2
10U_0805_10V4Z

0.1U_0402_16V4Z
1
1
C659
C660

2
2
0.1U_0402_16V4Z

C671
18P_0402_50V8K

PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0

PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0

100_0402_5%
PC I_AD17 R555 1
B

B8
A8
C7
C6
B6
B5
A5
B4
B2
B1
C1
D3
D2
D1
E3
K1
L2
L1
M3
M2
M1
N2
N3
P3
N4
P4
M5
N5
P5
P6
M7
N7

C4
F3
L3
M4

L AN_IDSEL

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

CBE3
CBE2
CBE1
CBE0

<17,23,25,28> PCI_FRAME#
<17,23,25,28> P C I_ IRDY#
<17,23,25,28> PCI_TRDY#
<17,23,25,28> PCI_DEVSEL#
<17,23,25,28> PCI_STOP#
<17,23,25,28> PCI_PERR#
<17,23,25,28> PCI_SERR#
<17,23,25,28> PCI_PAR
<14> CLK_PCI_LAN

A4
F2
F1
G3
H3
H1
J2
A2
J1
C LK_PCI_LAN A3

IDSEL
FRAME
IRDY
TRDY
DEVSEL
STOP
PERR
SERR
PAR
PCI_CLK

<17> PCI_PIRQF#
<17,23,25,28,32,33> PCI_RST#
<17> PCI_GNT#3
<17> PCI_REQ#3

H2
C2
J3
C3

INTA
PCI_RST
GNT
REQ

+3V_LAN

0.1U_0402_16V4Z
1

C654

2
2
10U_0805_10V4Z
D

C663

2
0.1U_0402_16V4Z

60mils

0.1U_0402_16V4Z
1
1

2
0.1U_0402_16V4Z

2
2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
C664

C665

2
2
0.1U_0402_16V4Z

C666

0.1U_0402_16V4Z
1
1

C667

C668

2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

C669

C670

2
0.1U_0402_16V4Z

2 LAN_AUXPWR
1K_0402_5%

1
R559

<25,28,32,33> ONBD_LAN_PME#

J12
F4
A6

U49B

TRD3+/(NC_E13)
TRD3-/(NC_E14)
TRD2+/(NC_D13)
TRD2-/(NC_D14)
TRD1+/(RDP)
TRD1-/(RDN)
TRD0+/(TDP)
TRD0-/(TDN)

E13
E14
D13
D14
C13
C14
B13
B14

REGSUP12/(NC_B9)
REGCTL12/(NC_B10)
REGSEN12/(REG18OUT)

B9
B10
A9

REGSUP25/(REGSUP18)
REGCTL25/(NC_C11)
REGSEN25/(REGSUP18)

B11
C11
C10

VESD1
VESD2
VESD3

LAN_MIDI3+
LAN_MIDI3LAN_MIDI2+
LAN_MIDI2LAN_MIDI1+
LAN_MIDI1LAN_MIDI0+
LAN_MIDI0-

LAN_CTRL_1.2V

<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>

+2.5V_LAN

(Output 3.3V for BCM4401)

+1.2V_LAN

(Output 1.8V for BCM4401)

LAN_CTRL_2.5V

+2.5V_LAN
+3V_LAN

P10
M10

GPIO0/(NC_H12)
GPIO1/(NC_K13)
GPIO2/(NC_J13)

H12
K13
J13

LINKLED/(LINKLED10)
SPD100LED/(LINKLED100)
SPD1000LED/(COL_LED)
TRAFFICLED/(ACT_LED)

G13
H13
G12
G14

PLLVDD2/(PLLVDD)
NC_P7

H14
P7

TCK
TDI
TDO
TMS
TRST

C12
D12
B12
A12
D11

LAN_EEDA
LAN_EECLK
LAN_EEWP 1
R553

2
10K_0402_5%

+3V_LAN

LAN_LINK# <27>
R554 1
1@
LAN _ACTIVITY#

2 0_0402_5%
LAN_ACTIVITY# <27>
+1.2V_LAN_PLLVDD

20mils
+1.2V_LAN_PLLVDD

XTALVDD
XTALO
XTALI

J14
N10
N11

NC_G11
NC_E10/(EEDATA_PXE)
NC_E11/(EECLK_PXE)
NC_H11

G11
E10
E11
H11

BIASVDD
RDAC

A7
B3
C5
E1
E4
G1
K3
L4
N6
P2

+3V_LOM_PCI

unpop R554 when use BCM4401

0.1U_0402_16V4Z
1
C673
C672

1
L35
0_0603_5%

+1.2V_LAN

K14
L13
P11

+2.5V_LAN

4.7U_0805_10V4Z
+3V_LAN

LAN_TRST# 1
R556

2
4.7K_0402_5%

<19,25,28,32,33> PM_CLKRUN#

VAUXPRSNT
M66EN/(NC_F4)
PME

E12
H5
H6
H7
H8
J5
J6
J7
J8
J9
J10
K5
K6
K7
K8
K9
K10
L5
L10
M14
N14
P8
P12
P13
P14

+1.2V_LAN

+3V_LAN

P1
G2
A1

EEDATA/(SPROM_CS)
EECLK/(SPROM_CLK)

BCM5788M
/(BCM4401)

LAN_MDI3+
LAN_MDI3LAN_MDI2+
LAN_MDI2LAN_MDI1+
LAN_MDI1LAN_MDI0+
LAN_MDI0-

PM_CLKRUN#

+2.5V_LAN
LAN_X1
LAN_X2_R 1
2 LAN_X2
R558
200_0402_1%

VDDC_E12
VDDC_H5
VDDC_H6
VDDC_H7
VDDC_H8
VDDC_J5
VDDC_J6
VDDC_J7
VDDC_J8
VDDC_J9
VDDC_J10
VDDC_K5
VDDC_K6
VDDC_K7
VDDC_K8
VDDC_K9
VDDC_K10
VDDC_L5
VDDC_L10
VDDC_M14
VDDC_N14
VDDC_P8
VDDC_P12
VDDC_P13
VDDC_P14

VSS_B7
VSS_D4
VSS_D5
VSS_D6
VSS_D7
VSS_D8
VSS_D9/(NC_D9)
VSS_E2
VSS_E5
VSS_E6
VSS_E7
VSS_E8
VSS_E9
VSS_F5
VSS_F6
VSS_F7
VSS_F8
VSS_F9
VSS_F10
VSS_G4
VSS_G5
VSS_G6
VSS_G7
VSS_G8
VSS_G9
VSS_G10
VSS_H9
VSS_K2
VSS_L6
VSS_L9
VSS_M6
VSS_M12
VSS_M13/(NC_M13)
VSS_N1
VSS_N12
VSS_N13

BCM5788M
/(BCM4401)

VDDIO-PCI_A7
VDDIO-PCI_B3
VDDIO-PCI_C5
VDDIO-PCI_E1
VDDIO-PCI_E4
VDDIO-PCI_G1
VDDIO-PCI_K3
VDDIO-PCI_L4
VDDIO-PCI_N6
VDDIO-PCI_P2

A11
F11
K12
L12

VDDP_K14/(NC_K14)AVDDL_F12/(AVDD_F12)
VDDP_L13/(NC_L13)AVDDL_F13/(AVDD_F13)
VDDP_P11/(NC_P11) AVDD_F14/(NC_F14)
AVDD_A13/(NC_A13)
VDDIO_A11
VDDIO_F11
VDDIO_K12
VDDIO_L12

C8
H4
H10
J4
K4
J11
K11
L7
L8

NC_C8
CLKRUN
NC_L11/(VSS_L11)
NC_H10
NC_L14/(VSS_L14)
NC_J4
NC_M8
NC_K4
NC_M9/(VREF)
NC_J11/(GPIO_1)LOW_POWER/(TESTMODE)
NC_K11/(GPIO_0)
NC_N8/(EXT_POR)
NC_L7
NC_N9/(DOUT)
NC_L8
NC_P9/(DIN)

1.24K for BCM5788


1.27K for BCM4401

B7
D4
D5
D6
D7
D8
D9
E2
E5
E6
E7
E8
E9
F5
F6
F7
F8
F9
F10
G4
G5
G6
G7
G8
G9
G10
H9
K2
L6
L9
M6
M12
M13
N1
N12
N13

5788

F12 +1.2V_LAN_AVDD
F13
F14 +2.5V_LAN_AVDD
A13
1
1
C674
2
0.1U_0402_16V4Z

L11
L14
M8
M9
M11
N8
N9
P9

A14
D10

LAN _RDAC 1
R560
10mils

LAN_X2
25MHZ_20P

C679
27P_0402_50V8J

Pop

Q60

Pop

R560

1.24K

1
R563
1
R564

1.27K

U50

Pop

C678

Pop

U51

Pop

R561

Pop

C677

Pop

R562

Pop

1
L36
0_0603_5%
1
L37
0_0603_5%

+1.2V_LAN

20mils

+2.5V_LAN

20mils
B

C675
0.1U_0402_16V4Z

2
10K_0402_5%

BCM5788M_FBGA196
C677

2 1000P_0402_50V7K

1
L38
2
0_0603_5%
1.24K_0402_1%

+2.5V_LAN

AT93C46 for BCM4401

R561
1@ 4.7K_0402_5%

+3V_LAN

2
@ 10K_0402_5%
2
@ 10K_0402_5%

+3V_LAN

Y4
LAN_X1

Q61

1
R557

BCM5788M_FBGA196

LAN_EEDA
LAN_EECLK
LA N_EEDI
LAN_EEDO

1
2
3
4

CS
SK
DI
DO

VCC
NC
NC
GND

8
7
6
5

LAN_EEWP
LAN_EECLK
LAN_EEDA

C678
2@ 0.1U_0402_16V4Z
2
2@ AT93C46-10SI-2.7_SO8

A10
C9

Pop

LA N_EEDI
LAN_EEDO

U50

NC_A10
NC_C9

Pop

L34

+3V_LAN
C676 1

10mils
+LAN_BIASVDD

4401

L33

2
1

<17,23,25,28>
<17,23,25,28>
<17,23,25,28>
<17,23,25,28>

1
R552
10_0402_5%

2
4

1@ 0.1U_0402_16V4Z

R562
1@ 4.7K_0402_5%
U51
8 VCC
7 WP
6 SCL
5 SDA

PC I_AD31
PC I_AD30
PC I_AD29
PC I_AD28
PC I_AD27
PC I_AD26
PC I_AD25
PC I_AD24
PC I_AD23
PC I_AD22
PC I_AD21
PC I_AD20
PC I_AD19
PC I_AD18
PC I_AD17
PC I_AD16
PC I_AD15
PC I_AD14
PC I_AD13
PC I_AD12
PC I_AD11
PC I_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

C LK_PCI_LAN

C655

U49A

Q61
1@ BCP69_SOT223
+1.2V_LAN

+2.5V_LAN

PCI_AD[0..31]

<17,23,25,28> PCI_AD[0..31]

60mils

10U_0805_10V4Z
0.1U_0402_16V4Z
1
1
1
1
C650
C651
C652
C653

2
2
10U_0805_10V4Z

0.1U_0402_16V4Z
1
1
C661
C662

2
2
0.1U_0402_16V4Z

LAN_CTRL_1.2V

C649

+1.2V_LAN

0.1U_0402_16V4Z
1
1
1
C656
C657
C658

unpop when use BCM4401


Q60
1@ BCP69_SOT223

20mils

+3V_LAN
+3V_LAN

0.1U_0402_16V4Z
1
1

2
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z

+3V_LOM_PCI

LAN_CTRL_2.5V

+3V_LAN

EN_WOL# = Low,
System can wake on LAN
( keep Low when Power On)

A0
A1
NC
GND

1
2
3
4
A

24C256 for BCM5788 1@ AT24C256_SO8~D


Unpop when use BCM4401

C680
27P_0402_50V8J
2

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, M/B LA-2601


Size
B
D ate:

Document Number

R ev
C

401336
P , 17, 2005

Sheet
1

26

of

51

RP125

L_LAN_MDI2L_LAN_MDI2+

2@ 0_0404_4P2R_5%
RP127

1
2

4
3

L_LAN_MDI1L_LAN_MDI1+

2@ 0_0404_4P2R_5%
RP128
LA N_MIDI0L AN_MIDI0+

1
2

4
3

L_LAN_MDI0L_LAN_MDI0+

4
3

A2

4B1
5B1

37
36

D_LAN_MDI2+
D_LAN_MDI2-

6B1
7B1

32
31

D_LAN_MDI3+
D_LAN_MDI3-

0LED1
1LED1
2LED1

D_L AN_ACTIVITY#
D _LAN_LINK#

A5

22
23
52

14

A6

0B2
1B2

46
45

L_LAN_MDI0+
L_LAN_MDI0-

15

A7

2B2
3B2

41
40

L_LAN_MDI1+
L_LAN_MDI1-

17

SEL

4B2
5B2

35
34

L_LAN_MDI2+
L_LAN_MDI2-

LED0
LED1
LED2

6B2
7B2

30
29

L_LAN_MDI3+
L_LAN_MDI3-

0LED2
1LED2
2LED2

25
26
51

L _LAN_ACTIVITY#
L_LAN_LINK#

D_LAN_MDI1+
D_LAN_MDI1-

<26> LAN_MIDI0-

<26> LAN_MIDI1+

L AN_MIDI1+

<26> LAN_MIDI1-

LA N_MIDI1-

A3

<26> LAN_MIDI2+

L AN_MIDI2+

11

A4

<26> LAN_MIDI2-

LA N_MIDI2-

12

<26> LAN_MIDI3+

L AN_MIDI3+

<26> LAN_MIDI3-

LA N_MIDI3-

49.9_0402_1%

RP129
L AN_LINK#
1
LAN _ACTIVITY# 2

A1

2B1
3B1

43
42

LA N_MIDI0-

2@ 0_0404_4P2R_5%

D_LAN_MDI0+
D_LAN_MDI0-

L_LAN_LINK#
L _LAN_ACTIVITY#

R571

R572

A0

R574

R573
1@ 49.9_0402_1%

DOCKIN#

<15,22,33,38> DOCKIN#

1@ 49.9_0402_1%
1@ 49.9_0402_1%

2@ 0_0404_4P2R_5%

1
C687
1@ 0.1U_0402_16V4Z
2

1@

LAN _ACTIVITY# 19
L AN_LINK#
20
54

<26> LAN_ACTIVITY#
<26> LAN_LINK#

1
C688
1@ 0.1U_0402_16V4Z
2

24ST0023-3(SP050004200) for BCM4401(10/100)


24HST1041A-3(SP050002110) for BCM5788M(GbE)

D_LAN_MDI1+ <38>
D_LAN_MDI1- <38>
D_LAN_MDI2+ <38>
D_LAN_MDI2- <38>
D_LAN_MDI3+ <38>
D_LAN_MDI3- <38>
D_LAN_ACTIVITY# <38>
D_LAN_LINK# <38>

NC

unpop when use BCM4401(10/100)

+2.5V_LAN

D_LAN_MDI0+ <38>
D_LAN_MDI0- <38>

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13

LA N_MIDI1L AN_MIDI1+

48
47

1@ PI3L500E_TQFN56~D

1
6
9
13
16
21
24
28
33
39
44
49
53
55

4
3

0B1
1B1

L AN_MIDI0+

1
2

U62

<26> LAN_MIDI0+

LA N_MIDI2L AN_MIDI2+

R569
49.9_0402_1%

RP126

+3V_LAN

R568
49.9_0402_1%

2@ 0_0404_4P2R_5%

R567
49.9_0402_1%

R566
49.9_0402_1%

L_LAN_MDI3L_LAN_MDI3+

4
3

1
2

LA N_MIDI3L AN_MIDI3+

56
50
38
27
18
10
4

C682
0.1U_0402_16V4Z

VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0

C681
0.1U_0402_16V4Z

T1

L_LAN_MDI0+
L_LAN_MDI0-

1
2
3

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

24
23
22

RJ45_MDI0+
RJ45_MDI0-

L_LAN_MDI1+
L_LAN_MDI1-

4
5
6

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

RJ45_MDI1+
RJ45_MDI1-

7
8
9

L_LAN_MDI2+
L_LAN_MDI2-

10
11
12

L_LAN_MDI3+
L_LAN_MDI3-

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

15
14
13

, LED
JP32
L_LAN_LINK#
+3V_LAN

R565

12

Amber LED-

1 301_0402_1%

11

Amber LED+

RJ45_MDI3-

RJ45_MDI3+

PR4+

RJ45_MDI1-

PR2-

RJ45_MDI2-

PR3-

RJ45_MDI2+

PR3+

RJ45_MDI1+

PR2+

RJ45_MDI0-

PR1-

RJ45_MDI0+

PR1+

RJ45_MDI2+
RJ45_MDI2RJ45_MDI3+
RJ45_MDI3-

24HST1041A-3

0.01U_0402_16V7K

1
C684

0.01U_0402_16V7K
2 0.01U_0402_16V7K
2
2

C686

R576
75_0402_1%

R575
75_0402_1%

1
C683

1
C685

L _LAN_ACTIVITY#

0.01U_0402_16V7K

+3V_LAN

R570

10

1 301_0402_1%

SHLD4

16

SHLD3

15

PR4-

SHLD2

14

SHLD1

13

Green LED-

Green LED+
TYCO_1566597-1

(AL50)
2 2@ 0_0402_5%
2 2@ 0_0402_5%

RJ45_MDI2+
RJ45_MDI2-

R579 1
R580 1

2 2@ 0_0402_5%
2 2@ 0_0402_5%

RJ4 5_GND

C690

RJ4 5_GND

Compal Electronics, Inc.

LAN BCM5788M/BCM4401KFB

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C691
4.7U_0805_10V4Z

0.1U_0402_16V4Z

R582
75_0402_1%

R581
75_0402_1%

reseved for BCM4401(10/100)


A

LAN GND
1

C689
1000P_1206_2KV7K

R577 1
R578 1

RJ45_MDI3+
RJ45_MDI3-

SCHEMATIC, M/B LA-2601


Size
B
D ate:

Document Number

R ev
C

401336
P , 17, 2005

Sheet
1

27

of

51

PCI_AD[0..31]

PCI_AD[0..31] <17,23,25,26>

MINI_PCI SOCKET
JP28
TIP

LAN RESERVED

+3VS_MINIPCI

+3VS

D6
RB751V_SOD323
1
2

<33> WL_ON
L13
1
2
0_0603_5%

PCI_PIRQH#

<17> PCI_PIRQH#

W= 40mils
CLK_PC I_MINI

<14> CLK_PCI_MINI
<17> PCI_REQ#1

PC I_AD31
PC I_AD29

CLK_PC I_MINI

PC I_AD27
PC I_AD25

R156
@ 33_0402_5%

<34> WLAN_BT_DATA
<17,23,25,26> PCI_C/BE#3

PC I_AD23
PC I_AD21
PC I_AD19

C174
@ 10P_0402_50V8J

PC I_AD17
<17,23,25,26> PCI_C/BE#2
<17,23,25,26> P C I_ IRDY#
<19,25,26,32,33> PM_CLKRUN#
<17,23,25,26> PCI_SERR#
<17,23,25,26> PCI_PERR#
<17,23,25,26> PCI_C/BE#1

PC I_AD14
PC I_AD12
PC I_AD10
PCI_AD8
PCI_AD7
PCI_AD5

PCI_AD3
W=30mils

+5VS_MINIPCI

+5VS

1
L12

PCI_AD1

W=30mils
0_0603_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

0603

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

RING

LAN RESERVED

W=30mils
PCI_ PIRQG#

+3VS_MINIPCI
+3V
PCI_RST# <17,23,25,26,32,33>

W= 40mils

PCI_GNT#1 <17>

L14
1
2
0_0603_5%

+3VS

WLANPME# <25,26,32,33>
W LAN_BT_CLK <34>

PC I_AD30
PC I_AD28
PC I_AD26
PC I_AD24
MINI_ IDSEL1
R162
PC I_AD22
PC I_AD20

PC I_AD18
100_0402_5%

IDSEL : PCI_AD18

PCI_PAR <17,23,25,26>

PC I_AD18
PC I_AD16

PCI_FRAME# <17,23,25,26>
PCI_TRDY# <17,23,25,26>
PCI_STOP# <17,23,25,26>
PCI_DEVSEL# <17,23,25,26>
PC I_AD15
PC I_AD13
PC I_AD11

+5VS_MINIPCI

2
C178
1000P_0402_50V7K

2
C181
0.1U_0402_16V4Z

1
C173
0.1U_0402_16V4Z

C175
10U_1206_16V4Z

PCI_AD9
PCI_C/BE#0 <17,23,25,26>
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

+3VS_MINIPCI

W=20mils

QTC_C102A-040B31-4

+5VS_MINIPCI

+5VS_MINIPCI
PCI_PIRQG# <17>

W=40mils
PCI_RST#

2
C182
0.1U_0402_16V4Z

2
C176
0.1U_0402_16V4Z

2
C171
0.1U_0402_16V4Z

2
C172
0.1U_0402_16V4Z

1
C177
0.1U_0402_16V4Z

C184
10U_1206_16V4Z

+3V

C183
0.1U_0402_16V4Z

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
E

28

of

51

R498
10K_0402_5%

C308

10U_0805_10V4Z

ERROR

VOUT

SENSE or ADJ

C312

1
8

CNOISE

GND

SD

1
R496
150K_0603_1%

1
C599

SI9182DH-AD_MSOP8

MO NO_IN

4.85V
C313
10U_0805_10V4Z

2
R497
51K_0603_1%

0.1U_0402_16V4Z

Q28
R502
2SC2411K_SC59 2.4K_0402_5%

2
B

+VDDA

2
DELAY

1U_0402_6.3V4Z

R493
1
2
560_0402_5%

C600
2
1

1U_0402_6.3V4Z

1
2
560_0402_5%

VIN

40mil

O
G

U25B
SN74LVC14APWLE_TSSOP14

1U_0402_6.3V4Z
1
2

R494

U24

C601
2
1

(output = 250 mA)

+5VAMP

60mil

L43
1
2
KC FBM-L11-201209-221LMAT_0805
L44
1
2
KC FBM-L11-201209-221LMAT_0805

22U_1206_16V4Z_V1

C604
1
2

14

+3V

<23> PCM_SPK#

1
2
560_0402_5%

1U_0402_6.3V4Z

+5VS

C603
1U_0402_6.3V4Z
2
1

R495

28.7K for Module Design (VDDA = 4.702)

R501
10K_0402_5%

U25A
SN74LVC14APWLE_TSSOP14
C602
2
1
O 2

2 0.1U_0402_16V4Z

14
P
1

<33> BEEP#

+VDDA

C296

+3V

+3V

14

+AUD_VREF

D12
RB751V_SOD323

R279
10K_0402_5%

P
I

C765
1U_0603_10V4Z

AC97 Codec

U25C
SN74LVC14APWLE_TSSOP14

10mil

<19> SB_SPKR

1
R307

2
0_0603_5%

1
R306

2
0_0603_5%

1
R284

2
0_0603_5%

C766
0.1U_0402_16V4Z

+AVDD_AC97

GND

0.1U_0402_16V4Z

14

AUX_L

LINE_OUT_L

35

C762 1

2 4.7U_0805_10V4Z

LINE_OUTL <31>

15

AUX_R

LINE_OUT_R

36

C763 1

2 4.7U_0805_10V4Z

LINE_OUTR <31>

16

JD2

MONO_OUT/VREFOUT3

37

17

JD1

HP_OUT_L

39

23

LINE_IN_L

HP_OUT_R

41

24

LINE_IN_R

18

CD_L

LINE _IN_L_AC
LINE_IN_R_AC
C332 1

C339 1

1U_0402_6.3V4Z
1U_0402_6.3V4Z

CD_R C_L
CD_RC_R

20

1U_0603_10V4Z

C_M IC
1U_0603_10V4Z

21

MIC1

1
2
C349
1U_0603_10V4Z
MDC_RC_SPK
2
0.1U_0402_16V4Z

22

MIC2

C344

CD_G NDA

19

R522 1

R290 1

<18,34> ICH_AC_SDOUT

2 22_0402_5%

SDATA_IN

XTL_IN

R288

2 22_0402_5%

ICH_AC_BITCLK <18,34>

2 22_0402_5%

ICH_AC_SDIN0 <18>

PC_BEEP

11

RESET#

XTL_OUT

AFILT1

C373 1

2 1000P_0402_50V7K

AFILT2

30

C388 1

2 1000P_0402_50V7K

VREFOUT

28

VREF

27

DCVOL

32

C389 1
C612 1

NC
VREFOUT2
VAUX
DISABLE#
SCK

31
33
34
43
44

C641 1
R523 1

<31,33> EAPD

47

SPDIFI/EAPD

<31> SPDIFO

48

SPDIFO

4
7

DVSS1
DVSS2

NC
AVSS1
AVSS2

40
26
42

CLK_14M_CODEC <14>

0_0402_5%
X4 1

C610
@ 22P_0402_50V8J

C611
@ 22P_0402_50V8J

+AUD_VREF
1U_0402_6.3V4Z

SDATA_OUT
SDA
XTLSEL

1 @ 24.576MHz_16P_3XG-24576-43E1 1

29

SYNC

U27

1
R291
R521
@ 1M_0402_1%

45
46

2 0.01U_0402_16V7K
1U_0603_10V4Z
2
2

1U_0603_10V4Z
2 @ 0_0402_5%

C368

C367
0.1U_0402_16V4Z

R704
@ 20K_0402_5%

ALC250-VD_LQFP48

AGND

Compal Electronics, Inc.

DGND

Title

With 14.318Mhz : R321 POP


With 24.576Mhz : R321 DEPOP
A

PHONE

12

CD_GND

13

10

1
2

2 22_0402_5%

R321
0_0402_5%

2 22_0402_5%

27P_0402_50V8J
C764 1
2
R289

BIT_CLK
CD_R

C334 1

R287 1

6.8K_0402_5%

C761
1000P_0402_50V7K

1U_0603_10V4Z

<18,34> IC H _AC_SYNC

R324

1U_0603_10V4Z

<18,34> ICH_AC_RST#

0_0402_5%

MO NO_IN

R282

20K_0402_5% CD _R_L
6.8K_0402_5%
6.8K_0402_5%
20K_0402_5% CD_R_R

CD_ GNA

1
C318

R315 2
1
20K_0402_5%

C760
1000P_0402_50V7K

CD_ GNA

<21> CD_AGND

0.1U_0402_16V4Z

C609

<31> MIC

C314
10U_1206_16V4Z

1
1
1
1

<21> INT_CD_R

2
2
2
2

R323
R309
R329
R328

2
9

2
0.1U_0402_16V4Z

<31> NBA_PLUG

<21> INT_CD_L

C317

C608

<30> LINE_IN_L_AC
<30> LINE_IN_R_AC

1
C316

C366

DVDD2

1
1

DVDD1

0.1U_0402_16V4Z
1
C369

38

25

C348
10U_0805_10V4Z

AVDD2

1
2
FBM-L10-160808-301-T_0603

AVDD1

+VDDA

GNDA

+3VS

L21

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005
G

Sheet

29

of
H

51

R336 2

1 @ 6.8K_0402_5%

R349 2

1 @ 6.8K_0402_5%

LINE _IN_L

R342 2

1 6.8K_0402_5%

2 C354
1U_0402_6.3V4Z

LINE_IN _R

R345 2

1 6.8K_0402_5%

2 C359
1U_0402_6.3V4Z

<31> LINE_IN_L
<31> LINE_IN_R

C639
@ 1U_0402_6.3V4Z

<31> AUD_INL

LINE _IN_L_AC
LINE_IN_R_AC

LINE_IN_L_AC <29>
LINE_IN_R_AC <29>

C640
@ 1U_0402_6.3V4Z

<31> A U D_INR

Compal Electronics, Inc.


Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate:

SCHEMATIC, M/B LA-2601


Document Number

R ev
C

401336
P , 17, 2005

Sheet
1

30

of

51

+5VAMP

R318
100K_0402_5%

+5VAMP

W=40mil

JP8
Q29
2N7002_SOT23
2
G

+5VAMP

Speaker Conn.

SHUTDOW N#
D

R657

C346
0.1U_0402_16V4Z

HIGH

PIN 6,20 ACTIVE

Pin 2

LOW

R658
1.5K_0402_1%

PIN 5,23 ACTIVE

EAPD

SPKL+
SPKR+
LINE_OUTL

<29> LINE_OUTL

1
C327

L INE_OUTR

<29> LINE_OUTR

1
C328

2
3
4
21
5
23
6
20

LEFT_2
R IGHT_2

2
0.47U_0603_16V4Z
2
0.47U_0603_16V4Z

17
HP_L
2
0.47U_0603_16V4Z
HP _R
2
0.47U_0603_16V4Z

1
C338

1
C335

TPA0232PWP_TSSOP24

1
1

C333

1
12
13
24

R348 1

2 100K_0402_5%

1
C364

BYPASS

+AUD_VREF

+5VAMP

NBA_PLUG

2
0.1U_0402_16V4Z
SPKLSPKR-

22
15
14
11
9
16
10
8

MIC_S -->ON Channel


-------------------------

R708
1@ 2.2K_0402_5%

L -->B1
H --->B2
Docking MIC

NBA_PLUG
VOL_AMP

<29> NBA_PLUG

PVDD SHUTDOWN#
PVDD
SE/BTL#
VDD
PC-BEEP
BYPASS
HP/LINE#
LOUTVOLUME
ROUTLOUT+
LIN
ROUT+
RIN
LLINEIN
RLINEIN
GND
LHPIN
GND
RHPIN
GND
GND
CLK

U66

AU D_MIC2

C361
1U_0402_6.3V4Z
1

EAPD <29,33>

U29

7
18
19

4
3
2
1
ACES_85204-0400

Q31
2
G
2N7002_SOT23

VOL_AMP

(0.65V -> 10dB )

EC_MUTE <33>

C347
4.7U_0805_10V4Z

10K_0402_5%

1
3

SPKL+
SPKLSPKR+
SPKR-

C351
1
1U_0402_6.3V4Z

C356
1U_0402_6.3V4Z

C873
1@ 220P_0402_50V7K

1
2
3

AU D_MIC1

B2
GND
B1

6
5
4

S
VCC
A

D OCK_MIC_S
+5VAMP
MIC <29>

1@ SN74LVC1G3157

R699 1

Docking :
Docking :

C353

2 2@0_0402_5%

MIC plug ---> HIGH


MIC Unplug ---> LOW

0.01U_0402_16V7K

0.1U_0402_16V4Z 2

HeadPhone JACK
JP5

D_AUD_OR
D_AUD_OL

1
2
3
4
5
6
7
8
9
10

D OCK_MIC_S
SPDIFO

<29> SPDIFO

JP22

1
2
3
4
5
6
7
8
9
10

SPKR+

150U_D2_6.3VM
C352 1
2 INTSPK_R1-2

SPKL+

C399 1

47_0402_5%
1
2

INTSPK_R1-3

INTSPK_L1-3

NBA_PLUG_S
FBM-11-160808-700T_0603
L22
1
2 INTSPK_R1-4

R356

<30> A UD_INR
<30> AUD_INL

INTSPK_L1-2

R362

A UD_INR
AUD_INL
AG ND
AU D_MIC2
AG ND
SPKR+
SPKL+
HP_S

47_0402_5%

150U_D2_6.3VM

1
2 INTSPK_L1-4
L24
FBM-11-160808-700T_0603

3
6
2
1
FOX_JA6033L-5S3-TR

C376
330P_0402_50V7K

1@ ACES_87213-1000

C370
330P_0402_50V7K

R709
1@ 100K_0402_5%
3

L45
1
2
FBM-11-160808-700T_0603
L46
1
2
FBM-11-160808-700T_0603

<30> LINE_IN_R
<30> LINE_IN_L

LINE_ IN_R-1
LIN E_IN_L-1

+AUD_VREF
+5VAMP

I0

I1

O
3

TC7SH32FU_SSOP5

NBA_PLUG_S

1
R351
@ 2.2K_0402_5%
LINE_ IN_R-1

INT_MIC1
AU D_MIC1

HP_S

LIN E_IN_L-1

C395
220P_0402_50V7K

C377
220P_0402_50V7K

4
3
6
2
1

FOX_JA6033L-5S3-TR
C767
220P_0402_50V7K

R663
100K_0402_5%

L23
FBM-11-160808-700T_0603

NBA_PLUG

R352
2.2K_0402_5%

U38

JP21

MOLEX_53398-0290

R662
100K_0402_5%

0.1U_0402_16V4Z

MIC JACK

1
2

INT_MIC1

C789

JP17

+5VAMP

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Size
B
D ate:

Document Number

R ev
C

401336
P , 17, 2005

Sheet
E

31

of

51

SUPER I/O SMsC LPC47N217

+3VS
IR @ 0.1U_0402_16V4Z

1
<18,33> LPC_AD[0..3]

+3VS

LPC_A D[0..3]

1
C220

C236

2
R224 1

S IO_PD#
2
IR @ 10K_0402_5%
SIO_SMI#
2
IR @ 10K_0402_5%

R211 1

IR @ 0.1U_0402_16V4Z

IR @ 4.7U_0805_10V4Z

1
C216

C227

IR @ 0.1U_0402_16V4Z
1

R204 1

<14> CLK_14M_SIO

19
20
21
6

CLKRUN#
PCI_CLK
SER_IRQ
IO_PME#

CLK_SIO_14M

R202
@ 10K_0402_5%

R225
@ 10_0402_5%

1
C225
@ 15P_0402_50V8J

SIO_GPIO11
SIO_SMI#
SIO_IRQ

CLK _PCI_SIO

CLK_SIO_14M

C239
@ 15P_0402_50V8J

CLK14

IRRX2
IRTX2
IRMODE/IRRX3

37
38
39

IRRX
IRTXOUT
IR MODE

INIT#
SLCTIN#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SLCT
PE
BUSY
ACK#
ERROR#
ALF#
STROBE#

41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

INIT#
S LCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
L PTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

VTR
VCC
VCC
VCC
VCC

7
11
26
45
54

FIR

CLOCK

23
24
25
27
28
29
30
31
32
33
34
35
36
40

GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO10
GPIO11/SYSOPT
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23

8
22
43
52

VSS
VSS
VSS
VSS

POWER

+3VS

IRRX <36>
IRTXOUT <36>
IRMODE <36>

PM_CLKRUN#
CLK _PCI_SIO
SERIRQ
SIO_PME#

SERIAL I/F

S IO_PD#

PCI_RESET#
LPCPD#

R216
@ 10K_0402_5%

IRRX

1
IR @ 10K_0402_5%
2
IR @ 10K_0402_5%

LFRAME#
LDRQ#

17
18

Base I/O Address


0 *= 02Eh
1 = 04Eh

SIO_GPIO11

R208 2

15
16

RXD1 <36>
TXD1 <36>
DSR#1 <36>
RTS#1 <36>
CTS#1 <36>
DTR#1 <36>
RI#1 <36>
DCD#1 <36>

R219
IR @ 1K_0402_5%
LPTSLCT <38>
LPTPE <38>
LPTBUSY <38>
LPTACK# <38>
LPTERR# <38>

SIO_IRQ

<19,25,26,28,33> PM_CLKRUN#
<14> CLK_PCI_SIO
<19,23,33> SERIRQ
<25,26,28,33> SIO_PME#

LPC_FRAME#
LPC_DRQ#1

RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
DCD1#

RXD1
TXD1
D SR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD #1

PARALLEL I/F

<17,23,25,26,28,33> PCI_RST#
<6,17,19,21,33> PLT_RST#

2
2 @ 0_0402_5%
IR @ 0_0402_5%

LAD0
LAD1
LAD2
LAD3

62
63
64
1
2
3
4
5

GPIO

<18,33> LPC_FRAME#
<18> LPC_DRQ#1
R545 1
R546 1

10
12
13
14

LPC I/F

U18
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

+3V

1
C222
+3VS

IR @ LPC47N217_STQFP64
IR @ 0.1U_0402_16V4Z

+5V_PRN

Close to Docking
+5VS

2
1
D5
1@ RB420D_SOT23

+5V_PRN

LPTSTB#

R43

1@ 2 33_0402_5%

R_LPTSTB#

LPTAFD#

R36

1@ 2 33_0402_5%

AFD#/3M#

INIT#

R22

1@ 2 33_0402_5%

LPTINIT#

S LCTIN#

R35

+5V_PRN
LPTSLCT
LPTPE
L PTBUSY
LPTACK#

1@

2 33_0402_5%

F D4
F D5
F D6
F D7

LPTSLCTIN#

R_LPTSTB# <38>
AFD#/3M# <38>
LPTINIT# <38>
LPTSLCTIN# <38>

10
9
8
7
6

10
9
8
7
6

RP3
RP5

RP6

LPD0
LPD1
LPD2
LPD3

1
2
3
4

8
7
6
5

F D0
F D1
F D2
F D3

FD0
FD1
FD2
FD3

<38>
<38>
<38>
<38>

1
2
3
4
5

1
2
3
4
5

1@ 68_1206_8P4R_5%
RP2
1@ 2.7K_10P8R_1206_5%

1@ 2.7K_10P8R_1206_5%
+5V_PRN
+5V_PRN

AFD#/3M#
LPTERR#
LPTINIT#
LPTSLCTIN#

F D3
F D2
F D1
F D0

LPD7
LPD6
LPD5
LPD4

4
3
2
1

5
6
7
8

F D7
F D6
F D5
F D4

FD7
FD6
FD5
FD4

<38>
<38>
<38>
<38>

1@ 68_1206_8P4R_5%
4

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
E

32

of

51

+RTCVCC

+3VALW

SKU ID definition,
Please see page 3.
R183
100K_0402_5%
1

Rc

SKU_ID

+3VALW

R184

Rd
1

0_0402_5%

<38> KB_CLK
<38> KB_DATA
<38> PS_CLK
<38> PS_DATA
<34> TP_CLK
<34> TP_DATA

C207
0.1U_0402_16V4Z

<35,44>
<35,44>
<4,44>
<4,44>

+5VS
RP81
1
2
3
4

8
7
6
5

KB_CLK
KB_DATA
PS_CLK
PS_DATA

4.7K_0804_8P4R_5%

<16> BKOFF#
<43,44> FSTCHG
<19> EC_SMI#
<21> IDE_LED#
<34> EN_WL#
<19> EC_SW I#
<26> EN_W OL#
<14> PE_REQ1#
<36> LID_SW #
<34> BT_ON#
<40,46> SYSON
<16,35,40,47> SUSP#
<46,48> VR_ON
<23> CARD_LED#
<14> PE_REQ2#
<19> PBTN_OUT#

RP84
8
7
6
5

EC_SMI#
FR D#
SELIO#
FSEL#

10K_0804_8P4R_5%

+5VALW

RP86
1
2
3
4

8
7
6
5

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

<38> EZ_SMBUS_ON#
<19> EC_SCI#
<38> EZ_PE_REQ1#
<19,38> EZ_PE_REQ2#

+3VALW
1
2
3
4

<21> CD_DK#
2
1
R467

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

4.7K_0804_8P4R_5%

100K_0402_5%
KB_CLK
KB_DATA
PS_CLK
PS_DATA
TP_CLK
TP_DATA
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SCI#

8
20
21
22
27
28
48
62
63
69
70
75
109
118
119
148
149
155
156
162
168

GPIO04
GPIO07
GPIO08
GPIO09
GPIO0D
GPIO0E
GPIO10
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO2A
GPIO2B
GPIO2D

ENBKL
BKOFF#
FSTCHG
EC_SMI#

PE_REQ1#
LID_SW #
BT_ON#
SYSON
SUSP#
VR_ON
PE_REQ2#
PBTN_OUT#

+5VS
2
4.7K_0402_5%
2
4.7K_0402_5%

+3VALW

1
C578

2
47K_0402_5%

1
R480

<34> CAPSLED#
<34> NUMLED#
<18> PHDD_LED#

CAPSLED#
NUMLED#

<18> EC_GA20
<18> EC_KBRST#

95

159

GPIAD0/AD0
GPIAD1/AD1
GPIAD2/AD2
GPIAD3/AD3
GPIAD4/AD4
GPIAD5/AD5
GPIAD6/AD6
GPIAD7/AD7

81
82
83
84
87
88
89
90

BATT_TEMP
SKU_ID
BATT_OVP
BATT_TEMPB

GPODA0/DA0
GPODA1/DA1
GPODA2/DA2
GPODA3/DA3
GPODA4/DA4
GPODA5/DA5
GPODA6/DA6
GPODA7/DA7

99
100
101
102
1
42
47
174

DAC_BRIG

Wake Up

Analog To Digital

SMBus

Digital To Analog

*GPIO18/XIO8CS#
*GPIO19/XIO9CS#
*GPIO1A/XIOACS#
*GPIO1B/XIOBCS#
Expanded I/O * GPIO1C/XIOCCS#
*GPIO1D/XIODCS#
*GPIO1E/XIOECS#
* GPIO1F/XIOFCS#

GPIO

FnLock#/GPIO12*
CapLock#/GPIO011*
NumLock#/GPIO0A *
ScrollLock#/GPIO0F *
MISC
ECRST#
GA20/GPIO02
KBRST#/GPIO03
ECSCI#

+3VALW

85
86
91
92
93
94
97
98

R168

Rb

0_0402_5%

PM_SLP_S3#
PM_SLP_S5#
EN_BT#
EC_PME#

INVT_PWM <16>
BEEP# <29>
TRICKLE <44>
ACOFF <43>
A/B#USE <44>
EC_ON <39>
EC_LID_OUT# <19>
EC_MUTE <31>

PM_SLP_S3# <19>
PM_SLP_S5# <19>
EN_BT# <34>

0.1U_0402_16V4Z
C

D33
1

AC IN <19,42,45>

CH751H-40_SC76

ECAGND
2
1
C209 0.01U_0402_16V7K

DOCKIN#
AD_BID0

C186

R479
10K_0402_5%

BATT_TEMPA <44>

ECAGND
2
1
C844 0.01U_0402_16V7K

BATT_OVP <43>

+3VALW

ON/OFF <39>

BATT_TEMPB <44>

DOCKIN# <15,22,27,38>

DAC_BRIG <16>
EZ_SUSON <38>
IR EF <43>
EN_DFAN1 <36>
W L_ON <28>

IR EF
EN_DFAN1#
W L_ON

CRY11 R476
2 CRY2
@ 20M_0603_5%

EZ_MAINON <38>
EZ_PERST# <38>
PW R_LED#
PW R_SUSP_LED#
BATT_FULL_LED#
BATT_CHGI_LED#
W L_ON_LED#
BT_ON_LED#
E_MAIL_LED#
MEDIA_LED#

171
12
11

FAN_SPEED1
DPLL_TP
TEST_TP

Timer PinTOUT2/GPIO2F

175

EC_THERM#

E51IT0/GPIO00
E51IT1/GPIO01
E51RXD/GPIO21/ISPCLK
E51TXD/GPIO22/ISPDAT

3
4
106
107

XCLKI
XCLKO

158
160

GPIO2E/TOUT1/FANFB1
DPLL_TP/GPIO06/FANFB3
FANTEST_TP/GPIO05/FAN3PWM

R475

PW R_LED# <34>
PW R_SUSP_LED# <34>
BATT_FULL_LED# <34>
BATT_CHGI_LED# <34>
W L_ON_LED# <34>
BT_ON_LED# <34>
E_MAIL_LED# <34>
MEDIA_LED# <34>

0_0402_5%

C576

FAN_SPEED1 <36>

EC_THERM# <19>

1
C575
X1

EC_RSMRST# <19>
EAPD
EC_TDO
CRY2
R474 1
CRY1

EAPD <29,31>
2 @ 0_0402_5%

32.768KHZ_12.5P_1TJS125DJ2A073
RTC_CLK

RTC_CLK <19>

2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
20K_0402_5%
2
10K_0402_5%

KBA1
1
R175
KBA4
1
R174
KBA5
1
R173
1 LID_SW #
R473
DOCKIN#
1
R683

1
R481
1
R229
1
R228

17
35
46
122
137
167

1 TP_CLK
R172
1 TP_DATA
R171

0.1U_0402_16V4Z
2

55
54
23
41
19
5
6
31

ON/O FF

SCL1
SDA1
SCL2
SDA2

Interface

2
26
29
30
44
76
172
176

GPWU0
GPWU1
GPWU2
GPWU3
Pin
GPWU4
GPWU5
TIN1/GPWU6
TIN2/FANFB2/GPWU7

163
164
169
170

Pulse

PSCLK1
PSDAT1
PSCLK2
PSDAT2PS2
PSCLK3
PSDAT3

BATGND

110
111
114
115
116
117

GPOW0/PWM0
GPOW1/PWM1
FAN2PWM/GPOW2/PWM2
GPOW3/PWM3
Width GPOW4/PWM4
GPOW5/PWM5
GPOW6/PWM6
FAN1PWM/GPOW7/PWM7

AD_BID0
1

0_0402_5%

INVT_PWM
BEEP#
TRICKLE
ACOFF
A/B#USE
EC_ON
EC_LID_OUT#
EC_MUTE

R170
100K_0402_5%

Ra

KSO16 <34>

32
33
36
37
38
39
40
43

+3VALW

10P_0402_50V8J

R548 1

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

Analog Board ID definition,


Please see page 3.

<6,17,19,21,32> PLT_RST#

LRST#

71
72
73
74
77
78
79
80

@ @96212-1011S

KSO[0..15] <34>

IN

2 @ 0_0402_5%

GPIK0/KSI0
GPIK1/KSI1
GPIK2/KSI2
GPIK3/KSI3
GPIK4/KSI4
GPIK5/KSI5
GPIK6/KSI6
GPIK7/KSI7

KSI[0..7] <34>

KSO[0..15]

OUT

R547 1

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16

NC

<17,23,25,26,28,32> PCI_RST#

ENBKL

0_0402_5%

KSI[0..7]
49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
153
154

GPOK0/KSO0
GPOK1/KSO1
GPOK2/KSO2
GPOK3/KSO3
GPOK4/KSO4
GPOK5/KSO5
GPOK6/KSO6
GPOK7/KSO7
GPOK8/KSO8
GPOK9/KSO9
GPOK10/KSO10
GPOK11/KSO11
GPOK12/KSO12
GPOK13/KSO13
GPOK14/KSO14
GPOK15/KSO15
GPOK16/KSO16
GPOK17/KSO17

NC

1
2
3
4
5
6
7
8
9
10

R478 1

EC_TDO

1U_0603_10V4Z

<8,16> GMCH_ENBKL

0.1U_0402_16V4Z

EC_PME#

VCCA

RD#
WR#
MEMCS#
IOCS#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1/XIOP_TP
A2
A3
A4/DMRP_TP
A5/EMWB_TP
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20/GPIO23
E51CS#/GPIO20/ISPEN

X-BUS Interface

<25,26,28,32> 1394_PME#
<25,26,28,32> ONBD_LAN_PME#
<25,26,28,32> WLANPME#
<25,26,28,32> LAN_PME#
<25,26,28,32> SIO_PME#

FR D#
FW R#
FSEL#
SELIO#
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19
CD_DK#

1
2
3
4
5
6
7
8
9
10

C217

<35> F RD#
<35> FW R#
<35> FSEL#

R205
10K_0402_5%

VCC
VCC
VCC
VCC
VCC
VCC
VCC

150
151
173
152
138
139
140
141
144
145
146
147
124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103
108
105

+3VALW

10P_0402_50V8J

<19,23,32> SERIRQ
<19,25,26,28,32> PM_CLKRUN#

+5VALW

0.1U_0402_16V4Z

Internal Keyboard

LRST#

<14> CLK_PCI_LPC

LAD0
LAD1
LAD2
LAD3
LFRAME# LPC Interface
LRST#/GPIO2C
LCLK
SERIRQ
CLKRUN#/GPIO0C *
LPCPD#/GPIO0B *

ENE-KB910-B4

1 @ 33_0402_5%

15
14
13
10
9
165
18
7
25
24

C218

GND
GND
GND
GND
GND
GND

R482 2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

16
34
45
123
136
157
166

U15
<18,32> LPC_AD0
<18,32> LPC_AD1
<18,32> LPC_AD2
<18,32> LPC_AD3
<18,32> LPC_FRAME#

For EC Tools
JP27

C557

C577
@ 22P_0402_50V8J
2
1

R199
0_0402_5%

C231
1000P_0402_50V7K
ECAGND

ECAGND
1
2
FBM-L11-160808-800LMT_0603

2
2
0.1U_0402_16V4Z

C241
1000P_0402_50V7K
1
1

96

2
2
0.1U_0402_16V4Z

L16

C219

161

C206

VCCBAT

ADB[0..7] <35>

R469
@ 0_0402_5%

L29
1
2
2 FBM-L11-160808-800LMT_0603

0.1U_0402_16V4Z
1
2

AGND

0.1U_0402_16V4Z
1
1 C215
1
C238

KBA[0..19] <35>

ADB[0..7]

+3VALW

KBA[0..19]

+3VALW

ENBKL
@ 120K_0402_5%
DPLL_TP
2
1K_0402_5%
TEST_TP
2
1K_0402_5%
2

KB910Q B4_LQFP176

Compal Electronics, Inc.


Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

SCHEMATIC, M/B LA-2601


Document Number

R ev
C

401336
, 17, 2005

Sheet
1

33

of

51

JP3

1
3
5
7
9
11
13
15
17
19

+5VALW

MDC CONN.

+3V

1
3
5
7
9
11

<18,29> ICH_AC_SDOUT
<18,29> IC H_AC_SYNC
<18> ICH_AC_SDIN1
<18,29> ICH_AC_RST#

1
R486

IC H_AC_SYNC
2 ICHAC_SDIN1_MDC
22_0402_5%

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

2
4
6
8
10
12

(CL56)

C253
1U_0805_25V4Z

+3V

TO M/B

ICHA C_BITCLK_MDC 1
2
R485 22_0402_5%

ICH_AC_BITCLK <18,29>

JP9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

13
14
15
16
17
18
19
20

+5VALW

13
14
15
16
17
18
19
20

ON/OFFBTN# <39>
CAPSLED# <33>
NUMLED# <33>
MEDIA_LED# <33>
E_MAIL_LED# <33>
KSO16 <33>

CAPSLED#
NUMLED#
MEDIA_LED#
E_MAIL_LED#
KSO16
K SI0
K SI1
K SI2
K SI3

SUYIN_80065AR-020G2T

JP30

2
4
6
8
10
12
14
16
18
20

+5VS

FOX_QT8A0121-4011~D

<33> TP_CLK
<33> TP_DATA

Connector for MDC Rev1.5


(EMW80)

<33> EN_WL#
<33> EN_BT#
<33> W L_ON_LED#
<33> BT_ON_LED#
<33> PW R_SUSP_LED#
<33> PW R_LED#
<33> BATT_FULL_LED#
<33> BATT_CHGI_LED#

TP_CLK
TP_DATA
EN_WL#
EN_BT#
W L_ON_LED#
BT_ON_LED#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

ACES_85201-2005

KSI[0..7]
KS O[0..15]

INT_KBD CONN.

KSI[0..7] <33>

BlueTooth Interface

KSO[0..15] <33>

(Right)

+3VALW

100P_0402_25V8K

KSO6

C626

100P_0402_25V8K

KSO14

C614

100P_0402_25V8K

KSO5

C627

100P_0402_25V8K

KSO13

C615

100P_0402_25V8K

KSO4

C628

100P_0402_25V8K

KSO12

C616

100P_0402_25V8K

KSO3

C629

100P_0402_25V8K

K SI0

C617

100P_0402_25V8K

K SI4

C630

100P_0402_25V8K

KSO11

C618

100P_0402_25V8K

KSO2

C631

100P_0402_25V8K

KSO10

C619

100P_0402_25V8K

KSO1

C632

100P_0402_25V8K

K SI1

C620

100P_0402_25V8K

KSO0

C633

100P_0402_25V8K

K SI2

C621

100P_0402_25V8K

K SI5

C634

100P_0402_25V8K

KSO9

C622

100P_0402_25V8K

K SI6

C635

100P_0402_25V8K

K SI3

C623

100P_0402_25V8K

K SI7

C636

100P_0402_25V8K

KSO8

C624

100P_0402_25V8K

KSO15
KSO14
KSO13
KSO12
K SI0
KSO11
KSO10
K SI1
K SI2
KSO9
K SI3
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
K SI4
KSO2
KSO1
KSO0
K SI5
K SI6
K SI7

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48

KSO15
KSO14
KSO13
KSO12
K SI0
KSO11
KSO10
K SI1
K SI2
KSO9
K SI3
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
K SI4
KSO2
KSO1
KSO0
K SI5
K SI6
K SI7

(Left)

<33> BT_ON#

Q12
BT@SI2301DS_SOT23

JP13
BT_VCC
<19> USB20_P5
<19> USB20_N5
<28> WLAN_BT_DATA
<28> W LAN_BT_CLK

USB20_P5
USB20_N5

R95
R94

(CL56)

2 BT@0_0402_5%
2 BT@0_0402_5%

BT_VCC

BT@10U_0805_10V4Z

1
2
3
4
5
6
7
8

BT@0_0402_5% USB5+
BT@0_0402_5% USB5-

R116 1
R226 1

C140

ACES_85203-2402

C613

KSO15

100P_0402_25V8K

C625

JP14
KSO7

BT@ACES_87212-0800

Bluetooth Connector

2 BT@0.1U_0402_16V4Z

C151

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet

34

of

51

U10D

ADB[0 ..7]

INT_FLASH_SEL

11

OE#

<33> KBA[0..19]
<33> ADB[0..7]

13

SB_INT_FLASH_SEL# <19>
KB A[0..19]

12

SUS_STAT# <19>

SN74LVC125APWLE_TSSOP14
+3VALW

2
+3VALW

+3VALW

+3VALW
R192
100K_0402_5%

R533
10K_0402_5%

SUSP# <16,33,40,47>

INT_FLASH_EN#

2
G
U14

FWE#

F RD# <33>
FSEL# <33>

I0

I1

3
Q23
2N7002_SOT23

TC7SH32FU_SSOP5

U10C

2
22_0402_5%

R503 1

100K_0402_5%

EC_FLASH# <19>
INT_FSEL# 1
R504

10

0.1U_0402_16V4Z

OE#

0.1U_0402_16V4Z
C153 1

C214

FWE#
KBA17
KBA14
KBA13
KBA8
KBA9
KBA11
F RD#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3

C638
0.1U_0402_16V4Z

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

VCC
WE*
A17
A14
A13
A8
A9
A11
OE*
A10
CE*
DQ7
DQ6
DQ5
DQ4
DQ3

NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
ADB0
ADB1
ADB2

U16

FSEL#

SN74LVC125APWLE_TSSOP14

FW R# <33>

29F040/SST39VF040_PLCC

(CL55)

1MB Flash ROM


1MB ROM Socket

+3VALW
U28

INT_FSEL#
F RD#
FWE#

22
24
9

CE#
OE#
WE#

VCC0
VCC1

+5VALW

+5VALW

C155
JP15

D0
D1
D2
D3
D4
D5
D6
D7

25
26
27
28
32
33
34
35

RP#
NC
READY/BUSY#
NC0
NC1

10
11
12
29
38

GND0
GND1

23
39

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
RESET#

1
2
R505
@ 100K_0402_5%

0.1U_0402_16V4Z

+3VALW

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#
RESET#
INT_FLASH_EN#
INT_FLASH_SEL
KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

31
30

KBA17
C187 1
KBA19
KBA10
ADB7
ADB6
ADB5
ADB4

2 0.1U_0402_16V4Z

R164
100K_0402_5%

21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37

U11

+3VALW

8
7
6
5

<33,44> EC_SMB_CK1
<33,44> EC_SMB_DA1

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

AT24C16N10SC-2.7_SO8
ADB3
ADB2
ADB1
ADB0
F RD#

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FSEL#
KBA0

R167
100K_0402_5%

@ SUYIN_80065AR-040G2T
@ SST39VF080-70_TSOP40

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet

35

of

51

FAN Conn
+5VS

+12VALW

Close to Docking
1
2
C522
0.1U_0402_16V4Z

2
2

C523
@ 0.1U_0402_16V4Z

1
D3
1SS355_SOD323

2
8.2K_0402_5%

R88

3
2
1
ACES_85205-0300

2 10K_0402_5%

FOXCONN_JM34613-L002-TR
JP48

<33> FAN_SPEED1

2
C107
@ 1000P_0402_50V7K

3
4

C106
@ 1000P_0402_50V7K

3
4

5
6

5
6

SW1

SATA HDD CONN

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

<18> SATA_DTX_C_IRX_N0
<18> SATA_DTX_C_IRX_P0

1
1
L47
0_0603_5%

GND
HTX+
HTXGND
HRXHRX+
GND

L48
0_0603_5%

(ELW80)

D30

@ PSOT03C

2
2

SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0

<18> SATA_ITX_C_DRX_P0
<18> SATA_ITX_C_DRX_N0

LID_SW # <33>

ESE11MV9_4P

JP50

1
2
3
4
5
6
7

DTR# <38>
RTS# <38>
TXD <38>
CTS# <38>
R I# <38>
RXD <38>
D C D# <38>
DSR# <38>

JP12
D26
1N4148_SOT23

+3VS

C108
10U_1206_16V4Z

DTR#
RTS#
TXD
CTS#
R I#
RXD
D CD#
DS R#

FA N1

1
R440

Q46
FMMT619_SOT23

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

U37A
LM358A_SO8

2
B

2
2
2
2
2
2
2
2

1
R441
100_0402_5%

1@
1@
1@
1@
1@
1@
1@
1@

1
2

R435
10K_0402_5%

E N_FAN1

1
1
1
1
1
1
1
1

1
2

OUT

-IN

R664
R665
R666
R667
R668
R669
R670
R671

DTR#1
RTS#1
TXD1
CTS#1
RI#1
RXD1
DCD#1
DSR#1

+IN

EN_ DFAN1

<33> EN_DFAN1

<32>
<32>
<32>
<32>
<32>
<32>
<32>
<32>

JP47
TIP
MRING

1
2
MOLEX_53398-0290

(ELW80)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

+5VS

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12

FIR Module

@ @OCTEK_STA-22RD1_22P
R366
IR @ 4.7_1206_5%
1
2

+3VS

R689
43K_0402_5%

C385
IR @ 22U_1206_16V4Z_V1

+3VS

C856

C396

R365
IR @ 4.7_1206_5%

@ 150U_D2_6.3VM

@ 150U_D2_6.3VM

R368
IR @ 47_1206_5%

2
1

<32> IRRX

2
R690

Close to SATA HDD

0_0402_5%

+IR_ANODE

<19> SATA_DET#

RA

+5VS

+3VALW

IR @ 10U_1206_16V4Z 2

C401

C402
IR @ 0.1U_0402_16V4Z

IR 1
IRRX
IR_3VS

2
4
6
8

IRED_C
RXD
VCC
GND

IRED_A
TXD
SD/MODE
MODE

1
3
5
7

IRTXOUT
IR MODE
R316 1

IRTXOUT <32>
IRMODE <32>
2
@ 0_0402_5%

IR @ IR_VISHAY_TFDU6101E-TR4_8P

SD/MODE: SHUTDOWN MODE, HIGH ACTIVE


MODE: HIGH/LOW SPEED SELECT

SATA Device Status


Presence
Removed

RA

Compal Electronics, Inc.

POP
NO POP

Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet

36

of

51

+USB_AS

+USB_AS
470P_0402_50V7K

470P_0402_50V7K

1
+

+5VALW

C768
150U_D2_6.3VM

+USB_AS

C770

C771

1
1

+ C769

150U_D2_6.3VM

U59

C776
4.7U_0805_10V4Z

1
2
3
4

GND
IN
IN
EN#

OUT
OUT
OUT
FLG

8
7
6
5

JP43
USB_OC#0 <19>
R659

G528_SO8

<19> USB20_N0
<19> USB20_P0

1
2
3
4

USB20_N0
USB20_P0

USB_OC#6 <19>

10K_0402_5%
SYSON#

10
12

1
1

1
C874
0.1U_0402_16V4Z

C772
@ 10P_0402_50V8J

C773

2 @ 10P_0402_50V8J

VCC VCC
D0- D1D0+ D1+
VSS VSS

5
6
7
8

G2
G4

9
11

G1
G3

USB20_N6
USB20_P6

USB20_N6 <19>
USB20_P6 <19>

1
C774

SUYIN_020122MR008S540ZU

@ 10P_0402_50V8J

C775
@ 10P_0402_50V8J

2
2

(CL55)

+USB_BS
C

470P_0402_50V7K
1
1
+
C778
C777
150U_D2_6.3VM
+5VALW

+USB_BS

U67

U60

C781
4.7U_0805_10V4Z

1
2
3
4

GND
IN
IN
EN#

USB20_N0

OUT
OUT
OUT
FLG

8
7
6
5

JP44
<19> USB20_N2
<19> USB20_P2

R660

G528_SO8

1
C779
@ 10P_0402_50V8J

SYSON#

1
2
3
4

USB20_N2
USB20_P2

USB_OC#2 <19>

10K_0402_5%
<40> SYSON#

1
2

USB20_P6

SDA

GND

ALERT

VDD

SCL

AS

USB20_P0
+USB_AS
USB20_N6

TOP
@ IP4220CZ6_SOT23-6

suyin_020167mr004s511zu_4p
C780
@ 10P_0402_50V8J

(ELW80)

(Left)

U68

C875
0.1U_0402_16V4Z

USB20_P2

AS

SDA

GND

ALERT

VDD

SCL

+USB_BS
USB20_N2

BOT
@ IP4220CZ6_SOT23-6

U69

+5VALW

+USB_CS

C784

USB20_N4

C859
4.7U_0805_10V4Z

GND
IN
IN
EN#
G528_SO8

SYSON#

SDA

GND

ALERT

VDD

SCL

+USB_CS
USB20_P4

TOP
OUT
OUT
OUT
FLG

@ 10P_0402_50V8J

8
7
6
5
R700
1

<19> USB20_P4
<19> USB20_N4

@ IP4220CZ6_SOT23-6

@ 10P_0402_50V8J
JP45

1
2
3
4

USB20_P4
USB20_N4
+USB_CS

USB_OC#4 <19>

10K_0402_5%
<40> SYSON#

AS

2
C785

U65

1
2
3
4

C782
150U_D2_6.3VM

C876
0.1U_0402_16V4Z

SUYIN_2569A-04G3T

C783

470P_0402_50V7K

(EAX00) (Top)

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size

Document Number

D ate:

P , 17, 2005

R ev
C

401336
Sheet
1

37

of

51

+5VS
+3VALW

1@ RB751V_SOD323
D40

<17> D_USB_SMI#2

D _LAN_LINK#
R_LPTSTB#
AFD#/3M#
F D0
LPTERR#
F D1
LPTINIT#
F D2
LPTSLCTIN#
F D3
F D4
F D5
F D6
F D7
LPTACK#
L PTBUSY
LPTPE
LPTSLCT

<27> D_LAN_LINK#
<32> R_LPTSTB#
<32> AFD#/3M#
<32> FD0
<32> LPTERR#
<32> FD1
<32> LPTINIT#
<32> FD2
<32> LPTSLCTIN#
<32> FD3
<32> FD4
<32> FD5
<32> FD6
<32> FD7
<32> LPTACK#
<32> LPTBUSY
<32> LPTPE
<32> LPTSLCT

D8

CLK_EZ_CLK1
CLK_EZ_CLK1#
D_L AN_ACTIVITY#

<14> CLK_EZ_CLK1
<14> CLK_EZ_CLK1#
<27> D_LAN_ACTIVITY#

D_LAN_MDI2+
D_LAN_MDI2-

<27> D_LAN_MDI2+
<27> D_LAN_MDI2-

1@ RB751V_SOD323

D_LAN_MDI3+
D_LAN_MDI3-

<27> D_LAN_MDI3+
<27> D_LAN_MDI3-

<36>
<36>
<36>
<36>
<36>
<36>
<36>
<36>
KB_DATA
KB_CLK
PS_DATA
PS_CLK

<33> KB_DATA
<33> KB_CLK
<33> PS_DATA
<33> PS_CLK

R672
R673
R674
R675

D_HP_S
D_SP DIFO
R I#
DTR#
CTS#
TXD
RTS#
RXD
DS R#
D CD#

R I#
DTR#
CTS#
TXD
RTS#
RXD
DSR#
D CD#

2 1@ 0_0603_5%
2 1@0_0603_5%
2 1@ 0_0603_5%
2 1@ 0_0603_5%

1
1
1
1

<33> EZ_SUSON
<33> EZ_MAINON
<33> EZ_PERST#
EZ_PCIE_TXP1
EZ_PCIE_TXN1
D_DVI_TXD2D_DVI_TXD2+

<19> EZ_PCIE_TXP1
<19> EZ_PCIE_TXN1
<22> D_DVI_TXD2<22> D_DVI_TXD2+

LAN0+

GND

LAN0GND
LAN1+
LAN1GND
GND
LAN_LINK#
PP_STB#
PP_AFD#
PP_D0
PP_ERR#
PP_D1
PP_INIT#
PP_D2
PP_SLIN#
PP_D3
PP_D4
PP_D5
PP_D6
PP_D7
PP_ACK#
PP_BUSY
PP_PE
PP_SLCT
PE_WAKE#
GND
GND
PCIECLK1+
PCIECLK1LAN_ACT#
RESERVE
GND
LAN2+
LAN2GND
LAN3+
LAN3GND
HP_S
SPDIF
COM_RI#
COM_DTR#
COM_CTS#
COM_SOUT
COM_RTS#
COM_SIN
COM_DSR#
COM_DCD#
GND
PS2_KBDT
PS2_KBCK
PS2_MSDT
PS2_MSCK
SUSON
MAINON
PE_RST#
GND
PCIETX1+
PCIETX1DVI2DVI2+

DVI_DET
DVI_DAT
GND
DVI_CLK
EZIN_EM#
MIC_S
AUD_INR
AUD_INL
AGND
AUD_MIC
AUD_OR
AUD_OL
AGND
GND
VGA_HS
VGA_VS
VGA_DAT
VGA_CLK
SERIRQ
PE_CLK
EZIN_ME#
PE_REQ2#
PE_DAT
PE_REQ1#
GND
PCIERX1+
PCIERX1DVI1DVI1+
GND
DVI0DVI0+
GND
DVICLK+
DVICLKGND
GND
TV_COMP
TV_Y
TV_C
GND
GND
VGA_R
VGA_G
VGA_B
GND
GND
PCIERX2+
PCIERX2GND
GND
PCIETX2+
PCIETX2GND
GND
PCIECLK2+
PCIECLK2VCC
VCC
GND
GND

FOX_QL10303-C44441-4F_120P

+3VS

D _DVI_DET
DE_DVI_SDATA
DE _DVI_SCLK
MZIN_EM#
D _MIC_S
D_AUD_INR
D_AUD _INL
D_A GND
D_A UD_MIC2
D_A UD_OR
D _AUD_OL
D_A GND

DE _DVI_SCLK

D_CRT_HSYNC <15>
D_CRT_VSYNC <15>
D_DDC_DATA <15>
D_DDC_CLK <15>
+5VS
R661 1

EZ_SMB_DAT

EZ_PE_REQ2# <19,33>
EZ_PE_REQ1# <33>

EZ_PCIE_RXP1
EZ_PCIE_RXN1
D_DVI_TXD1D_DVI_TXD1+
D_DVI_TXD0D_DVI_TXD0+
D_DVI_TXC+
D_DVI_TXCD_TV_COMPS
D_TV_LUMA
D_TV_CRMA
R535 1
R536 1
R537 1

1@ 2 0_0603_5%
1@ 2 0_0603_5%
1@ 2 0_0603_5%

EZ_PCIE_RXP2
EZ_PCIE_RXN2
EZ_PCIE_TXP2
EZ_PCIE_TXN2
CLK_EZ_CLK2
CLK_EZ_CLK2#

EZ_PCIE_RXP1 <19>
EZ_PCIE_RXN1 <19>
D_DVI_TXD1- <22>
D_DVI_TXD1+ <22>
D_DVI_TXD0- <22>
D_DVI_TXD0+ <22>
D_DVI_TXC+ <22>
D_DVI_TXC- <22>

JP2
D_AUD_INR
D_AUD _INL
D_A GND
D_A UD_MIC2
D_A GND
D_A UD_OR
D _AUD_OL
D_HP_S
D _MIC_S
D_SP DIFO

D_TV_COMPS <22>
D_TV_LUMA <22>
D_TV_CRMA <22>
D_ CRT_R
D_CRT_G
D_CRT_B

D_CRT_R <15>
D_CRT_G <15>
D_CRT_B <15>

EZ_PCIE_RXP2 <19>
EZ_PCIE_RXN2 <19>

1
2
3
4
5
6
7
8
9
10

EZ_PCIE_TXP2 <19>
EZ_PCIE_TXN2 <19>

CLK_EZ_CLK2 <14>
CLK_EZ_CLK2# <14>

DKN_B+

PJP23
@ JUMP_43X118
1 1
2 2

VIN

V IN
@ 0.1U_0402_25V4K @ 0.1U_0402_25V4K

2
G

2
G

1
C382

@ 0.1U_0402_25V4K

1
C383

1
C384

C386

@ 0.1U_0402_25V4K

+3VS

2
@ 4.7K_0402_5%

EZ_SMB_CLK

2
1@ 0_0603_5%

R98

2
G

R16
Q5
3
@ 2N7002_SOT23

R14

3 Q4
@ 2N7002_SOT23

4.7K_0402_5%

+3VS

EZ_SMB_DAT

1
2
3
4
5
6
7
8
9
10

1@ ACES_87213-1000

1
R99

D_DVI_SCLK <22>

2
1
+3VS
R530
1@ 6.8K_0402_5%

30mil

3 Q3
@ 2N7002_SOT23

<11,12,14> D_CK_SCLK

D_ DVI_SCLK

@ 0.1U_0402_25V4K

<11,12,14> D_CK_SDATA

D_DVI_SDATA <22>

1@ 2 1K_0402_5%

C381

Q21
1@ BSS138_SOT23

D_CRT_HSYNC
D_CRT_V SYNC
D _DDC_DATA
D_DD C_CLK
EZ_SMB_CLK
MZIN_ME#

D_DVI_SDATA

Q20
1@ BSS138_SOT23

PJP24
@ JUMP_43X118
1 1
2 2

EZ_SMBUS_ON# <33>

R15
100K_0402_5%

64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124

2
G

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62

D_LAN_MDI1+
D_LAN_MDI1-

<27> D_LAN_MDI1+
<27> D_LAN_MDI1-

D_LAN_MDI0-

1@ 4.7K_0402_5%
DE_DVI_SDATA
1

63

<27> D_LAN_MDI0-

<27> D_LAN_MDI0+

D_LAN_MDI0+

R529 1@ 6.8K_0402_5%
2
1
+3VS

R527

Docking
Conn.
JP23

<17> D_USB_SMI#1

R526
1@ 4.7K_0402_5%

1@ TC7SH08FU_SSOP5

R528
1@ 0_0402_5%

2
G

R17
1@ 10K_0402_5%

1@ RB411D_SOT23

DOCKIN# <15,22,27,33>

1@ 100K_0402_5%
DOCKIN#

2
2

U2

MZIN_EM#

D _DVI_DET

<22> D_DVI_DET

+3VS

D14

R525

1@ 0.1U_0402_16V4Z

1@ 10K_0402_5%
R13 2
1

C11

+3VALW

Compal Electronics, Inc.

2
1@ 0_0603_5%

Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
E

38

of

51

TOP Side
2

+3VALW

1
JOPEN

Power Button

RTC Battery

J2

1
JOPEN

J3

Button Side

100K_0402_5%

+RTCBATT

+RTCBATT
1

2
ON /OFFBTN#

<34> ON/OFFBTN#

BATT1

D29

O N/OFF <33>

1
51ON#

RTCBATT

51ON# <42>

R468

D28

DAN202U_SC70

BAS40-04_SOT23

+RTCVCC

R466
4.7K_0402_5%

C556
1000P_0402_50V7K

D27
RLZ20A_LL34

+CHGRTC

+3VALW

1
2 2
R463
33K_0402_5%

D
Q50

C558
0.1U_0402_16V4Z

Q49
DTC124EK_SC59

<33> EC_ON

1
E C_ON

2
G
3

2N7002_SOT23 S

Power ON Circuit
+3VS
+3V

+3V

14
P

O 8
+3V POWER

11

I
G

G
7

C289
1U_0805_25V4Z

U25E
SN74LVC14APWLE_TSSOP14

O 10
+3V POWER

SYS_PW ROK <19>

9
2

U25D
SN74LVC14APWLE_TSSOP14

14

R269
180K_0402_5%

R271

100K_0402_5%

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
E

39

of

51

+3VALW TO +3V

+3V

+5VALW TO +5VS

+1.8VS

+3V
+5VS

R161
470_0402_5%

1U_0805_25V4Z

U12

1
2
3
4

S
S
S
G

SYSON_ALW

SI4800DY_SO8

C180

R159
@ 1M_0402_1%

C189

+12VALW

1
1

C404
4.7U_0805_10V4Z

C403

2 SYSON#
G
Q18
2N7002_SOT23

1U_0805_25V4Z

C380
4.7U_0805_10V4Z

10U_1206_16V4Z

0.1U_0402_16V4Z
S

R157
100K_0402_5%
1
2

D
D
D
D

8
7
6
5

SI4800DY_SO8

R431
470_0402_5%

2 SUSP
G
Q45
2N7002_SOT23

5VS_GATE

2 SYSON#
G
Q19
2N7002_SOT23

+5VS

+3VS

+3VS

1U_0805_25V4Z

+1.5VALW
R490
100K_0402_5%
1
2

5VS_GATE

+12VALW

SI4800DY_SO8

10U_1206_16V4Z

C594

R484
@ 1M_0402_1%

C598

0.1U_0402_16V4Z
S

+1.5VS
U13

8
7
6
5

SUSP
2
G
Q53
2N7002_SOT23

D
D
D
D

S
S
S
G

1
2
3
4

SI4800DY_SO8

C211

C208

+DDRVCC

+1.5VS

4.7U_0805_10V4Z

1U_0805_25V4Z

C191
4.7U_0805_10V4Z

10U_1206_16V4Z

R489
@ 470_0402_5%

R707
470_0402_5%

5VS_GATE

1
2
3
4

S
S
S
G

D
D
D
D

+1.5VALW TO +1.5VS

C592

U40

C596

2 SUSP
G
Q38
@ 2N7002_SOT23

+3VALW

2 SUSP
G
Q37
2N7002_SOT23

+3VALW TO +3VS

R341
@ 470_0402_5%

R340
470_0402_5%

8
7
6
5

1
2
3
4

S
S
S
G

D
D
D
D

10U_1206_16V4Z

8
7
6
5

C190

+3VALW

C196

U32

+5VALW

2 SYSON#
G
Q67
2N7002_SOT23

2 SUSP
G
Q54
@ 2N7002_SOT23

+DDRVCC

R338
10K_0402_5%

U6
1@ 4.7U_0805_10V4Z

C61

R339
10K_0402_5%

+1.8VS

+1.8V TO +1.8VS (DDR2)

<46> SUSP

SUSP

SYSON#

<37> SYSON#

C72

1
2
3
4

S
S
S
G

D
D
D
D

8
7
6
5

+5VALW

+5VALW

1@ SI4800DY_SO8

1@ 1U_0805_25V4Z
<16,33,35,47> SUSP#

100K

S Y SON

<33,46> S YSON

100K

2
DTC115EKA_SOT23
Q34

100K

100K

DTC115EKA_SOT23
Q35
5VS_GATE

C90
1@ 4.7U_0805_10V4Z

Compal Electronics, Inc.


Title
PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate:

SCHEMATIC, M/B LA-2601


Document Number

R ev
C

401336
P , 17, 2005

Sheet
E

40

of

51

14

+3V

CF11
C F7
C F2
C F1
CF15
CF16
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80

+3VALW

13

I
7

14

F D2
F IDUCAL

F D1
F IDUCAL

F D4
F IDUCAL

0.1U_0402_16V4Z

12
D

SN74LVC14APWLE_TSSOP14

U10A

OE#

F D5
F IDUCAL

F D3
F IDUCAL

1
F D6
F IDUCAL

C170

O
G

U25F

C F9
C F4
CF10
C F5
C F6
CF14
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80

SN74LVC125APWLE_TSSOP14

+12VALW

H2
SCREW 8.5X2.8

H3
SCREW 8.5X2.8

H4
SCREW 8.5X2.8

H5
SCREW 8.5X2.8

H16
SCREW 8.5X2.8

H17
SCREW 8.5X2.8

H18
SCREW 8.5X2.8

H14
SCREW 8.5X2.8

H19
SCREW 8.5X2.8

U10B

LM358A_SO8

6
C

H10
SCREW 8.5X2.8

H15
SCREW 8.5X2.8

1
H13
SCREW 8.5X2.8

H9
SCREW 8.5X2.8

H12
SCREW 8.5X2.8

H11
SCREW 8.5X2.8

H8
SCREW 8.5X2.8

H7
SCREW 8.5X2.8

OUT
-IN

SN74LVC125APWLE_TSSOP14

H6
SCREW 8.5X2.8

OE#

H1
SCREW 8.5X2.8

U37B
5 +IN

H20
SCREW 8.5X2.8

H29
SCREW 8.5X2.8

1
1

H25
SCREW 8.5X2.8

H30
SCREW 8.5X2.8

1
1

1
H28
SCREW 8.5X2.8

H24
SCREW 8.5X2.8

H27
SCREW 8.5X2.8

H26
SCREW 8.5X2.8

H23
SCREW 8.5X2.8

H22
SCREW 8.5X2.8

H21
SCREW 8.5X2.8

M1
SCREW 8.5X2.8

H31
SCREW 8.5X2.8

Compal Electronics, Inc.


1

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

SCHEMATIC, M/B LA-2601


Size

Document Number

D ate:

P , 17, 2005

R ev
C

401336
Sheet
1

41

of

51

Detector
VIN

Vin Detector
18.234 17.841
17.597 17.210

PC4
1000P_0402_50V7K
2
1

VS

VIN

PC5
2
1
8

VSB+

2
1

VL

PR14
10K_0603_5%
2

B+

VS

PD7
RB715F_SOT323

ACIN

+5VALW

+1.8VP

PJP2
@ JUMP_43X118
1 1
2 2

PJP3
@ JUMP_43X118
1 1
2 2

PJP4
@ JUMP_43X118
1 1
2 2

+3VALWP

PJP5
@ JUMP_43X118
1 1
2 2

PJP6
@ JUMP_43X118
1 1
2 2

+1.5VALWP

PJP7
@ JUMP_43X118
1 1
2 2

+3VALW

+0.9VSP

+DDRVCC

+1.5VALW
+GMCH_COREP

PJP9
+12VALWP

@ JUMP_43X39

+12VALW
+2.5VSP

PJP16
@ JUMP_43X118
1 1
2 2

PR23
2
G

PQ2

N2

2 PACIN
47K_0603_5%

2N7002_SOT23
+5VALWP
2
PQ3

+0.9V_DDR_VTT

DTC115EUA_SC70

Precharge detector
7.558 7.333 7.112
6.108 5.933 5.704

+1.05VS

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601

+2.5VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BATT

PJP8
@ JUMP_43X118
1 1
2 2

Precharge detector
14.724 14.333 13.945
13.280 12.933 12.531

PR24
10K_0603_5%
N1
2
1

+5VALWP

PJP1
@ JUMP_43X118
1 1
2 2

1U_0805_50V4Z

VL

N3

5
6

PC12
10U_0805_10V4Z

PC10

GND

200_0603_5%

200_0603_5%

N10

PR21
200K_0603_1%

IN

OUT

N5

<43,44> GB

PU1B
LM393M_SO8
N4

PC14
1000P_0402_50V7K

PC13
0.1U_0603_25V7K

N12

G920AT24U_SOT89

<44> GA

200_0603_5%
PU2

3.3V

PR20

PR17
280K_0603_1%

1
3

PR18

<43,44> ACON

<18,45,49> MAINPWON

PD6
RB715F_SOT323

RTCVREF

PR15
1M_0603_0.5%
1

1K_1206_5%

PC11
1000P_0402_50V7K

N6

PR13
1

PR22
1.5M_0603_1%

PC9
0.1U_0603_25V7K

0.22U_1206_25V7K

PC8

22K_0402_5%

+CHGRTC

G
4

B+

PD5
1N4148_SOD80
PR11

PR16

1K_1206_5%

1
PR12

PR19

RTCVREF

1K_1206_5%

100K_0402_5%

PR8
10K_0603_5%
1

N11

VS

33_1206_5%
CHGRTCP

PR7
10K_0603_5%

PR9
1

PQ1
TP0610K_SOT23
3
1

PACIN <43,44>

3.3V
PR10

<39> 51ON#

PU1A
LM393M_SO8
PZD1

1
VMBB

PACIN

RLZ4.3B_LL34

PD4
1N4148_SOD80
2
1

ACIN <19,33,45>

PR4
1K_0603_5%
2

PR3
10K_0805_5%

1
2

PD3
1N4148_SOD80

N7

VMBA

N8

PC7
1000P_0402_50V7K

VIN

PR6
19.6K_0603_0.1%
2
1

PC6
0.1U_0402_16V7K
2
1

N9

PR5
22K_0603_1%
2

1
2

PR2
82.5K_0603_0.1%

PR1
1M_0603_0.5%
1
2
VIN

PD2
1N4148_SOD80

17.449
16.813

PC3
100P_0402_50V8J
2
1

1
2

SINGA_2DC-S756B200

PC2
1000P_0402_50V7K

3
PC1
100P_0402_50V8J
2
1

G
G

AD IN

PD1
SBM1040-13_POWERMITE3
2
1
3

0.01U_0402_25V7Z

ADPIN
PL1
FBM-L18-453215-900LMA90T_1812

PCN1

Size

Document Number

R ev
C

401336
Date:

, 17, 2005

Sheet
1

42

of

Charger

PJP20
@ JUMP_43X118
1 1
2 2

Iadp=0~3.0A
D

VIN

8
7
6
5

PR29
2 N25

47K_0402_5%
1

1
2

1
2
3

PC18
2200P_0402_50V7K

0.02_2512_1%

PR25

8
7
6
5

PQ6
AO4407_SO8

PJP18
@ JUMP_43X118
1 1
2 2
PC17
0.1U_0603_25V7K

1
2

PC19
0.1U_0603_25V7K

PR30
10K_0402_5%

N21
PU3
-INC2

1
PR32
100K_0402_1%
+INE2

OUTC2

-INE2

+INC2

24

GND

23

PR31
0_0402_5%

PQ57
@ 2N7002_SOT23

OUT

20

VH

19

PC21
0.1U_0603_25V7K

1
2

2
BATT+

18

VCC

1
1
2
68K_0402_5%

-INE3

PR42
10

OUTC1

15

FB3

11

OUTD

CTL

-INC1

+INC1

N27

1500P_0603_50V7K

FSTCHG
<33,44>

PQ13
2N7002_SOT23

PR46

4.2V

150K_0603_0.1%

300K_0603_0.1%

PR48
N26

N16

300K_0603_0.1%
2

PR49
499K_0603_1%

+3VALWP
VL
1

CS

GB <42,44>

S @ 2N7002_SOT23

CC=0.4~3.0A
CV=16.8V(8 CELLS LI-ION)
CV=12.6V(6 CELLS LI-ION)

PQ14

2
G

<33,44> FSTCHG

1
1

PQ15
DTC115EUA_SC70

N19

N20

PR51
@ 47K_0603_5%

1
2

PC34
0.01U_0402_25V7Z

PC35
0.1U_0402_16V7K

PQ16
2
G
PQ17
2N7002_SOT23

PR53
105K_0603_0.5%
2
1

PR50
100K_0402_5%
1
2

N18
1

P
G

PD30
@ SKS30-04AT_TSMA

+INC1

PR47
340K_0603_1%

PR54
40.2K_0603_1%
2
1

PD9
SKS30-04AT_TSMA

1
2
+

14
13

BATT+

MB3887_SSOP24

8
4

PR52
22K_0603_5%
2
1
A

N17

PC28
1
2

LXCHRG
PR40
0.02_2512_1%
PL3
15U_PLFC1045P-150A_3.7A_20%
1
2
1
2

-INE3

16

PC31
4.7U_1206_25V6K
2
1

+INE1

17

RT

PC29
4.7U_1206_25V6K
2
1

-INE1

PQ11
AO4407_SO8

+INE1

PU4A
LM358A_SO8
1 0

PC33
0.01U_0402_25V7Z

VS

PC27 0.1U_0603_25V7K
2

PR39

PR45

3S2P : 13.5V--> BATT_OVP= 2.0V


(BAT_OVP=0.14753 *BATT+)

ACOFF <33>

3
FB1

PC32
0.1U_0402_16V7K

1
PR44

PC24
1
2

N15

100K_0402_1%

2 ACOFF

5
6
7
8

12

Battery OVP voltage :


4S2P : 18V--> BATT_OVP= 2.0V
(BAT_OVP=0.1112*VMB)

N13

PQ9
DTC115EUA_SC70

ACOFF#
3
2
1

VREF

162K_0603_1%

PU4B
LM358A_SO8

N14

0.1U_0603_25V7K

PC26
PR38
1
2
1
2
1K_0402_1%
1500P_0603_50V7K
-INE1

OUTD

-INE2 VCC(o)
FB2

PR43

CS

21

47K_0402_1%

<33> IREF

<33> BATT_OVP

22

1
2

PR41
2
1 OUTC1
10K_0402_1%

IREF=1.048*Icharge
IREF=0.419~3.132V

CS

+INE2

PR36
1

N24

2
G
S
PC20 2200P_0402_50V7K
1
2

1
2

1
PR35
10K_0402_1%

<42,44> ACON

PC25
0.1U_0402_16V7K

PR37
3K_0603_5%

PC23
1
2

2200P_0603_50V7K 10K_0402_1%
MB3887VREF
6

N22

PC22
0.1U_0402_16V7K
2
1

2
G
3

PACIN

<42,44> PACIN

PR34
31.6K_0603_1%

2
ACOFF# 1

PQ12
2N7002_SOT23

PD8
1SS355_SOD323

ACOFF#

1
1

1.202V

PR33
150K_0603_1%

1
3

2
G
C

PQ8
DTC115EUA_SC70
PQ10
2N7002_SOT23

1
2

PC30
4.7U_1206_25V6K
2
1

N24

N23

PQ7
47K
DTA144EUA_SC70
2
47K

B++

B+

PC16
4.7U_1206_25V6K

1
2
3

1
PR27
47K_0402_5%

P3

1
2
3

PR26
15K_0603_5%

8
7
6
5

PR28
200K_0402_5%

VIN

PQ5
AO4407_SO8

P2

PC15
4.7U_1206_25V6K

PQ4
AO4407_SO8

@ DTC115EUA_SC70

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size
Document Number
Custom

R ev
C

401336

Date:

, 17, 2005

Sheet
1

43

of

1
GB

2
PR70
100_0603_5%

2
PR72
10K_0402_5%

PQ24
DTC115EUA_SC70

PQ25
DTC115EUA_SC70

2
74HC253_Y1

2
1
2

N38
1
2

PR78
442K_0603_1%

2
2

PR213
@ 0_0402_5%

PR87
499K_0603_1%

PQ26
DTC115EUA_SC70

N37
1

N36

PR84
1M_0603_0.5%

PR85
100K_0603_1%
1

PC45
1000P_0402_50V7K

8
+

N35

N457

PU6B
LM393M_SO8

Main Battery Detector


High:10.68V
Low :9.52V

PR88
5.6M_0603_5%

PC44
100P_0402_50V8J

VS

VMBA
PR82
10K_0402_5%

PR83
100K_0402_5%

2
PQ27
DTC115EUA_SC70

2
PQ28
DTC115EUA_SC70

N39

PR89
47K_0603_5%
1
2

PACIN <42,43>

PD13
3

<33> A/B#USE

Second Battery Detector


High:8.67V
Low :7.87V

PC42
100P_0402_50V8J

1
2
8
P
G

GND
S0
S1
1EN
2EN
14
2
1
15

PC40
0.01U_0402_25V7Z

9
2Y
2C0
2C1
2C2
2C3

1C0
1C1
1C2
1C3

N34

3
2

VL

N33

PR74
649K_0603_1%

PR76
100K_0603_1%
2
1

RTCVREF

EC_SMB_DA2

VMBB

2
1
PR79
5.6M_0603_5%

PR86
4.7K_0402_5%

ACON
<42,43>

PR212
@ 0_0402_5%
1
2

N431

PR77
4.7K_0402_5%

FSTCHG
<33,43>

PU6A
LM393M_SO8
2

1
2 N41
PR80
100K_0402_5%
1
2
PR81
100K_0402_5%

PR73
100K_0402_5%

N32
PC43
@ 4700P_0603_50V7K
1
2

PR218
0_0402_5%
1
2

PD12
@ 1SS355_SOD323

VCC

10
11
12
13

VS

VL

1Y
1

EC_SMB_CK2

<4,33> EC_SMB_DA2

6
5
4
3

1
2

<42,43> ACON

PC41
0.1U_0402_16V7K

16
PR75
@ 270K_0402_5%
1
2

PR69
100_0603_5%

74HC253_Y2

PU5
74HC253

<33> BATT_TEMPB

<4,33> EC_SMB_CK2

VL

N31

PR68
10K_0603_5%

<42,43> GB

2
PR71
10K_0402_5%

PR64
1K_0402_5%

PD11
1N4148_SOD80

N29

2
1
PR67
10K_0603_5%

1
1

GA

<42> GA

PR62
6.49K_0603_1%

PQ23
HMBT2222A_SOT23

EC_SMB_DA1 <33,35>
EC_SMB_CK1 <33,35>

+3VALWP

PD10
1N4148_SOD80
BATT_TEMPA <33>

2
B

PQ22
HMBT2222A_SOT23

PR63
1K_0402_5%

TSB
SMC2
SMD2

PR66
100_0603_5%

C
N30

2
B
E

2
2

PR65
100_0603_5%

2
PR60
22K_0603_5%

C
N28

VMBBB

+3VALWP

PR61
6.49K_0603_1%

8
7
6
5

Battery Select
PCN3
SUYIN_200275MR007G113ZL
7 BATT+ G 8
6 BATT+ G 9
5 TS
4 SMC
3 SMD
2 GND
1 GND

PR58
39K_0603_5%

1
BATTB_ON

PR59
22K_0603_5%
2

1
2
3

1
2
3

PL5
FBM-L18-453215-900LMA90T_1812

8
7
6
5

PQ21
AO4407_SO8

PC39
0.01U_0402_25V7Z

BATTA_ON

8
7
6
5

P4

1
2

PQ20
AO4407_SO8

1
2
3

2
PR55
1K_0603_5%

1
2
3

PR57
39K_0603_5%

8
7
6
5

VMBAA

VMBB
PQ19
AO4407_SO8

P5

1
AB/I
TSA
SMD1
SMC1

PC38
0.01U_0402_25V7Z

9
8

PQ18
AO4407_SO8

PL4
FBM-L18-453215-900LMA90T_1812

PC37
1000P_0402_50V7K

PJP15 @ JUMP_43X118
1 1
2 2

1
2
3
4
5
6
7

BATT+

VMBA

PCN2
SUYIN_200275MR007G113ZL
BATT+
ID
B/I
TS
SMD
G SMC
G GND

PJP14 @ JUMP_43X118
1 1
2 2

PC36
1000P_0402_50V7K
2
1

TRICKLE <33>

1N4148_SOD80

A/B#USE
High: Main Battery (A)
Low : Second Battery (B)

Title

Compal Electronics, Inc.


SCHEMATIC, M/B LA-2601

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size
Document Number
Custom

R ev
C

401336

Date:

, 17, 2005

Sheet
1

44

of

+3VALWP/+5VALWP/+12VALWP

B+

PJP10

PC46
4.7U_1206_25V6K
2
1

@ JUMP_43X118

21

1
P R96
0_0402_5%
2

P R95
1.54K_0603_1%

P R99
2M_0402_1%
2

PR104
698_0402_1%
+5VALWP

1
PR110
0_0402_5%

PR108
10.2K_0603_1%

PC65
4.7U_1206_25V6K

PC67
100P_0402_50V8J

1
+

P D18
SKUL30-02AT_SMA

1
PR109
@ 0_0402_5%

PC62
0.47U_0603_16V7K

VL

1
2.5VREF

PC66
680P_0402_50V7K

CS H5
CSL5
FB5

VL

P C56
2200P_0402_50V7K
P C60
47P_0402_50V8J
N 47
2
1

1
2

P C55
4.7U_1206_25V6K
2
1

1
2
3
4

PR112
47K_0402_5%

G2
D2
D1/S2/K
D2
D1/S2/K
G1
D1/S2/K S1/A

2
PR111
10K_0402_1%

2
1
P C58
4.7U_1206_25V6K

1
1N 54 2

RUN/ON3

VS

DH 51 8
7
6
5

PR97
0_0402_5%

28

PR107
@ 300K_0402_5%

PQ30
AO4912_SO8

MAX1902_VDD
BST5
D H5
LX5
DL5

MAX1902_SYNC

1
2
3
10
23

4
5
18
16
17
19
20
14
13
12
15
9
6
11

GND

CS H3
PR1032 CSL3
1
620_0402_5%
N51
1
2
PR105
10K_0402_5%

V+

26
24

0.1U_0603_25V7K

22

1
LX3
DL3

12OUT
VDD
BST5
DH5
LX3
LX5
DL3
DL5
MAX1902EAI_SSOP28 PGND
CSH5
CSH3
CSL5
CSL3
FB5
FB3
SEQ
SKIP#
REF
SHDN#
SYNC
RST#
TIME/ON5

<19,33,42> A C IN

DH3

2
1
P C64
100P_0402_50V8J

PR106
3.32K_0603_1%
1
2

P D17
SKUL30-02AT_SMA

FB3
P C63
150U_D2_6.3VM

P C57

2
P C61
2
1
CSL3A

BST3

27

N 50

25

D H3

1
PR102
0_0402_5%

0.47U_0603_16V7K

PR101
1.27K_0603_1%

+3VALWP

A C IN 2
G
PQ32
2N7002_SOT23

PU7
BST3

N 46 2
1
P C59
47P_0402_50V8J

1
2
PR98
1.27K_0603_1%

PR100
1M_0402_1%
1
2

PL6
10U_SPC-1204P-100_4.5A_20%

B+++
PR94
0_0402_5%

P R93
2.7K_1206_5%

+12VALWP

9U_SDT-1204P-9R0-120_4.5A_20%

P C54
4.7U_1206_25V6K
2
1

1
2
1
P C53
4.7U_1206_25V6K

1
2

PR92
0_0402_5%

P D16
1SS355_SOD323

DH 31

8
7
6
5

D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K

P R91
0_0402_5%
1
2

1
2
3
4

PC52
0.1U_0603_25V7K
2
1

P C68
150U_D2_6.3VM

4.7U_1206_25V6K

P C51
1

4.7U_1206_25V6K

P C50
1

2200P_0402_50V7K

P C49
2
1

N52

PT1

VS

MAX1902_V+

PR90
22_1206_5%

VL
PQ29
AO4912_SO8

N53

PD15
CHP202U_SC70

PD14
EC11FS2_SOD106

470P_0805_100V7K

BST5A

PC47
BST3A

B+++

PC48
0.1U_0603_25V7K
2
1

VL
N49

PR113
10K_0402_1%

806K_0603_1%

PC69
@ 0.047U_0603_25V7M

PR114

MAINPW ON <18,42,49>

PC70
0.47U_0603_16V7K

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Electronics, Inc.


SCHEMATIC, M/B LA-2601

Size

Document Number

R ev

401336

D ate: P , 17, 2005

Sheet
D

45

of

+GMCH_COREP/+1.8VP/0.9VSP

B+
PJP11
@ JUMP_43X118
1 1
2 2

PR115
0_0603_5%

+5VALWP

1
2

PC77
4.7U_1206_25V6K

1
2

PC76
4.7U_1206_25V6K

1
2
5
6
7
8

PC75
2200P_0402_50V7K

D
D
D
D

G
S
S
S
4
3
2
1

1
2

PD21
@SKS10-04AT_TSMA

1
2

PR123
8.06K_0402_1%

1
2

PR129
0_0603_5%
2
1

+
2

PR126
10K_0402_1%

MAX8743A_ILIM2
MAX8743A_ILIM1

2V
1.936V

PC87
@ 100P_0402_50V8K

SYSON

PC86
4.7U_0805_6.3V6K

5
6
7
8
D
D
D
D
G
S
S
S
4
3
2
1

2
PR124
0_0402_5%

PC147
220U_D2_4VM_R25

VDDA
FB1.8
N56

7
5

PR130
3.3K_0603_1%

22

9
UVP

VCC

PJP13
@ JUMP_43X118

15
14
12

13
3

DH1.8A

PQ55
SI4810BDY_SO8

PR132
100K_0603_1%

PR134
0_0402_5%

PR122
0_0402_5%
D H1.8 1
2
LX1.8
DL1.8

19
18
17
20
16

PR133
100K_0603_1%

OVP

PR131
@ 0_0402_5%

MAX8743A_SKIP

ILIM2
ILIM1

+1.8VP
PL14
4.7UH_PLFC1045P-4R7A_5.5A_30%
1
2

PC80

4
V+ 1U_0603_16V6K
2
1

ON1

+1.8VP

PQ35
SI4800BDY-T1_SO8

21

11

N57

PR125
0_0402_5%

PC89
0.22U_0603_16V7K

PGOOD
TON

1
2

PC88
@ 100P_0402_50V8K

PR127
100K_0402_1%

+DDRVCC

BST2
DH2
LX1
LX2
DL1
DL2
MAX8743EEI_QSOP28 CS2
CS1
OUT1
OUT2
FB2
FB1
ON2

REF

28
1

PR119
0_0402_5%
1
2

PC82
0.1U_0603_25V7K
VDD

DH1

SKIP

27
24

26

BST1

BST1.8

MAX8743A_REF 10

LX1.05
DL1.05

PU8

25

GND

BST1.05

PR118
0_0402_5%
PR121
0_0402_5%
DH1.05A 1
DH1.05
2

MAX8743_VCCA

PC78
4.7U_0805_6.3V6K

MAX8743_VCCA

23

FB1.05

2
1

VR_ON

PR117
20_0603_1%

BST1.8A

PC79
0.1U_0603_25V7K
2
1

PC81
0.1U_0603_25V7K
2
1

PR120
5.1K_0402_1%

1
2

PC84
4.7U_0805_6.3V6K

PC83
220U_D2_4VM

PL8
4.7UH_PLFC1045P-4R7A_5.5A_30%
2
1

PD20
@SKS10-04AT_TSMA

+GMCH_COREP

D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K

8
7
6
5

BST1.05A

1
2
3
4

PQ34
AO4912_SO8
C

MAX8743A_V+

PC74
4.7U_1206_25V6K

PD19
CHP202U_SC70

1
2

PC73
4.7U_1206_25V6K

PC72
4.7U_1206_25V6K

1
2

PC71
2200P_0402_50V7K

MAX8743_B+

PU10
VIN

VCNTL

GND

NC

VREF

NC

VOUT

NC

PC100

TP
VREF0.9

8
9

APL5331KAC-TR_SO8
1

PC104
10U_1206_6.3V7K

PR143
1K_0402_1%

+0.9VSP

PC102
0.1U_0402_16V7K
1

PQ39
2N7002_SOT23

2
G
3

1
PC103
@ 0.1U_0402_16V7K

N55

<40> SUSP

PR142
0_0402_5%
1
2

+3VALW

PR141
1K_0402_1%

10U_1206_6.3V7K

PC101
1U_0603_16V6K

VIN0.9

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size

SCHEMATIC, M/B LA-2601


Document Number

R ev
C

401336
Date: , 17, 2005

Sheet
1

46

of

+2.5VSP/+1.5VALWP

B+
PJP17
@ JUMP_43X118
1 1
2 2

PR188
0_0603_5%

+5VALWP

1
2

PC139
4.7U_1206_25V6K

1
2

0.844V
1.936V

MAX8743B_ILIM2
MAX8743B_ILIM1

PR202
137K_0603_1%
2
1

PC85
220U_D2_4VM

+
2

PR203
3.3K_0603_1%

1
SUSP#

1
2
1

2
PR197
0_0402_5%

7
5

FB2.5
N59

PC149
@ 100P_0402_50V8K

15
14
12

13
3

DH2.5A

PR196
15K_0402_1%

19
18
17
20
16

PR199
10K_0402_1%

PR195
0_0402_5%
D H2.5 1
2
LX2.5
DL2.5

ILIM2
ILIM1

21

2
PD29
@SKS10-04AT_TSMA

+2.5VSP

PC148
4.7U_0805_6.3V6K

VDDB

1
2
3
4

PR205
100K_0603_1%

PR206
100K_0603_1%

PR207
0_0402_5%

PR204
@ 0_0402_5%

PC138
4.7U_1206_25V6K

1
2
1
2

MAX8743B_SKIP

G2
D2
D1/S2/K
D2
D1/S2/K
G1
D1/S2/K S1/A

PL7
5UH_SPC-06704-5R0_2.9A_30%

PR192
0_0402_5%
BST2.5 1
2

22 PC142

UVP

ON1

PC151
0.22U_0603_16V7K

11

PR201
@ 0_0402_5%

N58

PGOOD
TON
REF

PR198
0_0402_5%

OVP

+3VALWP

PC150
@ 100P_0402_50V8K

PR200
10K_0402_1%

FB1.5

VDD

BST2
DH2
LX1
LX2
DL1
DL2
MAX8743EEI_QSOP28 CS2
CS1
OUT1
OUT2
FB2
FB1
ON2

10

27
24
28
1

8
7
6
5

PC144
0.1U_0603_25V7K

DH1

1MAX8743B_REF

26

BST1

25

SKIP

D H1.5

BST1.5

VCC

PU13

LX1.5
DL1.5

MAX8743_VCCB

2
1

PC143
0.1U_0603_25V7K
PR194
0_0402_5%
DH1.5A 1
2

4
V+ 1U_0603_16V6K
2
1

PR191
0_0402_5%
2

GND

PQ52
AO4912_SO8

PC140
4.7U_0805_6.3V6K

MAX8743_VCCB

PC141
0.1U_0603_25V7K
2
1

PR190
20_0603_1%

BST2.5A

23

PR193
5.36K_0402_1%

1
2

PC146
4.7U_0805_6.3V6K

PC145
220U_D2_4VM

1
+

8
7
6
5

PL13
4.7UH_PLFC1045P-4R7A_5.5A_30%

+1.5VALWP

PD28
@SKS10-04AT_TSMA

D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K

BST1.5A

1
2
3
4

PQ51
AO4912_SO8

PC137
2200P_0402_50V7K

MAX8743B_V+

PC136
4.7U_1206_25V6K

PD27
CHP202U_SC70

PC135
4.7U_1206_25V6K

1
2

PC134
4.7U_1206_25V6K

1
2

PC133
2200P_0402_50V7K

MAX8743_B++

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size

Document Number

R ev
C

401336
Date:

, 17, 2005

Sheet
1

47

of

CPU CORE
CPU_B+

TIME

FB

15

FB

12

CCV

CCI

14

CCI 1
PC118
BSTS

TON

BSTS

35

REF

DHS

33

D HS

1532ILIM

LXS

34

LXS

CSP

40

C SP
C SN

18

SKIP

CSN

39

11

GND

GNDS

13

PR176
10K_0402_1%

PC108
2200P_0402_50V7K

2
1

PC109
100U_25V_M

2
PR168
0_0603_5%

PL12
0.56UH_MPC1040LR56_23A_20%

909_0402_1%
2
1

2
PC156
680P_0603_50V8J

PR178

2
3
2
1

PR217
4.7_1206_5%

5
6
7
8
4

PQ48
RHU002N06_SOT323

1
3

1
2

PR173
0_0402_5%
2 DH SA

1
3

N61

PC120
0.022U_0603_16V7K
CPU_B+

N 65

2
B

PQ49
HMBT2222A_SOT23

C
N64

2
G

PC107
0.1U_0603_25V7K

5
6
7
8
2

1
<5> PSI#

PR179
0_0402_5%
1
2

N62

1
PC152
4.7U_0805_6.3V6K

1
BSTSA

32

SUS

DLS

PC126
0.1U_0603_25V7K

OFS

1532SUS

3K_0603_1%

+5VS

2
1
PC125
4.7U_1206_25V6K

D LS

2
1
PC124
4.7U_1206_25V6K

1532OFS

PR165

PR175
20K_0402_1%

N60

PD25
CHP202U_SC70
BSTMA
3

PR177
100K_0402_1%

909_0402_1%
2

P D26
SKS30-04AT_TSMA

+5VS

PR163
1

2
470P_0402_50V8J

2
1

PC115

0.47U_0603_16V7K

1532REF

ILIM

PC155
680P_0603_50V8J

PC116
1
2

OAIN-

@1000P_0402_50V7K

OA IN+

16

3K_0603_1%
2

17

OAIN-

499_0603_1%
2
1

OAIN+

SHDN#

CPU VCC SENSE

PR158

S1

499_0603_1%
2
1

PR157

C MN

CMP

38

PR156
909_0402_1%

37

CMN

CMP

S0

+CPU_CORE
PR151
2

0.001_2512_5%

PC123
2200P_0402_50V7K

MAX1532

PR216
4.7_1206_5%

DLM

31

29

PGND

VROK

2
1
PC106
4.7U_1206_25V6K

2
1
PC105
4.7U_1206_25V6K
DLM

LXM
P D24
SKS30-04AT_TSMA

LXM

27

PL11
0.56UH_MPC1040LR56_23A_20%

PQ41
AO4410_SO8

25

PC122
1
2

1
3

PQ44
RHU002N06_SOT323

1
2

D HM

PC127
2
1

1
PR172
0_0402_5%

PC121
100P_0402_50V8J

1
3

2
G

28

PU11

3
2
1

D5

1532SKIP
D

DHM

DHMA

PR149
0_0402_5%
1
2

2
2.2_0402_5%

5
6
7
8

19

D2

1
PR147

PC119 1

BSTM

0.22U_0603_16V7K

D5

1532CCV

26

PM_DPRSLPVR
<19>

N63 2
G

D4

PR167 100K_0402_1%
PR170
0_0402_5%
1
2
PM_STP_CPU#
<14,19>

20

0.22U_0603_16V7K

D3

D4

270P_0402_50V7K

PR164 200K_0402_1%

PQ43
RHU002N06_SOT323
PR169
10.7K_0402_1%
1
2

FB

PC117 1

36

BSTM

2
PR161
@ 100K_0402_5%
1

21

1532VCC

PR166
78.7K_0402_1%

D3

1532SHDN
30.1K_0402_1%
1532TIME
1

PR162
2

V+

D1

PR159
0_0402_5%
2

<33,46> VR_ON

22

1532VROK

D0

PQ45
AO4408_SO8

D2

27P_0402_50V8J

23

PQ46
AO4410_SO8

<6,14,19> VGATE

24

D1

PQ40
AO4408_SO8

3
2
1

<5> CPU_VID5

30

5
6
7
8

<5> CPU_VID4

D0

3
2
1

<5> CPU_VID3

VDD

0.22U_0603_16V7K

<5> CPU_VID2

VCC

2
PR171
2.2_0402_5%

<5> CPU_VID1

10

<5> CPU_VID0

0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2

BSTMA
PC114
2
1

PC113
2
1

1
PR145
1
PR146
1
PR148
1
PR150
1
PR152
1
PR153
1
PR154
1

0.01U_0402_25V7Z

PC111
2.2U_0603_6.3V4Z

B+

1532VCC

PC112
1U_0603_16V6K

PL15
FBM-L18-453215-900LMA90T_1812

PR160
1

PR144 10_0402_5%
2
1

+5VS

PC128
0.47U_0603_16V7K

PR180 909_0402_1%
1
2

PC153
1

1000P_0402_50V7K
2

OA IN+

PC154
1

1000P_0402_50V7K
2

OA IN+

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size
Document Number
C ustom

R ev
C

401336

D ate:

P , 17, 2005

Sheet
1

48

of

OTP

PH1 under CPU botten side :


CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

<18,42,45> MAINPWON
1

PH1
10KB_0603_1%_TH11-3H103FT

VL

N 71

2
1

PR181
47K_0402_1%
1
2

PR215
47K_0402_1%

PR187
100K_0402_1%

PU14A

OTP

LM393M_SO8

2N7002_SOT23
PQ56

2
G

PR185
100K_0402_1%
PR214
2.74K_0603_1%

VL

8
OTPREF2

OTPFB2

PR184
16.9K_0402_1%
1
2

PC132
0.22U_0603_16V7K

PR183
0_0402_5%
N72

PC130
0.1U_0603_25V7K

CPU

VS

VL

PC131
1000P_0402_50V7K
VS

PU14B

LM393M_SO8

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

SCHEMATIC, M/B LA-2601


Size

Document Number

R ev

401336

D ate: P , 17, 2005

Sheet
D

49

of

Version change list (P.I.R. List)


Item

Reason for change

Power section
PG#

Page 1 of 2

Modify List

Date

B.Ver#

Change DC JAck and second battery connect.

42,44

Change DC JAck from DC231105200 to DC231000500.


Change second battery connect from

2004.10.28

Modify OTP schematic.

45,49

Change
Change
Change
Change
Change
Delete

2004.11.30

To increase the pre-charge current.

42

Change PR21 from 169K_0603_1% to 200K_0603_1%;


Change PR10 from 47_1206_5% to 33_1206_5%;
Change PR9,PR11 and PR13 from 1.5K_1206_5%
to 1K_1206_5%.

2004.12.28

Change OTP schematic to EVT design.

49

Change PR183 from 1.37K_0402_1% to 0_0402_5%;


Change PR184 from 10K_0402_1% to 16.9K_0402_1%;
Change PC132 from 1U_0603_16V to 0.22u_0603_16V;
Add PR215 47K_0402_1%;
Add PR214 2.74K_0603_1%;
Add PU14 LM393 and PQ56 2N7002.

2005.01.05

PR114 from 47K_0402_5% to 806K_0603_1%;


PR183 from 0_0402_5% to 1.37K_0402_1%;
PR184 from 16.9K_0402_1% to 10K_0402_1%;
PC132 from 0.22u_0603_16V to 1U_0603_16V;
PC70 from 0.047uF to 0.47uF;
PR186, PR182, PU12 and PQ50.

For EMI request.

48

Add PR216 and PR217, 4.7_1206_5%;


Add P155 and PC156, 680P_0603_50V;
Add PL15, FBM-L18-453215-900LMA90T.

2005.01.10

To increase 1.5V power plan to 1.57V by H/W request.

47

Delete PR201;
Add PR200 10K_0402_1%;
Add PR193 5.36K_0402_1%.

2005.01.10

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size

B
Date:

Document Number

Rev

401336
, 17, 2005

Sheet
1

50

of

EAT10 PIR List


********** Rev:0.2 PIR List

2004/08/10 Writer by Jason **********

P05 : Add @ in R63


Del @ in R56
D

P06Del @ in R54
Del JP9

P18: New add R512


P21 : New add R513
New add X3
New add C607
P21 : New add R534, R535

Compal Electronics, Inc.


Title

SCHEMATIC, M/B LA-2601


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size

Document Number

R ev
C

401336
D ate:

P , 17, 2005

Sheet
1

51

of

51