Hardware Description Language (HDL) Introduction to HDL

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In electronics a HDL is a language from a class of computer language for formal description of electronic circuit. It can describe circuit operation, its design and tests to verify its operation at any level VHDL and VERILOG are popular HDL’s

Hardware Description Language (HDL) ► The automatic translation of design description into a set of logic equation is performed by HDL HDL are used to describe the architecture and behavior of discrete electronic system HDL are programming language that have been designed and optimized for digital circuit design and modeling. ► ► .

► ► ► ► ► . Increase flexibility to design changes. allow you to test architecture and design decision.they are: ► We can verify design functionality early in the design written as an HDL description. Better and easier design auditing and verification. Reduced non-recurring engineering costs.Advantages of Hardware Description Language (HDL) HDL’s has several advantages over traditional design methodology . Design reused is enabled. Design simulation at this higher level before implementation at gate level.

Introduction to VHDL ► Very High Speed Integrated Circuit (VHSIC) HDL (VHDL) was developed by US army in 1982. VHDL allows the behavior of complex electronics circuits to be captured into a design system for automatic circuit synthesis or for system simulation. One of the most important applications of VHDL is to capture the performance specification for circuit. ► ► ► ► . VHDL has many features appropriate for describing the behavior of electronic components ranging from simple logic gates to complete microprocessors and custom chips. VHDL is a programming language for describing the behavior of digital systems.

In VHDL. design is target independent. Each design element has a precise behavioral specification useful for simulating it. In VHDL. Each design element has a well defined interface useful for connecting it to other elements.Features of VHDL ► ► ► ► ► ► ► ► ► VHDL has powerful constructs. . VHDL handles asynchronous as well as synchronous sequential circuits. The language is not case sensitive. timing and clocking can be modeled. In VHDL. VHDL supports design library. design may be decomposed hierarchically.

architectures. a package declaration or a package body declaration. you write them into design file One or more design units make up a design file A design unit may be an entity declaration. Secondary Units a) Architecture body 2007) (May . A design library is an implementation dependent storage facility for previously analyzed design units. When you write VHDL description.Library ► ► ► ► ► ► Library is basically a subdirectory in the host environment for compiled entities. a configuration declaration. primary unit a) entity declaration b) configuration declaration c) package declaration 2. an architecture body. packages and configurations. Library units fall into two categories: 1.

Library Clause ► ► ► ► ► ► ► ► A library clause defines logical names for design libraries in the host environment A set of utility packages can be put inside the library. In such a cases. we need to type the “library” and “use” statement before that design unit. In many situations we need to see multivalued logic to represent don’t care values and tristate buses. . For using a library for a design unit. The keyword ALL causes all definitions in the std_logic_1164 packages to be used The syntax for library clause is library LIBRARY_NAME. it is recommended that one should use a package called std_logic_1164 from the IEEE library. The present working directory is identified by the keyword ‘WORK’ A package name STANDARD containing some basic definitions is automatically included in every program.

.Library Clause ► The syntax for library clause is library LIBRARY_NAME.ALL.PACKAGE NAME <list of definitions> Example: library IEEE. use IEEE.STD_LOGIC_1164. use LIBRARY_NAME.

packages and configuration) will be placed after they are analyzed. architectures.The work Library ► work is the default name of the current library. Unlike simulation environments. ► ► . The work library is where. the VHDL synthesizer only considers design units that are currently being compiled to be in the work library. in a simulation system. all of your design units( entities. unless you have specified an alternative library.

use library_name. use library_name.package_name.all.package_name. then the item clause should be substituted by the reserved word all. The syntax of use clause is: use library_name. . If a designer wants to have all declarations in a package visible.item.USE Clause ► ► ► The use clause makes visible item specified as suffixes in selected names listed in the clause.package_name.

► Example 2.STD_LOGIC_1164.STD_ULOGIC. The function uses the type STD_ULOGIC.STD_LOGIC_1164. use IEEE.USE Clause ► Example 1. therefore declaration of this type is also made visible . use IEEE.STD_LOGIC_1164.ALL. library IEEE. ► ► In the first example all the declarations specified in st_logic_1164(which belongs to the library IEEE) have been made visible. library IEEE.RISING_EDGE. The second example makes visible the RISING_EDGE function which is declare in same package. use IEEE.

the declaration and the body. including local types and subprogram implementations. You can collect constant. . Package body : holds private information. including constant. type and subprogram declarations. data types.Packages ► ► A package is a collection of declarations that more than one design can use. ► ► Package Declaration: Holds public information. Package structure: Packages have two parts. and subprograms into a VHDL package that can then be used by more than one design or entity. component declarations.

Package declarations: ► ► ► ► ► Package declaration defines the interface to a package. The syntax of package declaration is: package package_name is { use clause ( to include other package) type declaration subtype declaration constant declaration signal declaration subprogram declaration component declaration } end [package_name] . Package declarations collect information that is needed by one or more entities in a design. This information includes data type declaration. signal declarations. subprogram declarations and components declarations. Signal declared in packages cannot be shared across entities.

implementation of subprograms declared in the package declaration and internal support programs The syntax of package body is package body package_name is { use clause subprogram declaration subtype declaration type declaration constant declaration} end [package_name] . A package body includes.Package body: ► ► ► A package body is the bodies of subprograms and the values of constant declared in the package.

In large design.from the perspective of its input and output interfaces The second part of the minimal VHDL design description is the architecture declaration The architecture describes the actual function of the entity to which it bound ► ► ► ► ► .Structure of VHDL program: ► Every VHDL program consists of at least one entity/architecture pair Combination of an entity and its corresponding architecture is referred as a design entity. you will typically write many entities/architecture pairs and connect them together to form a complete circuit. An entity declaration describes the circuit as it appears from the “outside”.

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