DAC 2009 SystemVerilog-2009 Presentation

by Sunburst Design, Beaverton, Oregon, © 2009

5 of 59

The SystemVerilog Mantis Database
• The Mantis database contains corrections, clarifications & enhancement descriptions for SystemVerilog-2009 • www.eda.org/svdb
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• Mantis Item numbers are noted on appropriate slides • Mantis items details can be viewed in the Mantis database
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890
© 2009, Sunburst Design, Inc.

Scheduling of New SV Commands
Mantis 890
From Fromprevious previous time timeslot slot #1step #1step Preponed Preponed Region Region for for new new SV SV commands commands

6 of 59

Active Active Inactive Inactive Active Active region region set set Evaluate Evaluate concurrent concurrent assertions assertions Trigger Trigger clocking clocking blocks blocks Reactive Reactive region region set set Execute Execute pass/fail pass/fail assertion assertion code code program program block block code code

Used Usedfor forsampling sampling& & verifying verifyingDUT DUToutputs outputs
(testbench (testbenchinputs) inputs)

NBA NBA Observed Observed

Regions Regions for for new new SV SV commands commands

Reactive Reactive Re-Inactive Re-Inactive

Update to IEEE1800-2005 Standard

Re-NBA Re-NBA

New Newevent eventscheduling scheduling
© 2009, Sunburst Design, Inc.

(already (alreadyimplemented) implemented)

Postponed Postponed

To Tonext next time timeslot slot
Sunburst

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Rev 1.1

DAC 2009 SystemVerilog-2009 Presentation
by Sunburst Design, Beaverton, Oregon, © 2009

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SystemVerilog-2009 Display Enhancements

© 2009, Sunburst Design, Inc.

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Field Widths in Print Formats
Mantis 1175
program print; int a, b; initial repeat (8) begin ... randcase 3: a = 2: a = 2: a = 2: a = endcase randcase 1: b = 2: b = 2: b = 1: b = endcase $urandom_range( 5'h10); $urandom_range( 9'h100); $urandom_range(13'h1000); $urandom_range(17'h10000);

$display("a=%h
end endprogram
$display

b=%h", a, b);

$urandom_range( 5'h10); $urandom_range( 9'h100); $urandom_range(13'h1000); $urandom_range(17'h10000);
$display

Show Show all all leading leading 0's 0's
$display

("a=%h

b=%h" , a, b);
b=000000fb b=00000048 b=000000f4 b=00000860 b=0000003a b=00004895 b=0000007c b=000000da

("a=%0h

b=%0h" , a, b);

("a=%4h

b=%4h" , a, b);
a=71ec a=0003 a=0ed4 a=8fbb a=0003 a=00b1 a=0010 a=097a b=00fb b=0048 b=00f4 b=0860 b=003a b=4895 b=007c b=00da

a=000071ec a=00000003 a=00000ed4 a=00008fbb a=00000003 a=000000b1 a=00000010 a=0000097a

a=71ec b=fb a=3 b=48 a=ed4 b=f4 a=8fbb b=860 a=3 b=3a a=b1 b=4895 a=10 b=7c a=97a b=da

Remove Remove leading leading 0's (ragged display) display) 0's (ragged

4-character 4-character field field with with leading leading 0's 0's
(orderly (orderly display) display)

© 2009, Sunburst Design, Inc.

4 of 30

Rev 1.1

. Inc. im: 187} b='{re: 182. logic [7:0] im. b). assign sum = add(a. endmodule $monitor("sum=%4p $monitor("sum=%4p a=%4p a=%4p b=%4p b=%4p ". endmodule Sized Sizedformat format specifier specifier%4p %4pfor for orderly orderlyprinting printing initial $monitor(. Sunburst Design. b. Same Sameorderly orderlyprintout printout a=71ec a=0003 a=0ed4 a=8fbb a=0003 a=00b1 a=0010 a=097a b=00fb b=0048 b=00f4 b=0860 b=003a b=4895 b=007c b=00da %x %xis isjust just"syntactic "syntacticsugar" sugar" (C-like (C-like. end cplx_adder u1 (. $urandom_range(13'h1000). typedef struct { logic [7:0] re. im: 92} b='{re: 20. a.*). 180. input complex_s a. $display("a=%4x end endprogram b=%4x". randcase 3: a = 2: a = 2: a = 2: a = endcase randcase 1: b = 2: b = 2: b = 1: b = endcase $urandom_range( 5'h10). } complex_s. b). initial begin clk <= '0. b. module structprint. logic clk. 218.. im: x} b='{re: 23. sum. a. Beaverton.-not notreally reallyneeded) needed) © 2009.. int a.. sum.1 . im: 148} a='{re: 138. im: 41} b='{re: x.. $urandom_range( 9'h100). im: 80} b='{re: 72. endpackage import complex::*. b). sum. ". %x %xis isaasynonym synonymfor for%h %h initial repeat (8) begin .). im: 160} a='{re: 108. 216. im: 219} © 2009.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. 5 of 30 Rev 1. im: x} a='{re: 193. . $urandom_range(17'h10000). b). 158. © 2009 9 of 59 Print Format Specifier %x Mantis 1749 program print. sum='{re: sum='{re: sum='{re: sum='{re: sum='{re: x. im: 154} a='{re: 36. 10 of 59 Print Format Specifier %p (%4p) Mantis 331 package complex. $urandom_range(13'h1000). $urandom_range( 5'h10). Sunburst Design. complex_s a. b).. . module cplx_adder ( output complex_s sum. forever #(`CYCLE/2) clk = ~clk. $urandom_range(17'h10000). im: x} im: 240} im: 85} im: 240} im: 4} a='{re: x. $urandom_range( 9'h100). Inc... Oregon. a.

string s. int a = 32. exp). (Proposed synonym for $sformatf ) 12 of 59 $fatal/$error/$warning/$info Display Tasks Mantis 1641 module tb. $display("%s". $display("%s". s). exp=%h".. In InSystemVerilog2009 SystemVerilog2009 function void check_output. y. exp). int a = 32.. logic [31:0] b = 32'haabbccdd.y===exp) $display("PASS: y=%h else $display("FAIL: y=%h endfunction . Sunburst Design. y.. Sunburst Design. string s. Output Outputdisplay display end endmodule The value of b = 32'haabbccdd module test2. exp).. $fatal $fatal/ /$error $error/ /$warning $warning/ /$info $info could couldonly onlybe beused usedin inassertions assertions In InSystemVerilog2005 SystemVerilog2005 function void check_output. y. Beaverton. $fatal $fatal/ /$error $error/ /$warning $warning/ /$info $info can canbe beused usedanywhere anywhere$display $displaycan canbe beused used exp=%h". Inc. endmodule module tb. Inc. SystemVerilog2009 SystemVerilog2009adds adds $sformatf $sformatffunction function that thatreturns returnsaastring string initial begin s = $sformatf("\nThe value of b = %0d'h%h\n". exp=%h".. logic [31:0] b = 32'haabbccdd. . Oregon. a.y===exp) $info ("PASS: y=%h else $fatal("FAIL: y=%h endfunction . a.. exp). exp=%h". endmodule © 2009. Mantis Mantis1651: 1651: end $psprintf was $psprintf wasrejected rejected endmodule (Proposed synonym for $sformatf ) © 2009. b).. SystemVerilog2005 SystemVerilog2005 $sformat $sformattask taskassigns assigns string )) stringto tooutput outputargument argument(s (s initial begin $sformat(s. s). "\nThe value of b = %0d'h%h\n". if (cb1. b). 6 of 30 Rev 1. © 2009 11 of 59 $sformatf Returns a Formatted String Mantis 1589 & 1651 module test1.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design.1 . if (cb1.. y. .

Sunburst Design.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. Inc. input bit_t d. 7 of 30 Rev 1. © 2009 13 of 59 SystemVerilog-2009 Design Enhancements © 2009. always_ff @(posedge clk. Sunburst Design.1 . clk. negedge rst_n) if (!rst_n) q <= 0. Inc. 14 of 59 always_ff Logic-Specific Process • always_ff – Conveys designer's intent to infer clocked logic module dff1 ( output bit_t q. else q <= d. endmodule Correct Correctsensitivity sensitivity list list © 2009. Beaverton. rst_n). Oregon.

name 8 of 30 Rev 1. input bit_t d. endmodule Equivalent Equivalentto toboth both posedge / negedge posedge / negedge No )) Noposedge posedge(clk (clk No negedge ( clk ) No negedge (clk) Remove Removeposedge posedgeto topermit permit triggering on both triggering on bothedges edges ?? ?? always_ff always_ffshows shows designer's designer'sintent intent always_ff @(edge clk.name .name Instantiation & Unconnected Ports Mantis 1660 SystemVerilog-2009 SystemVerilog-2009 clarification clarification alu_accum.name . Inc. Sunburst 16 of 59 .For DDR Logic Mantis 2396 • SV2009 adds edge keyword Currently Currentlyillegal illegalsyntax syntax for forsynthesis synthesis module ddrff ( output bit_t q. Inc. © 2009 15 of 59 Edge Event . Sunburst Design.nameallows allowsunconnected unconnected ports portsto tobe beomitted omitted clk rst_n dataout[15:8] 8 dataout[7:0] 16 dataout © 2009. negedge rst_n) if (!rst_n) q <= 0. Sunburst Design.1 .DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design.v alu_accum. Beaverton. clk. Not Notthe theoriginal original intent intentfor for.v ain 8 bin 8 opcode[2:0] 3 alu (8-bit) alu_out[7] alu_out 1 8 1 1 zero ones 8 xtend accum 8 Dangling Dangling zero zero & & ones ones outputs outputs . Oregon. rst_n). negedge rst_n) Could Couldthis thissynthesize synthesizeto toaaDDR DDRflip-flop flip-flop in inan anASIC ASICvendor vendorlibrary library?? ?? © 2009. always_ff @(clk. else q <= d.

Legal ): Legal(but (butnot notrequired required ): list unconnected ports list unconnected ports alu alu (. . omit omitunconnected unconnectedports ports alu alu (.dataout(dataout[7:0]). ..alu_out.rst_n). 3'b110: y[a]=1. Sunburst Design. input logic [1:0] a. input logic en). endmodule . .rst_n)... xtend xtend (. )) omit omitdesign designport port(alu_out (alu_out alu alu (. .datain(alu_out).name Instantiation & Unconnected Ports Mantis 1660 module alu_accum ( output [15:0] dataout. rst_n). .datain(alu_out). Beaverton.opcode). .a}) 3'b100: y[a]=1.ain. bin. .clk. . .1 . .zero().ain. .rst_n).dataout(dataout[7:0]).opcode). unique case ({en.clk.one(). input [2:0] opcode.. © 2009 17 of 59 .name 18 of 59 2-to-4 Decoder w/ Enable SystemVerilog-2005 Style module dec2_4a ( output logic [3:0] y. .alu_out. © 2009. . .clk.rst_n).din(alu_out[7]).. Legal ): Legal(but (butWRONG! WRONG! ): Another Anothergood goodreason reasonto toavoid avoidusing using.name . Sunburst Design.datain(alu_out). 9 of 30 Rev 1.bin. endcase end endmodule unique unique case case with withinitial initialdefault default assignment assignment ============================ | Line | full/parallel | ============================ | # | user/user | ============================ unique unique Same Sameas asfull_case full_case parallel_case parallel_case SystemVerilog SystemVerilog simulators simulators are are required required to en=0 to give give a a run-time run-time warning warning when when en=0 parallel_case parallel_case (uniqueness) (uniqueness) full_case full_case all allpossible possiblecases casesare aredefined defined (others are "don't (others are "don'tcares") cares") unique unique means: means: (1) case expression (1) case expressioncan canonly onlymatch match11case caseitem item (2) (2)case caseexpression expressionMUST MUSTmatch match11case caseitem item © 2009. accum accum (. ..bin.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design.bin. . . Inc. accum accum (. wire [7:0] alu_out. .opcode).ain. .dout(dataout[15:8]).. accum accum (. Oregon. . 3'b101: y[a]=1. 3'b111: y[a]=1. . input clk. Inc.dataout(dataout[7:0]). . input [7:0] ain. Legal: Legal: . . always_comb begin y = 0..clk. .

3'b110: y[a]=1. Sunburst Design. 20 of 59 2-to-4 Decoder w/ Enable SystemVerilog-2005 Current Work-Around module dec2_4b ( output logic [3:0] y. Oregon. input logic [1:0] a. unique case ({en. input logic en). 3'b111: y[a]=1. 10 of 30 Rev 1.a}) 3'b100: y[a]=1. © 2009 19 of 59 2-to-4 Decoder with Enable WRONG Synthesis Results! Dangling Danglingenable! enable! en unique uniquecase case dec2_4a dec2_4a unique unique infers infersthe the wrong wronglogic logic SystemVerilog SystemVerilogsimulation simulation should shouldwarn warnabout aboutthis thiserror error y[3] y[2] y[1] a[1] a[0] y[0] © 2009.but butfixes fixesthe the synthesis synthesisresults results © 2009.1 . Ugly. Inc. 3'b101: y[a]=1. always_comb begin y = 0. Sunburst Design. endcase end endmodule unique unique case case with withinitial initialdefault default assignment assignment ============================ | Line | full/parallel | ============================ | # | auto/user | ============================ unique unique with withempty emptydefault default same sameas asparallel_case parallel_case Empty Emptydefault default kills killsfull_case full_case Ugly. default: . Beaverton.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. Inc.

a}) 3'b100: y[a]=1. 11 of 30 Rev 1. unique0 case ({en. 3'b111: y[a]=1. input logic [1:0] a. NOT NOTfull_case full_case (others (otherscovered coveredby byinitial initial default defaultassignment) assignment) 22 of 59 2-to-4 Decoder with Enable Correct Synthesis Results a[1] SystemVerilog SystemVerilog dec2_4b dec2_4b dec2_4c dec2_4c a[0] en y[3] y[2] y[1] y[0] © 2009. © 2009 21 of 59 Unique0 . 3'b110: y[a]=1. input logic en). Beaverton.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design.1 . Inc. endcase end endmodule unique0 unique0 case case with withinitial initialdefault default assignment assignment ============================ | Line | full/parallel | ============================ | # | auto/user | ============================ unique0 unique0 same sameas as parallel_case parallel_case Simulation Simulation is is correct correct when when en=0 en=0 parallel_case parallel_case (uniqueness) (uniqueness) unique0 unique0 means: means: (1) case expression (1) case expressioncan canonly onlymatch match11case caseitem item (2) (2)case caseexpression expressioncan canmatch match11or or00case caseitems items © 2009. Sunburst Design. Oregon.parallel_case Equivalent Mantis 2131 module dec2_4c ( output logic [3:0] y. Inc. 3'b101: y[a]=1. always_comb begin y = 0. Sunburst Design.

end © 2009. endmodule module register ( output logic [7:0] input logic [7:0] input logic input logic New Newversion versionof of Old Oldversion versionof of Default Defaultvalues valuesmight mightbe beuseful useful for forinfrequently infrequentlyused usedinputs inputs Default Defaultvalues valuesonly onlylegal legal with withANSI-style ANSI-styleport portlist list q. else q <= d. Inc. negedge rst_n. rst_n). negedge set_n) if (!rst_n) q <= '0. (vendors (vendorsdid didnot notwant want to toreport reportfalse-errors) false-errors) Reported Reportedas asviolations violations Ask Askvendors vendorsto toprovide provide fatal-on-violation fatal-on-violationoption option Simulation Simulationscenario: scenario: (1) (1)a agoes goesto to1 1 (2) ) )triggers (2)always_comb always_comb(a1 (a1 triggers (3) (3)unique uniquecase casedetects detectsviolation violation (a )) (a& &not_a not_aboth bothmatch match1'b1 1'b1 (4) violation report generated (4) violation report generated (scheduled (scheduledinto intoObserved ObservedRegion) Region) (5) ) )triggers (5)always_comb always_comb(a2 (a2 triggers (6) (6)not_a not_agoes goesto to0 0 (7) ) )re-triggers (7)always_comb always_comb(a1 (a1 re-triggers (8) unique case detects (8) unique case detectsNO NOviolation violation (9) (9)violation violationreport reportcleared cleared (before (beforeentering enteringObserved ObservedRegion) Region) 24 of 59 Default Inputs For Module/Interface Ports Mantis 2399 (Corrects Mantis1619 Enhancement) register module register ( registermodule module output logic [7:0] q. negedge rst_n) if (!rst_n) q <= '0. else if (!set_n) q <= '1. Inc. © 2009 23 of 59 priority/unique/unique0 Violations Mantis 2008 Reported Reportedas aswarnings warnings • SV-2005: priority/unique warnings • SV-2009: priority/unique/unique0 violations unique : :Only unique Onlyone onecase case item itemshould shouldmatch matchthe the case caseexpression expression always_comb begin: a1 unique case (1’b1) a : z = b. input logic clk. CAUTION: else q <= d. clk. set_n='1 ). d. Sunburst Design. CAUTION:instantiation instantiationrules rules can endmodule canbe beconfusing confusing 12 of 30 Rev 1. register registermodule module with withset_n set_ninput input New Newinput inputhas has aadefault defaultvalue value © 2009. rst_n. input logic [7:0] d. Oregon. endcase end always_comb begin: a2 not_a = !a. Beaverton.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. Sunburst Design. always_ff @(posedge clk.1 . not_a : z = c. always_ff @(posedge clk.

d(d).clk(clk). set_n. . . .rst_n(rst_n). . . . . rst_n. // register . register register keeps keeps default default set_n set_n // rst_n rst_n values values tb tb only only overrides overrides default rst_n value value default rst_n CAUTION: CAUTION:this thiscan canbe beconfusing confusing register r1 (. . .clk.rst_n). .. register r1 (.set_n)). . input logic set_n='1 ). rst_n. set_n endmodule set_nand andrst_n rst_ninputs inputs have havedefault defaultvalues values module tb. .d(d). logic [7:0] logic [7:0] set_n logic set_n assigned logic assigned declared declared q.rst_n(rst_n). register registerinstantiation instantiation endmodule register r1 (. . input logic [7:0] d. tb tb only only overrides overrides default rst_n value value default rst_n register r1 (.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. . .clk(clk).clk.*). . Sunburst Design. © 2009.rst_n. input logic rst_n='1 . clk.q.rst_n(rst_n)). register registerinstantiation instantiation endmodule register r1 (. Inc. .d. clk.d. input logic [7:0] d.set_n(set_n)).d(d). .rst_n)..clk. d. set_n endmodule set_nand andrst_n rst_ninputs inputs have havedefault defaultvalues values module tb.clk(clk).. ERROR: ERROR: set_n set_n not not declared declared in in tb tb 13 of 30 Rev 1.q(q). © 2009 25 of 59 Default Inputs For Module/Interface Ports Mantis 2399 (Corrects Mantis1619 Enhancement) set_n set_n/ /rst_n rst_n module register ( output logic [7:0] q.q(q). Beaverton. input logic clk. register r1 (.q.d.rst_n. tb tb overrides overrides default default set_n set_n // rst_n rst_n values values register r1 (. 26 of 59 Default Inputs For Module/Interface Ports Mantis 2399 (Corrects Mantis1619 Enhancement) set_n set_nNOT NOT module register ( output logic [7:0] q. logic [7:0] logic [7:0] logic logic both bothdeclared declared q. .. tb tb overrides overrides default default set_n set_n // rst_n rst_n values values register r1 (. Inc. . © 2009.d.set_n).1 . assign set_n = d[7]. d. .set_n(.q(q). . Oregon. . . . register r1 (.q(q). .clk(clk). ..d(d). input logic set_n='1 ). .clk. .. input logic clk...rst_n(rst_n)). Sunburst Design. .q.q.set_n). input logic rst_n='1 . // register .

Oregon. Inc. logic [2:0] y.-to toreference referenceaapart part select selecton onthe theLHS LHSexpression expression Might Mightrequire require extra extracode code © 2009. assign y = tmp[4:2]. Inc. assign y . endmodule SystemVerilog-2009 SystemVerilog-2009 allows allowsbit bitand andpart partselects selects on onRHS RHSconcatenations concatenations NOTE: concatenation }}braces NOTE:{{ concatenation braces are arerequired requiredto todo doaapart partselect select on the result of the expression on the result of the expression CAUTION: CAUTION:more moreconcise concisebut but perhaps perhapsmore moreconfusing(?) confusing(?) = {(a & b) | c}[4:2]. Sunburst Design. logic [7:0] tmp.. Sunburst Design. logic [2:0] y. . endmodule Correction Correctionto toDAC2009 DAC2009 presentation presentation module expr_range.1 . b. c. logic [7:0] a.. Compiler Directives © 2009. Parameters. 14 of 30 Rev 1.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. Beaverton. Verilog Verilogonly onlyallows allowsbit bit and andpart partselects selectsof of nets and variables nets and variables ILLEGAL ILLEGAL. c. assign tmp = (a & b) | c. b.. 28 of 59 SystemVerilog-2009 Packages. © 2009 27 of 59 Bit Selects & Part Selects of Expressions Mantis 1197 module expr_range.. logic [7:0] a.

Sunburst Design...somewhat somewhatverbose verbose © 2009. endpackage package bit_pkg.. Inc. rst_n). ...DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. . import bit_pkg::rst_t. 15 of 30 Rev 1. endmodule ( q.. Sunburst Design... endmodule q. endpackage import data_pkg::*. . typedef logic clk_t. module register output data_t input data_t input clk_t input rst_t . endpackage module register ( output data_pkg::data_t input data_pkg::data_t input data_pkg::clk_t input bit_pkg::rst_t . d. Inc. typedef logic clk_t. d.packages packageshave havebeen beenimported imported into /$root intothe the$unit $unit /$rootspace space (depending (dependingupon uponthe thesimulator) simulator) © 2009. typedef bit rst_t... typedef logic [7:0] data_t. 30 of 59 Package Import in Design Element Header Mantis 329 SystemVerilog-2005 SystemVerilog-2005 package packageusage usagestyle style#2 #2 Declare Declarethe thedata_pkg data_pkg and andbit_pkg bit_pkg bit_pkg::clk_t bit_pkg::clk_t not notused used Use Usethe thedata_t data_tand andclk_t clk_t from fromthe thedata_pkg data_pkg Use Usethe therst_t rst_tfrom from the thebit_pkg bit_pkg package data_pkg. clk.. typedef bit clk_t. rst_n).1 . typedef bit clk_t. typedef bit rst_t. clk. typedef logic [7:0] data_t.. endpackage package bit_pkg. Oregon. Use Usethe thedata_t data_tand andclk_t clk_t from fromthe thedata_pkg data_pkg Use Usethe therst_t rst_tfrom from the thebit_pkg bit_pkg . Beaverton. © 2009 29 of 59 Package Import in Design Element Header Mantis 329 SystemVerilog-2005 SystemVerilog-2005 package packageusage usagestyle style#1 #1 Declare Declarethe thedata_pkg data_pkg and bit_pkg and bit_pkg bit_pkg::clk_t bit_pkg::clk_t not notused used package data_pkg.

typedef bit rst_t. data_t fld5. typedef struct packed { src1_t fld1. input rst_t rst_n).Export in a Package Mantis 1323 package pkg1. localpackage packagedeclarations declarationsin inmodule module interface interfaceand andprogram programheaders headers Declare Declarethe thedata_pkg data_pkg and bit_pkg and bit_pkg bit_pkg::clk_t bit_pkg::clk_t not notused used Packages Packagesare areavailable available to tothe themodule moduleheader header Use Usethe thedata_t data_tand andclk_t clk_t from fromthe thedata_pkg data_pkg Use Usethe therst_t rst_tfrom from the thebit_pkg bit_pkg module register import bit_pkg::rst_t.1 . endpackage SystemVerilog-2005 SystemVerilog-2005did didnot notpermit permit package import packagenesting/ nesting/ import [2:0] src1_t. } pkt_t. typedef logic typedef logic typedef logic typedef struct src1_t fld1.. dst1_t fld2. input logic rst_n). typedef logic [7:0] data_t. .re-declaration re-declarationof ofsrc1_t src1_t and anddst1_t dst1_twas wasrequired required import importand anduse usethe the expanded expandedpkg2a pkg2apackage package © 2009. input pkt_t d. . typedef logic [2:0] dst2_t. Inc. Sunburst Design. 16 of 30 Rev 1. endpackage module register ( output pkt_t q. } pkt_t. endpackage SystemVerilog-2009 SystemVerilog-2009adds addsimport importof of local .DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. dst2_t fld4. import pkg2a::*.... [7:0] data_t. data_t fld3. Oregon. Sunburst Design. input logic clk. used. typedef logic [2:0] src2_t. { package pkg2a. typedef logic clk_t. input data_t d... Beaverton.. typedef bit clk_t. typedef logic [2:0] src1_t. [2:0] dst1_t. typedef logic [2:0] dst1_t. packages packageshave havebeen beenimported imported locally locallyinto intothe theregister registermodule module 32 of 59 Package Chaining . © 2009 31 of 59 Package Import in Design Element Header Mantis 329 package data_pkg. . endpackage package bit_pkg.. Inc. endmodule © 2009. endmodule If Ifused.. src2_t fld3. data_pkg::*. input clk_t clk. (output data_t q. dst1_t fld2. typedef logic [15:0] data_t. .

Beaverton.. Inc. Add Addthe thesrc2_t src2_t endpackage src2_t fld3. and dst2_t types and dst2_t types dst2_t fld4.. . typedef logic [15:0] data_t. Oregon. import pkg3c::*. typedef logic [2:0] dst1_t. endpackage package pkg3c. . Mantis 1323 module register ( output pkt_t q. export *::*. typedef logic [2:0] src1_t. endpackage export exportall allpackages packages (using (usingwildcards) wildcards) Like Likedoing doingpackage package extension extension.. import pkg1::*. import/export the src1_t and } pkt_t. input logic clk. typedef struct packed { data_t fld3. import pkg3d::*. Sunburst Design.. src1_t fld1.. endpackage package pkg3d..Export in a Package SystemVerilog-2009 SystemVerilog-2009allows allows package import /export packagenesting/ nesting/ import /export package pkg1.1 . typedef struct { typedef logic [2:0] dst2_t. .. dst1_t fld2. .DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. . . input pkt_t d..with withmultiple multiple inheritance inheritance!! !! 17 of 30 Rev 1. endpackage import importeach eachpackage package separately separately package pkg4. typedef logic [2:0] src2_t. import pkg2::*.. import pkg3b::*. Inc. } pkt_t. Sunburst Design. anddst1_t dst1_ttypes types endpackage Override Overridethe thedata_t data_t and andpkt_t pkt_ttypes types import importand anduse usethe the expanded expandedpkg2 pkg2package package © 2009. dst1_t fld2. import / export the src1_t data_t fld5. package pkg2. endmodule 34 of 59 Multiple Package Export Mantis 1323 package pkg3a. . src1_t fld1. © 2009 33 of 59 Package Chaining . endpackage package pkg3b.. typedef logic [7:0] data_t.. © 2009.... import pkg3a::byte_t. export pkg1::*.... typedef logic [7:0] byte_t. input logic rst_n).. .

.16) ram1 (. b.re = a. Sunburst Design. .DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. parameter DWIDTH=8) (inout [DWIDTH-1:0] data. Sunburst Design. assign data = (!cs_n && r_wn) ? mem[addr] : 'z..re + b.re..im + b.).re.. Oregon. .1 . . sum.. typedef struct { logic [7:0] re. endmodule Cannot Cannotoverride overridelocalparam localparam Ordered Orderedparameter parameterreplacement replacement omits omitsthe thelocalparam localparamvalue value DEPTH DEPTHnot not listed listed ram raminstantiation: instantiation: AWIDTH=20 AWIDTH=20(1MB) (1MB) DWIDTH=16 DWIDTH=16 © 2009. sum. endfunction endpackage © 2009. 18 of 30 Rev 1. input [AWIDTH-1:0] addr.. Inc. } complex_s. logic [DWIDTH-1:0] mem [DEPTH]. typedef struct { logic [7:0] re. logic [7:0] im. input complex_s a.. always_latch if (!cs_n && !r_wn) mem[addr] <= data. . input r_wn..im = a. cs_n). b. automatic automatic package package . package complex. endfunction endpackage function complex_s add. © 2009 35 of 59 Package Automatic Declarations Mantis 1524 SystemVerilog-2005 SystemVerilog-2005had: had: • •module module automatic automatic • •program program automatic automatic • •interface interface automatic automatic SystemVerilog-2009 SystemVerilog-2009adds: adds: • •package package automatic automatic Normal Normalpackage package .. logic [7:0] im... sum. 36 of 59 Localparams in ANSI-Style Headers Mantis 1134 localparam localparamcan canbe bein in the parameter port the parameter portlist list `timescale 1ns / 1ns module ram #(parameter AWIDTH=10. return(sum).. sum.im = a.. function function complex_s add..im + b.automatic automatic function } complex_s. .re = a.im.static static function function package automatic complex.. Inc.. Beaverton.re + b. ram #(20..im. . input complex_s a. complex_s sum.. complex_s sum. return(sum). localparam DEPTH=1<<AWIDTH.

pipeline #(.sv. endmodule module tb. Sunburst Design.SZ(16)). input logic [SIZE-1:0] d.WIDTH(SZ)) p1 (. .p2. q.map library tbLib tb/*. //. negedge rst_n) if (!rst_n) q <= '0.q({q. Oregon.. ..cfg config rtl. instance tb use (. always_ff @(posedge clk. Inc. endconfig Parameter Parametervalues values before beforeconfig config SZ SZ =12 =12 WIDTH=12 )) WIDTH=12(default (default4 4 SIZE )) SIZE =12 =12(default (default8 8 Parameter Parametervalues values after afterrtl rtlconfig config SZ SZ =16 =16 WIDTH=16 WIDTH=16 SIZE SIZE =16 =16 module pipeline #(WIDTH=4) ( output logic [WIDTH-1:0] q.sv.tb.*). always_ff @(posedge clk) q <= d.p1}).DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. input logic clk). register #(..SIZE(WIDTH)) r[1:3] (. endmodule © 2009.d}). 19 of 30 Rev 1. endmodule File: File:rtl. parameter SIZE = logic [SIZE-1:0] logic [SIZE-1:0] logic Parameter Parametermust mustbe be defined definedwhen whenthe the module moduleis isinstantiated instantiated 64. else q <= d. d. Inc. input logic [SIZE-1:0] d.cfg rtl.*). clk. .p1. parameter SZ = 12. design tbLib. logic [WIDTH-1:0] p1. library rtlLib rtl/*. endmodule module register #(SIZE=8) ( output logic [SIZE-1:0] q.. input logic clk). Beaverton. rst_n. input logic clk. endmodule © 2009. p2. register #(SIZE) r1 (. 38 of 59 Setting Parameters in Configurations Mantis 2037 module tb. © 2009 37 of 59 Blank And Illegal Parameter Defaults Mantis 907 NOTE: NOTE:SIZE SIZEparameter parameternot not assigned assignedaadefault defaultvalue value module register #(SIZE) ( output logic [SIZE-1:0] q.1 . default liblist rtlLib. Sunburst Design. rst_n). More Moreconfig configparameter parameter capabilities capabilitieshave havebeen beenadded added (not (notshown) shown) File: File:lib.d({p2...clk(clk)). .map lib. input logic [WIDTH-1:0] d.

. Use Usedefault defaultclk clk Use Useclk2 clk2 20 of 30 Rev 1.. 40 of 59 Macros with Default Arguments Mantis 1571 • SystemVerilog-2009 permits macros to have arguments with default values By Bydefault.. clk2).1 .macro macrouses usesclk clk for forassertion assertionsampling sampling `define assert_clk(arg. ) \ assert property (@(posedge clk) disable iff (!rst_n) . © 2009 39 of 59 Verilog-95 Macro Capabilities `define CYCLE 100 .DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. Sunburst Design. Sunburst Design.. Inc. forever #(`CYCLE/2) clk = ~clk. ck=clk) \ assert property (@(posedge ck) disable iff (!rst_n) arg) ERROR_q_did_not_follow_d: `assert_clk(q==$past(d)). initial begin clk <= '0. end Line Linecontinuation continuation character character \ \ Define Defineaamulti-line multi-linemacro macro (not all Verilog coders know this) `define assert_clk( . Beaverton. Oregon. ERROR_q_did_not_follow_d: `assert_clk(q==$past(d). ) (not all Verilog coders know this) (every Verilog coder knows this style) (every Verilog coder knows this style) Define Defineand anduse useaamacro macro Pass Passan anargument argumentto to the themacro macro arg arg Define Defineaamulti-line multi-linemacro macro with input with inputarguments arguments (not all Verilog coders know this) (not all Verilog coders know this) `define assert_clk( arg ) \ assert property (@(posedge clk) disable iff (!rst_n) arg ) © 2009. © 2009. Inc. default...

always @* begin if (!rw_n && en) mem[addr] <= data. assign data = (rw_n && en) ? mem[addr] : {`DSIZE{1'bz}}. end endmodule `undef DSIZE `undef ASIZE `undef MDEPTH © 2009. size. Beaverton. input en. input [`ASIZE-1:0] addr. 21 of 30 Rev 1. always_latch begin if (!rw_n && en) mem[addr] <= data. logic [`DSIZE-1:0] mem [0:`MEM_DEPTH-1].1 . Inc. `undef `undefaddress addresssize size `undef `undefmemory memorydepth depth 42 of 59 `undefineall Mantis 1090 `define DSIZE 8 `define ASIZE 10 `define MDEPTH 1024 module ram1 ( inout [`DSIZE-1:0] data. assign data = (rw_n && en) ? mem[addr] : {`DSIZE{1'bz}}. logic [`DSIZE-1:0] mem [0:`MEM_DEPTH-1]. `define `definedata datasize. input [`ASIZE-1:0] addr. Inc.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. size. Sunburst Design. Oregon. `define `defineaddress addresssize size `define `definememory memorydepth depth `undefineall `undefineallun-defines un-defines all all`define `definemacros macros © 2009. © 2009 41 of 59 Verilog `define & `undef `define DSIZE 8 `define ASIZE 10 `define MDEPTH 1024 module ram1 ( inout [`DSIZE-1:0] data. `define `defineaddress addresssize size `define `definememory memorydepth depth `undef `undefdata datasize. size. end endmodule `undefineall `define `definedata datasize. rw_n). Sunburst Design. input en. rw_n).

local localto tothe themodule module module ram1 #(parameter ASIZE=10. Inc. rw_n). always_latch begin if (!rw_n && en) mem[addr] <= data. 22 of 30 Rev 1. input en. localparam MEM_DEPTH = 1<<ASIZE. end endmodule Make Makethe thememory memorydepth depth aalocalparam localparam Calculate Calculatethe thememory memorydepth depth from fromthe theaddress addresssize size © 2009. Sunburst Design. © 2009 43 of 59 SystemVerilog Parameterized Model A Better Solution Consider Considerthis: this: If Ifyou youare areusing using`undefineall `undefineall it itlooks lookslike likeaalocal localconstant constant Declare Declareparameters. assign data = (rw_n && en) ? mem[addr] : {DSIZE{1'bz}}. Oregon. Inc. DSIZE=8) (inout [DSIZE-1:0] data. Sunburst Design. logic [DSIZE-1:0] mem [0:MEM_DEPTH-1].DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. parameters.1 . Guideline: Guideline:choose chooseparameter parameterfirst first Guideline: Guideline:choose choose`define `defineonly onlyif ifneeded needed 44 of 59 SystemVerilog-2009 Arrays & Queues Enhancements © 2009. Beaverton. input [ASIZE-1:0] addr.

$display("%0d ARRAY ELEMENTS %0d"..1 .size()).num()). 1 ARRAY ELEMENTS aa[1234]=aa 9 ARRAY ELEMENTS aa[ 0]=cc aa[ 1]=cc aa[ 2]=cc aa[ 3]=cc aa[ 4]=cc aa[ 5]=cc aa[ 6]=cc aa[ 7]=cc aa[1234]=aa 12 ARRAY ELEMENTS aa[ 0]=cc aa[ 1]=cc aa[ 2]=cc aa[ 3]=cc aa[ 4]=cc aa[ 5]=dd aa[ 6]=cc aa[ 7]=cc aa[ 10]=dd aa[ 15]=dd aa[ 20]=dd aa[1234]=aa module aa2.num()). . Sunburst Design. Beaverton. . i<8. Oregon. Sunburst Design. © 2009 45 of 59 Associative Array Clarifications Mantis 1457 foreach foreachcommand commandworks workswith with non[*] non[*]associative associativearrays arrays byte_t aa [*]. function void aa_display. aa[i]).num()method method 23 of 30 Rev 1. for (int i=5. aa_display. end endmodule SV2009 SV2009clarifies clarifies foreach foreachfails failswith with [*] [*]assoc assocarrays arrays © 2009.size() method – Asosciative arrays: . endfunction function void aa_display.size() .num() . i++) aa[i]=8'hCC. aa_display.num() method Returns Returnsthe thesize sizeof of the thedynamic dynamicarray array Returns Returnsthe thesize sizeof of the thequeue queue Returns Returnsthe thenumber numberof of elements elementsin inthe the associative associativearray array function void aa_display. $display("%0d ARRAY ELEMENTS %0d". i<21. endfunction © 2009. foreach (aa[i]) $display("aa[%4d]=%2". for (int i=0. aa.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. i.synonym synonymfor for . endfunction foreach foreach stores stores each each aa[] aa[] index index in in the the i i variable variable 46 of 59 Associative Array Clarifications Mantis 1723 • SystemVerilog 2005 array types & methods – Dynamic arrays: . i+=5) aa[i]=8'hDD. SV2009 SV2009defines defines . aa. initial begin aa[2143] = 8'hAA.size()method method. typedef bit [7:0] byte_t. Inc... aa_display..size() method – Queues: . aa. $display("%0d ARRAY ELEMENTS %0d". Inc. byte_t aa [int].

bit [7:0] q[$] = '{8'hA0. Sunburst Design.push_back(8'hcc). int q_size. data=q. bit [7:0] data.delete(1).size=%0d".size()).insert(2.pop_back(). Sunburst Design. q. $display $display Initial Initial values values data=8'h00 8'hA0 8'hA1 8'hA2 8'hA0 8'hA1 8'hFF 8'hA2 8'hA0 8'hFF 8'hA2 8'hFF 8'hA2 8'hFF 8'hBB 8'hFF 8'hBB 8'hFF 8'hCC <empty> q. q. 24 of 30 Rev 1.delete() end endprogram No Noargument argument means meansto todelete delete entire entirequeue queue © 2009. Inc. © 2009 47 of 59 Queue Delete Mantis 1560 SV2009 SV2009adds addsaabuilt-in built-inmethod method to todelete deletean anentire entirequeue queue program q_methods. 8'hA1.push_front(8'hbb). 8'hA2}.size=3 initial begin $display("q.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. insert(@2) insert(@2) delete(@1) delete(@1) data=8'hA0 data=8'hA2 push_front push_front push_back push_back New New to to SV2009 SV2009 delete delete entire entire queue queue 48 of 59 SystemVerilog-2009 Classes & Verification Enhancements © 2009. Beaverton. Oregon.8'hff). pop_front pop_front data=q. q. Inc.pop_front(). q.1 . q. pop_back pop_back q.

j<3. end end $display("\n"). for (int j=0. for (int i=0. $write("%3d". i++) begin automatic int loop3 = 0. 25 of 30 Rev 1.initialization initializationhappens happensbefore beforetime time00 automatic automaticvariable variable assignment assignmentexecutes executeseach each time the outer loop time the outer loopis iscalled called Display Display values values 1 2 3 1 2 3 1 2 3 The Thestatic staticvariable variable assignment assignmentexecutes executes once oncebefore beforetime time00 Display Display values values 1 2 3 4 5 6 7 8 9 50 of 59 Pure Virtual Methods Mantis 1308 • pure virtual is an abstract method prototype defined in an abstract class (virtual class) virtual virtualrequires requires • virtual requires: argument compatibility argument compatibility – – – – argument types must match argument directions must match number of arguments must match return types must match pure purecreates createsaaplace-holder place-holder pure purerequires requiresthat thataa method methodbe beoverridden overriddenwith with an anactual actualimplementation implementation • pure requires: – – – – method shall only be a prototype no code can be included for the prototype not even allowed to have endfunction/endtask keywords pure virtual methods MUST be overridden in non-abstract classes © 2009. j<3. j++) begin loop3++. end endmodule © 2009. int svar1 = 1. i<3. for (int j=0. i++) begin static int loop2 = 0. initial begin for (int i=0. loop2). j++) begin loop2++. Sunburst Design.1 . Inc. Beaverton. Oregon. i<3. © 2009 49 of 59 Static Variable In-Line Initialization Mantis 1556 module top. end end $display("\n"). Sunburst Design. loop3). static statickeyword keywordis isoptional optional.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. Inc. $write("%3d".

endfunction Nonblocking Nonblockingassignment assignmentlegal legal in infunction functionwhen whensurrounded surrounded fork / join_none by by fork / join_none endmodule Output Outputdisplay display © 2009. time time(3+3+4=10ns) (3+3+4=10ns) join_none $display("%t: Initial Sequence started". 0ns: Initial Sequence started 1ns: 2nd Sequence started . #3 a=8'h88. Sunburst Design. int b. Inc.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. Inc. $time. $time.1 . $time). b). #3 run."ns". endtask 26 of 30 Rev 1. $time). int a.b=%2h". #1 $display("%t: 2nd Sequence started . fork b <= 8'hcc. a). Beaverton. #4 $display("RUN(%t): a=%2h". initial startup.0.b=cc 2ns: 3rd Sequence started RUN( 10ns): a=88 task run. Oregon. Sunburst Design.6). – Every pure constraint MUST be overridden in non-abstract classes Again: Again: pure purecreates createsaaplace-holder place-holder pure purerequires requiresthat thataa constraint constraintbe beoverridden overridden with withan anactual actualconstraint constraint © 2009. task taskcall callthat thatconsumes consumes #2 $display("%t: 3rd Sequence started". © 2009 51 of 59 Pure Constraint Mantis 2514 • pure constraint is an constraint prototype defined in an abstract class (virtual class) • pure requires: – constraint shall only be a prototype pure constraint constraint-name. functions functionsto tospawn spawnoff off time-consuming time-consumingcode code time-1 time-1 time-2 time-2 time-0 time-0 function void startup. 52 of 59 Allow Functions to Spawn Processes Mantis 1336 fork fork/ /join_none join_noneallows allows module forkprocess. initial $timeformat(-9.

aand andx xvalues valuesto tothe thecovergroup covergroup localvariable variablex=b sampleda property p1. return p + C::p.set set covergroupcg1 cg1(p_cg (p_cg andpass passthe the local sampled x=b . return p + p. Inc.1 . high..C#(5)::f()). 27 of 30 Rev 1. .sample(a. int x).. a. cg1. int x. endfunction SystemVerilog-2009 SystemVerilog-2009adds addsthe the ability abilityto tohave haveparameterized parameterized classes with external methods classes with external methods Declaration Declarationof of extern externstatic staticfunction function(method) (method) with type) withreturn returntype typeT T (parameterized (parameterized type) initial $display(“%0d %0d”.ififc cis ishigh high##1 ##1cycle cyclelater. C#()::f(). coverpoint x. C#()::f(). endproperty c1: cover property (p1).. Whena ais ishigh. x)). x = b) ##1 (c. endclass function int C::f(). 54 of 59 Covergroup Sample Method w/ Arguments Mantis 2149 covergroup covergroupwith withsample sample arguments argumentsa aand andx x covergroup p_cg with function sample(bit a.C#(5)::f()).DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. © 2009. Sunburst Design. Sunburst Design. endfunction Fixed Fixedmethod method return returntype type SystemVerilog-2005 SystemVerilog-2005does doesnot not allow allowaaclass classtype typeto touse useboth both parameters and external methods parameters and external methods Output Outputdisplay display 2 initial $display("%0d %0d".. Beaverton. @(posedge clk)(a. Oregon. endclass function C::T C::f(). extern static function int f(). cross x. 10 class C #(int p = 1. . extern static function T f(). Inc. later.sample samplethe the When covergroup ) )and p_cg cg1 = new. type T = int). © 2009... endgroup .. © 2009 53 of 59 External Methods w/ Parameterized Classes Mantis 1857 class C #(int p = 1)..

input logic clk). Inc.. Combined Combined 1-line 1-line syntax syntax Must Must be be placed placed immediately immediately after after module module header header 100ps/100ps 100ps/100ps local localtimescale timescale always_ff @(posedge clk) q <= #1 d.)... always_ff @(posedge clk) q <= #1 d. endmodule module blka (. endmodule module register ( output logic [7:0] q. input logic [7:0] d. timeprecision 100ps. .. endmodule 1ns/1ns 1ns/1ns timescale timescale again againactive active 28 of 30 Rev 1. Beaverton. Oregon. 2-line 2-line syntax syntax SystemVerilog-2009 SystemVerilog-2009 1ns/1ns 1ns/1ns timescale timescale active active `timescale 1ns/1ns module tb... timeunit 100ps/100ps.. endmodule module register ( output logic [7:0] q.1 . timeunit 100ps. Sunburst Design.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. input logic clk)... 56 of 59 New Concise timeunit Syntax Mantis 1623 SystemVerilog-2005 SystemVerilog-2005 `timescale 1ns/1ns module tb. input logic [7:0] d. Sunburst Design. . © 2009 55 of 59 SystemVerilog-2009 Miscellaneous Enhancements timeunit $system task `__FILE__ & `__LINE__ Macros SDF Annotation of $timeskew & $fullskew © 2009.... Inc. . .). endmodule © 2009. endmodule module blka (.

Inc. 29 of 30 Rev 1. © 2009 57 of 59 $system Task to Invoke SystemCommands Mantis 1863 • The $system task allows SystemVerilog code to call operating system commands module top. task. Sunburst Design.1 .but butititwas wasnever never part partof ofthe theVerilog Verilogstandard standard © 2009. Beaverton. Oregon. endmodule Most MostVerilog Verilogsimulators simulatorsalready already have havethis thistask.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design. initial $system("mv design. 58 of 59 `__FILE__ & `__LINE__ Macros Mantis 1588 • SystemVerilog-2009 adds the C-like macros ‘__FILE__ ‘__LINE__ • These macros allow access to the current file and line number from within SystemVerilog code © 2009. Sunburst Design.v adder.v"). Inc.

Oregon. Sunburst Design.com sponsored by © 2009. Beaverton. Inc. Sunburst Design. Inc.1 . © 2009 59 of 59 SDF Annotation of $timeskew & $fullskew Mantis 1140 • Verilog-2001 added the timing skew checks $timeskew $fullskew • SystemVerilog-2009 defines how these checks are annotated from SDF files © 2009. Cummings Sunburst Design. Inc. stuart@sutherland-hdl.com Stuart Sutherland Sutherland HDL. 60 of 59 SystemVerilog Is Getting Even Better! An Update on the Proposed 2009 SystemVerilog Standard Part 1 Presented by Clifford E.sunburst-design. Inc. cliffc@sunburst-design. 30 of 30 Rev 1.DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design.com www.com www.sutherland-hdl.

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