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# Switching Theory and Logic Design (April/May-2012, Set-1) JNTU-Anantapur

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## April/May - 2012 SWITCHING THEORY & LOGIC DESIGN

( Common to EEE, EIE, E.Con.E, ECE & ECC )

Set-1
Solutions
Max. Marks: 70

Time: 3 Hours Answer any FIVE Questions All Questions carry equal marks --1. (a) (b) (c) 2. (a) (b) (c) 3. (a) (b) What is the necessity of binary codes in computers? (Unit-I, Topic No. 1.1) Why the ASCII code was developed? Explain ASCII code with table. (Unit-I, Topic No. 1.1) Encode the word DIGITAL in to 7 bit ASCII code. (Unit-I, Topic No. 1.1)

What are universal gates? Realize AND, OR, NOT, XOR gates using universal gates. (Unit-II, Topic No. 2.3) Determine the canonical sum of minterms form of the following function. F(W, X, Y, Z) = 1. (Unit-II, Topic No. 2.2) Prove the Boolean identity x + yz = (x + y) (x + z). (Unit-II, Topic No. 2.2) What are the advantages of tabulation method over K-map? (Unit-III, Topic No. 3.2) Simplify the following Boolean function using tabulation method, (Unit-III, Topic No. 3.2) Y(A, B, C, D) = (0, 1, 3, 7, 8, 9, 11, 15).

4.

(a) (b)

Design a combinational circuit that accepts a three-bit binary number and generates an output binary number equal to the twice the input number. (Unit-IV, Topic No. 4.1) Design 2*4 decoder using NOR gates. (Unit-IV, Topic No. 4.2) For the figure given below, obtain the logic expression for the threshold element and determine its equivalent gate circuit. (Unit-V, Topic No. 5.3)

5.

(a)

A B C
(b) 6. (a) (b) 7. (a) (b) 8. (a) (b) What are the capabilities and limitations of T-gate? (Unit-V, Topic No. 5.2) What is meant by race around condition? Briefly explain. (Unit-VI, Topic No. 6.1) Explain the operation of synchronous counter. (Unit-VI, Topic No. 6.2) Discuss Mealy and Moore machine models of sequential machines. (Unit-VII, Topic No. 7.1) Explain the minimization procedure for determining the set of equivalent state of a specified machine M.

2 3 2

## (Unit-VII, Topic No. 7.2)

How do you indicate Moore outputs and Mealy outputs in an ASM block? (Unit-VIII, Topic No. 8.1) Obtain the ASM chart for the following state transition. Start for state T1; then if xy = 00, go to T2, if xy = 01, go to T3; if xy = 10 go to T1; otherwise go to T3. (Unit-VIII, Topic No. 8.1)

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## SOLUTIONS TO APRIL/MAY-2012, SET-1, QP

Q1. (a) What is the necessity of binary codes in computers? Answer : April/May-12, Set-1, Q1(a) Necessity of Binary Codes in Computers All the computers use binary system to represent all the data types such as numbers, characters, sound, pictures etc. Due to the following advantages, the use of binary codes in computers is necessary. (i) As the binary code uses only 2 symbols i.e., 0 and 1 to represent the data it is very simple to use and easy to construct the particular code. (ii) It is immuno to noise. (iii) It is very much suitable for computer applications. (b) Why the ASCII code was developed? Explain ASCII code with table. Answer : April/May-12, Set-1, Q1(b) ASCII Code An ASCII is the abbreviation of American Standard Code for Information Interchange. It was developed in 1963 to obtain the set of standards for characters and to expand the available characters included on the keyboard. ASCII is a fixed length 7-bit code. It is the extended form of six-bit trans code. Due to the 7-bit representation, ASCII can represent 128 (27) characters.
MSB b7 b6 b5 b4 b3 b2 b1 LSB b0

Figure: Bit Sequence of ASCII Code When an ASCII character is transmitted, the receiver first receives b0 bit then b1 bit and finally b7 bit. Hence, b0 is referred as the Least Significant Bit (LSB) and b7 as Most Significant Bit (MSB). However, these notations do not really indicate the significance of b0 and b7 they are used to indicate the first bit and last bit of a character. When talking about character codes, the position of bits is not considered. Rather, their order is considered. For example, b0 is referred as zero-order bit, b1 as first-order bit and so on. Bit b7 is not considered as the part of ASCII code. However, it is used to represent parity of a character. To convert a character with odd parity to even parity, we can simply complement b7 bit. The ASCII code table is shown below.
De c Hx Oct 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 A B C D E F 000 001 002 003 004 005 006 007 010 011 012 013 014 015 016 017 Char NUL (null) SOH (start of heading) STX (start of text) ETX (end of text) EOT (end of transmission) ENQ (enquiry) ACK (acknowledge) BEL (bell) BS (backspace) TAB (horizontal tab) (NL line feed, new line) LF VT FF CR SO SI (vertical tab) (carriage return) (shift out) (shift in) De c Hx 32 33 34 35 36 37 38 39 40 41 42 43 45 46 47 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F Oct 040 041 042 043 044 045 046 047 050 051 052 053 054 055 056 057 Html &#32; &#33; &#34; &#35; &#36; &#37; &#38; &#39; &#40; &#41; &#42; &#43; &#44; &#45; &#46; &#47; Char Space ! # \$ % & ' ( ) * + . / De c Hx 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F Oct 100 101 102 103 104 105 106 107 110 111 112 113 114 115 116 117 Html &#64; &#65; &#66; &#67; &#68; &#69; &#70; &#71; &#72; &#73; &#74; &#75; &#76; &#77; &#78; &#79; Char @ A B C D E F G H I J K L M N O De c Hx Oct Html 96 97 98 99 60 61 62 63 140 &#96; 141 &#97; 142 &#98; 143 &#99; 144 &#100; 145 &#101; 146 &#102; 147 &#103; 150 &#104; 151 &#105; Char ` a b c d e f g h i j k l m n o

## 100 64 101 65 102 66 103 67 104 68 105 69

106 6A 152 &#106; 107 6B 153 &#107; 108 6C 154 &#108; 109 6D 155 &#109; 110 6E 156 &#110; 111 6F 157 &#111;

## B.Tech. II-Year II-Sem.

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## Switching Theory and Logic Design (April/May-2012, Set-1) JNTU-Anantapur

( 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 10 11 12 13 14 15 16 17 18 19 020 021 022 023 024 025 026 027 030 031 ) 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 060 061 062 063 064 065 066 067 070 071 072 073 074 075 076 077 ; &#48; &#49; &#50; &#51; &#52; &#53; &#54; &#55; &#56; &#57; &#58; &#59; &#60; &#61; &#62; &#63; 0 1 2 3 4 5 6 7 8 9 : ; < = > ? 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 120 121 122 123 124 125 126 127 130 131 132 133 134 135 136 137 ; &#80; &#81; &#82; &#83; &#84; &#85; &#86; &#87; &#88; &#89; &#90; &#91; &#92; &#93; &#94; &#95; P Q R S T U V W X Y Z [ \ ] ^ _ 112 70 113 71 114 72 115 73 116 74 117 75 118 76 119 77 120 78 121 79 ; 160 &#112; 161 &#113; 162 &#114; 163 &#115; 164 &#116; 165 &#117; 166 &#118; 167 &#119; 170 &#120; 171 &#121; DLE (data link escape) DC1 (device control 1) DC2 (device control 2) DC3 (device control 3) DC4 (device control 4) NAK (negative acknowledge) SYN (synchronous idle) ETB (end of trans. Block) CAN (cancel) EM (end of medium) SUB (substitute) ESC (escape) FS GS RS US (file separator) (group separator) (record separator) (unit separator)

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p q r s t u v w x y z { | } ~ D

## 1A 032 1B 033 1C 034 1D 035 1E 036 1F 037

122 7A 172 &#122; 123 7B 173 &#123; 124 7C 174 &#124; 125 7D 175 &#125; 126 7E 176 &#126; 127 7F 177 &#127;

Table (c) Answer : The given word is, DIGITAL From the 7-bit ASCII code table A = 65, If A = 0, B = 1, C = 2, D = 3 . . . . Z = 25 then, D 65 + 3 = 68 I 65 + 8 = 73 G 65 + 6 = 71 I 65 + 8 = 73 T 65 + 19 = 84 A 65 + 0 = 65 L 65 + 11 = 76 Encode the word DIGITAL in to 7 bit ASCII code. April/May-12, Set-1, Q1(c)

## DIGITAL = 68, 73, 71, 73, 84, 65, 76

Q2. (a) What are universal gates? Realize AND OR, NOT, XOR gates using universal gates. April/May-12, Set-1, Q2(a)

Answer : For answer refer Unit-II, Q24. Implementation of XOR Gate (i) (ii) Using NAND Gates For answer refer Unit-II, Q21. Using NOR Gates The Boolean expression of XOR gates is given by, F = A'B + AB'

F = AB + AB
= ( A + B)( A + B )

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Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 The implementation of above expression using NOR gates is shown in the following figure,
A+A+B

A B

A+B

F = AB + A B

B + (A + B)

Figure (b) Determine the canonical sum of minterms form of the following function. F(W, X, Y, Z) = 1. April/May-12, Set-1, Q2(b) Answer : The given function is, F(W, X, Y, Z) = 1 The given function produces output as 1 for all the input combinations. Then, the truth table is obtained as shown table below.
Inputs W X Y Z 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Minterm Representation m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 Output F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Table From the above table output Boolean expression is given by, F(W, X, Y, Z) = m0 + m1 + m2+ m3 + m4 + m5 + m6 + m7 + m8 + m9 + m10 + m11 + m12 + m13 + m14 + m15 = m( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) The canonical sum of minterms of F is

## B.Tech. II-Year II-Sem.

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## Switching Theory and Logic Design (April/May-2012, Set-1) JNTU-Anantapur

(c) Answer : The given Boolean identity is, x + yz = (x + y) (x + z) Consider the truth table for Boolean identity x + yz = (x + y)(x + z) as shown below, x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 yz 0 0 0 1 0 0 0 1 x+y 0 0 1 1 1 1 1 1 x+z 0 1 0 1 1 1 1 1 x + yz 0 0 0 1 1 1 1 1 (x + y)(x + z) 0 0 0 1 1 1 1 1 Prove the Boolean identity x + yz = (x + y) (x + z).

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April/May-12, Set-1, Q2(c)

From the above truth table, x + yz = (x + y) (x + z) Hence proved. Q3. (a) What are the advantages of tabulation method over K-map? April/May-12, Set-1, Q3(a)

Answer : For answer refer Unit-III, Q17. (b) Simplify the following Boolean function using tabulation method, Y(A, B, C, D) = (0, 1, 3, 7, 8, 9, 11, 15). Answer : The given Boolean function is, Y(A, B, C, D) = (0, 1, 3, 7, 8, 9, 11, 15) Step 1 The binary representation of given Boolean function is shown in table (1),
Minterm 0 1 3 7 8 9 11 15 Binary Representation 0000 0001 0011 0111 1000 1001 1011 1111

Table (1)

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Step 2

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 In the above steps, the unmarked minterms are referred as prime implicants, which are tabulated in table (5),
Prime Implicants BC BD CD 0, 1, 8, 9 1, 3, 9, 11 3, 7, 11, 15 Binary Representation 00 01 11

## Group the minterms based on the number of 1s as shown in table (2),

Number of 1s 0 1 2 3 4 Minterm 0 1 8 3 9 7 11 15 Binary Representation 0000 0001 1000 0011 1001 0111 1011 1111

Table (5) Prime Implicant Chart Table (6) represents the prime implicant selection chart.
Minterms BC BD CD 0, 1, 8, 9 1, 3, 9, 11 3, 7, 11, 15 0 1 3 7 8 9 11 15

Table (2) Step 3 Comparing each minterm with the adjacent higher category group and mark the minterms which are differ by only one position. Copy the binary representation with _ mark at the differed place as shown in table (3),
Minte rms (0, 1) (0, 8) (1, 3) (1, 9) (8, 9) (3, 7) (3, 11) (9, 11) (7, 15) (11, 15) Binary Representation 000 000 001 001 100 011 011 101 111 111

Table (6) From the above tabular column, the function F can be represented by selecting the minimum number of prime implicants which cover all the minterms.

F(A, B, C, D) = B C + B D + CD
Q4. (a) Design a combinational circuit that accepts a three-bit binary number and generates an output binary number equal to the twice the input number. April/May-12, Set-1, Q4(a)

Design of combinational circuit that accepts 3-bit binary number and produces twice input number as output. Let us assume the three bits of input binary number are a, b, c and outputs are w, x, y, z. Then the truth table which converts the normal inputs to twice of the number is shown in table,
Inputs a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 Minte rm Re presentation m0 m1 m2 m3 m4 m5 m6 m7 Outputs w 0 0 0 0 1 1 1 1 x 0 0 1 1 0 0 1 1 y 0 1 0 1 0 1 0 1 z 0 0 0 0 0 0 0 0

Table (3) Step 4 Repeat step-3 until no further possible comparisons can be made.
Minterms 0, 1, 8, 9 0, 8, 1, 9 1, 3, 9, 11 1, 9, 3, 11 3, 7, 11, 15 3, 11, 7, 15 Binary Representation 00 00 01 01 11 11

Table (4)

Table

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## Switching Theory and Logic Design (April/May-2012, Set-1) JNTU-Anantapur

From the above table, the output equations can be obtained as, w = m4 + m5 + m6 + m7 = m(4, 5, 6, 7) x = m2 + m3 + m6 + m7 = m(2, 3, 6, 7) y = m1 + m3 + m5 + m7 = m(1, 3, 5, 7) z =0 These equations can be simplified using K-maps as described below, K-map for w
y=c x=b w=a a b c

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bc 0 1

00 0 4 1

01 1 5 1

11 3 7 1

10 2 6 1 a
Figure (b) Design 2*4 decoder using NOR gates. Answer : April/May-12, Set-1, Q4(b) 2 to 4 Line Decoder The truth table of a 2 to 4 line decoder including enable input is shown in table.
z=0

w = a
K-map for x

bc 0 1

00 0 4

01 1

11 3 1 5 1 7

10 2 1 6 1 b

Inputs e 1 1 1 1 x 0 0 1 1 y 0 1 0 1 D0 1 0 0 0

Outputs D1 0 1 0 0 D2 0 0 1 0 D3 0 0 0 1

x = b
K-map for y

bc 0 1

00 0

01 1 1 4 1 5

11 3 1 7 1

10 2 6

Table From above table, output equations of decoder can be given as, D0 = x y e ... (1) ... (2) ... (3)

D1 = x y e D2 = x y e

y =c
The simplified output equations are given by, w= a x=b y=c z =0 These output equations can be implemented using logic gates as shown in figure,

D3 = x y e ... (4) In order to design a decoder using only NOR gates above four equations can be rewritten as, D0 = x y e = ( x + y + e ) D1 = x y e = ( x + y + e ) D2 = x y e = ( x + y + e ) D3 = x y e = ( x + y + e )

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x y

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 The implementation of above equations using only NOR gates is shown in the following figure,
D0 = x y e

D1 = x y e

D2 = x y e

D3 = x y e

Figure Functioning In the above figure enable input e must be always high. And, for different input combinations of x and y decoder gives different outputs as described below, For e = 1, x = 0, y = 0 For e =1, x = 0, y = 1 For e = 1, x = 1, y = 0 For e = 1, x = 1, y = 1 Q5. (a) D0 = 1 = x y e D1 = 1 = x y e D2 = 1 = x y e D3 = 1 = x y e

For the figure given below obtain the logic expression for the threshold element and determine its equivalent gate circuit.
A B C 2 3 2 2 F

A B C 2 3 2 2 F

Figure (i)

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## Switching Theory and Logic Design (April/May-2012, Set-1) JNTU-Anantapur

From figure (i), weighted sum and output expressions are given by, w = 2A + 3B + 2C
1 ; for w 2 And F = 0 ; for w < 2

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## Then, the truth table is shown in the following table,

Input Variables A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Weighted Sum w = 2A + 3B + 2C 0 2 3 5 2 0 1 3 Output F 0 1 1 1 0 0 0 1

Table From the above truth table output Boolean function is given by, F(A, B, C) = m(1, 2, 3, 7) By using K-map above expression can be simplified as,

BC A 00 0 1 0

AC 01 1 1 4 5 1 1 7 11 3 1 6 BC 10 2 AB

F = A C + A B + BC The equivalent gate circuit of the given function can be obtained by implementing the above function using logic gates as shown in figure (ii),
A B C

F = AC + AB + BC

Figure (ii)

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(b)

Spectrum ALL-IN-ONE Journal for Engineering Students, 2013 Explain the operation of synchronous counter. Answer : April/May-12, Set-1, Q6(b) Synchronous Counter The counter in which, the clock pulse is connected simultaneously to all the flip-flops is called synchronous counter. Let us consider a 4-bit synchronous binary counter the construction of which using JK flip-flop involves the following steps, 1. All the bits of a flip-flop present in the least significant position are complemented. 2. Consider flip-flops present at a position other than the least significant position. The bits in these flipflops are complemented if and only if all the bits at least significant position are 1. For instance, consider a present state of a 4-bit counter be Q3 Q2 Q1 Q0 = 0011 and 0100 for next count. Then, (a) The flip-flop, Q0 is complemented completely. (b) The flip-flop, Q1 is also complemented as the present state of Q0 = 1 (c) As Q1 Q0 = 11, Q2 is complemented (d) But Q3 is not complemented since the present state of Q2 Q1 Q0 = 011 i.e., not all 1s condition. Figure below shows a 4-bit synchronous binary counter using JK flip-flop.
J C Count enable EN K Q0

What are the capabilities and limitations of T-gate? Answer : April/May-12, Set-1, Q5(b) For answer refer Unit-V, Q18. Q6. (a) What is meant by race around condition? Briefly explain. Answer : April/May-12, Set-1, Q6(a) Race Around Condition We know that in a JK flip-flop, when both the inputs J = K 1 and a clock pulse of width tp is applied, then the output changes to the complement state. Thus, when Q(t) = 0, it is changed to 1. This change is output state from 0 to 1 takes place in a time interval t which is nothing but the propagation delay due to the logic gates. If the clock pulse tp is more than the time delay t(tp > t), then after Q(t) changes to 1, Q again changes to 0 after another t is the duration tp as shown in figure (1).
Q=1 t t Q=0 O tp T

(b)

Figure (1) This results in the oscillated value of Q between 0 and 1 during tp. The reason behind this being the output feedback to the input in JK flip-flop. This results is changes in the input while there are any changes in output. Thus at the end of a clock pulse, the output value of Q becomes ambiguous. This is called as the race around condition. The race around condition can be over come by reducing the pulse width tp by using a pulse generator on by increasing the value of t by using lumped delay lines. However, it is difficult to design a circuit using the pulse generator and almost worthless to use the lumped delay lines.
tp t

J C K

Q1

J C K

Q2

J C
O T

Q3

## K Carry Output (CO) Clock

Figure (2) Thus another way to overcome the race around condition is to either use edge triggering or switch to the master slave flip-flop configuration.

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## Switching Theory and Logic Design (April/May-2012, Set-1) JNTU-Anantapur

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It consists of a regular pattern. The counter is implemented using complementary flip-flops and gates. The clock input C is given as a common clock to all the flip-flops. Using the count enable input, the counters in the circuit are enabled as follows, Case 1 For Enable Input = 0, If the enable input is set to 0, then all the J and K inputs are also equal to 0 with the clock C remaining in its same state of counter. Case 2 For Enable Input = 1, For enable input = 1, J and K inputs of Q0 is also set to 1. The J and K inputs of other flip-flops are equal to 1 if both the count is enabled and the previous least significant stages are equal to 1. The logic desired for both J and K is produced by the series of AND gates present in each stage. The 4-bit synchronous binary counter is triggered using either a positive or negative clock edge. Q7. (a) Discuss Mealy and Moore models of sequential machines. April/May-12, Set-1, Q7(a)

Explain the minimization procedure for determining the set of equivalent state of a specified machine M. April/May-12, Set-1, Q7(b) How do you indicate Moore outputs and Mealy outputs in an ASM block? April/May-12, Set-1, Q8(a)

Answer : ASM Chart for Moore Outputs In Moore circuits, the outputs are the function of present state of the circuit.

Let X be the input variable and Z1, Z2 be the output variables. The next state of the state diagram depends on the input variable X. For example consider the Moore state diagram shown in figure (i),
0/10

0/01 C

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## Spectrum ALL-IN-ONE Journal for Engineering Students, 2013

The ASM chart of the above state diagram is shown in figure (ii).

A Z1

X 1 B Z2

X 1 C Z1Z2

X 1

Figure (ii): ASM Chart of Moore State Diagram ASM Chart for Meely Outputs For answer refer Unit-VIII, Q6. (b) Answer : For answer refer Unit-VIII, Q3. Obtain the ASM chart for the following state transition. Start for state T1; then if xy = 00, go to T2, if xy = 01 go to T3; if xy = 10 go to T1; otherwise go to T3. April/May-12, Set-1, Q8(b)

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