# Circuit Diagram CE Amplifier with Fixed Bias

Pin Diagram Bottom view of BC107
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EC2208 - Electronic Circuits – I LAB

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Ex. no: Date: Aim

1. COMMON EMITTER AMPLIFIER WITH FIXED BIAS

To design and construct BJT Common Emitter Amplifier using fixed bias . To measure the gain and to plot the frequency response and to determine the Gain Bandwidth product (GBW). Apparatus Required S.No 1. 2. 3. 4. 5. 6. Equipments / Components Power Supply Resistor Capacitor Transistor AFO CRO Range / Details (0 – 30) V Qty 1

BC 107

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5.1 KΩ, 3MΩ

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Fixed Bias with Emitter Resistor

The fixed bias circuit is modified by attaching an external resistor to the emitter. This resistor introduces negative feedback that stabilizes the Q-point. From Kirchhoff's voltage law, the voltage across the base resistor is VRb = VCC - IeRe - Vbe

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(0 – 1) MHz (0 – 20) MHz

EC2208 - Electronic Circuits – I LAB

Tabulation

Frequency (Hz)

Vo (V)

Gain = Vo / Vs

Gain = 20log(Vo/Vs)dB

Model Graph

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From Ohm's law, the base current is Ib = VRb / Rb. The way feedback controls the bias point is as follows. If Vbe is held constant and temperature increases, emitter current increases. However, a larger Ie increases the emitter voltage Ve = IeRe, which in turn reduces the voltage VRb across the base resistor. A lower baseresistor voltage drop reduces the base current, which results in less collector current because Ic = ß IB. Collector current and emitter current are related by Ic = α Ie with α ≈ 1, so increase in emitter current with temperature is opposed, and operating point is kept stable. Similarly, if the transistor is replaced by another, there may be a change in IC (corresponding to change in β-value, for example). By similar process as above, the change is negated and operating point kept stable. For the given circuit, IB = (VCC - Vbe)/(RB + (β+1)RE). Merits:

Demerits:

In this circuit, to keep IC independent of β the following condition must be met:

• • •

Usage: The feedback also increases the input impedance of the amplifier when seen from the base, which can be advantageous. Due to the above disadvantages, this type of biasing circuit is used only with careful consideration of the trade-offs involved.

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As β-value is fixed for a given transistor, this relation can be satisfied either by keeping RE very large, or making RB very low. If RE is of large value, high VCC is necessary. This increases cost as well as precautions necessary while handling. If RB is low, a separate low voltage supply should be used in the base circuit. Using two supplies of different voltages is impractical. In addition to the above, RE causes ac feedback which reduces the voltage gain of the amplifier.

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which is approximately the case if ( β + 1 )RE >> RB.

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The circuit has the tendency to stabilize operating point against changes in temperature and βvalue.

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fL si ve .6 KΩ X 100) = 0. VCC – IBRB – VBE = 0 IB = IC/ β = 1mA/250 = 4µA RB = (VCC – VBE) / IB = (12 – 0.825M Ω ≈ 3M Ω Design of input capacitor F = 1/2πhieC Take F = 100Hz and hie = 1.Design Choose β = 250.9µF ≈ 1µF w w w . VCC = 12V.b l ~5~ og EC2208 . ICRC = 6V RC = 6V/10-3 = 6KΩ Choosing a standard value for RC as 5.c o m .7)/4x10-6 = 2. VCC – ICRC – VCE = 0 VCC = ICRC – VCE Assume equal drops across RC and VCE VRC = VCE = 6V.1Ω By applying KVL to the input side.6 KΩ C1 = 1/ (2π X 1.e ee ex cl u Calculation Bandwidth = fH . IC = 1 mA By applying KVL to output side.Electronic Circuits – I LAB sp ot .

vary the frequency from 1Hz to 1MHzin regular steps. 4) Plot the graph: Gain in dB Vs Frequency in Hz.e) Bandwidth = fH .e the frequency response curve is plotted. 4) The lower frequency point is called the lower 3dB point. (i.b l ~6~ scale gives the bandwidth of the amplifier. 5) Calculate the Bandwidth from the Frequency response graph To plot the Frequency Response 1) The frequency response curve is plotted on a semi-log scale. Keeping input voltage constant.Procedure 1) Connect the circuit as per the circuit diagram 2) Set Vin = 50mV in the signal generator.c o EC2208 .Electronic Circuits – I LAB m 2) The mid frequency voltage gain is divided by √2 and these points are marked in the . ee Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and ex Result cl u si ve 6) From the plotted graph the bandwidth is obtained. frequency response curve. w w The bandwidth is found to be __________________ w .fL . og 5) The difference between the upper 3dB point and the lower 3dB point in the frequency sp ot 3) The high frequency point is called the upper 3dB point. . 3) Note down the corresponding output voltage.

no: w .e 2. COMMON EMITTER AMPLIFIER WITH SELF BIAS ~7~ EC2208 .b l og sp ot .Circuit Diagram CE Amplifier with Self Bias w w Ex.Electronic Circuits – I LAB ee ex cl u si ve .c o m .

Date: Frequency (Hz) Aim Vo (V) Gain = Vo / Vs Gain = 20log(Vo/Vs)dB To design and construct BJT Common Emitter Amplifier using voltage bias (self bias) with and without bypassed emitter resistor. 61KΩ. ~8~ EC2208 . If Cbp is large enough. 4.e . 3. 6. Apparatus Required 1. Merits • • • w Unlike above circuits. 2. 10KΩ. Operating point is almost independent of β variation. To measure the gain and to plot the frequency response and to determine the Gain Bandwidth product (GBW). In this circuit. allow minimal ac signal degeneration. only one dc supply is necessary. the voltage divider holds the base voltage fixed independent of base current provided the divider current is large compared to the base current. The voltage divider is formed using external resistors R1 and R2. 4. rapid signal variations will not change its charge materially and no degeneration of the signal will occur. to provide long-term or dc thermal stability.c o m S. the operating point of the transistor can be made independent of β. The voltage across R2 forward biases the emitter junction.7KΩ . even with a fixed base voltage. However.b l og BC 107 (0 – 1) MHz (0 – 20) MHz sp ot 1KΩ. However. One of the most widely used combination-bias systems is the voltage-divider type.No Equipments / Components Range / Details Qty 1 1 1 1 1 1 1 µF ve ee ex cl u si Theory Voltage divider bias (Self bias) A combination of fixed and self-bias can be used to improve stability and at the same time overcome some of the disadvantages of the other two biasing methods. the bypass capacitor (Cbp) is placed across R3.Electronic Circuits – I LAB w w . By proper selection of resistors R1 and R2. Power Supply Resistor Capacitor Transistor AFO CRO (0 – 30) V . collector current varies with temperature (for example) so an emitter resistor is added to stabilize the Q-point. Operating point stabilized against shift in temperature. and at the same time. 5.

Electronic Circuits – I LAB w w w .c o m .e ee ex cl u si ve .b l og sp ot .Tabulation Model Graph Design ~9~ EC2208 .

e Design of input capacitor ee ex cl u si ve .6 KΩ X 100) = 0.5 KΩ. IE ≈ IC = 1mA Drop across VBE = 0.Drop across RE (VRE) is assumed to be 1V.7V Drop across R2 (VR2) = VBE + VRE = 1. Drop across VCE with the supply of 12V is given by 12V – 1V = 11V Assume equal drops across ICRC and VCE So ICRC = VRC = 11/2 = 5.7 – 10) = 60. Then RC = VRC / IC = 5.5 KΩ Instead of using 5.6 KΩ w w F = 1/2πhieC .5V / 1mA = 5.5 KΩ R1 is assumed to be 61 KΩ C1 = 1/ (2π X 1.7 KΩ VRE = 1V.5V Assume IC = 1 mA.7V Assume R2 = 10 KΩ VR2 = VCC.R2/ (R1+R2) R1 = (12 X 10) / (1.b l og sp ot Design of R1 and R2 .Electronic Circuits – I LAB w Take F = 100Hz and hie = 1.9µF ≈ 1µF Calculation ~ 10 ~ EC2208 .c o RE = VRE/IE = 1V/1mA = 1KΩ m . we can use a standard value of 4.

fL Procedure To plot the Frequency Response ~ 11 ~ EC2208 .Bandwidth = fH .e ee ex cl u si ve .c o m .b l og sp ot .Electronic Circuits – I LAB w w w .

fL Result Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency response curve is plotted.b l ~ 12 ~ og EC2208 . (i.1) The frequency response curve is plotted on a semi-log scale.Electronic Circuits – I LAB sp ot .e) Bandwidth = fH . 3) The high frequency point is called the upper 3dB point.c o m .e ee ex cl u si ve . 6) From the plotted graph the bandwidth is obtained. 4) The lower frequency point is called the lower 3dB point. Bandwidth = Circuit diagram: w w w . 5) The difference between the upper 3dB point and the lower 3dB point in the frequency scale gives the bandwidth of the amplifier. 2) The mid frequency voltage gain is divided by √2 and these points are marked in the frequency response curve.

b l ~ 13 ~ og EC2208 .c o m VO (CRO) .e ee ex cl u si ve .+ BC 107 47 µF AFO 5 mV a R2 10 KΩ RE 6 KΩ + 47 µF w w w .Electronic Circuits – I LAB sp ot .VCC = 12 V R1 8 KΩ .

The quiescent current of 1mA is assumed. 4. 10KΩ (all are ¼ W) 47µF . Transistors Regulated Power Supply Audio Frequency Oscillator Resistors Capacitors CRO BC107 1.6 18. . 3. To measure the gain and to plot the frequency response & to determination of Gain Bandwidth Product Apparatus required: 1.6V R1 + 10 X 103 120 X 103 = R1 + 10 X 103 6. 2. Now RE = VRE = 6V = 6KΩ IE 1X 10-3 Design of R1 & R2 Drop across RE is 6V Drop across VBE is 0.Ex.6 V R1 + R2 12 X 10 X 103 = 6. We assume a standard supply of Vcc = 12V.6V Assume R2 =10KΩ w w . we assume equal drops across VCE and Emitter Resistance RE.c o m .6V Drop across the resistance R2 is VR2 = VBE + VRE =6.e ee VCC R2 = 6.Electronic Circuits – I LAB ex cl u si ve Design: Since voltage amplification is done in the transistor amplifier circuit. 6.7 K) ~ 14 ~ EC2208 .b l og sp ot 6KΩ. w Drop across RE is assumed to be VRE =6V Drop across VCE is VCC –VRE =6V We know that ICQ =IE. 5. 8KΩ. no: Date: Aim: 3.18 X 103 = R1 + 10 X 103 R1 = 8 KΩ (3. VRE = 6V. 2.3 K + 4. COMMON COLLECTOR TRANSISTOR AMPLIFIER To design and construct BJT Common Collector Amplifier using voltage divider bias (self-bias).

Electronic Circuits – I LAB ~ 15 ~ og sp ot .c o m .b l fH frequency (Hz) EC2208 .Tabular column Vs = Frequency (Hz) VO (Volts) Gain = VO / VS Gain = 20 log (VO/VS) (dB) Model graph (frequency response) A/max 3dB Line w Gain dB w w .e ee fL ex cl u si ve .

Procedure 1. 3W. 2. 50V – 1A. Plot the graph gain Vs frequency. Set VS = 5 mV using AFO. Regulated Power Supply (0. vary the frequency from 0 Hz to 1 MHz in regular steps and note down the corresponding output voltage. Transistor BC107. Connect the circuit as per the circuit diagram. 3.e ee ex cl u si ve .b l ~ 16 ~ og EC2208 .30). Calculate bandwidth from the graph. 5. 300 MHz 2. Bandwidth = Specifications: 1. Keeping the input voltage constant. 1A w w Thus a BJT Common Collector Amplifier is designed and implemented and the frequency w .c o m . 4.Electronic Circuits – I LAB sp ot . Result response curve is plotted.

b l ~ 17 ~ og EC2208 .7 KΩ + 47 µF .Circuit diagram: VCC = 12 V R1 47 KΩ RC 4.e ee ex cl u si ve .100 µF m VO (CRO) .Electronic Circuits – I LAB sp ot .7 KΩ RE 1 KΩ BC 107 w w w .c o + CE .+ BC 107 47 µF AFO 5 mV a R2 10 KΩ RE1 4.

we assume equal drops across VCE and load resistance RC. So the ICBO(β+1) will flow through this resistance and a part of this current might flow through hie + βdcRE.1mA . no: Date: Aim: 1.c o m . Drop across VBE1 & VBE2 is 0. So to reduce the effect of ICBO the 1st stage ICBO flowing through the emitter of the 1st stage is not allowing to enter the 2nd stage by paralleling a resistor between B & E of the 2nd stage T2. We assume standard supply of 12V. Hence the 2nd stage IE current will be IE = (β+1)2ICO For silicon transistor ICBO is the order of 10nA at room temperature β = 100. This shunting resistance will be the range of 1 to 4.7 KΩ) IC Design of R1 & R2: Drop across RE is 1V.b l og sp ot Design: . CRO 5. 4. Since voltage amplification is done in the Darlington transistor amplifier circuit. The ICQ = 1mA is assumed. RPS 7.5V RC = VRC = 5. ex cl u si ve Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base current for the 2nd stage. To plot the frequency response and to calculate the Gain Bandwidth Product (GBW). DARLINGTON COMMON EMITTER AMPLIFIER To design a Darlington amplifier using BJT and to measure the gain and input resistance. Capacitors 47µF. 2. 100µF 4. It is equal to VRC & VCE = 5. Drop across the resistance R2 is VRE + VBE1 + VBE2 Tabular column: ~ 18 ~ EC2208 . 10KΩ (all are ¼ W) 3.6V. Transistors BC 107 2. Connecting wires & Breadboard Assume R2 = 10KΩ and Ic = 1mA. 4.Ex. The drop across VCE with a supply of 1.e ee This current will get double with every 100 rise in temperature.2 V is given by 12 – 1 = 1V. Now.Electronic Circuits – I LAB w w w Biasing Design: . Drop across Re is assumed to be 1V. IE = (101)2 X 10 nA IE ≅ 105 nA ≅ 0. 47KΩ. Resistors 1KΩ.7 KΩ. Apparatus required: 1.7KΩ.5 KΩ (4. AFO 6.

Vs = Frequency (Hz) VO (Volts) Gain = VO / VS Gain = 20 log (VO/VS) (dB) Model graph (frequency response): Gain dB A/max 3dB Line w w w .Electronic Circuits – I LAB sp ot .b l fH frequency (Hz) ~ 19 ~ og EC2208 .c o m .e ee fL ex cl u si ve .

4. 1A Circuit diagram: ~ 20 ~ EC2208 . 300 MHz 2. Keeping the input voltage constant. 3W.c o m . Plot the graph gain Vs frequency.2V R2 is assumed to be 10 KΩ VCC R2 = 2.fL = w 1. Calculate bandwidth from the graph. cl u si ve .6 + 0.2 54.e ee ex 1. 2. 3. The frequency response curve is plotted on a log scale.Electronic Circuits – I LAB w Bandwidth = fH . Connect the circuit as per the circuit diagram.2 R1 + 10 X 10 3 120 X 103 = R1 + 10 X 103 2. From the graph the bandwidth is obtained w . Regulated Power Supply (0.2 X 10 X 103 = 2. Transistor BC107.= 1 + 0.5 X 103 = R1+ 10 X 103 R1 = 54.5 X 103 – 10 X 103 R1 = 44. vary the frequency from 0 Hz to 1 MHz in regular steps and note down the corresponding output voltage.30).5 X 103Ω R1 is rounded to be 47 KΩ Procedure: Result: Specifications: 1. Set VS = 5 mV using AFO.2V R1 + R2 1.6 VR2 = 2. 2. 5.b l og sp ot . 50V – 1A.

Electronic Circuits – I LAB cl u si ve Pin Details .b l og sp ot . no: .c o m .w w w Ex.e ee ex 5. COMMON DRAIN AMPLIFIER ~ 21 ~ EC2208 .

7KΩ. CRO 7. Bread board and connecting wires Bias design: Theory: Here input is applied between gate and source & output between source and Drain.1µ F 6. So choose the value of resistance RG very large with in The range of 1MΩ to 10MΩ ee ex cl u si ve . we can select standard value = 4. VP = -4V. IDSS = 9.ID = IDSS{1-(VGS/VP)}2 RS = 2. Apparatus required: 1. As VGS is fairly constant and Vs varies with Vi. 2.VG varies with the signal.7=9.e VDD = 12 V. Voltage drop across R S = 2.65KΩ Instead of 4. Here Vs = VG + VGS. ID = 1mA. input resistance and output resistance with and without Bootstrapping.7KΩ.5mA.Electronic Circuits – I LAB w w w . Resistors . Transistor .7KΩ FET input is always reverse bias. Capacitor . Ci = 1µF VGS = ID RS . Assume equal drops across VRD & VDS VRD = VDS = 4.3V.c o m .4. Audio Frequency Oscillator 4.65KΩ.BC-107 2. Here output voltage follows the change in the signal voltage applied to the gate.7KΩ .b l og sp ot .Date: Aim: To design a common drain amplifier and to measure the gain. the circuit is also called as Source follower Tabulation ~ 22 ~ EC2208 . Regulated Power supply 3.7V VRD + VDS = VDD-VRS = 12-2. When a signal is applied to JFET gate via Cin. 1MΩ 5.65V RD = VRD/ID = 4.

Electronic Circuits – I LAB w Model Graph w w .c o m .e ee ex cl u si ve .Frequency (Hz) Vo (V) Gain = Vo / Vs Gain = 20log(Vo/Vs)dB Procedure: ~ 23 ~ EC2208 .b l og sp ot .

input resistance and output resistance are calculated using the measured parameters. Calculate the bandwidth from the Graph Result: Thus a common drain amplifier is designed and the gain.b l og sp ot . Plot the graph: gain Vs Frequency 5.1. Keeping the input voltage constant.c o m . Set Vs= 50 mv in AFO 3. vary the frequency from 0 Hz to1MHz in regular steps and note down the corresponding output voltage. Connect the circuit as shown in the circuit diagram 2.e ee ex cl u si ve .Electronic Circuits – I LAB w w w . 4. Circuit Diagram – Differential Amplifier ~ 24 ~ EC2208 .

Electronic Circuits – I LAB cl u si ve . no: w w w . DIFFERENTIAL AMPLIFIER ~ 25 ~ EC2208 .b l og sp ot .c o m .Common mode Configuration Differential mode Configuration Ex.e ee ex 6.

R = Ad/Ac Higher the value of C.R. better the performance of the differential amplifier.R we have to increase differential mode gain and decrease common mode gain w w w Theory The Differential amplifier amplifies the difference between two input voltage signals. To improve C.Date: Aim To construct the Differential Amplifier in a) Common mode and b) Differential mode.V1 and V2 are input voltages.Electronic Circuits – I LAB C.R. Hence it is called differential amplifier.M. Vo is proportional to difference between two input signals. Such an average level of two input signals is called common mode signal . 3. .R. Power Supply CRO Function Generator Transistors Resistors - Formula C.2 nos.M.c o m BC107 1KΩ 470Ω -1 no . Apparatus required 1.R. -1 no.M.M. If we apply two input voltages equal in all respects then in ideal case output should be zero. and to find the common mode rejection ratio (CMRR). 4. But output voltage depends on the average common level of the inputs. 5.b l ~ 26 ~ og EC2208 .e ee ex cl u si ve Ad = Differential mode gain Ac = Common mode gain .R in dB = 20 log Ad/Ac sp ot . 2.R.

b l ~ 27 ~ og EC2208 .Electronic Circuits – I LAB sp ot .c o m .Model Calculation For common mode signal Gain Ac = Vo / Vi Ac = For differential mode signal Gain Ad = Vo / Vi Ad = CMRR = 20 log (Ad / Ac) = w w w .e ee ex cl u si ve .

M.e ee ex cl u si ve . Calculate the gain for both the modes 4.b l ~ 28 ~ og EC2208 .R Formulae For common mode signal: Gain Ac = Vo / Vi For differential mode signal: Gain Ad = Vo / Vi Result Thus a differential amplifier is constructed in both common mode and differential mode and the corresponding gains are obtained and the CMRR is calculated. Set Vi=5mV and note down Vo in both differential mode & common mode 3. CMRR = w w w . Calculate C.Procedure 1.Electronic Circuits – I LAB sp ot .c o m Common Mode Rejection Ratio: CMRR = 20 log (Ad / Ac) .R. Connections are given as per the circuit diagram 2.

e E ee B ex Bottom view of BC 107 cl u Pin Diagram si ve .+ .Circuit diagram: Vcc=12V Rc = 4.7KΩ R1 = 61KΩ CRO 100µF - C 3-d view w w w .b l ~ 29 ~ og EC2208 .Electronic Circuits – I LAB sp ot Vi= 10mv ` R2= 10KΩ RE 1KΩ + .c o m 1µF .

3.c o m . no: Date: Aim 7. 5. we assume a standard supply of 12V.7V R1=60.5V VCE = 5.Electronic Circuits – I LAB w w w .5V VC = 5.5V IC = 1mA RC = 5.A AMPLIFIER To design and construct a Class – A power amplifier. To observe the output waveform and to measure the maximum power output and to determine the efficiency Apparatus required: 1. 2.5V/1mA = 5.5V Now the voltage across the resistance RE is 5.5V≅61KΩ Model graph: ~ 30 ~ EC2208 . R2 is assumed to be 10KΩ VCCR2 / (R1 + R2 ) = VR2 10*12KΩ/(R1+10KΩ)=1. Hence VBB = IERE+VBE Hence VBE is neglected when compared to IERE Hence IE = VBB / RE.e ee ex cl u si ve . 4. We can use a standard value of 4. Transistor BC107 1 Resistors 1KΩ.7KΩ. We as equal drops across VCE & load resistance RE.61KΩ.5KΩ .5KΩ Instead of using 5. DESIGN OF R1 & R2: Voltage drop across RE = VRE = 1V Drop across VBE = 0. The quiescent current of 1mA is assumed.7V Drop across the resistance R2 = VBE +VRE = VR2 VR2=1.100µf(all are electrolytic) CRO (0-20MHz) AFO (0-1MHz) Regulated Power Supply Breadboard & Connecting Wires Bias design: Since voltage amplification is done in the transistor amplifier circuit. 7. It is assumed that RBB / (βdc+1) = RE / 10 Hence RBB / (βdc+1) is neglected when compared RE.10KΩ(all are ¼ watts) Capacitors 1µf.4. CLASS .the drop across VCE with a supply of 12V is given by 12V1V=11V It is equal to 11/2=5.Ex.b l og sp ot . Drop across RE is assumed to be 1V.7V . 6.7KΩ.

Electronic Circuits – I LAB sp ot .b l ~ 31 ~ og EC2208 .707 A fL Tabular column: VI = fh f (Hz) w w w .gain (dB) A 0.e ee ex cl u si ve .c o Frequency (KHz) V0 (mV) Gain = V0 / Vi Gain (dB) = 20 log V0 / Vi dB m .

5. Connect the circuit as per the circuit diagram. When an a.c o m .b l ~ 32 ~ og EC2208 . position of the Qpoint is approximately at the midpoint of the load line. 4. Calculate bandwidth from the graph. one full cycle. The collector current flows for 360°(full cycle)of the input signal. the transistor remains in the active region &never enters into cut-off or saturation region. 2.c input signal is applied. constructed and the output waveform is observed. In other words.Electronic Circuits – I LAB sp ot .e ee ex cl u si ve . 3. the collector voltage varies sinusoidally hence the collector current also varies sinusoidally. vary the frequency from few Hz to 1MHz in regular steps & note down the correspondingly output voltage. Keeping the input voltage constant. For all the values of input signal.Theory: The Power amplifier is said to be class-A amplifier if the Q-point & the input signal are selected such that the output signal is obtained for a full input cycle. the angle of the collector current flow is 360° i. Set VS=10mV using AFO. Procedure: 1. Result: The class-A amplifier is designed.e. Plot the graph: gain Vs frequency. w w w . For this. The maximum power output and the efficiency are determined.

Circuit diagram Pin Diagram Bottom view of BC 107 / BC 178 B E C 3-d view w w w . CLASS – B POWER AMPLIFIER ~ 33 ~ EC2208 .b l og sp ot . no: ee ex 8.e Ex.c o m .Electronic Circuits – I LAB cl u si ve .

When the signal voltage is negative. which employs one PNP. Connect the circuit as per the diagram. 4. T1 (the NPN transistor) conducts.c o - 1No 1No 1No 1No m EC2208 . In regular steps. gain (dB) Vs frequency (on a semi – log graph) w w w . the two transistor have identical characteristics but one is PNP and the other NPN. The disadvantage is obtaining pause of transistor matched closely enough to achieve low distortion. Note down the corresponding output voltage. Keeping the input voltage constant.e some advantages of the circuit are that the transformer less operation saves on weight and cost and balanced push – pull input signals are not required. Function Generator 4. ee ex cl u iL = ic1 – ic2 si Theory: The figure illustrates a Class – B Power Amplifier.Date: Aim: To design and construct a Class – B (complementary symmetry) power amplifier.b l ~ 34 ~ og sp ot . i. Its operation can be explained by referring to the figure. CRO 3.e.. The load current is ve . while T2 (the PNP transistor) is cut off. When the signal voltage is positive. T2 conducts while T1 is cut off. 2.e. 3.To observe the output waveform with crossover Distortion and to measure the maximum power output and to determine the efficiency. vary the frequency from 0Hz to 1MHz. Transistors (0 – 30) V (0 – 20) MHz (0 – 1) MHz 47 KΩ 1 KΩ BC 107 BC 178 Procedure: 1. Plot the graph i. Resistor 5. Set VS = 50mV(say) using the signal generator. Apparatus required: 1.Electronic Circuits – I LAB . and one NPN transistor and require no transformed. This type of amplifier uses complementary symmetry.. Power Supply 2.

c o m .b l cl u si I = 1 mA Gain (dB) = 20 log V0 / Vi dB Gain = V0 / Vi w w w .Electronic Circuits – I LAB sp ot .Model graph: Tabular column: VI = 50 mV Frequency (KHz) V0 (mV) ve .e ee ex ~ 35 ~ og EC2208 .

c o m .Electronic Circuits – I LAB w w w .e ee ex cl u si ve .η = Π  V min  1− 4 Vcc    Powergain = 1 Vcc 2   2  Π 2  RL  Result Thus a Class – B (complementary symmetry) power amplifier is constructed and the output waveforms are observed and the maximum power output and efficiency is calculated.b l og sp ot . Circuit diagram: ~ 36 ~ EC2208 .Formulae Efficiency.

b l ~ 37 ~ og 500Ω R sp ot + .25 V Vac EC2208 .e ee ex cl u si ve .Half Wave Rectifier without filter 12 1N 4007 230 V 0 12 500Ω R a + Vdc - + -100 µF /25V a Vac 12 1N 4007 230 V 0 12 w w w .Electronic Circuits – I LAB Half Wave Rectifier with filter m .c o 100 µF CRO .

b l Vac Vdc ~ 38 ~ Procedure og EC2208 . 50Hz source to the primary coil of the transformer and si (i) Without Capacitor r = ve Half wave rectifier . Apparatus Required 1. Diode 4. 3. 2. 5. 2. no: Date: Aim 9. To design a Half wave rectifier with simple capacitor filter. Multimeter 3.c o 500Ω-1/4W(carbon film resistors) m 230V / 12 – 0. Connect the half wave rectifier as shown in figure. Compare the theoretical ripple factor with the practical ripple factor. Capacitor 1N4007 (0-20 MHz) 7. Resistor 6. Transformer 5. 200 mA . To block DC component 100µf (Electrolytic) Condenser is used. Measure the Vdc & Vac using DC and AC Voltmeters. To measure the DC voltage under load and ripple factor and to compare with calculated values.Electronic Circuits – I LAB sp ot 100µF /25V . Note: The rectifier output consists of both AC & DC components.e ee ex cl u 1. Connecting Wires and Bread Board observe the AC waveform of rated value without any distortion at the secondary of the transformer. CRO 2.Ex. Calculate the Ripple factor w . w w 4. HALF WAVE RECTIFIER 1.12v. Test your transformer: Give 230v.

b l og sp ot Without filter With filter .e ee ex Half Wave Rectifier Output ~ 39 ~ m EC2208 .c o T(m sec) w w w .Model Graph VI(v) T(m sec) Vo (V) cl u si ve .Electronic Circuits – I LAB Input Wave Form .

4. Connect CRO across load. Diode 1N4007 2. Switch the CRO into DC mode and observe the waveform. Idc = 1A) (0-30). Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the X-axis. RPS w Specifications: w . 2. Assume r= 10% of ripple peak-to-peak voltage for R= 500Ω. .1A si og EC2208 .PIV. Connect the half wave rectifier with filter circuit as shown in fig.Electronic Circuits – I LAB sp ot Thus the Full wave rectifier is designed with and without capacitor filter and the corresponding dc output voltages and the ripple factors are measured and verified with the theoretical values.(ii) With capacitor 1.e ee ex cl u (700V.b l Practical ~ 40 ~ Ripple Factor w 1. Calculate C using the formula r = 1/2√3fRC 3.c o Result m . Theoretical ve . 5.

25 V a D2 a Vac 12V D1 230 V D3 1N 4007 si ve .c o m .e ee ex cl u og EC2208 .b l D2 D4 R + 100 µF CRO 25 V ~ 41 ~ w w w .Electronic Circuits – I LAB sp ot Full Wave Rectifier with filter .Circuit diagram: Full Wave Rectifier without filter 12V D1 230 V D3 1N 4007 D4 R 500Ω + Vdc + 100 µF .

To measure the DC voltage under load and ripple factor and to compare with calculated values. To block DC component 100µf (Electrolytic) Condenser is used. 2. Compare the theoretical ripple factor with the practical ripple factor. 5. Transformer 5. Capacitor 1N4007 (0-20 MHz) 7.Ex. 2. Multimeter 3. Resistor 6. FULL WAVE RECTIFIER 1.c o 500Ω-1/4W(carbon film resistors) m 230V / 12 – 0. To design a Full wave rectifier with and without simple capacitor filter. 3. w w si ve r = Vac Vdc .e Measure the Vdc & Vac using DC and AC Voltmeters. CRO 2. Connecting Wires and Bread Board Procedure Full wave rectifier (i) Without Capacitor 1.12v. 50Hz source to the primary coil of the transformer Note: The rectifier output consists of both AC&DC components.Electronic Circuits – I LAB sp ot 100µF /25V . ee ex cl u Test your transformer: Give 230v. Apparatus Required 1.b l ~ 42 ~ og EC2208 . no: Date: Aim 10. and observe the AC waveform of rated value without any distortion at the secondary of the transformer. Connect the full wave rectifier as shown in figure. Calculate the Ripple factor w . 200 mA . Diode 4. 4.

b l og Without filter w w w .Electronic Circuits – I LAB m Input Wave Form .e ee ex cl u si Full Wave Rectifier Output ve t (m sec) ~ 43 ~ sp ot .c o With filter EC2208 .Model graph: VI(v) t (m sec) VO (V) .

5W of resistance are to be connected in parallel.Electronic Circuits – I LAB 1. 4. Idc = 1A) (0-30).e ee Specifications: ex si ve ~ 44 ~ sp ot . 1A og Practical EC2208 .PIV.c o m .15 is assumed. Diode 1N4007 2.(ii) With capacitor: 1. Hence Idc = Vdc /( N X 500). To plot ripple peak-to-peak voltage Vs. Result Thus the Full wave rectifier is designed with and without capacitor filter and the corresponding dc output voltages and the ripple factors are measured and verified with the theoretical values. Idc to choose C a ripple factor of 0. Where N is number of 500Ω resistances connected in parallel. Ripple Factor Theoretical .b l cl u (700V. Plot the graph Idc Vs ripple peak to peak. To get a variable load resistance a number of 500Ω. 3. RPS w w w . 2. The above steps are repeated for the various values of capacitance.