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1/3 D.GNANA SAI DATTATREYA REDDY Mob No : 9493868985 Email : gnanasaibtech.sree22@gmail.com, gnanasai.dattatreya@amd.

com Objective: Seeking a challenging and growth oriented job in VLSI frontend to utilize my skills and abilities and a position that offers me professional growth while being resourceful, innovative and flexible.

SUMMARY:
Working at AMD as consultant from past 1 year and 8 months, through SoCtronics as ASIC Engineer. Worked on SoC Low power verification, which involved verification of system states and core states in multi voltage SoCs. Power aware Gate simulations, Setting up the GateCosim environment Worked at Soctronics on verifying OVM complaint USB 2.0 using System Verilog for 7 months

EDUCATIONAL QUALIFICATION:
B.Tech in Electronics and Communication with an aggregate of 65% from DRK Institue of Science and Technology, Bowrampet,Qutubullapur Mandal Hyderabad (JNTU) in June-2009 Intermediate (Maths, Physics, Chemistry) with First Class (89%) from Sri Chaithanya Junior College, Kukatpally, Hyderabad in June-2005 SSC with First Class (90.5%) from CAM (EM) High School, Gudur, Nellore in June-2003

TECHNICAL SKILLS:
Programming Languages Scripting Languages HDLs Relevant Concepts Tools used ACHEIVEMENTS: : : : : : C, C++ C-SHELL, PERL Verilog, System Verilog LEC, Synthesis VCS, Verdi

Received Spot Recognition Award from AMD for delivering results for the tasks assigned.

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PROJECT PROFILE:
PROJECT #1

Verification X86 processor at Block level


Languages Duration Role failures : Verilog, C++ : 10 months : Porting the testcases, running test cases and debugging the

Description : Verification of the net list using the Gates-Cosim.


As part of this ported the test cases, developed verification environment for GateCosim, debugged the failures and proposed some RTL coding guidelines which will avoid GateCosim mismatches For early verification of the SoC, all the blocks are merged together and created merged SoC net list and verified much before the full chip net list is available. PROJECT #2

Low power verification of next generation Fusion client SoC


Languages Duration Role : Verilog, System verilog, PERL : 9 months : Analyzing the specification Developing the test plan Developing the environment and test bench Verification of the functionality.

Description : This is a brand new product and it has many low power states, which
can be verified only at the SoC level. Developed the test plan, developed the voltage regulator model for client fusion SoC, and checkers for the checking the critical power signals, and successfully executed all the tasks.

3/3 PERSONAL PROFILE: Name Fathers Name Address Mob no Date of birth Sex Marital status Nationality Languages known : : : : : : : : : Gnana Sai Dattatreya Reddy Venkata Krishna Reddy Plot No:72, Sri Sai nagar, Ashok Nagar, Ramachandra Puram, Medak Dist, Andhra Pradesh 9493868985 Male Single Indian English, Telugu & Hindi (D. Gnana Sai Dattatreya Reddy)

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