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use ieee.std_logic_1164.all;
entity merg_fsm is
port
(
clk
: in std_logic;
inp_pattern
: in string(1 to 4);
--bcdf
virus_pattern1 : inout std_logic_vector(31 downto 0):="00000010000000110000010000000110";
--pcdg
virus_pattern2 : inout std_logic_vector(23 downto 0):="000100000000001100000111";
sub_pattern1 : inout std_logic_vector(7 downto 0);
sub_pattern2 : inout std_logic_vector(7 downto 0);
sub_pattern3 : inout std_logic_vector(7 downto 0)
);
end merg_fsm;
begin
process(inp_pattern)
begin
if inp_pattern(1)='b' then
end if;
if inp_pattern(2)='b' then
end if;
if inp_pattern(3)='b' then
end if;
if inp_pattern(4)='b' then
end if;
end process;
process(clk)
begin
end if;
end process;
process(inp_pattern,present_state,sub_pattern1,sub_pattern2,sub_pattern3,sub_pattern4,
virus_pattern1,virus_pattern2,pathvec_ifinal,prereg)
begin
case present_state is
when s0 =>
else
end if;
when s1 =>
else
end if;
else
end if;
else
end if;
when s4 =>
when s5 =>
else
end if;
when s8 =>
when others=>
end case;
end process;
end beh;