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Philips 8051

Philips 8051

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Published by: Omkar Shete on Jul 10, 2013
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INTEGRATED CIRCUITS

80C51/87C51/80C52/87C52 80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM
Product specification Replaces datasheet 80C51/87C51/80C31 of 2000 Jan 20 2000 Aug 07

Philips Semiconductors

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

DESCRIPTION
The Philips 80C51/87C51/80C52/87C52 is a high-performance static 80C51 design fabricated with Philips high-density CMOS technology with operation from 2.7 V to 5.5 V. The 8xC51 and 8xC52 contain a 128 × 8 RAM and 256 × 8 RAM respectively, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the device is a low power static design which offers a wide range of operating frequencies down to zero. Two software selectable modes of power reduction—idle mode and power-down mode are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data and then the execution resumed from the point the clock was stopped.

FEATURES

• 8051 Central Processing Unit
– 4k × 8 ROM (80C51) – 8k × 8 ROM (80C52) – 128 × 8 RAM (80C51) – 256 × 8 RAM (80C52) – Three 16-bit counter/timers – Boolean processor – Full static operation – Low voltage (2.7 V to 5.5 V@ 16 MHz) operation

• Memory addressing capability
– 64k ROM and 64k RAM

• Power control modes:
– Clock can be stopped and resumed – Idle mode – Power-down mode

SELECTION TABLE
For applications requiring more ROM and RAM, see the 8XC54/58 and 8XC51RA+/RB+/RC+/80C51RA+ data sheet. Note: 80C31/80C32 is specified in separate data sheet. ROM/EPROM Memory Size (X by 8) RAM Size (X by 8) Programmable Timer Counter (PCA) Hardware Watch Dog Timer

• CMOS and TTL compatible • TWO speed ranges at VCC = 5 V
– 0 to 16 MHz – 0 to 33 MHz

80C31*/80C51/87C51 0K/4K 80C32*/80C52/87C52 0K/8K/16K/32K 256 No No 128 No No

• Three package styles • Extended temperature ranges • Dual Data Pointers • Security bits:
– ROM (2 bits) – OTP/EPROM (3 bits)

80C51RA+/8XC51RA+/RB+/RC+ 0K/8K/16K/32K 8XC51RD+ 64K 1024 Yes Yes 512 Yes Yes

• Encryption array – 64 bytes • 4 level priority interrupt • 6 interrupt sources • Four 8-bit I/O ports • Full–duplex enhanced UART
– Framing error detection – Automatic address recognition

• Programmable clock out • Asynchronous port reset • Low EMI (inhibit ALE and slew rate controlled outputs) • Wake-up from Power Down by an external interrupt

2000 Aug 07

2

853–0169 24291

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low power, high speed (33 MHz), 128/256 B RAM

80C51/87C51/80C52/87C52

80C51/87C51 ORDERING INFORMATION
MEMORY SIZE 4K × 8 ROM OTP ROM OTP ROM OTP ROM OTP ROM OTP ROM OTP ROM OTP ROM OTP ROM OTP P80C51SBPN 0 to +70 +70, Plastic Dual In In-line line Package P87C51SBPN P80C51SBAA +70 Plastic Leaded Chip Carrier 0 to +70, P87C51SBAA P80C51SBBB 0 to +70 +70, Plastic Quad Flat Pack P87C51SBBB P80C51SFP N –40 40 to +85 +85, Plastic Dual In In-line line Package P87C51SFP N P80C51SFA A –40 40 to +85, +85 Plastic Leaded Chip Carrier P87C51SFA A P80C51SFB B –40 40 to +85 +85, Plastic Quad Flat Pack P87C51SFB B P80C51UBAA 0 to +70, +70 Plastic Leaded Chip Carrier P87C51UBAA P80C51UBPN 0 to +70 +70, Plastic Dual In In-line line Package P87C51UBPN P80C51UFA A P87C51UFA A –40 40 to +85, +85 Plastic Leaded Chip Carrier 5V 0 to 33 SOT187 2 SOT187-2 5V 0 to 33 SOT129 1 SOT129-1 5V 0 to 33 SOT187 2 SOT187-2 2 7 V to 5.5 2.7 55V 0 to 16 SOT307 2 SOT307-2 2 7 V to 5.5 2.7 55V 0 to 16 SOT187 2 SOT187-2 2 7 V to 5.5 2.7 55V 0 to 16 SOT129 1 SOT129-1 2 7 V to 5.5 2.7 55V 0 to 16 SOT307 2 SOT307-2 2 7 V to 5.5 55V 2.7 0 to 16 SOT187 2 SOT187-2 2 7 V to 5.5 2.7 55V 0 to 16 SOT129 1 SOT129-1 TEMPERATURE RANGE °C AND PACKAGE VOLTAGE RANGE FREQ. (MHz) DWG. #

PART NUMBER DERIVATION
DEVICE NUMBER ROM ROM OTP OTP DEVICE NUMBER P80C51 P80C52 P87C51 P87C52 OPERATING FREQUENCY, MAX (S) S = 16 MHz S = 16 MHz U = 33 MHz U = 33 MHz TEMPERATURE RANGE (B) B = 0_ to +70_C B = 0_ to +70_C F = –40_C to +85_C F = –40_C to +85_C PACKAGE (AA) AA = PLCC AA = PLCC BB = PQFP BB = PQFP

2000 Aug 07

3

5 2. (MHz) DWG. Plastic Dual In In-line line Package P87C52SBPN P80C52SBAA +70 Plastic Leaded Chip Carrier 0 to +70. P87C52SBAA P80C52SBBB 0 to +70 +70.7 V–5.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. +85 Plastic Leaded Chip Carrier 5V 0 to 33 SOT187 2 SOT187-2 5V 0 to 33 SOT129 1 SOT129-1 5V 0 to 33 SOT187 2 SOT187-2 2 7 V to 5. Plastic Dual In In-line line Package P87C52SFP N P80C52SFA A –40 40 to +85. Plastic Quad Flat Pack P87C52SFB B P80C52UBAA 0 to +70.7 55V 0 to 16 SOT187 2 SOT187-2 2 7 V to 5.7 55V 0 to 16 SOT129 1 SOT129-1 2 7 V to 5. high speed (33 MHz).5 2. Plastic Quad Flat Pack P87C52SBBB P80C52SFP N –40 40 to +85 +85.7 0 to 16 SOT187 2 SOT187-2 2 7 V to 5.7 55V 0 to 16 SOT129 1 SOT129-1 TEMPERATURE RANGE °C AND PACKAGE VOLTAGE RANGE FREQ.5 2.5 55V 2. Plastic Dual In In-line line Package P87C52UBPN P80C52UFA A P87C52UFA A –40 40 to +85. +70 Plastic Leaded Chip Carrier P87C52UBAA P80C52UBPN 0 to +70 +70.5 2.5 V).7 55V 0 to 16 SOT307 2 SOT307-2 2 7 V to 5. +85 Plastic Leaded Chip Carrier P87C52SFA A P80C52SFB B –40 40 to +85 +85. low power. 128/256 B RAM 80C51/87C51/80C52/87C52 80C52/87C52 ORDERING INFORMATION MEMORY SIZE 8K × 8 ROM OTP ROM OTP ROM OTP ROM OTP ROM OTP ROM OTP ROM OTP ROM OTP ROM OTP P80C52SBPN 0 to +70 +70. # 2000 Aug 07 4 .7 55V 0 to 16 SOT307 2 SOT307-2 2 7 V to 5.5 2.

Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. high speed (33 MHz).7 PORT 3 DRIVERS P3. low power.0–P2.0–P1.7 V–5.7 P2.7 PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER RAM PORT 0 LATCH PORT 2 DRIVERS PORT 2 LATCH ROM/EPROM 8 B REGISTER STACK POINTER ACC TMP2 TMP1 PROGRAM ADDRESS REGISTER ALU SFRs PSW TIMERS BUFFER PC INCREMENTER 8 PROGRAM COUNTER 16 PSEN ALE/PROG EAVPP RST PD TIMING AND CONTROL INSTRUCTION REGISTER DPTR’S MULTIPLE PORT 1 LATCH PORT 3 LATCH OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 P1. 128/256 B RAM 80C51/87C51/80C52/87C52 BLOCK DIAGRAM P0.0–P3.0–P0.7 SU00845 2000 Aug 07 5 .5 V).

6 P1.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.3/AD3 P0.1/AD1 P0.5 P1.7/A15 PSEN ALE NIC* EA/VPP P0.6/A14 26 P2.7/AD7 22 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.7 RST P3.7/RD XTAL2 XTAL1 VSS NIC* P2.2/AD2 P0. 128/256 B RAM 80C51/87C51/80C52/87C52 LOGIC SYMBOL VCC XTAL1 PORT 0 ADDRESS AND DATA BUS VSS PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS 6 1 40 7 39 LCC XTAL2 T2 T2EX RST EA/VPP PSEN SECONDARY FUNCTIONS ALE/PROG RxD TxD INT0 INT1 T0 T1 WR RD PORT 1 17 29 18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NIC* P1.1 2 P1.7 V–5.3/INT1 P3.1 11 INT0/P3.7 17 XTAL2 18 XTAL1 19 VSS 20 DUAL IN-LINE PACKAGE 40 VCC 39 P0.2/INT0 P3.7/RD XTAL2 XTAL1 12 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VSS NIC* P2.0/AD0 38 P0.6/AD6 P0.4/AD4 P0.0/AD0 VCC NIC* P1.0/RxD NIC* P3.2 12 INT1/P3.2/AD2 P0.0/A8 P2.1/T2EX P1.5 6 P1.4/AD4 P0.0 10 TxD/P3.6/AD6 32 P0.5/AD5 33 P0.3 4 P1.3 P1.3 P1.0/A8 P2.6/WR P3.4/T0 P3.4 14 T1/P3.2/A10 P2.2 P1.5 15 WR/P3.1/A9 P2.2 P1.5/A13 P2.4 P1.3/INT1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function P3.6/A14 P2.6 7 P1.0/AD0 VCC PORT 3 PORT 2 ADDRESS BUS SU00830 PIN CONFIGURATIONS T2/P1.5/AD5 P0.3 13 T0/P3.6 P1.1/AD1 * NO INTERNAL CONNECTION SU01062 PLASTIC QUAD FLAT PACK PIN FUNCTIONS 44 34 37 P0.5/A13 P2.6 16 RD/P3. high speed (33 MHz).6/AD6 P0.2 3 P1.0/T2 P1.7/A15 27 P2.0/A8 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.7 RST P3.1/A9 21 P2.7/AD7 P0.7/AD7 31 EA/VPP 30 ALE 29 PSEN 28 P2.5/A13 25 P2.5/T1 P3.5 V).2/INT0 P3.4/AD4 34 P0.4/A12 24 P2.1/A9 P2.3/A11 P2.4 11 23 PQFP 33 SU01063 * NO INTERNAL CONNECTION SU01064 2000 Aug 07 6 .5/AD5 P0.3/A11 P2.4 5 P1.3/AD3 1 35 P0.6/A14 28 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2. low power.6/WR P3.7 8 RST 9 RxD/P3.7/A15 PSEN ALE NIC* EA/VPP P0.1/TxD P3.4/A12 P2.2/A10 22 P2.5/T1 P3.4/A12 P2.1/T2EX P1.0/T2 P1.0 1 T2EX/P1.5 P1.0/RxD NIC* P3.2/A10 P2.4/T0 P3.1/AD1 P0.3/A11 23 P2.2/AD2 36 P0.3/AD3 P0.1/TxD P3.

Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. Port 0: Port 0 is an open-drain.5 V or VSS – 0. Some Port 2 pins receive the high order address bits during EPROM programming and verification. Alternate functions for Port 1 include: T2 (P1. ALE will be active only during a MOVX instruction. ALE can be disabled by setting SFR auxiliary. (See DC Electrical Characteristics: IIL). as listed below: RxD (P3.0–0. and can be used for external timing or clocking. During accesses to external data memory that use 8-bit addresses (MOV @Ri).1): Serial output port INT0 (P3. low power. PSEN is activated twice each machine cycle. it uses strong internal pull-ups when emitting 1s. 13–19 5.6): External data memory write strobe RD (P3. (See DC Electrical Characteristics: IIL). Program Store Enable: The read strobe to external program memory.5): Timer 1 external input WR (P3.0): Serial input port TxD (P3. port 3 pins that are externally being pulled low will source current because of the pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. high speed (33 MHz). Port 0 also outputs the code bytes during program verification and received code bytes during EPROM programming. port 2 emits the contents of the P2 special function register. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to 0FFFH.5 V). External pull-ups are required during program verification.7 1 2 21–28 2 3 24–31 40 41 18–25 I/O I I/O P3. PSEN is not activated during fetches from internal program memory. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. except that two PSEN activations are skipped during each access to external data memory.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running. (See DC Electrical Characteristics: IIL).75 V programming supply voltage (VPP) during EPROM programming. Crystal 2: Output from the inverting oscillator amplifier. the device executes from internal program memory unless the program counter contains an address greater than the on-chip ROM/OTP. Port 1 also receives the low-order address byte during program memory verification. In this application.5 V.7 10–17 11. EA will be internally latched on Reset. bidirectional I/O port with Schmitt trigger inputs.0–P3.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. ALE is emitted at a constant rate of 1/6 the oscillator frequency. 1–3 I/O P2.7 1–8 2–9 40–44.7 39–32 LCC 22 44 43–36 QFP 16 38 37–30 TYPE I I I/O NAME AND FUNCTION Ground: 0 V reference. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger inputs.0–P1. and power-down operation.0–P2. P1. This pin also receives the 12. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger inputs. This pin is also the program pulse input (PROG) during EPROM programming.3): External interrupt T0 (P3. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. the voltage on any pin at any time must not be higher than VCC + 0. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. When the device is executing code from the external program memory. Power Supply: This is the power supply voltage for normal. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). 2000 Aug 07 7 . Port 3 also serves the special features of the 80C51 family. With this bit set. port 1 pins that are externally pulled low will source current because of the internal pull-ups. respectively. As inputs. port 2 pins that are externally being pulled low will source current because of the internal pull-ups. In this application.7 V–5.0. If EA is held high. idle. As inputs. Note that one ALE pulse is skipped during each access to external data memory.1): Timer/Counter 2 Reload/Capture/Direction control Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger inputs. If security bit 1 is programmed. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. As inputs.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out) T2EX (P1. it uses strong internal pull-ups when emitting 1s.4): Timer 0 external input T1 (P3. 128/256 B RAM 80C51/87C51/80C52/87C52 PIN DESCRIPTIONS PIN NUMBER MNEMONIC DIP VSS 20 VCC 40 P0.2): External interrupt INT1 (P3. In normal operation. 7–13 I/O RST 10 11 12 13 14 15 16 17 9 11 13 14 15 16 17 18 19 10 5 7 8 9 10 11 12 13 4 I O I I I I O O I ALE/PROG 30 33 27 O PSEN 29 32 26 O EA/VPP 31 35 29 I XTAL1 19 21 15 I XTAL2 18 20 14 O NOTE: To avoid “latch-up” effect at power-on. resets the device.

OR ALTERNATIVE PORT FUNCTION MSB LSB E7 E6 E5 E4 E3 E2 E1 E0 – – – – – – – AO – – – LPEP2 WUPD 0 – DPS F7 F6 F5 F4 F3 F2 F1 F0 RESET VALUE 00H xxxxxxx0B xxx000x0B 00H 00H 00H 0x000000B xx000000B xx000000B FFH FFH FFH FFH 00xx0000B 000000x0B 00H 00H 00H 00H xxxxxxxxB 00H 07H 00H 00H xxxxxx00B 00H 00H 00H 00H 00H 00H 00H 9F SM0/FE 9E SM1 8E TR1 CE EXF2 – 9D SM2 8D TF0 CD RCLK – 9C REN 8C TR0 CC TCLK – 9B TB8 8B IE1 CB EXEN2 – 9A RB8 8A IT1 CA TR2 – 99 TI 89 IE0 C9 C/T2 T2OE 98 RI 88 IT0 C8 CP/RL2 DCEN T2CON* Timer 2 Control C8H T2MOD# Timer 2 Mode Control C9H TH0 Timer High 0 8CH TH1 Timer High 1 8DH TH2# Timer High 2 CDH TL0 Timer Low 0 8AH TL1 Timer Low 1 8BH TL2# Timer Low 2 CCH TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 NOTE: Unused register bits that are not defined should not be set by the user’s program. the device could function incorrectly. – Reserved bits. high speed (33 MHz). SYMBOL. * SFRs are bit addressable. low power.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.5 V). 1.7 V–5. # SFRs are modified from or added to the 80C51 SFRs. 128/256 B RAM 80C51/87C51/80C52/87C52 Table 1. Reset value depends on reset source. If violated. LPEP – Low Power EPROM operation (OTP/EPROM only) 8F TF1 CF TF2 – 2000 Aug 07 8 . SYMBOL ACC* AUXR# AUXR1# B* DPTR: DPH DPL IE* IP* IPH# P0* P1* P2* P3* PCON#1 PSW* RACAP2H# RACAP2L# SADDR# SADEN# SBUF SCON* SP TCON* 80C51/87C51/80C52/87C52 Special Function Registers DESCRIPTION Accumulator Auxiliary Auxiliary 1 B register Data Pointer (2 bytes) Data Pointer High Data Pointer Low Interrupt Enable Interrupt Priority Interrupt Priority High Port 0 Port 1 Port 2 Port 3 Power Control Program Status Word Timer 2 Capture High Timer 2 Capture Low Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control DIRECT ADDRESS E0H 8EH A2H F0H 83H 82H A8H B8H B7H 80H 90H A0H B0H 87H D0H CBH CAH A9H B9H 99H 98H 81H 88H AF EA BF – B7 – 87 AD7 97 – A7 AD15 B7 RD SMOD1 D7 CY AE – BE – B6 – 86 AD6 96 – A6 AD14 B6 WR SMOD0 D6 AC AD ET2 BD PT2 B5 PT2H 85 AD5 95 – A5 AD13 B5 T1 – D5 F0 AC ES BC PS B4 PSH 84 AD4 94 – A4 AD12 B4 T0 POF D4 RS1 AB ET1 BB PT1 B3 PT1H 83 AD3 93 – A3 AD11 B3 INT1 GF1 D3 RS0 AA EX1 BA PX1 B2 PX1H 82 AD2 92 – A2 AD10 B2 INT0 GF0 D2 OV A9 ET0 B9 PT0 B1 PT0H 81 AD1 91 T2EX A1 AD9 B1 TxD PD D1 – A8 EX0 B8 PX0 B0 PX0H 80 AD0 90 T2 A0 AD8 B0 RxD IDL D0 P BIT ADDRESS. 2.

Design Consideration • When the idle mode is terminated by a hardware reset. The CPU contents. because the input to the internal clock circuitry is through a divide-by-two flip-flop. Pull ALE low while the device is in reset and PSEN is high. On-chip hardware inhibits access to internal RAM in this event. While the device is in ONCE Mode. For lowest power consumption the Power Down mode is suggested. The ONCE Mode is invoked by: 1. This bit should be set ONLY for applications that operate at a VCC less than 4 V.7 V–5. The on-chip RAM and Special Function Registers retain their values down to 2. but are required for a VCC greater than 4 V. from where it left off. and the other port pins and ALE and PSEN are weakly pulled high. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. INT0 or INT1 must be enabled and configured as level-sensitive. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued). the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. The oscillator circuit remains active. the SFRs but does not change the on-chip RAM. To drive the device from an external clock source. the RAM and Special Function Registers retain their values. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Hold ALE low as RST is deactivated. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. There are no requirements on the duty cycle of the external clock signal. To insure a good power-up reset. the on-chip RAM. With an external interrupt. Power-Down Mode To save even more power. Reset A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods). as shown in the logic symbol. the device normally resumes program execution. when set. an emulator or test CPU can be used to drive the circuit. of an inverting amplifier. While the device is in this mode. The pins can be configured for use as an on-chip oscillator. while the oscillator is running. the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. high speed (33 MHz). XTAL1 should be driven while XTAL2 is left unconnected. However. or by a hardware reset which starts the processor in the same manner as a power-on reset.4). will powerdown these analog circuits resulting in a reduced supply current.5 V). minimum and maximum high and low times specified in the data sheet must be observed. Normal operation is restored when a normal reset is applied. WUPD (AUXR1. For the 87C51 and 80C51 either a hardware reset or external interrupt can be used to exit from Power Down. low power. up to two machine cycles before the internal reset algorithm takes control. Once the interrupt is serviced. and all of the special function registers remain intact during this mode. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. Stop Clock Mode The static design enables the clock speed to be reduced down to 0 MHz (stopped). Idle Mode In idle mode (see Table 2). Where: WUPD = 0 Disable WUPD = 1 Enable To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). LPEP The eprom array contains some analog circuits that are not required when VCC is less than 4 V. the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down. a Power Down mode (see Table 2) can be invoked by software. Reset redefines all Table 2. respectively. but access to the port pins is not inhibited. the CPU puts itself to sleep while all of the on-chip peripherals stay active. In this mode.0 V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down Mode is terminated. The LPEP bit (AUXR.3–Wakeup from Power Down) enables or disables the wakeup from power down with external interrupt.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. 2. 128/256 B RAM 80C51/87C51/80C52/87C52 OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output. External Pin Status During Idle and Power-Down Modes MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data 2000 Aug 07 9 . To eliminate the possibility of an unexpected write when Idle is terminated by reset. ONCE™ Mode The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. the Port 0 pins go into a float state. When the oscillator is stopped.

If DCEN bit is set. and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. This mode allows pin T2EX to control the direction of count. TL2 and Table 3. In addition. In this mode there are two options selected by bit EXEN2 in T2CON register. as selected by C/T2* in the special function register T2CON (see Figure 1). then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which. When a logic 1 is applied at pin T2EX Timer 2 will count up. The external flag EXF2 toggles when Timer 2 underflows or overflows. the counter keeps on counting T2EX pin transitions or osc/12 pulses. bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. To configure the Timer/Counter 2 as a clock generator. then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow.5 V). Note. upon overflowing sets bit TF2. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register).RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. low power. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency.and Baud Rate Generator. When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. Timer 2 will overflow at 0FFFFH and set the TF2 flag. if enabled. This pin. Even when a capture event occurs from T2EX. the transition at T2EX causes bit EXF2 in T2CON to be set.).0. which can then generate an interrupt. which are selected by bits in the T2CON as shown in Table 3. to input the external clock for Timer/Counter 2. The EXF2 flag does not generate an interrupt in this mode of operation. respectively. then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. When reset is applied the DCEN=0 which means Timer 2 will default to counting up. It can be programmed: 1.to -0 transition at external input T2EX causes the current value in the Timer 2 registers. Timer 2 Operating Modes RCLK + TCLK 0 0 1 X CP/RL2 0 1 X X TR2 1 1 1 0 16-bit Auto-reload 16-bit Capture Baud rate generator (off) MODE 2000 Aug 07 10 . The Timer 2 interrupt. If EXEN2=0. This EXF2 bit can be used as a 17th bit of resolution if needed.7 V–5. TIMER 2 OPERATION Timer 2 Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter. If EXEN2= 1.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. Bit TR2 (T2CON. Timer 2 has three operating modes:Capture. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. besides being a regular I/O pin. however. Figure 4 shows Timer 2 which will count up automatically since DCEN=0. Auto-Reload Mode (Up or Down Counter) In the 16-bit auto-reload mode. If EXEN2=0. high speed (33 MHz). can be generated when either TF2 or EXF2 are 1. has two alternate functions. or 2. The values in RCAP2L and RCAP2H are preset by software means. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H. RCAP2L) TH2. Oscillator Frequency (65536 * RCAP2H. if the interrupt is enabled. 128/256 B RAM 80C51/87C51/80C52/87C52 Programmable Clock-Out A 50% duty cycle clock can be programmed to come out on P1. that the baud-rate and the Clock-Out frequency will be the same. If EXEN2=1. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. RCAP2L) as shown in this equation: 4 Where: (RCAP2H. This transition also sets the EXF2 bit. The capture mode is illustrated in Figure 2 (There is no reload value for TL2 and TH2 in this mode. This is similar to when it is used as a baud-rate generator. to be captured into registers RCAP2L and RCAP2H.2) also must be set to start the timer. This timer overflow also causes the 16–bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. Timer 2 can be configured (as either a timer or counter (C/T2* in T2CON)) then programmed to count up or down. but with the added feature that a 1. Timer 2 operates as described above. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see Figure 3). Auto-reload (up or down counting) . the timer 2 overflow bit. Timer 2 can count up or down depending on the value of the T2EX pin. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. Capture Mode In the capture mode there are two options which are selected by bit EXEN2 in T2CON.

Timer/Counter 2 (T2CON) Control Register OSC ÷ 12 C/T2 = 0 TL2 (8-bits) C/T2 = 1 TH2 (8-bits) TF2 T2 Pin Control TR2 Transition Detector Capture Timer 2 Interrupt RCAP2L RCAP2H T2EX Pin EXF2 Control EXEN2 SU00066 Figure 2. 128/256 B RAM 80C51/87C51/80C52/87C52 (MSB) TF2 Symbol TF2 EXF2 Position T2CON.5 V). RCLK = 0 causes Timer 1 overflow to be used for the receive clock. When Timer 2 interrupt is enabled.7 V–5. causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. EXF2 must be cleared by software. Timer or counter select. Start/stop control for Timer 2. When either RCLK = 1 or TCLK = 1. When set. SU00728 RCLK TCLK EXEN2 T2CON.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TF2 will not be set when either RCLK or TCLK = 1. captures will occur on negative transitions at T2EX if EXEN2 = 1.7 T2CON.5 T2CON.1 CP/RL2 T2CON.4 T2CON.2 T2CON. EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. When set. Timer 2 external enable flag. When cleared. A logic 1 starts the timer. auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When set.6 EXF2 RCLK TCLK EXEN2 TR2 C/T2 (LSB) CP/RL2 Name and Significance Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. low power. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Timer 2 in Capture Mode 2000 Aug 07 11 . Receive clock flag.3 TR2 C/T2 T2CON. Transmit clock flag.0 Figure 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. high speed (33 MHz). (Timer 2) 0 = Internal timer (OSC/12) 1 = External event counter (falling edge triggered). When set. Capture/Reload flag.

Figure 3.5 V). and its active value will be 1. this allows Timer 2 to be configured as an up/down counter. Down Count Enable bit. reserved for future use. low power.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. Timer 2 in Auto-Reload Mode (DCEN = 0) 2000 Aug 07 12 .* Timer 2 Output Enable bit. 128/256 B RAM 80C51/87C51/80C52/87C52 T2MOD Address = 0C9H Not Bit Addressable — Bit 7 — 6 — 5 — 4 — 3 — 2 T2OE 1 Reset Value = XXXX XX00B DCEN 0 Symbol — T2OE DCEN * Function Not implemented. high speed (33 MHz). The value read from a reserved bit is indeterminate. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case. Timer 2 Mode (T2MOD) Control Register SU00729 OSC ÷ 12 C/T2 = 0 TL2 (8-BITS) C/T2 = 1 TH2 (8-BITS) T2 PIN CONTROL TR2 RELOAD TRANSITION DETECTOR RCAP2L RCAP2H TF2 TIMER 2 INTERRUPT T2EX PIN EXF2 CONTROL EXEN2 SU00067 Figure 4. the reset or inactive value of the new bit will be 0. When set.7 V–5.

Freq.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.5 V). low power. is divided by 2. ÷2 C/T2 = 0 TL2 (8-bits) C/T2 = 1 T2 Pin Control TH2 (8-bits) “1” ÷2 “0” “1” SMOD “0” RCLK OSC ÷ 16 TR2 “1” Reload “0” RX Clock TCLK Transition Detector RCAP2L RCAP2H ÷ 16 TX Clock T2EX Pin EXF2 Timer 2 Interrupt Control EXEN2 Note availability of additional external interrupt. 128/256 B RAM 80C51/87C51/80C52/87C52 (DOWN COUNTING RELOAD VALUE) FFH FFH TOGGLE EXF2 OSC ÷12 C/T2 = 0 OVERFLOW TL2 TH2 TF2 INTERRUPT T2 PIN C/T2 = 1 CONTROL TR2 COUNT DIRECTION 1 = UP 0 = DOWN RCAP2L RCAP2H T2EX PIN (UP COUNTING RELOAD VALUE) SU00730 Figure 5. Timer 2 in Baud Rate Generator Mode 2000 Aug 07 13 . SU00068 Figure 6.7 V–5. high speed (33 MHz). Timer 2 Auto Reload Mode (DCEN = 1) Timer 1 Overflow NOTE: OSC. not 12.

. under these conditions. Timer 2 Generated Commonly Used Baud Rates Timer 2 Osc Freq 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 6 MHz 6 MHz RCAP2H FF FF FF FF FE FB F2 FD F9 RCAP2L FF D9 B2 64 C8 1E AF 8F 57 Ba d Rate Baud 375 K 9. because a write might overlap a reload and cause write and/or reload errors. the above equation can be rewritten as: RCAP2H. Usually. if needed. Thus.e. a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H. As a baud rate generator. but should not be written to. RCAP2L)]] Where: (RCAP2H. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Also see Table 6 for set-up of Timer 2 as a counter. The baud rates in modes 1 and 3 are determined by Timer 2’s overflow rate given below: Modes 1 and 3 Baud Rates + Timer 2 Overflow Rate 16 The timer can be configured for either “timer” or “counter” operation. which are preset by software. As a baud rate generator.8 K 2. bit TR2 must be set. the baud rate is: Baud Rate + f OSC [65536 * (RCAP2H. The baud rate generation mode is like the auto-reload mode. Note that a rollover in TH2 does not set TF2. to turn the timer on.7 V–5. separately. RCLK has the same effect for the serial port receive baud rate. the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. In many applications. T2EX can be used as an additional external interrupt. With these two bits.TL2). 2000 Aug 07 14 .6 K 2. the other by Timer 2. the values given for T2CON do not include the setting of the TR2 bit. RCAP2L + 65536 * ǒ 32 f OSC Baud Rate Ǔ Timer/Counter 2 Set-up Except for the baud rate generator mode. Timer 2 is used as the serial port transmit baud rate generator. The RCAP2 registers may be read.5 V). Therefore when Timer 2 is in use as a baud rate generator. When TCLK= 1. as a timer it would increment every machine cycle (i. in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L. Timer 1 is used as the serial port transmit baud rate generator. RCAP2L)= The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Table 4. The Timer 2 as a baud rate generator mode shown in Figure 6. is valid only if RCLK and/or TCLK = 1 in T2CON register. Table 4 shows commonly used baud rates and how they can be obtained from Timer 2. one should not try to read or write TH2 and TL2.2 K 300 110 300 110 Summary Of Baud Rate Equations Timer 2 is in baud rate generating mode. 1/12 the oscillator frequency).Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. and will not generate an interrupt. it increments every state time (i. Timer operation is different for Timer 2 when it is being used as a baud rate generator. RCAP2L) to (TH2. 1/2 the oscillator frequency). high speed (33 MHz). When Timer 2 is in the baud rate generator mode. Figure 6 shows the Timer 2 in baud rate generation mode.. the serial port can have different receive and transmit baud rates – one generated by Timer 1. Therefore.0) the baud rate is: Baud Rate + Timer 2 Overflow Rate 16 If Timer 2 is being clocked internally. If Timer 2 is being clocked through pin T2(P1. RCAP2L)]] [32 Where fOSC= Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L. Timer 2 is incremented every state time (osc/2) or asynchronously from pin T2. a read or write of TH2 or TL2 may not be accurate.4 K 1. Thus the baud rate formula is as follows: Modes 1 and 3 Baud Rates = Oscillator Frequency [32 [65536 * (RCAP2H. it is configured for “timer” operation (C/T2*=0). See Table 5 for set-up of Timer 2 as a timer. 128/256 B RAM 80C51/87C51/80C52/87C52 Baud Rate Generator Mode Bits TCLK and/or RCLK in T2CON (Table 3) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2.e. Also if the EXEN2 (T2 external enable flag) is set. low power. When TCLK= 0.

Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. Two special Function Registers are used to define the slave’s address.5 V). and automatic address recognition. The UART also fully supports multiprocessor communication. The FE bit shares the SCON. Timer 2 as a Counter MODE 16-bit Auto-Reload TMOD INTERNAL CONTROL (Note 1) 02H 03H EXTERNAL CONTROL (Note 2) 0AH 0BH NOTES: 1. Use of the Given address allows multiple slaves to be recognized while excluding others. A missing bit will set the FE bit in the SCON register. Automatic address recognition is shown in Figure 9. SADEN is used to define which bits in the 2000 Aug 07 15 SADDR are to b used and which bits are “don’t care”. Enhanced UART The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. Timer 2 as a Timer MODE 16-bit Auto-Reload 16-bit Capture Baud rate generator receive and transmit same baud rate Receive only Transmit only T2CON INTERNAL CONTROL (Note 1) 00H 01H 34H 24H 14H EXTERNAL CONTROL (Note 2) 08H 09H 36H 26H 16H Table 6. low power. mode 2 and mode 3. If SMOD0 is set then SCON. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. To select Slaves 0 . All of the slaves may be contacted by using the Broadcast address. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. When used for framing error detect the UART looks for missing stop bits in the communication.7 bit with SM0 and the function of SCON. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Refer to Figure 8. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101.6 (SMOD0) (see Figure 7). SCON.7 can only be cleared by software. Slave 0 requires a 0 in bit 0 and it ignores bit 1. both could be addressed with 1100 0000.7 is determined by PCON. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011.7 functions as SM0 when SMOD0 is cleared. and the address mask. This feature is enabled by setting the SM2 bit in SCON.7 functions as FE. Mode 0 is the Shift Register mode and SM2 is ignored. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. In the 9 bit UART modes. Thus. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port.7 V–5. 80C51-Based 8-Bit Microcontrollers. 2. In addition the UART can perform framing error detect by looking for missing stop bits. high speed (33 MHz). In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 1110 0000 1111 1010 1110 0X0X 1110 0000 1111 1100 1110 00XX Slave 1 Slave 2 In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. Capture/reload occurs only on timer/counter overflow. SADEN. The 8 bit mode is called Mode 1. SADDR. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. When used as FE SCON. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1101 1100 00X0 1100 0000 1111 1110 1100 000X Slave 1 In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves.1) pin except when Timer 2 is used in the baud rate generator mode. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. 128/256 B RAM 80C51/87C51/80C52/87C52 Table 5. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.

and the received byte is a Given or Broadcast Address. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1. and the received byte is a Given or Broadcast Address. The FE bit is not cleared by valid frames but should be cleared by software. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. **fOSC = oscillator frequency SU00043 Figure 7. RB8 is the stop bit that was received. or halfway through the stop bit time in the other modes. RB8 is not used. Receive interrupt flag. The 9th data bit that will be transmitted in Modes 2 and 3. REN TB8 RB8 Tl Rl NOTE: *SMOD0 is located at PCON6. SM2 should be 0. in any serial reception (except see SM2). In Mode 1. (SMOD0 must = 0 to access bit SM0) Serial Port Mode Bit 1 SM0 SM1 Mode 0 0 1 1 0 1 0 1 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate** fOSC/12 variable fOSC/64 or fOSC/32 variable SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. if SM2 = 0. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. 128/256 B RAM 80C51/87C51/80C52/87C52 and 1 and exclude Slave 2 use address 1110 0100. Clear by software to disable reception. In Mode 1. Must be cleared by software. the 9th data bit that was received. Serial Port Mode Bit 0. Set by hardware at the end of the 8th bit time in Mode 0. The SMOD0 bit must be set to enable access to the FE bit. Enables serial reception. or at the beginning of the stop bit in the other modes. Set by hardware at the end of the 8th bit time in Mode 0. since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address will be FF hexadecimal.7 V–5. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. in any serial transmission. Zeros in this result are trended as don’t-cares.5 V). In most cases. interpreting the don’t-cares as ones. indicating an address. This bit is set by the receiver when an invalid stop bit is detected. SCON Address = 98H Bit Addressable SM0/FE Bit: SM1 SM2 5 REN 4 Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. Must be cleared by software. Reset Value = 0000 0000B TB8 3 RB8 2 Tl 1 Rl 0 7 6 (SMOD0 = 0/1)* Symbol FE SM0 SM1 Function Framing Error bit. Set or clear by software as desired. In Mode 0. low power. In Mode 0. In modes 2 and 3. high speed (33 MHz). SCON: Serial Port Control Register 2000 Aug 07 16 .Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. if SM2 = 1 then Rl will not be activated unless a valid stop bit was received. Set by software to enable reception. Transmit interrupt flag.

low power.7 = FE SU01191 Figure 8. CLEAR SM2 TO RECEIVE DATA BYTES – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. 128/256 B RAM 80C51/87C51/80C52/87C52 D0 D1 D2 D3 D4 D5 D6 D7 D8 START BIT DATA BYTE ONLY IN MODE 2. UART Multiprocessor Communication. high speed (33 MHz). SU00045 Figure 9.5 V).7 V–5. 3 STOP BIT SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL SM0 / FE SM1 SM2 REN TB8 RB8 TI RI SCON (98H) SMOD1 SMOD0 – POF GF1 GF0 PD IDL PCON (87H) 0 : SCON. UART Framing Error Detection D0 D1 D2 D3 D4 D5 D6 D7 D8 SM0 1 1 SM1 1 0 SM2 1 REN 1 TB8 X RB8 TI RI SCON (98H) RECEIVED ADDRESS D0 TO D7 PROGRAMMED ADDRESS COMPARATOR IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1.7 = SM0 1 : SCON.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. Automatic Address Recognition 2000 Aug 07 17 . RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS” – WHEN OWN ADDRESS RECEIVED.

) The IPH (Interrupt Priority High) register that makes the four-level interrupt structure possible. the new interrupt will wait until it is finished before being serviced.0 SYMBOL EA — ET2 ES ET1 EX1 ET0 EX0 FUNCTION Global disable bit.7 V–5. The structure of the IPH register and a description of its bits is shown in Figure 12. high speed (33 MHz). They are the IE. External interrupt 1 enable bit. Interrupt Table POLLING PRIORITY 1 2 3 4 5 6 REQUEST BITS IE0 TP0 IE1 TF1 RI. each interrupt can be individually enabled or disabled by setting or clearing its enable bit. If an interrupt of equal or higher level priority is being serviced. 128/256 B RAM 80C51/87C51/80C52/87C52 Interrupt Priority Structure The 80C51/87C51 and 80C52/87C52 have a 6-source four-level interrupt structure. Not implemented. External interrupt 0 enable bit. EXF2 HARDWARE CLEAR? N (L)1 Y N (L) Y (T) Y N N Y (T)2 VECTOR ADDRESS 03H 0BH 13H 1BH 23H 2BH X0 T0 X1 T1 SP T2 SOURCE NOTES: 1. 11. Timer 2 interrupt enable bit.7 IE. Timer 0 interrupt enable bit.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. If a lower priority level interrupt is being serviced.4 IE. Timer 1 interrupt enable bit.2 IE. Enable Bit = 0 disables it.6 IE. If EA = 0. low power. T = Transition activated 7 IE (0A8H) EA 6 — 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Enable Bit = 1 enables the interrupt. IP and IPH. the lower priority level interrupt that was stopped will be completed. Table 7.x 0 1 0 1 INTERRUPT PRIORITY LEVEL Level 0 (lowest priority) Level 1 Level 2 Level 3 (highest priority) An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. L = Level activated 2. all interrupts are disabled. SU00571 Figure 10. When the new interrupt is finished. Serial Port interrupt enable bit.3 IE. it will be stopped and the new interrupt serviced. TI TF2. The function of the IPH SFR is simple and when combined with the IP SFR determines the priority of each interrupt. BIT IE. (See Figures 10.x 0 0 1 1 IP. Reserved for future use. IE Registers 2000 Aug 07 18 .5 IE.5 V). If EA = 1. The IPH is located at SFR address B7H. and 12. The priority of each interrupt is determined as shown in the following table: PRIORITY BITS IPH.1 IE.

External interrupt 0 priority bit.7 IPH. Timer 1 interrupt priority bit.5 IPH. External interrupt 0 priority bit high.3 IPH. IPH Registers SU01058 2000 Aug 07 19 . Timer 2 interrupt priority bit. low power. reserved for future use. reserved for future use. Not implemented. reserved for future use. Figure 12. Serial Port interrupt priority bit. Timer 2 interrupt priority bit high. Not implemented. Timer 0 interrupt priority bit. Serial Port interrupt priority bit high.2 IPH.7 IP.4 IPH.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.6 IP. Timer 0 interrupt priority bit high.6 IPH.5 IP. 128/256 B RAM 80C51/87C51/80C52/87C52 7 IP (0B8H) — 6 — 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority BIT IP.0 SYMBOL — — PT2 PS PT1 PX1 PT0 PX0 FUNCTION Not implemented. Timer 1 interrupt priority bit high.3 IP. high speed (33 MHz).4 IP.1 IPH. reserved for future use.2 IP. Figure 11.1 IP.0 SYMBOL — — PT2H PSH PT1H PX1H PT0H PX0H FUNCTION Not implemented.5 V). IP Registers SU00572 7 IPH (B7H) — 6 — 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority BIT IPH.7 V–5. External interrupt 1 priority bit. External interrupt 1 priority bit high.

low power. Select Reg DPTR0 DPTR1 DPS 0 1 The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. Note that bit 2 is not writable and is always read as a zero.7 V–5. This allows the DPS bit to be quickly toggled simply by executing an INC DPTR instruction without affecting the WOPD or LPEP bits. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. See application note AN458 for more details. SU00745A Dual DPTR The dual DPTR structure (see Figure 13) enables a way to specify the address of an external data memory location. high speed (33 MHz). 2000 Aug 07 20 . 128/256 B RAM 80C51/87C51/80C52/87C52 Reduced EMI All port pins of the 8xC51 and 8xC52 have slew rate controlled outputs. Figure 13. A JMP @ A + DPTR Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Reduced EMI Mode The AO bit (AUXR. AUXR (8EH) 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 AO DPS BIT0 AUXR1 DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY AUXR. #data16 MOV A.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. There are two 16-bit DPTR registers that address the external memory. @ A+DPTR MOVX A. The slew rate is factory set to approximately 10 ns rise and fall times.0) in the AUXR register when set disables the ALE output.0 AO Turns off ALE output. The six instructions that use the DPTR are as follows: INC DPTR MOV DPTR. This is to limit noise generated by quickly switching output signals. @ DPTR 5 – 4 LPEP 3 WUPD 2 0 1 – 0 DPS • New Register Name: AUXR1# • SFR Address: A2H • Reset Value: xxx000x0B AUXR1 (A2H) 7 – 6 – Increments the data pointer by 1 Loads the DPTR with a 16-bit constant Move code byte relative to DPTR to ACC Move external RAM (16-bit address) to ACC Move ACC to external RAM (16-bit address) Jump indirect relative to DPTR MOVX @ DPTR . and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them.5 V). The DPS bit status should be saved by software when switching between DPTR0 and DPTR1.

5 15 UNIT °C °C V V mA Power dissipation (based on package heat transfer limitations. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Parameters are valid over operating temperature range unless otherwise specified. 3. AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C CLOCK FREQUENCY RANGE –f SYMBOL 1/tCLCL FIGURE 29 PARAMETER Oscillator frequency Speed versions : S (16 MHz) U (33 MHz) MIN 0 0 MAX 16 33 UNIT MHz MHz 2000 Aug 07 21 . This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied.7 V–5. 3 PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin RATING 0 to +70 or –40 to +85 –65 to +150 0 to +13.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.5 to +6. Nonetheless. 128/256 B RAM 80C51/87C51/80C52/87C52 ABSOLUTE MAXIMUM RATINGS1.0 –0. 2. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.5 W NOTES: 1. high speed (33 MHz). All voltages are with respect to VSS unless otherwise noted. low power. not device power consumption) 1. 2.5 V).

5 0. This value applies to Tamb = 0°C to +70°C. 1. and PSEN = 100 pF. except when ALE is off then VOH is the voltage specification. Pin capacitance is characterized but not tested. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin. ALE is tested to VOH1.2 mA VIN = 0. 3 Logical 1-to-0 transition current.9 0. 3.7 VCC TYP1 MAX 0. The transition current reaches its maximum value when VIN is approximately 2 V.4 0.5 VCC+0. and a nominal 15 ns glitch rejection circuitry has been added to the INT0 and INT1 pins. EA) Input high voltage. For Tamb = –40°C to +85°C.1 0. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 7. In the worst cases (capacitive loading > 100 pF). ports 1.1 mA Idle mode: ICC = 0. IOL must be externally limited as follows: Maximum IOL per port pin: 15 mA (*NOTE: This is 85°C specification. port 0.6 mA2 VCC = 2. 8.7 V IOL = 3. Output low voltage. 2 and 3 source a transition current when they are being externally driven from 1 to 0.2 VCC–0. +1. Active mode: ICC = 0.5 –0. Typical ratings are not guaranteed. 2. it may be desirable to qualify ALE with a Schmitt Trigger.7 V IOH = –20 µA VCC = 4. + 1. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3.5 V). The values listed are at room temperature. 7 VOH O voltage ports 1. 128/256 B RAM 80C51/87C51/80C52/87C52 DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C. ALE.0 V RST11 VCC = 2. 2. 6. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations.7 V IOL = 1. In such cases.4 V VIN = 2. 2.7 V<VCC< 4.7 V to 5.7 VCC – 0. PSEN8. 2000 Aug 07 22 . 9.5 V 2. port 0 Power supply current (see Figure 21): Active mode @ 16 MHz Idle mode @ 16 MHz Power-down mode or clock stopped (see Figure for conditions) Fi 25 f diti ) Internal reset pull-down resistor Tamb = 0°C to 70°C Tamb = –40°C to +85°C 40 3 50 75 225 RRST CIO Pin capacitance10 (except EA) 15 pF NOTES: 1. 36 Input leakage current. 3 VOH1 IIL ITL ILI ICC Output high voltage (port 0 in external bus mode). Previous devices provided only an inherent 5 ns of glitch rejection. ports 1. high speed (33 MHz).7 specification when the address bits are stabilizing. 11. or use an address latch with a Schmitt Trigger STROBE input. VSS = 0 V (16 MHz devices) SYMBOL PARAMETER TEST CONDITIONS 4.3 See note 5 µA µA µA µA kΩ VCC – 0. 3. 1 2. load capacitance for all other outputs = 80 pF. PSEN3 Logical 0 input current.0 V See note 4 0.5 0.) 26 mA Maximum IOL per 8-bit port: Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition. 5. ITL = –750 µA.01 mA. See Figures 22 through 25 for ICC test conditions.7 V IOH = –3. 5 V. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 VCC – 0. VCC = 2. Load capacitance for port 0. VOL may exceed the related specification.9 × FREQ. the noise pulse on the ALE pin may exceed 0.5 V IOH = –30 µA VCC = 2.7 –1 –50 –650 ±10 LIMITS MIN –0.18 × FREQ. 10. ALE9. 2. ALE. Pins are not guaranteed to sink current greater than the listed test conditions. XTAL1. Pin capacitance is less than 25 pF.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. Pins of ports 1. 2 3 Output high voltage. 4. 8 Output low voltage.7 VCC+0. Under steady state (non-transient) conditions.7 V–5. See Figure 21. ports 1.2 mA2 VCC = 2.5 V.45 < VIN < VCC – 0.8 V.2 VCC+0.0 V < VCC < 5.4 UNIT V V V V V V V V V µA µA µA VIL VIH VIH1 VOL VOL1 Input low voltage11 Input high voltage (ports 0. low power. 2.

11. Previous devices provided only an inherent 5 ns of glitch rejection.7 VCC TYP1 UNIT MAX 0.5 V LIMITS MIN –0. VSS = 0 V SYMBOL VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL ITL ILI ICC PARAMETER Input low voltage11 Input high voltage (ports 0. 3 3 Output high voltage (port 0 in external bus mode). 3.2mA2 VCC = 4. and a nominal 15 ns glitch rejection circuitry has been added to the INT0 and INT1 pins. PSEN3 Logical 0 input current.5 VCC+0. Pins of ports 1. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 2. 2. high speed (33 MHz).5 V IOH = –30µA VCC = 4. ports 1. 3. In the worst cases (capacitive loading > 100 pF). The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations.18 × FREQ. PSEN 7. 3 8 Output low voltage. 2.7 specification when the address bits are stabilizing.1 VCC+0.4 V VIN = 2.2 VCC–0.0 V See note 4 0. ALE is tested to VOH1. RST11 Output low voltage.8 V. the noise pulse on the ALE pin may exceed 0. 7.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. Active mode: ICC(MAX) = 0.6mA2 VCC = 4. load capacitance for all other outputs = 80 pF. low power.45 < VIN < VCC – 0. 4.7 V–5.1 mA Idle mode: ICC(MAX) = 0. except when ALE is off then VOH is the voltage specification. it may be desirable to qualify ALE with a Schmitt Trigger. 2000 Aug 07 23 .4 V V V V V V V µA µA µA Tamb = 0°C to 70°C Tamb = –40°C to +85°C 40 3 50 75 225 15 µA µA kΩ pF RRST CIO NOTES: 1.7 VCC – 0. The values listed are at room temperature. ALE9. See Figures 22 through 25 for ICC test conditions. 10. 5 V. Load capacitance for port 0.0 mA. The transition current reaches its maximum value when VIN is approximately 2 V. Pin capacitance is characterized but not tested.9 0. ITL = –750 µA. 2. 2.5 0. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin.5 V). In such cases. 5. port 0 Power supply current (see Figure 21): Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Figure 25 f for conditions) diti ) Internal reset pull-down resistor Pin capacitance10 (except EA) VCC = 4. 6.) Maximum IOL per port pin: Maximum IOL per 8-bit port: 26 mA 71 mA Maximum total IOL for all outputs: If IOL exceeds the test condition.5 V IOH = –3. 128/256 B RAM 80C51/87C51/80C52/87C52 DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C. 2 and 3 source a transition current when they are being externally driven from 1 to 0.7 –1 –50 –650 ±10 TEST CONDITIONS 4. 33 MHz devices. port 0. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. Under steady state (non-transient) conditions. EA) Input high voltage. VOL may exceed the related specification. IOL must be externally limited as follows: 15 mA (*NOTE: This is 85°C specification.4 0. 5 V ±10%.5 V IOL = 1. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.3 See note 5 VCC – 0. This value applies to Tamb = 0°C to +70°C.5 0. 9. 8 Output high voltage. XTAL1. 2. ports 1.5 V < VCC < 5. See Figure 21. For Tamb = –40°C to +85°C. + 1.2 VCC+0. Pins are not guaranteed to sink current greater than the listed test conditions. Pin capacitance is less than 25 pF.9 × FREQ.5 V IOL = 3. ALE. ports 1. 3 Logical 1-to-0 transition current. ports 1. 8. 1. +1. and PSEN = 100 pF. 36 Input leakage current. or use an address latch with a Schmitt Trigger STROBE input.2mA VIN = 0. Typical ratings are not guaranteed. ALE.

16 15. 4. 16 15. 80C51. 16 15. 16 15. the RST pin should be held high for a minimum of 20 µs for power-on or wakeup from power down.5 MAX 16 UNIT MHz ns ns ns 4tCLCL–100 tCLCL–30 3tCLCL–45 3tCLCL–105 0 tCLCL–25 5tCLCL–105 10 6tCLCL–100 6tCLCL–100 5tCLCL–165 0 2tCLCL–60 8tCLCL–150 9tCLCL–165 3tCLCL–50 4tCLCL–130 tCLCL–50 tCLCL–50 7tCLCL–150 0 tCLCL–40 20 20 tCLCL+40 tCLCL–tCLCX tCLCL–tCHCX 20 20 12tCLCL 10tCLCL–133 2tCLCL–117 0 3tCLCL+50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 85 22 32 150 2tCLCL–40 tCLCL–40 tCLCL–30 External Clock tXHDV 17 Clock rising edge to input data valid 492 10tCLCL–133 ns NOTES: 1.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. 16 16 15. 5.5 V. load capacitance for all other outputs = 80 pF. VCC = +2. 128/256 B RAM 80C51/87C51/80C52/87C52 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C. Interfacing the 87C51. 3.7 V–5. This limited bus contention will not cause damage to Port 0 drivers. Load capacitance for port 0. See application note AN457 for external memory interface. low power. Parameters are valid over operating temperature range unless otherwise specified. 16 15. 16 15. 87C52. 16 18 18 18 18 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time 23 20 20 20 20 137 122 13 13 287 0 103 0 65 350 397 239 275 275 147 FIGURE 14 14 14 14 14 14 14 14 14 14 14 14 PARAMETER Oscillator frequency5 Speed versions :S ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 37 207 10 32 142 82 MIN MAX VARIABLE CLOCK MIN 3. high speed (33 MHz). 2. 16 15. 3 16 MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV 4 tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX 17 17 17 17 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 750 492 8 0 15.5 V). 2000 Aug 07 24 . 16 15. 16 15. VSS = 0 V1.7 V to +5. Parts are guaranteed to operate down to 0 Hz. and PSEN = 100 pF. ALE. When an external clock source is used. 16 15. or 80C52 to devices with float times up to 45 ns is permitted. 16 15. 2.

4. 16 15.38tCLCL tCLCL–tCLCX tCLCL–tCHCX 5 5 ns ns ns ns 15. 3 VARIABLE CLOCK4 16 MHz to fmax SYMBOL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX 17 17 17 17 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 12tCLCL 10tCLCL–133 2tCLCL–80 0 0 360 167 ns ns ns ns 18 18 18 18 High time Low time Rise time Fall time 0. 80C51. VSS = 0 V1. For frequencies equal or less than 16 MHz. low power. 16 15. 16 15. 16 15. 16 15. 16 15. 16 15. 2.7 V–5.38tCLCL 0. 5. VCC = 5 V ±10%. When an external clock source is used. 2000 Aug 07 25 . Variable clock is specified for oscillator frequencies greater than 16 MHz to 33 MHz. Interfacing the 87C51. 16 15. page 24. 16 16 15. see 16 MHz “AC Electrical Characteristics”. 87C52 or 80C52 to devices with float times up to 45ns is permitted. 16 15.5 V). and PSEN = 100 pF. 3. 128/256 B RAM 80C51/87C51/80C52/87C52 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C. load capacitance for all other outputs = 80 pF.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. Parts are guaranteed to operate down to 0 Hz. Parameters are valid over operating temperature range unless otherwise specified. 16 15. Load capacitance for port 0. the RST pin should be held high for a minimum of 20 µs for power-on or wakeup from power down. 16 15. high speed (33 MHz). 16 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high tCLCL–25 3tCLCL–50 4tCLCL–75 tCLCL–30 tCLCL–25 7tCLCL–130 0 tCLCL+25 5 0 2tCLCL–28 8tCLCL–150 9tCLCL–165 3tCLCL+50 40 45 0 5 80 0 55 6tCLCL–100 6tCLCL–100 5tCLCL–90 0 32 90 105 140 82 82 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 14 14 14 14 14 14 14 14 14 14 14 PARAMETER ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 tCLCL–25 5tCLCL–80 10 tCLCL–25 3tCLCL–45 3tCLCL–60 0 5 70 10 MIN 2tCLCL–40 tCLCL–25 tCLCL–25 4tCLCL–65 5 45 30 55 MAX 33 MHz CLOCK MIN 21 5 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns tXHDV 17 Clock rising edge to input data valid 10tCLCL–133 167 ns NOTES: 1. 2. This limited bus contention will not cause damage to Port 0 drivers. ALE.

7 V–5.0–P2. or ALE P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: tAVLL = Time for address valid to ALE low. high speed (33 MHz). The first character is always ‘t’ (= time).Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. low power.7 OR A8–A15 FROM DPF A0–A15 FROM PCH SU00025 Figure 15. tLLPL =Time for ALE low to PSEN low. The other characters. depending on their positions. indicate the name of a signal or the logical status of that signal.5 V). 128/256 B RAM 80C51/87C51/80C52/87C52 EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. tLHLL ALE tAVLL tLLPL PSEN tPLPH tLLIV tPLIV tPLAZ tPXIX INSTR IN tLLAX tPXIZ PORT 0 A0–A7 A0–A7 tAVIV PORT 2 A0–A15 A8–A15 SU00006 Figure 14. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL RD tRLRH tAVLL PORT 0 tLLAX tRLAZ A0–A7 FROM RI OR DPL tRLDV tRHDX DATA IN tRHDZ A0–A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2. External Data Memory Read Cycle 2000 Aug 07 26 . The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low.

7 OR A8–A15 FROM DPF A0–A15 FROM PCH SU00026 Figure 16.7 V–5. External Clock Drive 2000 Aug 07 27 .7VCC 0.5 V).5 0. External Data Memory Write Cycle INSTRUCTION ALE 0 1 2 3 4 5 6 7 8 tXLXL CLOCK tQVXH OUTPUT DATA 0 WRITE TO SBUF tXHQX 1 2 3 4 5 6 7 tXHDV INPUT DATA VALID CLEAR RI VALID tXHDX SET TI VALID VALID VALID VALID VALID VALID SET RI SU00027 Figure 17. 128/256 B RAM 80C51/87C51/80C52/87C52 ALE tWHLH PSEN tLLWL WR tWLWH tAVLL PORT 0 tLLAX tQVWX tQVWH tWHQX A0–A7 FROM RI OR DPL DATA OUT A0–A7 FROM PCL INSTR IN tAVWL PORT 2 P2.1 tCHCL tCLCX tCLCL tCHCX tCLCH SU00009 Figure 18.45V 0.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.0–P2. low power. Shift Register Mode Timing VCC–0. high speed (33 MHz).2VCC–0.

5 0.7 V–5. low power. Float Waveform 35 30 25 ICC(mA) MAX ACTIVE MODE ICCMAX = 0.9 VLOAD 0. ICC vs. + 1. high speed (33 MHz). AC Testing Input/Output Figure 20.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.1V VLOAD–0. 128/256 B RAM 80C51/87C51/80C52/87C52 VCC–0.45V NOTE: AC inputs during testing are driven at VCC –0. a port is no longer floating when a 100mV change from load voltage occurs.1 VLOAD+0. FREQ Valid only within frequency specifications of the device under test 2000 Aug 07 28 .9 X FREQ. and begins to float when a 100mV change from the loaded VOH/VOL level occurs.1V VOL+0. NOTE: For timing purposes.1 20 15 TYP ACTIVE MODE 10 MAX IDLE MODE 5 TYP IDLE MODE 4 8 12 16 20 24 28 32 36 FREQ AT XTAL1 (MHz) SU01413 Figure 21.1V TIMING REFERENCE POINTS VOH–0.2VCC+0. IOH/IOL ≥ ±20mA. SU00717 SU00718 Figure 19.2VCC–0.5 for a logic ‘1’ and 0.1V 0. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.5 V).45V for a logic ‘0’.

Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns VCC ICC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS VCC SU00016 Figure 25.5 V 2000 Aug 07 29 . low power. VCC = 2 V to 5.45V 0. ICC Test Condition.7 V–5. Power Down Mode All other pins are disconnected.1 tCHCL tCLCX tCLCL tCHCX tCLCH SU00009 Figure 24. Active Mode All other pins are disconnected Figure 23. Idle Mode All other pins are disconnected VCC–0.5 0.7VCC 0. 128/256 B RAM 80C51/87C51/80C52/87C52 VCC ICC VCC VCC P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS VCC RST P0 EA VCC VCC ICC VCC RST SU00719 SU00720 Figure 22. ICC Test Condition. high speed (33 MHz).2VCC–0.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.5 V). ICC Test Condition.

* ALE/PROG receives 5 programming pulses for code data (also for user array. EA is latched on Reset and all further programming of the EPROM is disabled. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. The signature bytes identify the device as being manufactured by Philips. Program Verification If security bits 2 and 3 have not been programmed. The user will have to know the encryption table contents in order to correctly decode the verification data. PSEN and pins of ports 2 and 3 specified in Table 8 are held at the ‘Program Code Data’ levels indicated in Table 8. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses.75 V ±0. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. verification cycles will produce only encrypted data. 2. the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The ALE/PROG is pulsed low 5 times as shown in Figure 27. The other pins are held at the ‘Verify Code Data’ levels indicated in Table 8. device. Security Bits With none of the security bits programmed the code in the program memory can be verified. low power. repeat the 5 pulse programming sequence for addresses 0 through 1FH.75 V.7 0 1 0 1 1 1 0 P2. EPROM Programming Modes MODE Read signature Program code data Verify code data Pgm encryption table Pgm security bit 1 Pgm security bit 2 Pgm security bit 3 RST 1 1 1 1 1 1 1 PSEN 0 0 0 0 0 0 0 ALE/PROG 1 0* 1 0* 0* 0* 0* EA/VPP 1 VPP 1 VPP VPP VPP VPP P2.6 0 0 0 0 1 1 1 P3. Encryption Array 64 bytes of encryption array are initially unprogrammed (all 1s). After one security bit is programmed. The values are: (030H) = 15H indicates manufactured by Philips (031H) = 92H indicates 87C51 Quick-Pulse Programming The setup for microcontroller quick-pulse programming is shown in Figure 26.6 and P3. MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 26 and 27. and which satisfies the timing specifications. Table 8 shows the logic levels for reading the signature byte. verify mode is disabled. However. The code byte to be programmed into that location is applied to port 0. To program the security bits.7 V–5. except that P3. Each programming pulse is low for 100 µs (±10 µs) and high for a minimum of 10 µs. When only security bit 1 (see Table 9) is programmed. ™Trademark phrase of Intel Corporation. high speed (33 MHz). VCC = 5 V±10% during programming and verification. When all three security bits are programmed. 5 pulses for encryption or security bits) while VPP is held at 12. The contents of the address location will be emitted on port 0. and for programming the program memory. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H. the other security bits can still be programmed. VPP = 12. 3. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 28. the code will be encrypted when verified. 2000 Aug 07 30 . all of the conditions above apply and all external program memory execution is disabled. The encryption table itself cannot be read out.25 V.6 0 1 1 0 1 0 1 NOTES: 1. External pull-ups are required on port 0 for this operation. Figure 28 shows the circuit configuration for normal program memory verification. using the ‘Pgm Encryption Table’ levels. repeat the 5 pulse programming sequence using the ‘Pgm Security Bit’ levels. is suitable. ‘0’ = Valid low for that pin. 128/256 B RAM 80C51/87C51/80C52/87C52 EPROM CHARACTERISTICS These devices can be programmed by using a modified Improved Quick-Pulse Programming™ algorithm.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. The address of the EPROM location to be programmed is applied to ports 1 and 2. in addition to the above. If the encryption table is programmed. the on-chip program memory can be read out for program verification. The VPP source should be well regulated and free of glitches and overshoot. further programming of the code memory and encryption table is disabled. Even a narrow glitch above that voltage can cause permanent damage to the Program/Verify Algorithms Any algorithm in agreement with the conditions listed in Table 8. and the security bits. ‘1’ = valid high for that pin.5 V). Table 8. The family contains two signature bytes that can be read and used by an EPROM programming system to identify the device. To program the encryption table.7 0 1 1 1 1 0 0 P3. RST. as shown in Figure 26. Note that the device is running with a 4 to 6 MHz oscillator. Do not forget that after the encryption table is programmed.7 need to be pulled to a logic low. If the 64 byte encryption table has been programmed. the encryption table. When security bits 1 and 2 are programmed.

low power.75V 5 PULSES TO GROUND 0 1 0 A8–A12 EA/VPP ALE/PROG PSEN P2. Same as 2. U – unprogrammed. +5V A0–A7 1 1 1 P1 RST P3. and further programming of the EPROM is disabled. Same as 3. PROG Waveform 2000 Aug 07 31 . external execution is disabled.7 EPROM/OTP XTAL2 VCC P0 PGM DATA +12. 3 4 P P P P U P NOTES: 1. 128/256 B RAM 80C51/87C51/80C52/87C52 Table 9. also verify is disabled. P – programmed. 2. Programming Configuration 5 PULSES 1 ALE/PROG: 0 1 2 3 4 5 SEE EXPLODED VIEW BELOW tGHGL = 10µs MIN tGLGH = 100µs±10µs 1 ALE/PROG: 0 1 SU00875 Figure 27.0–P2.5 SU00873 Figure 26. EA is sampled and latched on Reset.7 V–5.7 P2.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.5 V).6 4–6MHz XTAL1 VSS P2. 2 SB1 1 2 U P SB2 U U SB3 U U PROTECTION DESCRIPTION No Program Security features enabled.6 P3. high speed (33 MHz). Any other combination of the security bits is not defined. Program Security Bits for EPROM Devices PROGRAM LOCK BITS1. Internal data RAM is not accessible. (Code verify will still be encrypted by the Encryption Array if programmed.) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory.

low power.0 50 6 1 UNIT V mA MHz 2000 Aug 07 32 . VSS = 0 V (See Figure 29) SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL NOTE: 1.0–P2.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.7 EPROM/OTP XTAL2 4–6MHz XTAL1 VSS ALE/PROG PSEN P2. high speed (33 MHz).5 P0 PGM DATA 1 1 0 0 ENABLE 0 A8–A12 EA/VPP SU00839 Figure 28. Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data hold after PROG P2.6 P3.6 P2. Not tested.7 V–5.7 P2.5 V).5 MAX 13. Program Verification EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Tamb = 21°C to +27°C. 128/256 B RAM 80C51/87C51/80C52/87C52 +5V VCC A0–A7 1 1 1 P1 RST P3.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 110 48tCLCL 48tCLCL 48tCLCL µs µs µs µs PARAMETER MIN 12. VCC = 5 V±10%.

EA is latched on Reset and all further programming of the EPROM is disabled.0–P1. Table 10. in addition to the above. MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory. Any other combination of the security bits is not defined.5 P3.0 – P0. EPROM Programming and Verification MASK ROM DEVICES Security Bits With none of the security bits programmed the code in the program memory can be verified.7 P2. and further programming of the EPROM is disabled.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. P – programmed.7 (D0 – D7) tDVGL tAVGL ALE/PROG tGHDX tGHAX tGLGH tSHGL tGHGL tGHSL LOGIC 1 EA/VPP LOGIC 0 LOGIC 1 tEHSH P2.0–P2. EA is sampled and latched on Reset. Figure 29. Encryption Array 64 bytes of encryption array are initially unprogrammed (all 1s).5 V). verify mode is disabled. Program Security Bits PROGRAM LOCK BITS1. 128/256 B RAM 80C51/87C51/80C52/87C52 PROGRAMMING* P1. U – unprogrammed.) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. low power. 2000 Aug 07 33 . When only security bit 1 (see Table 10) is programmed. FOR VERIFICATION CONDITIONS SEE FIGURE 28.4 (A0 – A12) ADDRESS VERIFICATION* ADDRESS tAVQV DATA IN DATA OUT PORT 0 P0. NOTES: 1.7 V–5. 2 SB1 1 2 U P SB2 U U PROTECTION DESCRIPTION No Program Security features enabled. If the encryption table is programmed.7 ** tELQV tEHQZ SU01414 NOTES: * FOR PROGRAMMING CONFIGURATION SEE FIGURE 26. ** SEE TABLE 8. (Code verify will still be encrypted by the Encryption Array if programmed. When security bits 1 and 2 are programmed. 2. the code will be encrypted when verified. high speed (33 MHz).

NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. the following information must be included with the ROM code. Security Bit 2: When programmed. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. Security Bit 2: When programmed. this bit inhibits Verify User ROM. the following must be specified: 1.7 V–5. must send key file.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. must send key file. ROM security bits. 128/256 B RAM 80C51/87C51/80C52/87C52 80C51 ROM CODE SUBMISSION When submitting ROM code for the 80C51. For each of the following.5 V). If the ROM Code file does not include the options. low power. this bit has two effects on masked ROM parts: 1. ADDRESS 0000H to 0FFFH 1000H to 103FH 1040H 1040H CONTENT DATA KEY SEC SEC BIT(S) 7:0 7:0 0 1 COMMENT User ROM Data ROM Encryption Key ROM Security Bit 1 ROM Security Bit 2 Security Bit 1: When programmed. External MOVC is disabled. high speed (33 MHz). 4k byte user ROM data 2. check the appropriate box. 8k byte user ROM data 2. EA is latched on Reset. and send to Philips along with the code: Security Bit #1: Security Bit #2: Encryption: V V V Enabled Enabled No V V V Disabled Disabled Yes If Yes. the following information must be included with the ROM code. 64 byte ROM encryption key 3. External MOVC is disabled. For each of the following. 64 byte ROM encryption key 3. check the appropriate box. 80C52 ROM CODE SUBMISSION When submitting ROM code for the 80C52. ADDRESS 0000H to 1FFFH 2000H to 203FH 2040H 2040H CONTENT DATA KEY SEC SEC BIT(S) 7:0 7:0 0 1 COMMENT User ROM Data ROM Encryption Key ROM Security Bit 1 ROM Security Bit 2 Security Bit 1: When programmed. and send to Philips along with the code: Security Bit #1: Security Bit #2: Encryption: V V V Enabled Enabled No V V V Disabled Disabled Yes If Yes. If the ROM Code file does not include the options. this bit inhibits Verify User ROM. this bit has two effects on masked ROM parts: 1. ROM security bits. and 2. and 2. EA is latched on Reset. the following must be specified: 1. 2000 Aug 07 34 .

low power. 40 leads (600 mil) SOT129-1 2000 Aug 07 35 .7 V–5. 128/256 B RAM 80C51/87C51/80C52/87C52 DIP40: plastic dual in-line package.5 V). high speed (33 MHz).Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2.

5 V). 44 leads SOT187-2 2000 Aug 07 36 . high speed (33 MHz).Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. low power. 128/256 B RAM 80C51/87C51/80C52/87C52 PLCC44: plastic leaded chip carrier.7 V–5.

high speed (33 MHz).75 mm SOT307-2 2000 Aug 07 37 . 44 leads (lead length 1.5 V). body 10 x 10 x 1.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. low power. 128/256 B RAM 80C51/87C51/80C52/87C52 QFP44: plastic quad flat package.7 V–5.3 mm).

128/256 B RAM 80C51/87C51/80C52/87C52 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. described or contained herein in order to improve design and/or performance. Stress above one or more of the limiting values may cause permanent damage to the device. Box 3409 Sunnyvale. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. For detailed information see the relevant data sheet or data handbook. Date of release: 08-00 Document order number: 9397 750 07404 Philips Semiconductors 2000 Aug 07 38 . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.5 V). or mask work right to these products. devices or systems where malfunction of these products can reasonably be expected to result in personal injury.Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4 K/8 K OTP/ROM low voltage (2. and supplementary data will be published at a later date.O. This data sheet contains preliminary data. conveys no license or title under any patent. Disclaimers Life support — These products are not designed for use in life support appliances. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Specification may change in any manner without notice. Application information — Applications that are described herein for any of these products are for illustrative purposes only. and makes no representations or warranties that these products are free from patent. California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 2000 All rights reserved. This data sheet contains final specifications. and/or software. including circuits. copyright. Exposure to limiting values for extended periods may affect device reliability. copyright.S. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Right to make changes — Philips Semiconductors reserves the right to make changes. or mask work right infringement. in the products. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Philips Semiconductors assumes no responsibility or liability for the use of any of these products.7 V–5.A. without notice. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. standard cells. low power. Printed in U. Philips Semiconductors 811 East Arques Avenue P. high speed (33 MHz). Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. unless otherwise specified.

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