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Document Number: AN535 Rev. 1.0, 02/2006

**Phase-Locked Loop Design Fundamentals
**

by: Garth Nash Applications Engineering

Abstract

The fundamental design concepts for phase-locked loops implemented with integrated circuits are outlined. The necessary equations required to evaluate the basic loop performance are given in conjunction with a brief design example. NOTE This document contains references to obsolete part numbers and is offered for technical information only.

Contents

1 2 3 4 5 6 7 8 9 10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 1 Parameter Definition . . . . . . . . . . . . . . . . . . 2 Type - Order . . . . . . . . . . . . . . . . . . . . . . . . . 3 Error Constants . . . . . . . . . . . . . . . . . . . . . . 4 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Phase-Locked Loop Design Example . . . 11 Experimental Results . . . . . . . . . . . . . . . . . 18 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . 21

1

Introduction

The purpose of this application note is to provide the electronic system designer with the necessary tools to design and evaluate Phase-Locked Loops (PLL) configured with integrated circuits. The majority of all PLL design problems can be approached using the Laplace Transform technique. Therefore, a brief review of Laplace is included to establish a common reference

© Freescale Semiconductor, Inc., 1994, 2006. All rights reserved.

Parameter Definition

with the reader. Since the scope of this article is practical in nature all theoretical derivations have been omitted, hoping to simplify and clarify the content. A bibliography is included for those who desire to pursue the theoretical aspect.

2

Parameter Definition

The Laplace Transform permits the representation of the time response f(t) of a system in the complex domain F(s). This response is twofold in nature in that it contains both transient and steady state solutions. Thus, all operating conditions are considered and evaluated. The Laplace transform is valid only for positive real time linear parameters; thus, its use must be justified for the PLL which includes both linear and nonlinear functions. This justification is presented in Chapter Three of Phase Lock Techniques by Gardner1. The parameters in Figure 1 are defined and will be used throughout the text.

Figure 1. Feedback System

Using servo theory, the following relationships can be obtained2. 1 θ e ( s ) = -------------------------------- = θi(s) 1 + G(s)H(s ) G(s) θ o ( s ) = -------------------------------- = θi(s) 1 + G(s)H(s) These parameters relate to the functions of a PLL as shown in Figure 2.

Eqn. 1

Eqn. 2

**Figure 2. Phase Locked Loop
**

Phase-Locked Loop Design Fundamentals Application Note, Rev. 1.0 2 Freescale Semiconductor

we obtain a type 1 second order system.E. any time variant signal appearing on the control signal will frequency modulate the VCO/VCM. 8 Eqn.Type . The type of a system refers to the number of poles of the loop transfer function G(s) H(s) located at the origin. and to date there has not been an established standard. 3 during phase lock. The roots of the characteristic equation become the closed loop poles of the overall transfer function. However. For example: Let 10 G ( s ) H ( s ) = --------------------s ( s + 10 ) Eqn.). 1. 5 which is termed the Characteristic Equation (C. As a result. The phase detector. Identification and examples of these loops are contained in the following two sections. Various types and orders of loops can be constructed depending upon the configuration of the overall loop transfer function. For example: 10 G ( s ) H ( s ) = --------------------s ( s + 10 ) Then 10 1 + G ( s ) H ( s ) = 1 + --------------------. for the given G(s) H(s). Phase-Locked Loop Design Fundamentals Application Note. the output frequency is then equal to that of the input. Removal of the programmable counter produces unity gain in the feedback path (N = 1). 4 This is a type one system since there is only one pole at the origin. Rev. 9 which is a second order polynomial. 3 Type . The order of a system refers to the highest degree of the polynomial expression 1 + G ( s ) H ( s ) = 0 ∆ C. 6 Eqn.Order These two terms are used somewhat indiscriminately in published literature. This voltage upon filtering is used as the control signal for the VCO/VCM (VCM – Voltage Controlled Multivibrator). E.0 Freescale Semiconductor 3 . and VCO/VCM compose the feed forward path with the feedback path containing the programmable divider. filter.= 0 s ( s + 10 ) C. E. the most common usage will be identified and used in this article. Eqn. Thus. E. The output frequency is f o = Nfi Eqn. = s ( s + 10 ) + 10 C. = s + 10s + 10 2 Eqn.Order The phase detector produces a voltage proportional to the phase difference between the signals θiand θo/N. 7 Therefore Eqn. Since the VCO/VCM produces a frequency proportional to its input voltage.

The response of type 1. 15 2 s where Cv is the magnitude of the rate of change of phase in radians per second. in Laplace notation: Cv θ i ( s ) = ----Eqn. these include step position. t≥0 Eqn. θe(s) represents the phase error that exists in the phase detector between the incoming reference signal θi(s) and the feedback θo(s)/N. Rev. This theorem permits finding the steady state system error θe(s) resulting from the input θi(s) without transforming back to the time domain3. 10 s→o t≥0 Eqn. and 3 systems will be examined with the various inputs. θe(s) must be examined in order to determine if the steady state and transient characteristics are optimum and/or satisfactory. and acceleration. In evaluating a system. Typically. Simply stated Lim [ θ ( t ) ] = Lim [ s θ e ( s ) ] t→∞ Where 1 -θ (s) θ e ( s ) = -------------------------------1 + G(s)H(s) i The input signal θi(s) is characterized as follows: Step position: θi ( t ) = Cp or. velocity. This corresponds to inputting a frequency that is different than the feedback portion of the VCO frequency. This corresponds to shifting the phase of the incoming reference signal by Cp radians: Step velocity: θi ( t ) = Cv t or. 1. The steady state evaluation can be simplified with the use of the final value theorem associated with Laplace. 11 Eqn.Error Constants 4 Error Constants Various inputs can be applied to a system. 14 Phase-Locked Loop Design Fundamentals Application Note. The transient response is a function of loop stability and is covered in the next section. in Laplace notation: Cp θ i ( s ) = ----s Eqn. Thus. 13 Eqn. Cv is the frequency difference in radians per second seen at the phase detector.0 4 Freescale Semiconductor . 2. 12 where Cp is the magnitude of the phase step in radians.

and 3 are: Type 1 K G ( s ) H ( s ) = -----------------s(s + a) Type 2 (s + a) G(s)H(s) = K -------------------2 s Type 3 (s + a)(s + b ) G(s)H(s) = K ------------------------------------3 s Eqn.0 Freescale Semiconductor 5 . 22 Phase-Locked Loop Design Fundamentals Application Note. ⎛ ⎞ C ( s + a ) Cp 1 p⎞ ⎜ ⎟ ⎛ ------------------------------. 20 Eqn. 2. This is characterized by a time variant frequency input. Typical loop G(s) H(s) transfer functions for types 1. 17 3 s Ca is the magnitude of the frequency rate of change in radians per second per second. 16 The final value of the phase error for a type 1 system with a step phase input is found by using Equation 11 and Equation 13. 19 Eqn. 21 ⎜ 2 K ⎟⎝ s ⎠ 1 + -----------------( s + as + K ) ⎝ ⎠ s( s + a) s+a ⎞ θ e ( t = ∞ ) = Lim s ⎛ -------------------------. Similarly. Rev. 18 2 t≥0 Eqn. the final value of the phase error is zero when a step position (phase) is applied. and 3 systems and utilizing the final value theorem. 1.Error Constants Step acceleration: θi ( t ) = Ca t or. applying the three inputs into type 1. Table 1. the following table can be constructed showing the respective steady state phase errors. in Laplace notation: 2C a θ i ( s ) = --------Eqn. 2.= ------------------------------θe ( s ) = Eqn. Steady State Phase Errors for Various System Types Type 1 Step Position Step Velocity Step Acceleration Zero Constant Continually increasing Type 2 Zero Zero Constant Type 3 Zero Zero Zero Eqn.C = 0 ⎝ s 2 + as + K⎠ p s→o Thus.

For instance. The relationship of the system poles and zeroes then determine the degree of stability. 2.Breakaway points from negative real axis is given by: Eqn. 1. . = Σ -------------------#P – #Z Eqn. the system type can be determined for specific inputs. Using Table 1. A constant phase error identifies a phase differential between the two input signals at the phase detector. Rule 4 . 24 where ΣP (ΣZ) denotes the summation of the poles (zeroes).On a given section of the real axis. This is an unlocked condition for the phase loop. Rule 6 .: P – ΣZ C. if it is desired for a PLL to track a reference frequency (step velocity) with zero phase error. 5 Stability The root locus technique of determining the position of system poles and zeroes in the s-plane is often used to graphically visualize the system stability. The magnitude of this differential phase error is proportional to the loop gain and the magnitude of the input step. a minimum of type 2 is required. For stability. Rev. Rule 3 . The number of zeroes at infinity is the difference between the number of finite poles and finite zeroes of G(s) H(s). whichever is greater. 23 #P – #Z where #P (#Z) is the number of poles (zeroes). where K is loop gain. Rule 5 . where K is the loop gain variable factored from the characteristic equation.The root locus begins at the poles of G(s) H(s) (K = 0 and ends at the zeroes of G(s) H(s) (K = ∞). Rule 1 . The graph or plot illustrates how the closed loop poles (roots of the characteristic equation) vary with loop gain. all poles must lie in the left half of the s-plane.0 6 Freescale Semiconductor .Stability A zero phase error identifies phase coherence between the two input signals at the phase detector.The intersection of the asymptotes is positioned at the center of gravity C.The root locus contour is bounded by asymptotes whose angular position is given by: ( 2n + 1 ) ------------------. 1. G.The number of root loci branches is equal to the number of poles or number of zeroes. The root locus contour can be determined by using the following guidelines2.G. root loci may be found in the section only if the #P + #Z to the right is odd. n = 0.π. Eqn. 25 dK = 0 -----ds Again. Rule 2 . . A continually increasing phase error identifies a time rate change of phase. Phase-Locked Loop Design Fundamentals Application Note.

can be found by first writing the characteristic equation. 30 Taking the derivative with respect to s and setting it equal to zero. the determines the breakaway point. 33 Eqn. the root locus can be plotted as in Figure 3. 27 2 π for n = 1 ⎪3 ----⎩2 The position of the intersection according to Rule 4 is: P – ΣZ (– 4 – 0) – (0) s = Σ -------------------. C. The second order characteristic equation.Stability Example: The root locus for a typical loop transfer function is found as follows: K G ( s ) H ( s ) = -----------------s(s + 4 ) Eqn. the equation becomes: ⎧π -. as been normalized to a standard form2 s + 2 ζω n s + ω n 2 2 Eqn. 26 The root locus has two branches (Rule 2) which begin at s = 0 and s = -4 and ends at the two zeroes located at infinity (Rule 1). 32 where the damping ratio ξ = COSφ(0° ≤ φ ≤ 90°) and ωn is the natural frequency as shown is Figure 3. The asymptotes can be found according to Rule 3. Phase-Locked Loop Design Fundamentals Application Note. Since there are two poles and no zeroes. as defined by Rule 6. = 1 + G ( s ) H ( s ) = 0 2 K = 1 + -----------------. Rev. E.= ---------------------------------2–0 #P – #Z s = –2 The breakaway point. given by Equation 29. 28 Now solving for K yields: K = – s – 4s 2 Eqn. 29 Eqn. 34 Eqn.( – s – 4s ) Eqn. 31 -----ds ds dK = – 2s – 4 = 0 -----ds or s = –2 is the point of departure. 1.for n = 0 ⎪2 2n + 1 --------------π = ⎨ Eqn. 2 d dK = ---.= s + 4s + K = 0 s(s + 4) Eqn. Using this information.0 Freescale Semiconductor 7 .

Type 1 Second Order Root Locus Contour The response of this type 1. 1. second order system to a step input. The output frequency response as a function of time to a step velocity (frequency) input is also characterized by the same set of figures.0 8 Freescale Semiconductor . is shown in Figure 4. These curves represent the phase response to a step position (phase) input for various damping ratios. Figure 4. Type 1 Second Order Step Response Phase-Locked Loop Design Fundamentals Application Note. Rev.Stability Figure 3.

5.5 -----. Rev. Example: Assume ξ = 0. Type 2 Second Order Root Locus Contour Phase-Locked Loop Design Fundamentals Application Note. the poles would move along the jω axis as a function of gain and the system would at all times be oscillatory in nature.5 curve error is less than 10% of the final value for all time greater than ωnt = 4.5 = ( 4. 36 Eqn.= -----------t 0.0 Freescale Semiconductor 9 .) The root locus shown in Figure 5 has two branches beginning at the origin with one asymptote located at 180°. A zero is added to provide stability. 37 -----------------2 s This is a type 2 second order system.5krad ) ⁄ s ω n = 4.5 error < 10% for t > 1ms From ξ = 0. Example: Another common loop transfer function takes the form: s + a)k G(s)H(s) = ( Eqn. The breakaway point is s = -2a. there is no intersection at this point. with only one asymptote.5 or 4. 1.001 ξ is typically selected between 0. The center of gravity is s = a. Each response is plotted as a function of the normalized time ωnt.Stability The overshoot and stability as a function of the damping ratio ξ is illustrated by the various plots. The required ωn can then be found by: ω n t = 4. The root locus lies on a circle centered at s = -a and continues on all portions of the negative real axis to left of the zero. the ωn required to achieve the desired results can be determined. however. (Without the zero. For a given ξ and a lock-up time t.5 and 1 to yield optimum overshoot and noise performance. 35 Figure 5. Eqn.

As illustrated in the previous example.Bandwidth The respective phase or output frequency response of this type 2 second order system to a step position (phase) or velocity (frequency) input is shown in Figure 6. Phase-Locked Loop Design Fundamentals Application Note. Rev. and by: 2 2 4⎞ ω – 3dB = ω n ⎛ ⎝1 + 2ξ + 2 + 4ξ + 4ξ ⎠ 1⁄2 Eqn. 1. Type 2 Second Order Step Response 6 Bandwidth 2 2 4 ω – 3dB = ω n ⎛ 1 – 2 ξ + 2 – 4 ξ + 4 ξ ⎞ ⎝ ⎠ The -3dB bandwidth of the PLL is given by: 1⁄2 Eqn. 39 for a type 2 second order1 system. Figure 6. 38 for a type 1 second order4 system.0 10 Freescale Semiconductor . the required ωn can be determined by the use of the graph when ξ and the lock-up time are given.

1. Phase-Locked Loop Circuit Parameters The devices used to configure the PLL are: Frequency-Phase Detector Voltage Controlled Multivibrator (VCM) Programmable Counter MC4044/4344 MC4024/4324 MC4016/4316 The forward and feedback transfer functions are given by: G ( s ) = Kp Kf Ko Where Kn = 1 ⁄ N Eqn. 40 Phase-Locked Loop Design Fundamentals Application Note. From the given specifications. selecting the proper bandwidth.0 Freescale Semiconductor 11 . the circuit parameters shown in Figure 7 can now be determined.0MHz Frequency Steps Phase Coherent Frequency Output Lock-Up Times Between Channels Overshoot 100KHz — 1ms < 20% NOTE These specifications characterize a system function similar to a variable time base generator or a frequency synthesizer.Phase-Locked Loop Design Example 7 Phase-Locked Loop Design Example The design of a PLL typically involves determining the type of loop required. Figure 7. A fundamental approach to these design constraints is now illustrated. 41 H ( s ) = Kn Eqn. and establishing the desired stability. Rev. It is desired for the system to have the following specifications: Output Frequency 2.0MHz to 3.

The desired operating range is then centered within the total range of the device. f o min f o min 2MHz = 20 N min = -------------. 43 Eqn.to ----K n = ----20 30 Eqn.= -------------.Phase-Locked Loop Design Example The programmable counter dives ration Kn can be found in Equation 3. The input voltage versus output frequency is shown in Figure 8. Selecting the VCM control capacitor according to the rules contained on the data sheet yields C = 100pF. 42 Eqn.= ------------------f step 100kHz 1 1 . 44 A type 2 system is required to produce a phase coherent output relative to the input (See Table 1). 45 Phase-Locked Loop Design Fundamentals Application Note. Eqn. Rev.= ------------------fi f step 100kHz f o max 3MHz = 30 N max = --------------. 1.0 12 Freescale Semiconductor . Figure 8. The root locus contour is shown in Figure 5 and the system step response is illustrated by Figure 6. MC4324 Input Voltage versus Output Frequency (100pF Feedback Capacitor) the transfer function of the VCM is given by: Kv K o = -----s Where Kv is the sensitivity in radians per second per volt. The operating range of the MC4024/4324 VCM must cover 2MHz to 3MHz.

The gain constant for the MC4044/4344 phase detector is found by5 – UFLow = 2. 1.2 π rad ⁄ s ⁄ V K v = -----------------------------------------5V – 3. R1. R2 and C are then the variables used to establish the overall loop characteristics. The circuit shown in Figure 9 yields the desired results. Ko. 49 Eqn.for l arg e A K f = ---------------------R 1 Cs Eqn.2 -----------------------s 6 6 Eqn. 46 Eqn.9V = 0.Phase-Locked Loop Design Example From the curve in Figure 8.5MHz .= -------------------2 s s Thus.3V – 0. Figure 9. 4MHz – 1. 47 The s in the denominator converts the frequency characteristics of the VCM to phase. The MC4044/4344 provides the active circuitry required to configure the filter Kf. Kv is found by taking the reciprocal of the slope.0 Freescale Semiconductor 13 .6V K v = 11. Kn leaving only Kf as the variable for design. The parameters thus far determined include Kp. Active Filter Design Kf is expressed by R 2 Cs + 1 .e. i. Kf must take the form +a Kf = s ---------s Eqn.2 × 10 rad ⁄ s ⁄ V Thus × 10 rad ⁄ s ⁄ V K o = 11. 51 where A is voltage gain of the amplifier. 50 in order to provide all of the necessary poles and zeroes for the required G(s) H(s). 48 Since a type 2 system is required (phase coherent output) the loop transfer function must take the form of Equation 19. thus minimizing the Phase-Locked Loop Design Fundamentals Application Note. An additional low current high β buffering device or FET can be used to boost the input impedance.. Rev.111V ⁄ rad K p = DFHigh -------------------------------------------------------------------------2(2π) 4π Eqn. Kp Kv Kn Kf K(s + a) G ( s ) H ( s ) = --------------------------. phase is the integral of frequency. Writing the loop transfer function and relating it to Equation 19.

Laplace Representation of diagram in Figure 11 Phase-Locked Loop Design Fundamentals Application Note. Since the gain of the active filter circuitry in the MC4044/4344 is not infinite.5 ⎜ ---------------------Eqn.0 14 Freescale Semiconductor .) The PLL circuit diagram is shown in Figure 11 and its Laplace representation in Figure 10. a gain correction factor Kc must be applied to Kf in order to properly characterize the function. As a result. Rev.5. 52 ⎝ R 1 Cs ⎠ (For large gain. Kc is found experimentally to be Kc = 0.Phase-Locked Loop Design Example leakage current from the capacitor C between sample updates. Figure 10. 1. longer sample periods are achievable. ⎛ R 2 Cs + 1⎞ -⎟ K fc = K f K c = 0. Equation 51 applies.

0 Freescale Semiconductor 15 . 53 Eqn. Circuit Diagram of Type 2 Phase-Locked Loop The loop transfer function is G ( s ) H ( s ) = K p K fc K o K n ⎛ R 2 Cs + 1⎞ ⎛ K v⎞ ⎛ 1 ⎞ -⎟ -----.5 ) ⎜ ---------------------⎝ R 1 Cs ⎠ ⎝ s ⎠ ⎝ N⎠ Eqn.--G ( s ) H ( s ) = K p ( 0. 54 Phase-Locked Loop Design Fundamentals Application Note. 1.Phase-Locked Loop Design Example Figure 11. Rev.

= ωn2 R 1 CN and 0.Phase-Locked Loop Design Example The characteristic equation takes the form C. 1. 60 The percent overshoot and settling time are now used to determine ωn. 59 -------------. Rev.5K p K v R 2 2 .0 16 Freescale Semiconductor Eqn. From Figure 6. it is seen that a damping ratio ξ = 0. 56 Eqn.5K p K v 2 0.2 × 10 ) = ------------------------------------------------------------2 ( 4500 ) ( 30 ) R 1 C = 0. The required lock-up time is 1ms. 58 Eqn.5K p K v R 2 ---------------------------.8 will produce a peak overshoot less than 20% and will settle within 5% at ωnt = 4.= s + 2 ξω n s + ω n 2 R1 N R 1 CN Equating like coefficients yields 0.= -----------. 4. 57 Eqn.5krad ⁄ s t 0. = 1 + G ( s ) H ( s ) = 0 0. Equation 57 and Equation 58 become Kp Kv Eqn.s + --------------------s + ---------------------------. 61 Eqn.= ωn2 R 1 CN Kp Kv R2 -------------------.5K p K v R 2 .= 2 ξω n R1 N Eqn.5.111 ) ( 11.= 4.00102 (Maximum overshoot occurs at Nmax which is minimum loop gain) Phase-Locked Loop Design Fundamentals Application Note.5 ω n = -----. E.5K p K v 2 0. 62 6 .5 ) ( 0. 55 With the use of an active filter whose open loop gain (A) is large (Kc = 1).5K p K v --------------------.= 2 ξω n R1 N Eqn.001 Rewriting Equation 57 0.s + --------------------= s + ---------------------------R1 N R 1 CN Relating Equation 55 to the standard form given by Equation 34 0.5 4.5K p K v R 1 C = --------------------ωn 2 N ( 0.

Phase-Locked Loop Design Example Let C = 0. 63 Use R2 = 680Ω All circuit parameters have now been determined and the PLL can be properly configured.04k Ω R 1 = -----------------------–6 0. Since the loop gain is a function of the divide ratio Kn. the closed loop poles will vary its position as Kn varies. Rev.= 711 Ω –6 ( 0.8 ) = --------------------------------------------.5k ) Eqn.00102 = 2. The system response for N = 20 exhibits a wider bandwidth and larger damping factor. 1.= ---------K p K v ( 0. thus reducing both lock-up time and percent overshoot (see Figure 14).5 ) C ωn 2 ( 0. The loop was designed for the programmable counter N = 30.5 × 10 ) ( 4. The root locus shown in Figure 12 illustrates the closed loop pole variation.0 Freescale Semiconductor 17 . Solving for R2 in Equation 58 2 ξω n R 1 N 2ξ R 2 = -------------------------. Root Locus Variation Phase-Locked Loop Design Fundamentals Application Note.5 × 10 R 1 = 2k Ω R1 is typically selected greater than 1kΩ. Figure 12.5 µ F Then Use 0.

a type 2 loop still offers an optimum design. Upon changing the counter divide ratio to 30. With the programmable counter set at 29 the quiescent control voltage at pin 2 is approximately 4. The curve N = 20 illustrates the output frequency change as the programmable counter is stepped from 21 to 20. Figure 14 illustrated that the experimental results obtained from the configured system follows the predicted results shown in Figure 13. but short compared to the PLL response time.37 volts. The curve N = 30 illustrates the frequency response when the programmable counter is stepped from 29 to 30. Rev. Frequency-Time Response Phase-Locked Loop Design Fundamentals Application Note. there is no cycle slippage at the phase detector. Even in systems that do not require phase coherency. An overshoot of 18% is obtained and the output frequency is within 5kHz of the final value one millisecond after the applied step. Linearity is maintained for phase errors less than 2π.0MHz. i. 1. The average frequency response as calculated by the Laplace method is found experimentally by smoothing this voltage at pin 2 with a simple RC filter whose time constant is long compared to the phase detector sampling rate. A similar transient occurs when stepping the programmable counter from 21 to 20. thus producing a change in the output frequency from 2.43 volts as shown in Figure 14. Figure 13. the control voltage increases to 4.Experimental Results NOTE The type 2 second order loop was illustrated as a design sample because it provides excellent performance for both type 1 and 2 applications. 8 Experimental Results Figure 13 shows the theoretical transient frequency response of the previously designed system.e. the PLL frequency response can be observed with an oscilloscope by monitoring pin 2 of the VCM.0 18 Freescale Semiconductor . Since the frequency is proportional to the VCM control voltage.9MHz to 3.

the transient will be negative. 9 Summary This application note describes the basic control system techniques required for phase-locked loop design.) Figure 14 and Figure 15 also exhibit a close correlation between experimental and analytical results.0. Rev. A design example is illustrated in a step-by-step approach along with the comparison of the experimental and analytical results. (If stepping from a higher divide ratio to a lower one. Phase-Locked Loop Design Fundamentals Application Note.Summary Figure 14. The lock-up time can then be readily determined as the various parameters are varied. The program prints or plots control voltage transient versus time for desired settings of the programmable counter. VCM Control Voltage (Frequency) Transient Figure 15 is a theoretical plot of the VCM control voltage transient as calculated by a computer program.0 Freescale Semiconductor 19 . The computer program is written with the parameters of Equation 58 and Equation 59 (type 2) as the input variables and is valid for all damping ratios of ξ ≤1. 1. Criteria for the selection of the optimum type of loop and methods for establishing the desired performance characteristics are presented.

0 20 Freescale Semiconductor . Rev. 1.Summary Figure 15. VCM Control Signal Transient Phase-Locked Loop Design Fundamentals Application Note.

Topic: Laplace Techniques McCollum. Phase Lock Techniques. J.. B.. Automatic Control Systems. New Jersey. Jon. C. 1955 5. Inc. 1965 4. Automatic Feedback Control System Synthesis. Laplace Transform Tables and Theorems. New York. MTTL and MECL Avionics Digital Frequency Synthesizer.. Second Edition. Topic: Type Two System Analysis Gardner. Holt..0 Freescale Semiconductor 21 . Topic: Phase Detector Gain Constant DeLaune. G.. 1. Prentice-Hall. Topic: Root Locus Techniques Kuo. 1962 3. M. AN532 Phase-Locked Loop Design Fundamentals Application Note. and Brown. 1967 2. Rev. Topic: Type One System Analysis Truxal.Bibliography 10 Bibliography 1. Wiley. McGraw-Hill. New York. B. P. New York. F.

Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup. All rights reserved. Inc. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. or other applications intended to support or sustain life. Middle East. Shimo-Meguro. even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. and reasonable attorney fees arising out of. Meguro-ku.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.0 02/2006 . and specifically disclaims any and all liability. Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.T. including without limitation consequential or incidental damages. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor. CH370 1300 N. Freescale Semiconductor makes no warranty.com E-mail: support@freescale.asia@freescale. 1. directly or indirectly. Alma School Road Chandler. damages.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. 1994.japan@freescale. affiliates.com Japan: Freescale Semiconductor Japan Ltd. including “Typicals”. 2006. Inc. costs. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po. and distributors harmless against all claims. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Hong Kong +800 2666 8080 support. or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur.freescale. All other product or service names are the property of their respective owners. © Freescale Semiconductor. Tokyo 153-0064. Japan 0120 191014 or +81 3 5437 9125 support.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P. intended. All operating parameters. employees. subsidiaries. Freescale Semiconductor reserves the right to make changes without further notice to any products herein..How to Reach Us: Home Page: www. Freescale Semiconductor products are not designed.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen. and expenses. any claim of personal injury or death associated with such unintended or unauthorized use. must be validated for each customer application by customer’s technical experts.com Europe. N. representation or guarantee regarding the suitability of its products for any particular purpose. Headquarters ARCO Tower 15F 1-8-1. nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit. Document Number: AN535 Rev. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application. Buyer shall indemnify and hold Freescale Semiconductor and its officers. Box 5405 Denver. or authorized for use as components in systems intended for surgical implant into the body.O.

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