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Set No. 1

III B.Tech Supplimentary Examinations, Aug/Sep 2008 FAULT TOLERANT SYSTEMS (Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Distinguish between failures, and faults ? Explain [2+2]

(b) Explain the diﬀerent modeling schemes of faults that generally come across in digital circuits. [3x2=6] (c) Explain the following terms with respect to digital circuits with suitable examples. i. Fault diagnosis. ii. Fault detection test set. iii. Test vector generation.

[3x2=6]

2. (a) A circuit realizes the function. Z=X1 X4 +X2 X3 +X1 X4 Using Boolean Diﬀerence method ﬁnd the test vectors for SA0, SA1 faults on all input lines of the circuit. (b) What are the diﬀerent properties of Boolean diﬀerences? Explain [5+5+6]

3. (a) Explain the 5MR Reconﬁguration scheme. Explain in detail the function of each block. [4+4] (b) Discuss the 3 cases for which the 5MR system automatically reconﬁgure to tolerate single and multiple faults. Explain each with an example. [3+3+2] 4. (a) What is the mechanism adopted in COPRA a fault Tolerant system. Explain in detail. (b) What is meant by Time redundancy? Explain. [4+4+4+4]

5. (a) Design a checker for 1 out of 3 codes that satisfy the partially strongly fault secure properties. (b) Explain the principle of operation of strongly fault secure circuit with one example. [8+8] 6. (a) Explain the general appraoch to the design of totally self-checking PLAs. (b) Explain why self-checking machines are essential in digital system. [10+6]

7. (a) Prove that ﬁve tests are suﬃcient to detect all faults in a combinational logic circuit by inserting addition control logic to the following function, obtain the test pattern. f=(A,B,C,D)=AB +BC +BD 1 of 2

. (a) What is meant by controllability? Explain with suitable examples... 1 [3+5] [3+5] (b) Obtain the ten sequences denoted as P = {xo x1 .Code No: RR321503 Set No. (b) What is meant by Observability? Explain with suitable examples. [8+8] 8..xa } from the basic module of the above circuit and get the compatable pair from the set P.. ⋆⋆⋆⋆⋆ 2 of 2 .

(b) Design a redundant circuit for f = a ⊕ b [9+7] 4.2. [6+10] f1 (A. For the circuit shown as in ﬁgure 2 . (b) minimal complete ﬁxed scheduled fault location experiment.99 reliability of this system.13. Derive the expression for the MTTR. 4 output function design a totally self checking checker circuit using PLAs. derive Figure 2 (a) minimal complete ﬁxed scheduled fault detection experiment.Tech Supplimentary Examinations.5% per 1000 hours.C.Code No: RR321503 Set No.12.8. (b) What is meant by Time redundancy? Explain. [6+3+3+4] 2. Aug/Sep 2008 FAULT TOLERANT SYSTEMS (Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. What is the period of 0. (b) What is meant by active repair time and passive repair time referred in maintainability of a system. (a) A computer system contains 10.B. [5+5] 6. (a) Construct a seven-bit error correcting code to represent the decimal digit by augmenting the Excess-3 code and by using add-1 parity check.7.15) 1 of 2 .Explain with an example the design procedure. (a) Explain the advantages of PLA and how it is used as totally self-checking circuit.3. 2 III B. (a) What is the mechanism adopted in COPRA a fault Tolerant system. [8+8] 3. [4+4+4+4] 5.D) = (0.10.000 components each with failure rate 0. [3+3] (b) Design a totally self checking checker circuit for a given berger code of length I bits. Explain in detail. (b) For the given 4 input. (a) List out the advantages and disadvantages of self-checking circuit in all aspects.

2.D) = f4 (A.13.C.9.Code No: RR321503 f2 (A.3.8.8. List Level Sensitive Scan Design rules and explain. Distinguish between single and double latch LSSD. (b) Obtain the Reed Muller circuit for the given function.11.4.C.B. 2 7.14).B. [10+3+3] ⋆⋆⋆⋆⋆ 2 of 2 .2.9.D) = f3 (A.5.D) = (0. f = AB + AC + BC [8+4+4] 8. Also give the test set for the same.2.15) (0.1.B. Set No. (a) Explain the Reed-Muller expansion Technique used in Design for testable circuit.C.6.12.4.4.10.14) (0.1.

Tech Supplimentary Examinations. (a) Explain the design consideration of self checking PLA considering stray faults with suitable example. 1 of 2 [8+8] .000 components each with failure rate 0. 3 III B. [5+5+4] 4. (b) What is meant by active repair time and passive repair time referred in maintainability of a system. (b) What are the diﬀerent ways to have software redundancy. (a) Analyze the circuit shown in ﬁgure3a. (b) What are the diﬀerent properties of Boolean diﬀerences? Explain [5+5+6] 3. (a) What is the need for self checking circuits (b) Design a totally self checking checker by using reddy’s partition method for 2out of 5 code. Aug/Sep 2008 FAULT TOLERANT SYSTEMS (Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. SA1 faults on all input lines of the circuit. [6+3+3+4] 2.5% per 1000 hours.99 reliability of this system. Z=X1 X4 +X2 X3 +X1 X4 Using Boolean Diﬀerence method ﬁnd the test vectors for SA0. 5. What is the period of 0. (a) A computer system contains 10. (a) Explain in detail the practicle fault Tolerant space shuttle computer complex system. below for static hazards. [6+10] 6. Derive the expression for the MTTR. (a) A circuit realizes the function. Redesign the circuit so that it becomes hazard free? Figure 3a (b) What is the importance of Hamming code in Fault Tolerant System.Code No: RR321503 Set No.

[6+4+6] 8. 3 [8+8] (b) How do you implement strong fault service for the functional PLA. (b) What is meant by Observability? Explain with suitable examples. 7. (a) What is meant by controllability? Explain with suitable examples. (a) What are the goals of a design for testability? (b) What are the diﬀerent DET methods available? Explain at least two such techniques. ⋆⋆⋆⋆⋆ [3+5] [3+5] 2 of 2 .Code No: RR321503 Set No.

(a) Draw the logic diagram of Built-in Logic Block Observer.1.D) = (0.B.8.5.5% per 1000 hours.B. [8+8] [5+5+6] 5.B.11. 4 III B.14). Aug/Sep 2008 FAULT TOLERANT SYSTEMS (Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1.10.C.99 reliability of this system.8.Tech Supplimentary Examinations.13.15) f2 (A. (b) time redundancy.000 components each with failure rate 0. (a) Explain the Reed-Muller expansion Technique used in Design for testable circuit. (a) Design a redundant circuit for f = ab + a′ b′ (b) Explain the Dynamic redundancy Technique of a fault Tolerant system. With an example explain : (a) software redundancy.4. Also give the test set for the same. 1 of 2 .7. (a) Explain the advantages of PLA and how it is used as totally self-checking circuit.2. [8+4+4] f = AB + AC + BC 8.3.2. (b) What is meant by active repair time and passive repair time referred in maintainability of a system.13.3.Code No: RR321503 Set No.2.12.D) = (0. Design a totally self-checking checker for maximal-length Berger codes also give the procedure to generate test vectors of 8 bit long.8.C. (b) Obtain the Reed Muller circuit for the given function.D) = (0.[8+8] 4.2.9. Derive the expression for the MTTR.12. What is the period of 0. 7.C.15) f3 (A. [6+3+3+4] 2. [6+10] f1 (A. (b) What are the diﬀerent properties of Boolean diﬀerences? Explain 3.4.C.14) f4 (A. (a) A circuit realizes the function.D) = (0.B. SA1 faults on all input lines of the circuit.9.1.4. (a) A computer system contains 10.6. Z=X1 X4 +X2 X3 +X1 X4 Using Boolean Diﬀerence method ﬁnd the test vectors for SA0. [8+8] 6.10. 4 output function design a totally self checking checker circuit using PLAs. (b) For the given 4 input.

Code No: RR321503 (b) Discuss BILBO based BIST architecture. 4 [8+8] 2 of 2 . ⋆⋆⋆⋆⋆ Set No.

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