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# ASSIGNMENT NO: 01 TTL CHARACTERISTIC AIM: To study of the TTL characteristics.

THEORY: A group of compatible ICs with the same logic levels and supply voltages for performing various logic functions have been fabricated using a specific circuit configuration which is referred to as logic family. I.) Characteristics of TTL ICs: The various characteristics of digital ICs used to compare their performances are 1. Speed of operation 2. Power dissipation 3. Figure of merit 4. Fan out 5. Current and voltage parameters 6. Noise immunity 7. Operating temperature range 8. Power supply requirements 9. Flexibilities available 1. Speed of operation: The speed of a digital circuit is specified in terms of the propagation delay time. The propagation delay time is the time interval between the application of input voltage and occurrences of resultant o/p voltage and is measured between 50% voltage levels of input and output waveforms. There are two delay times: tpHL = when output is changing from HIGH state to LOW state. tpLH= when output is changing from LOW state to HIGH state. The propagation delay time is taken as the average of these two delay times.

The propagation delay time is expressed in terms of: 1.) tpHL (time it takes for a change in the input to cause a HIGH-to-LOW transition in the output) 2.) tpLH (time it takes for a change in the input to cause a LOW-to-HIGH transition in the output) Standard TTL has maximum tpHL of 15 ns and maximum tpLH of 22ns 2. Power dissipation: This is the amount of power dissipated in an IC. It is given by the product of Icc and Vcc, where Icc is the amount of current drawn from the supply Vcc. Icc is the average value of Icc(0) & Icc(1). This power is specified in milliwatts. i.e. Iccavg = Icc(0) + Icc(1)/2.

Where Icc(0)= The value of Icc drawn from Vcc when output is low. Icc(1)= The value of Icc drawn from Vcc when output is high. Pd=Vcc * Iccavg 3. Figure of merit: The figure of merit of a digital IC is defined as the product of speed and power. The speed is specified in terms of propagation delay time expressed in nanoseconds. Figure of merit = propagation delay time (ns) * Power (mW). It is specified in pico joules (pJ) (ns * mW = pJ). A low value of speed power product is desirable. 4. Fan out: This is the number of similar gates which can be driven by a gate. Fan-out is a measure of the number of loads that a gate can drive. High fan out is advantageous because it reduces the need of additional drivers to drive more gates. Fan out = IOL of the driving gate IIL of the driven gate where IOL and IIL are low level output current and low level input current respectively, as explained below. 5. Current and Voltage parameters: High level input voltage (VIH): This is the minimum input voltage which is recognized by the gate as logic 1. Low level input voltage (VIL): This is the maximum input voltage which is recognized by the gate as logic 0. High level output voltage (VOH): This is the minimum voltage available at the output corresponding to logic 1. Low level output voltage (VOL): This is the maximum voltage available at the output corresponding to logic 0. High level input current (IIH): This is the minimum current which must be supplied by a driving source corresponding to logic 1 level voltage. Low level input current (IIL): This is the minimum current which must be supplied by a driving source corresponding to logic 0 level voltage. High level output current (IOH): This is the maximum current which the gate can sink in 1 level. Low level output current (IOL): This is the maximum current which the gate can sink in 0 level. High level supply current, ICC (1): This is the supply current when the output of the gate is at logic 1. Low level supply current, ICC (0): This is the supply current when the output of the gate is at logic 0. Calculations for fan-out: Sinking current is the conventional current flowing into the gate and the gate is said to be sinking current. Sourcing current is the conventional current flowing out of the gate and the gate is said to be sourcing or supplying current A TTL device can source current (high output) or sink current (low output). Data sheets of standard TTL devices indicate that any 7400 series device can sink up to 16mA, designated, IOL, max = 16mA and can source up to 400 A, designated, IOH, max = -400 A (minus sign means that the conventional current is out of the device, and a plus sign means that it is into the device.) The worst case TTL input currents are:

## IIL, max = -1.6mA

IIH, max = 40 A

Fig 1.: TTL fan-out The figure 1 above shows a 7400 NAND gate sinking current from ten other gates, each with a low-level input current of -1.6 mA. The 1.6 mA is said to be one standard TTL load. Fan-out is a measure of the number of loads that a gate can drive. Fan out = IOL of the driving gate IIL of the driven gate For a NAND gate driving other NAND gates or inverters, Fan-out = IOL = 16 mA = 10 standard loads IIL 1.6 mA Therefore, each of the standard TTL gates can drive ten other standard gates. Input and output currents for TTL subfamilies:

Example: Q. How many 54ALS00 gates can a 54L00 drive? Ans. From the table above, we can see that IOL for a 54L00 is 2mA and IIL for a 54ALS00 is -0.2mA Fan-out = IOL IIL = 2 mA = 10 standard loads 0.2 mA

6. Noise Immunity: Stray electric and magnetic fields may induce unwanted voltages, known as noise, on the connecting wires between logic circuits. This may cause the voltage at the input to a logic circuit to drop below VIH or rise above VIL and may produce undesired operation. The circuits ability to tolerate noise signals is referred to as the noise immunity, a quantitative measure of which is called as noise margin. (Ref fig.2)

Voltages VOH 1 State noise margin 1 = VOH-VIH VIH VIL 0 State noise margin 0 = VIL-VOL VOL

Fig.:2 Noise Margins 7. Operating Temperature: The temperature range in which an IC functions properly is specified. The accepted temperature ranges are: 0 to +70C for consumer and industrial applications and -55C to +125C for military purposes. 8. Power supply requirements: The supply voltage(s) and the amount of power required by an IC are important characteristics required to choose the proper power supply. 9. Flexibilities available: Various flexibilities are available in different IC logic families and these must be considered while selecting a logic family for a particular job. Some of the flexibilities available are: The breadth of the series: Type of different logic functions available in the series. Popularity of the series: the cost of manufacturing depends upon the number of ICs manufactured. When a large number of ICs of one type are manufactured, the cost per function will be very small and it will be easily available because of multiple sources.

Wired logic capability: The outputs can be connected together to perform additional logic without any extra hardware. Availability of complement outputs: This eliminates the need for additional inverters. Type of output: Passive pull-up, active pull-up, open-collector/drain, and tristate. Specifications for TTL logic sub-families:

II.) Transistor Transistor Logic (TTL): ICs are identified by a number code stamped on the top. The prefix is a manufacturers code. The next two numbers denote the family of ICs such as TTL or CMOS. If letters follow, they indicate the subfamily of the IC. The next numbers indicate the function of the IC, and the last letters indicate the package style. DM 74 LS 283 N

Digital monolithic

TTL commercial

## Plastic Dual In-line Package

Transistor-Transistor Logic, or TTL, refers to the technology for designing and fabricating digital integrated circuits that employ logic gates consisting primarily of bipolar transistors. TTL is named for its dependence on transistor alone to perform basic logical operations. TTL ICs with numbering scheme: Sr. No. 1 2. 3. 4. 5. 6. 7. Series Standard TTL High Power TTL Low power TTL Schottky TTL Low power Schottky TTL Advanced Schottky TTL Advanced Low power Schottky TTL Prefix 7474H74L74S74LS74AS74ALSExamples 7402,74193 74H02,74H193 74L02,74L193 74S02,74S193 74LS02,74LS193 74AS02,74AS193 74ALS02,74ALS193

Comparison of TTL digital logic sub-families: Sr. No. 1. 2. 3. 4. 5. 6. 7. Family Basic Gate NAND NAND NAND NAND NAND NAND NAND Fanout Power Dissipation (mW/gate) 10 22 1 2 19 10 1 Noise Immunity Very good Very good Very good Very good Very good Very good Very good Prop. delay (ns/gate) 10 6 33 9.5 3 1.5 4 Clock (MHz) 35 50 3 45 125 175 50

## TTL TTL-H TTL-L TTL-LS TTL-S TTL-AS TTL-ALS

10 10 20 20 10 40 20

Standard values of TTL characteristics: Characteristics Supply voltage Values For 74 series 4.75 to 2.2.5v For 54 series 4.5 to 2.5v

## TPHL TPLH Fan out Current level Parameters

For 74 series 0 to 70 C For 54 series -55 to + 125C Vth = 2v VIL = 0.8v VOH =2.7v VOL =0.5v 15ns 15ns 20 IIH = 20 micro amperes IIL = -0.36 mA IOH = -400 micro amperes I OL = 8mA Icc(1)=1.6 mA Icc(2)=4.4mA

III.) Operation of Basic TTL NAND gate: The most basic TTL circuit has a single output transistor configured as an inverter with its emitter grounded and its collector tied to Vcc with a pull-up resistor, and with the output taken from its collector. (Ref fig. 3 below)

Fig. 3 Basic TTL NAND gate Analysis with one or more inputs low: With an input low, Q3 should be cutoff. We will assume Q2 is cutoff and then check our assumption. If Q2 is cutoff, then there can be no current coming out of the collector of Q1, hence its base-collector junction can be modeled as an open circuit. The base-emitter junction of Q1 will be conducting. The two unused inputs are assumed to be high, and are thus open. Analysis with input high: Both Q2 and Q3 are saturated. With the inputs high, Q1 is modeled as two diodes with the B-E diodes cutoff, and B-C diode conducting. The current coming out of the emitter of Q2 is the sum of the base and collector currents. Part of this current will go down through the 1 K resistor to ground and the rest will enter the base of Q3. Disadvantages of basic TTL NAND gate: One of the problems with the TTL gate circuit is that the pull-up resistor on the output transistor will prevent rapid charging of any wiring capacitance on the output. One way to improve the rise time is to reduce the resistance value as is often done, but this also increases the power dissipation when the output is low.

If we look at the circuit, we observe that when the transistor is saturated, it presents a very low effective resistance to ground. The problem arises when the output is high and the pull-up resistor is too large. Ideally a very low resistance pull-up is required when the output is high, but a very high pull-up resistance when the output is low. In this way, we could get quick charging and very low power dissipation. This is overcome by the totem-pole output stage for TTL. IV.) Different ways of output representation: 1. Wired - AND connection Because the active pull-up or totem-pole output of the TTL gate always has one transistor cutoff and the other turned on, you cannot connect two outputs together. If one is trying to pull the output high, and the other is trying to pull it low, you will have a very low impedance path to ground and very large currents. For the same reason, the output must not be connected to any voltage source or to ground through a low impedance path. In one state or the other, there would be a low impedance path and large currents. TTL circuits with open-collector outputs are available which can be used for wired-AND connections. Wire ANDing: For gates where the logic 0 level is caused by saturating a transistor, an additional level of logic can be obtained by connecting the outputs or collectors of several gates together. The technique is called wire ANDing TTL circuits with totem-pole outputs are not suitable for wire ANDing as they may suffer from current spikes, thereby damaging the transistors. 2. Open collector gates In order to overcome the limitations created by the totem pole output circuit, some gates are manufactured with the output collector left open. One example is the 7405, a quad 2-input NAND gate with open collector outputs. If you connect a resistor as the pull-up, you can use this resistor to source current when the output is high and/or you can wire- AND the collectors together. Operation of TTL open collector output stage:

Fig. 4 TTL open collector output stage As shown in figure 4, in order to get the proper HIGH and LOW logic levels of the circuit, the external pull-up resistor must be connected to Vcc from the collector of Q3. When Q3 is off,

the output is pulled up to Vcc through the external resistor. When Q3 is on, the output is connected to near-ground through the saturated transistor. V) Operation of 2-input TTL NAND Gate with a Totem Pole Output Stage: Most TTL circuits use a totem pole output circuit, which replaces the pull-up resistor with a Vcc-side transistor sitting on top of the GND-side output transistor. The emitter of the Vcc-side transistor (whose collector is tied to Vcc) is connected to the collector of the GND-side transistor (whose emitter is grounded) by a diode. The output is taken from the collector of the GND-side transistor. Figure 5 shows a basic 2-input TTL NAND gate with a totem-pole output.

Fig. 5 Two-input TTL NAND Gate with Totem Pole Output Stage Case I: Applying a logic '1' input voltage to both emitter inputs of T1, reverse-biases both baseemitter junctions, causing current to flow through R1 into the base of T2, which is driven into saturation. When T2 starts conducting, the stored base charge of T3 dissipates through the T2 collector, driving T3 into cut-off. On the other hand, current flows into the base of T4, causing it to saturate and pull down the output voltage Vo to logic '0', or near ground. Also, since T3 is in cut-off, no current will flow from Vcc to the output, keeping it at logic '0'. Note that T2 always provides complementary inputs to the bases of T3 and T4, such that T3 and T4 always operate in opposite regions, except during momentary transition between regions. Case II: On the other hand, applying a logic '0' input voltage to at least one emitter input of T1 will forward-bias the corresponding base-emitter junction, causing current to flow out of that emitter. This causes the stored base charge of T2 to discharge through T1, driving T2 into-cutoff. Now that T2 is in cut-off, current from Vcc will be diverted to the base of T3 through R3, causing T3 to saturate. On the other hand, the base of T4 will be deprived of current, causing T4 to go into cut-off. With T4 in cut-off and T3 in saturation, the output Vo is pulled up to logic '1', or closer to Vcc. Outputs of different TTL gates that employ the totem-pole configuration must not be connected together since differences in their output logic will cause large currents to flow from the logic '1' output to the logic '0' output, destroying both output stages. The output of a typical TTL gate under normal operation can sink currents of up to 16 mA.

VI.) Comparison of TTL and CMOS logic families: Sr. No. 1 Parameter Operating temperature range TTL Military : 54, 54L, 54LS - 55 oC to 125 oC General : 74, 74L, 74LS 0oC to 70 oC 2. Technologies Bipolar Junction (Here, transistors are current operated, so lower number of gates can be put on an IC.) Field Effect (Here, transistors are voltage operated devices, so results in a much higher density of logic gates that can be put on an IC.) High power dissipation Low power (10mW/gate) dissipation (0.01 mW/gate 10 50 10nS/gate 70 nS/gate Fastest logic family Comparatively slow Much less sensitive to More susceptible to damage from electrostatic damage from discharge electrostatic discharge CMOS

3. 4. 5. 6. 7.

Power Dissipation Fan out Propagation Delay Speed of operation Static Electricity

CONCLUSION: The important TTL characteristics as well as their typical values are studied. Different logic families of TTL and basic configurations are also viewed in detail. Comparison of TTL with CMOS logic families is described.

FAQs: 1) What is a logic family? A group of compatible ICs with the same logic levels and supply voltages for performing various logic functions have been fabricated using a specific circuit configuration which is referred to as logic family. 2) What are the basic electrical characteristics of TTL? The various characteristics of digital ICs are: 1. Speed of operation 2. Power dissipation 3. Figure of merit 4. Fan out 5. Current and voltage parameters 6. Noise immunity 7. Operating temperature range 8. Power supply requirements 9. Flexibilities available (Description is as given in the write-up above) 3) What are the disadvantages of basic TTL NAND gate? One of the problems with the TTL gate circuit is that the pull-up resistor on the output transistor will prevent rapid charging of any wiring capacitance on the output. One way to improve the rise time is to reduce the resistance value as is often done, but this also increases the power dissipation when the output is low. If we look at the circuit, we observe that when the transistor is saturated, it presents a very low effective resistance to ground. The problem arises when the output is high and the pull-up resistor is too large. Ideally a very low resistance pull-up is required when the output is high, but a very high pull-up resistance when the output is low. In this way, we could get quick charging and very low power dissipation. This is overcome by the totem-pole output stage for TTL. 4) What is wired AND-ing? For gates where the logic 0 level is caused by saturating a transistor, an additional level of logic can be obtained by connecting the outputs or collectors of several gates together. The technique is called wire ANDing. References: R.P.Jain, Modern digital electronics, 3rd edition, Tata McGraw Hill publication. James W. Bignell, Robert Donovan, Digital Electronics, 5th edition, Cengage Learning publication. Malvino, Leach, Saha Digital Principles and Applications, 6th edition, Tata McGraw Hill publication.

ASSIGNMENT NO: 02 CODE CONVERTER AIM: To Design (truth table, K map) and implement the circuit for the following 4-bit code conversion. Binary to Gray Code Gray to Binary Code BCD to Excess-3 Code Excess-3 to BCD Code ICs Used: IC 7404 (Hex INV), 7432 (OR-gate), 7408 (AND-gate), 7486 (Ex-or gate) THEORY: There is a wide variety of binary codes used in digital systems. Some of these codes are binarycoded - decimal (BCD), Excess-3, Gray, octal, hexadecimal, etc. Often it is required to convert from one code to another. For example the input to a digital system may be in natural BCD and output may be 7-segment LEDs. The digital system used may be capable of processing the data in straight binary format. Therefore, the data has to be converted from one type of code to another type for different purpose. The various code converters can be designed using gates. 1) Binary Code: It is straight binary code. The binary number system (with base 2) represents values using two symbols, typically 0 and 1. Computers call these bits as either off (0) or on (1). The binary code are made up of only zeros and ones, and used in computers to stand for letters and digits. It is used to represent numbers using natural or straight binary form. It is a weighted code since a weight is assigned to every position. Various arithmetic operations can be performed in this form. Binary code is weighted and sequential code. 2) Gray Code: It is a modified binary code in which a decimal number is represented in binary form in such a way that each Gray- Code number differs from the preceding and the succeeding number by a single bit. (E.g. for decimal number 5 the equivalent Gray code is 0111 and for 6 it is 0101. These two codes differ by only one bit position i. e. third from the left.) Whereas by using binary code there is a possibility of change of all bits if we move from one number to other in sequence (e.g. binary code for 7 is 0111 and for 8 it is 1000). Therefore it is more useful to use Gray code in some applications than binary code. The Gray code is a non-weighted code i.e. there are no specific weights assigned to the bit positions. Like binary numbers, the Gray code can have any no. of bits. It is also known as reflected code. Applications: 1. Important feature of Gray code is it exhibits only a single bit change from one code word to the next in sequence. This property is important in many applications such as Shaft encoders where error susceptibility increases with number of bit changes between adjacent numbers in sequence. 2. It is sometimes convenient to use the Gray code to represent the digital data converted from the analog data (Outputs of ADC). 3. Gray codes are used in angle-measuring devices in preference to straight forward binary encoding. 4. Gray codes are widely used in K-map. The disadvantage of Gray code is that it is not good for arithmetic operation

A) Binary to Gray Conversion In this conversion, the input straight binary number can easily be converted to its Gray code equivalent. Record the most significant bit as it is. EX-OR this bit to the next position bit, record the resultant bit. Record successive EX-ORed bits until completed. Convert 0011 binary to Gray. 0 0 1 1 Binary code

+ 0 (MSB) 0

+ 1

## + 0 Gray code (LSB)

B) Gray To Binary Conversion The Gray code can be converted to binary by a reverse process. Record the most significant bit as it is. EX-OR binary MSB to the next bit of Gray code and record the resultant bit. Continue the process until the LSB is recorded. Convert 1011 Gray to Binary code. 1 0 + + 1 + 1 Gray code

1 (MSB)

## Binary code (LSB)

3) BCD Code: Binary Coded Decimal (BCD) is used to represent each of decimal digits (0 to 9) with a 4-bit binary code. For example (23)10 is represented by 0010 0011 using BCD code rather than(10111)2 This code is also known as 8-4-2-1 code as 8421 indicates the binary weights of four bits(23, 22, 21, 20). It is easy to convert between BCD code numbers and the familiar decimal numbers. It is the main advantage of this code. With four bits, sixteen numbers (0000 to 1111) can be represented, but in BCD code only 10 of these are used. The six code combinations (1010 to 1111) are not used and are invalid. Applications: Some early computers processed BCD numbers. Arithmetic operations can be performed using this code. Input to a digital system may be in natural BCD and output may be 7-segment LEDs. It is observed that more number of bits are required to code a decimal number using BCD code than using the straight binary code. However in spite of this disadvantage it is very convenient and useful code for input and output operations in digital systems.

EXCESS-3 Code: Excess-3, also called XS3, is a non weighted code used to express decimal numbers. It can be used for the representation of multi-digit decimal numbers as can BCD. The code for each decimal number is obtained by adding decimal 3 and then converting it to a 4-bit binary number. For e.g. decimal 2 is coded as 0010 + 0011 = 0101 in Excess-3 code. This is self complementing code which means 1s complement of the coded number yields 9s complement of the number itself. Self complementing property of this helps considerably in performing subtraction operation in digital systems, so this code is used for certain arithmetic operations. BCD To Excess 3 Code Conversions: Convert BCD 2 i. e. 0010 to Excess 3 code For converting 4 bit BCD code to Excess 3, add 0011 i. e. decimal 3 to the respective code using rules of binary addition. 0010 + 0011 = 0101 Excess 3 code for BCD 2 Excess 3 code To BCD Conversion: The 4 bit Excess-3 coded digit can be converted into BCD code by subtracting decimal value 3 i.e. 0011 from 4 bit Excess-3 digit. e.g. Convert 4-bit Excess-3 value 0101 to equivalent BCD code. 0101-0011= 0010- BCD for 2 DESIGN: A) Binary to Gray Code Conversion: Truth Table: INPUT (BINARY CODE) B3 B2 B1 B0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 K-Map: OUTPUT (GRAY CODE) G3 G2 G1 G0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 0 0

Circuit Diagram:

Fig. 1 Logical Circuit Diagram for Binary to Gray Code Conversion B) Gray to Binary Code Conversion: Truth Table: INPUT (GRAY CODE) G3 G2 G1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 0 OUTPUT (BINARY CODE) B3 B2 B1 B0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0

G0 0 1 1 0 0 1 1

0 1 1 1 1 1 1 1 1 K-Map:

1 1 1 1 1 0 0 0 0

0 0 0 1 1 1 1 0 0

0 0 1 1 0 0 1 1 0

0 1 1 1 1 1 1 1 1

1 0 0 0 0 1 1 1 1

1 0 0 1 1 0 0 1 1

1 0 1 0 1 0 1 0 1

Circuit Diagram:

Fig. 2 Logical Circuit Diagram for Gray to Binary Code Conversion C) BCD To Excess-3 Code Conversion:

## Truth Table: INPUT (BCD CODE) B3 B2 B1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 K-Map:

B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

## OUTPUT (EXCESS-3 CODE) E3 E2 E1 E0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 x x x x x x x x x x x x x x x x x x x x x x x x

Circuit Diagram:

Figure.3 Logical Circuit Diagram for BCD to Excess-3 Code Conversion D) Excess-3 To BCD Conversion: Truth Table: INPUT E3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 K-Map: (EXCESS-3 CODE) E2 E1 E0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 OUTPUT (BCD CODE) B3 B2 B1 X X X X X X X X X 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 X X X X X X X X X

B0 X X X 0 1 0 1 0 1 0 1 0 1 X X X

Circuit Diagram:

## Figure 4: Logical Circuit Diagram for Excess-3 to BCD Conversion

Hardware Requirements Table: GATE XOR NOT AND OR IC 7486 7404 7408 7432 Quantity 8 7 12 6

Test the circuit for all possible combinations of input and output codes. CONCLUSION: Thus, we studied different codes and their conversions including applications. The truth tables have been verified using IC 7486, 7432, 7408, and 7404.

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FAQs with answers: Q.1) What is the need of code converters? There is a wide variety of binary codes used in digital systems. Often it is required to convert from one code to another. For example the input to a digital system may be in natural BCD and output may be 7segment LEDs. The digital system used may be capable of processing the data in straight binary format. Therefore, the data has to be converted from one type of code to another type for different purpose. Q.2) What is Gray code? It is a modified binary code in which a decimal number is represented in binary form in such a way that each Gray- Code number differs from the preceding and the succeeding number by a single bit. (e.g. for decimal number 5 the equivalent Gray code is 0111 and for 6 it is 0101. These two codes differ by only one bit position i. e. third from the left.) It is non weighted code. Q.3) What is the significance of Gray code? Important feature of Gray code is it exhibits only a single bit change from one code word to the next in sequence. Whereas by using binary code there is a possibility of change of all bits if we move from one number to other in sequence (e.g. binary code for 7 is 0111 and for 8 it is 1000). Therefore it is more useful to use Gray code in some applications than binary code. Q.4) What are applications of Gray code? 1. Important feature of Gray code is it exhibits only a single bit change from one code word to the next in sequence. This property is important in many applications such as Shaft encoders where error susceptibility increases with number of bit changes between adjacent numbers in sequence. 2. It is sometimes convenient to use the Gray code to represent the digital data converted from the analog data (Outputs of ADC). Gray codes are used in angle-measuring devices in preference to straight forward binary encoding. Gray codes are widely used in K-map Q.5) What are weighted codes and non-weighted codes? In weighted codes each digit position of number represents a specific weight. The codes 8421, 2421 and 5211 are weighted codes. Non weighted codes are not assigned with any weight to each digit position i.e. each digit position within the number is not assigned a fixed value. Gray code, Excess-3 code are nonweighted code. Q.6) Why is Excess-3 code called as self-complementing code? Excess-3 code is called self-complementing code because 9s complement of a coded number can be Obtained by just complementing each bit. Q.7) What is invalid BCD? With four bits, sixteen numbers (0000 to 1111) can be represented, but in BCD code only 10 of these are used as decimal numbers have only 10 digits fro 0 to 9. The six code combinations (1010 to 1111) are not used and are invalid. 22 / 84

References: 1. Digital Fundamentals by Floyd & Jain 2. Modern Digital Electronics by R P Jain 3. Digital Principles and Applications by Malvino, Leach, Saha 4. Digital Electronics by Bignell

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Valid BCD result = (11) BCD CASE III : Sum < = 9 & carry = 1.

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Truth Table for design of combinational circuit for BCD adder to check invalid BCD : INPUT S3 0 0 S2 0 0 S1 0 0 S0 0 1 OUTPUT Y 0 0

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0 0 0 0 0 0 1 1 1 1 1 1 1 1 Y = S3S2 + S3S1

0 0 1 1 1 1 0 0 0 0 1 1 1 1

1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1

## Circuit diagram for BCD adder :

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B ) BCD SUBTRACTOR: BCD subtractor is a circuit that subtracts two BCD digits & produces a result also in BCD. Rules for BCD subtraction : 1. Find 9s complement of the subtrahend. a) To find 9s complement first find 1s complement of subtrahend. b) Add (10)10 i.e. (1010)2 to it. 2. Add 9s complement of the subtrahend to the minuend using BCD rules of addition. 3. After BCD addition if MSD is 0, result is negative expressed in 9s complement form to get it in natural form find 9s complement of the LSD of the result. 4. But after BCD addition if MSD is 1 it indicates that result is positive expressed in natural form & add ( 1 )10 i. e. ( 0001 )2 to it.

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CASE I : carry = 1, answer is positive Subtract BCD digit 2 from 8. 1. 9s complement of (2)10 i.e. (0010)2 a) 1s complement of (2)10 1101 b) add (1010)2 + 1010 --------1 0111 2.

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## OBSERVATION : A] BCD adder :

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INPUT 1st Operand A3 (MSB ) A2 A1 A0 (LSB) B3 (MSB ) 2nd Operand B2 B1 MSD B0 Cout (LSB)

## OUTPUT LSD S3 (MSB ) S2 S1 S0 (LSB)

B] BCD Subtractor : INPUT 1st Operand (Minuend) A3 (MSB A2 ) OUTPUT 2nd Operand (Subtrahend) A1 B3 A0 (MSB (LSB) ) B2 B1 Sign Magnitude S3 (MSB ) S2 S1 S0 (LSB)

B0 Cout (LSB)

## CONCLUSION : Based on observation.

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ASSIGNMENT NO 4 MULTIPLEXER AIM: Realization of Boolean expression using Multiplexer 74151/74153. Verification of Functional table. Verification of Sum of Product (SOP) and Product of Sum (POS) with the help of given Boolean expression. Verify the functional table using cascading of two multiplexers. Realization of Boolean expression using hardware reduction method for the given equation. For Example: F(A,B,C,D) = m ( 2,4,6,7,9,10,11,12,15 ) Or F(A,B,C ) = m( 0,3,6,10 ) APPRATUS: Digital trainer board, Power supply, patch cords. THEORY: Multiplexer is a digital switch which allows digital information from several sources to be routed onto a single output line. Basic multiplexer has several data inputs and a single output line. The selection of a particular input line is controlled by a set of selection line. There are 2n input lines & n is the number of selection line whose bit combinations determines which input is selected .It is Many into One. Significance and application of multiplexer : No need to simplify logic expression, The IC package count is minimized. Logic design is simplified. It is possible to expand the range of inputs for multiplexers beyond the available Range in the integrated circuits. This can be accomplished by interconnecting several multiplexers. So it is used in the data acquisition circuit in designing the combinational circuit. To minimize number of connections in communication system were we need to handle thousands of connections. Ex. Telephone exchange Demultiplexer is a logic used to perform exactly reverse function performed by multiplexer. It accepts a single input and distributes among several outputs. The selection of a particular output line is controlled by a set of selection line. There are n input lines & 2m is the number of selection line whose bit combinations determine which output to be selected. Point Input Output Select line Multiplexer Many input lines Single output line 2m = n Demultiplexer Single input line Many output line n = 2m Decoder Many input line also Acts as select line Many output line, Active low output Enable inputs used

Encoder and decoder : Encoders are used to encode given digital number into different numbering format .like decimal to BCD Encoder, Octal to Binary. Decoders are used to decode a coded binary word like BCD to seven segment decoder. Thus encoder and decoder are application specific logic develop, we can not use any type of input for any encoder and decoder. Need to select input according to encoder and decoder being selected for a particular application as mention in examples above.

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## DESIGN: Truth Table of MUX is as shown. SELECTION LINES STROBE OUTPUT C X 0 0 0 0 1 1 1 1 B X 0 0 1 1 0 0 1 1 A X 0 1 0 1 0 1 0 1 Y 0 D0 D1 D2 D3 D4 D5 D6 D7

1 0 0 0 0 0 0 0 0

X = dont care condition. Convert the given Boolean expression into standard SOP / POS format if required and complete the logic diagram design accordingly for realization of the same. As an example: Function = Sum Of Product (SOP) Y = m (1, 2, 3 4, 5, 6,7) SELECTION STROBE OUTPUTS LINES ____ C B A Y Y 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0

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1 1

1 1

0 1

0 0

1 1

0 0

As an example Function = Product Of Sum (POS) Y = M (0, 5, 6, 7) SELECTION STROBE OUTPUTS LINES ____ C B A Y Y 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1

Design the MUX Tree to verify the functional table for logical connection of two cascaded multiplexers 74151/74153. Example: implementing 8:1 using two 4:1 MUX as cascading of two 4:1 multiplexer results in 8:1 E= S2 S1 S0 output Multiplexer1 0 0 0 D0

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0 0 0 1 1 1 1

0 1 1 0 0 1 1

1 0 1 0 1 0 1

D1 D2 D3 D4 D5 D6 D7

Multiplexer2

## Use Enable pin of MUX as third select line.

Use hardware reduction method and implement the given Boolean expression with the help of neat logic diagram. Use any one method. Example: F(A,B,C,D) = m ( 2,4,5,7,10,14 ) First method D0 0 A 8 0 D1 1 9 0 D2 2 10 1 D3 3 11 0 D4 4 12 D5 5 13 D6 6 14 A D7 7 15

Consider B,C,D as a select line Use NOT gate to obtain A and complement of it.

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Second method: F (A, B, C, D) = m (2,4,6,7,9,10,11,12,15 ) 1. Make a combination of pair according to same Values of A,B,C 2. Check the output values with respect to value of D. A B C D output output 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 0 1 D D 1 D 1 D D

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Hardware requirement: Name of the IC Description Quantity 74151/74153 8:1MUX/4:1MUX 02/01 7404 NOT 01 7432 OR 01

CONCLUSION Multiplexer is used as a data selector to select one out of many data inputs. It is used for simplification of logic design. It is used to design combinational circuit. Use of multiplexer minimizes no. of connections.

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FAQ: 1) What is a MULTIPLEXER? Multiplexer is a digital switch which allows digital information from several sources to be routed onto a single output line. Basic multiplexer has several data inputs and a single output line. 2) What is a DE-MULTIPLEXER? Demultiplexer is a logic used to perform exactly reverse function performed by multiplexer. It accepts a single input and distributes among several outputs. The selection of a particular output line is controlled by a set of selection line. 3) Enlist applications of MUX? 1. It is used in the data acquisition circuit 2. In designing the combinational circuit 3. . Telephone exchange 4) Define the terms Encoder and Decoder Encoders are used to encode given digital number into different numbering format .like decimal to BCD Encoder, Octal to Binary. Decoders are used to decode a coded binary word like BCD to seven segment decoder. Thus encoder and decoder are application specific logic develop, we can not use any type of input for any encoder and decoder.

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ASSIGNMENT NO 5 -ASSIGNMENT NO ASYNCHRONOUS COUNTER AIM: To design and implement 4 bit UP, Down, Controlled UP/Down Ripple Counter using MSJK Flip-flop. ICs USED: IC 7476 (MS-JK Flip-flop), IC 7408(Quad 2 i/p AND Gate), IC 7432 (Quad 2 i/p OR Gate) and IC 7404 (Hex Inverter). THEORY: A digital counter is a set of flip flop. When state changes in response to pulse applied at i/p to counter. The flip flop are connected such that their combined state at any time is binary equivalent of total no. of pulses that have occurred up to that time. Thus its name implies a counter is used to count pulse. A counter is used as frequency dividers. To obtain waveform with frequency that is specific fraction of clock frequency. Counter may be Asynchronous or synchronous. An Asynchronous counter uses T flip flop to perform a counting function. The actual hardware used is usually J-K flip flop connected to logic1.Even D flip flops may be used here. In asynchronous counter commonly called ripple counter, the first flip-flop is clocked by the external clock pulse & then each successive flip-flop is clocked by the Q or /Q output the previous flip-flop. Therefore in an asynchronous counter the flip-flop are not clocked simultaneously. The input of MS-JK is connected to VCC because when both inputs are one output is toggled. As MS-JK is negative edge triggered at each high to low transition the next flip-flop is triggered. On this basis the design is done for MOD-8 counter. 1) UP Counter: Fig 1 shows 4 bit Asynchronous Up Counter. Here Flip-flop A act as a MSB Flip-flop and Flip-flop D can act as a LSB Flip-flop. Clock pulse is connected to the Clock of Flip-flop D. Output of Flip-flop D (QD) is connected to clock of next flip-flop(i.e Flip-flop C) and so on. As soon as clock pulse changes output is going to change(at the negative edge of clock pulse) as a Up count sequence. 2) DOWN Counter: Fig 2 shows 4 bit Asynchronous Down Counter. Here Flip-flop A act as a MSB Flip-flop and Flip-flop D can act as a LSB Flip-flop. Clock pulse is connected to the Clock of Flip-flop D. Output of Flip-flop D (QD) is connected to clock of next flip-flop(i.e Flip-flop C) and so on. As soon as clock pulse changes output is going to change(at the negative edge of clock pulse) as a Down count sequence. In both the counters Inputs J and K are connected to Vcc, hence J-K Flip flop can work in toggle mode. Preset and Clear both are connected to logic 1. A) Truth Table Up Counter Down Counter

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Counter States 7 6 5 4 3 2 1 0

Count QA QB 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0

QC 1 0 1 1 1 0 1 0

B) Logic diagram

## Fig 1: 3 Bit Asynchronous Up Counter

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Fig 2: 3 Bit Asynchronous Down Counter Hardware requirements: Sr. No 1 IC 7476 Quantity 2

3- bit Asynchronous up/Down counter: As name indicates an up/ down counter which can count both in upward & downward direction. It is also called as forward/backward counter or bidirectional counter so a control signal or a mode signal M is required to choose the directional of count. When M=1 for up counting Q1 is transmitted to clock of FF2 & M=2 for down counting Q1 is transmitted to clock of FF2. This is achieved by using two AND gate & one OR gate as shown in fig. the external clock signal is applied to FF1. The design of combination circuit as shown in fig is desired from truth table. The combinational circuit is designed from the present state & next state. Conditioning the starry of control or mode signal. After solving the K-map for truth table of counter we get equation for clock signal so as Clock signal FF=Q1M+Q1M. Thus this counter will count upward as well as downward direction. Excitation table of 3-Bit up/down Counter: M=0 for down counter and M=1 for up counter

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Present state Q3 Q2 Q1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1

Mode M 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Next state Q3 Q2 Q1 1 1 1 0 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0

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LSB Fig. 3: 3-Bit Asynchronous UP/Down Counter Hardware requirements: Sr. No 1 2 3 4 IC 7476 7408 7404 7432 Quantity 2 1 1 1

MSB

CLK

Qa

Qb

Qc

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CLK

Qc

Qb

Qa

## Timing Diagram for 3 Bit Asynchronous Up/Down Counter

Up/Dn=1

CLK 0 0 0
Up/Dn=0

1 0 0

0 1 0

1 1 0

0 0 1

1 0 1

0 1 1

1 1 1

CLK 0 1 0 1 0 1 1 1 1 1

1 0

0 1 0 1 0

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Uses: The synchronous counters are specially used as the counting devices. They are also used to count number of pulses applied. It also works for dividing frequency. It helps in counting the number of product coming out of the machinery where product is coming out at equal interval of time. CONCLUSION: Thus we checked & verified truth table of counters.

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FAQs with answers: 1) What do you mean by Counter? A Counter is a register capable of counting the no. of clock pulses arriving at its clock inputs. Count represents the no. of clock pulses arrived. A specified sequence of states appears as the counter output. 2) What are the types of Counters? Explain each. There are two types of counters as Asynchronous Counter and Synchronous Counter. Asynchronous Counter: In this counter, the first flip-flop is clocked by the external clock pulse and then each successive flip-flop is clocked by the Q or Q o/p of the previous flip-flop. Hence in Asynchronous Counter flipflops are not clocked simultaneously and hence called as Ripple Counter. Synchronous Counter: In this counter, the common clock input is connected to all the flip-flops simultaneously. 3) What are the problems involved in Ripple Counter? There are two problems in Ripple Counter as Glitch and Propagation delay of flip-flop. 4) Why asynchronous counters are called as ripple counters? In asynchronous counter the first flip-flop is clocked by the external clock pulse & then each successive flip-flop is clocked by the Q or /Q output of the previous flip-flop i.e. clock (pulses) applied ripple from stage to stage to stage (LSB to MSB) hence asynchronous counters are called as ripple counters. 5) What do you mean by pre-settable counters? A counter in which starting state is not zero can be designed by making use of the preset inputs of the flip flops. This is referred to as loading the counter asynchronously. This is referred to as pre-settable counter. 6)What are the applications of asynchronous counters? Digital clock, Frequency divider circuits etc 7) Whether frequency division takes place in asynchronous counters? Yes. In counter, the signal at the output of last flip flop (i.e. MSB) will have a frequency equal to the input clock frequency divided by the MOD number of the counter. 8) Can n- bit up asynchronous counter will act as n- bit down asynchronous counter without changing the position of the clock? Yes. Instead of taking output of a counter from uncomplimentary output (Q), if we take it from complimentary output (Q bar) ,the same counter circuit will work as down counter. References : 1) Modern Digital Electronics by R P Jain

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ASSIGNMENT NO 8 SYNCHRONOUS COUNTER AIM: To design and implement 4 bit UP, Down, Controlled UP/Down Synchronous Counter using MSJK Flip-flop. ICs USED: Digital Trainer Kit, IC 7476 (MS-JK Flip-flop), IC 7408 (Quad 2 i/p AND Gate), IC 7432 (Quad 2 i/p OR Gate) and IC 7404 (Hex Inverter). THEORY: Counters are logical device or registers capable of counting the no of states or no of clock pulse arriving at its clock input where clock is a timing parameter arriving at regular intervals of time, so counters can be also used to measure time & frequencies. They are made up of flip flops. Where the pulse are counted to be made of it goes up step by step & the o/p of counter in the flip flop is decoded to read the count to its starting step after counting n pulse incase of module & counters. When counter is clocked such that each flip flop in the counter is triggered at the same time, the counter is called as synchronous counter. Synchronous binary counter have regular & can easily be constructed with complimentary flip flop & gates. The gates propagation delay at reset time will not be present or we may say will not occur. 1) Synchronous up counter: The up counter counts binary form 0 to7 i.e.(000 to 111).for this we are using JK flip flop. In IC 74LS76, 2 J-K flip flops are present. The clock pulse is given at pin 1 to 6 of the 1st IC & pin 1 of 2nd IC. This unable to apply clock at a time to all these flip flop. The State table is as shown. Present state C B A 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 K-Map : BA C 0 1 0 01 0 0 0 X X JC=BA 0 01 47 / 84 11 1 X 11 10 0 X 10 Next state C B A 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 Flip flop 3 JC KC 0 x 0 x 0 x 1 x x 0 x 0 x 0 x 1 Flip flop 2 JB KB 0 x 1 x x 0 x 1 0 x 1 x x 0 x 1 flip flop 1 JA KA 1 X x 1 1 X x 1 1 X x 1 1 X x 1

BA

C 0 1

## 0 X X 0 0 KC=BA BA 0 01 0 0 1 0 1 JB=A 0 01 0 X X X X KB=A

X 1 11 X X 11 1 1

X 0 10 X X 10 0 0

C 0 1

## BA C 0 1 Similarly JA=1 and KA=1

2) Synchronous down counter: This is used to count pulse from 7-0 i.e.(111-000).for this also 2 ICs of 74LS76 are required & hence we use 3 JK flip flops. Here also clock is given to 1st & 6th pin of 1st IC & 1st pin of 2nd IC enabling to apply clock to all flip flop at a time. State table is as shown. Present state Next state Flip flop 3 Flip flop 2 Flip flop 1 C B A C B A JC KC JB KB JA KA

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1 1 1 1 0 0 0 0

1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0

1 1 1 0 0 0 0 1

1 0 0 1 1 0 0 1

0 1 0 1 0 1 0 1

X X X X 0 0 0 1

0 0 0 1 X X X X

X X 0 1 X X 0 1

0 1 X X 0 1 X X

X 1 X 1 X 1 X 1

1 X 1 X 1 X 1 X

The 3-bit binary Up/Down synchronous counter with a direction control M using J-K Flip-flop. Excitation Table - The designing is given in excitation table. For M = 0, it acts as an Up counter and for M =1 as an Down counter. The number o flip-flops required is 3. The inputs of flip-flops are determined by using excitation table. Present State 0 0 1 1 Next State 0 1 0 1 J 0 1 X X K X X 1 0

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Control input M 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Present State QC QB QA 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0

## Next State QC+1 QB+1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 1 1 1 0 1 0 0 1 0 1 0 0 0 0 1 1

QA+1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1

## Input for Flip-flop JC KC JB KB 0 X 0 X 0 X 1 X 0 X X 0 1 X X 1 X 0 0 X X 0 1 X X 0 X 0 X 1 X 1 X 0 1 X X 0 X 0 X 0 X 1 X 1 0 X 0 X 1 X 0 X X 0 0 X X 1 1 X 1 X

JA 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X

KA X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1

## JB = MQA + MQA KB = MQA + MQA

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QBQA 00 MQC 00 01 11 10 0 X X 1 01 0 X X 0 11 1 X X 0 10 0 X X 0

VCC

J B K

Q Q

J C K

Q Q

QB

QC

## IC 7476 7408 7404 7432

Quantity 2 1 1 1

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Uses: The synchronous counter is specially used as the counting devices. They are also used as counter to count the no of clock pulses applied. It also works for counting frequency & is used in frequency divider circuit. It is used in digital voltmeter. It is also used in counter type A to D converter. It is also used for time measurement. It is also used in digital triangular wave generator. It helps in counting the no of product coming out from machinery where product is coming out at equal interval of time. CONCLUSION Up and down counters are successfully implemented, the counters are studied & o/p are checked. The truth table is verified.

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FAQs with answers: 1) What are the applications of synchronous counters? Digital clock, Frequency divider circuits, Frequency counters, Used in analog to digital converters 2) What are the advantages of synchronous counters over asynchronous counters? Propagation delay time is reduced. Can operate at a much higher frequency than the asynchronous counters. 3) Ring counter is an example of synchronous counters or asynchronous counter? Synchronous counter. Since all the flip flops are clocked simultaneously. 4) Twisted Ring (Johnsons) counter is an example of synchronous counters or asynchronous counter? Synchronous counter. Since all the flip flops are clocked simultaneously. 5) What is the difference between ring counter and twisted ring counter? In ring counter pulses to be counted are applied to a counter , it goes from state to state and the output of the flip flop s in the counter is decoded to read the count. Here the uncomplimentary output (Q) of last flip flop is fed back as an input to first flip flop. Ring counters are referred as MOD N counters. But in Twisted ring counter the complimentary output (Q bar) of last flip flop is fed back as an input to first flip flop. Twisted Ring counters are referred as MOD 2N counters. 6) What are the applications of ring counters? Ring counter outputs are sequential non-overlapping pulses which are useful for control state counters, Used in stepper motor, which requires pulses to rotate it from one position to the next. Used as divide by N ((MOD N) counters. 7) What are the applications of ring counter twisted ring counters? Used as divide by 2N ((MOD 2N) counters. Used for control state counters. Used for generation of multiphase clock. 11) List the Synchronous Counter ICs. IC 74160 : Decade Up Counter IC 74161 : 4 bit binary Up Counter IC 74162 : Decade Up Counter IC 74163 : 4 bit binary Up Counter IC 74168 : Decade Up/Down Counter IC 74169 : 4 bit Binary Up/Down Counter IC 74190 : Decade Up/Down Counter IC 74191 : 4 bit Binary Up/Down Counter IC 74192 : Decade Up/Down Counter IC 74193 : 4 bit Binary Up/Down Counter References: 1)Modern Digital Electronics, r.p.jain,3rd edition ,tmh

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ASSIGNMENT NO 09 MOD N COUNTER AIM: Modulo N asynchronous and synchronous counter ( IC 7490 & 74191 ) A) To design and implement mod - 10, mod - 99 BCD counter using IC 7490. B) To design and implement up, down, truncated Binary counter using IC 74191. IS USED: IC 7490, IC 74191, basic gates. THEORY: IC 7490 is a TTL MSI (medium scale integration) decade counter. It contains 4 master slave flip flops internally connected to provide MOD-2 i.e. divide by 2 and MOD-5 i.e. divide by 5 counter.. MOD-2 and Mod-5 counters can be used independently or in cascading. It is a 4-bit ripple type decade counter. The device consists of 4-master slave flip flops internally connected to provide a divide by two and divide by 5 sections. Each section has a separate clock i/p to initiate state changes of the counter on the high to low clock transition. Since the o/p from the divide by 2 section is not internally connected to the succeeding stages. The device may be operated in various counting modes. In a BCD counter the CP1 input must be externally connected to QA o/p. The CP0 i/p receives the incoming count producing a BCD count sequence. It is also provided with additional gating to provide a divide by 2 counter and binary counter for which the count cycle length is divide by 5. the device may be operated in various counting modes. There are 2 reset i/ps R0(1) and R0(2) both of which need to be connected to the logic 1 for clearing all flip flops. Two set i/ps Rg(1) and Rg(2) when connected to logic are used for setting counter to 1001 (BCD 9). Pin out of IC 7490:
U1 14 1 2 3 6 7 INA INB R01 R02 R91 R92 7490N QA QB QC QD 12 9 8 11

Function table:

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I/p clock 01 02 03 04 05 06 07 08 09 10

Output QD QC 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0

QB 0 0 1 1 0 0 1 1 0 0

QA 0 1 0 1 0 1 0 1 0 1

Count 0 1 2 3 4 5 6 7 8 9

## Timing diagram of MOD 10:

CLK

QA

QB

QC

0 QD

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Design of Mod-7 Counter using IC 7490: Mod-7 counter counts through seven states from 0 to 6 counters and it should reset as soon as the count becomes 7. The o/p of reset logic should be 1 corresponding to invalid states. The reset logic o/p should be applied to pin 2 and 3. QD QC QB QA Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1

RESET I/PS

SET I/PS

R1

R2

S1

S2

VCC

I/P A

FF-A MOD-2

I/P B

GND

QA

QB

QC

QD

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## Timing diagram of MOD 7:

CLK

QA A QB A

QC A

Design of Mod-99 using IC 7490: For MOD-99 two IC 7490s will be required. Hence to implement a divide by 99 counter we have to use two decade counters ICs. A divide by 99 counter counts through 99 states from 0 to 98 and the counter should reset as soon as the count becomes 99. So in order to reset the counter of 99 connect the Q o/p which are equal to 1 in the count of 99 to an And gate & then connect and o/p to the reset i/p of both ICs.

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IC 74191: IC74191 is 4-bit binary synchronous, reversible, up down counter. It contains 4 master slave flip flops with internal gating and steering logic to provide asynchronous reset and synchronous count up/down operations, its asynchronous parallel capability permits the counter to be preset to any desire number D0 to D3 are the parallel data inputs. Information present on the parallel data inputs D0 to D3 is loaded into the counter and appears on the output when the load PL input is low this operation is overrides the counting function .counting is inhabited by the high level on the enable g input, when g input is low internal state changes are initiated synchronously by the low to high transitions of the clock inputs the up/down input signal determines the direction of input.

Pin details : Low voltage level one setup time prior to the low to high clock transition low to high clock transition D0 to D3 input lines PL parallel load. G is Enable input enabling the counting. Q0 to Q3 output lines. Down/up determines the direction of counting. CP clock input for counter. Terminal Count: Max (1111) min (0000). For this stages signal goes high for one clock Pulse. Ripple clock: Clock input for next higher state. Functional Table of IC 74191 : Operating mode Parallel load Count up Count down Hold(No change) Inputs PL L L H H H Outputs U/D X X L H X G X X 1 1 H CP X X X Dn L H X X X L H Count up Count down No change

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## UP counter Logic Diagram no connection vcc

Clock

D3 D2 D1 D0

PL

IC 74191 UP/Down G Q3 Q2 Q1 Q0 TC RC NC NC

## 1 1 1 1 1 1 1 1 1 DOWN counter Logic Diagram

1 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 1

0 0 1 1 0 0 1 1 1

0 1 0 1 0 1 0 0 1

0 0 0 0 0 0 0 0 0

## D3 D2 D1 D0 UP/Down Clock IC 74191

PL

RC G Q3 Q2 Q1 Q0 TC

NC NC

## Outputs DOWN counter Truth Table CLK 1 1 1 1 1 1 1 1 1 Q3 1 1 1 1 1 1 1 0 0 Q2 1 1 1 1 0 0 0 0 1 Q1 1 1 0 0 1 1 0 0 1 Q0 1 0 1 0 1 0 1 0 1 down 1 1 1 1 1 1 1 1 1

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1 1 1 1 1 1 1 0 1 1

0 0 0 0 0 0 0

1 1 1 0 0 0 0 0

1 0 0 1 1 0 0

0 1 0 1 0 1 0

1 1 1 1 1 1 1

G PL UP/DOWN RC

D3

D2

D1 74191

D0

Q3

Q2

Q1

Q0

IC 74191 is 4 bit counter. Thus it counts 0000 to 1111 different 16 states. For MOD11 counter we require states different 11 states so 5 steps must be skipped from 16 states We get MOD11 by presetting counter to value 5. According to the table given make the connection and check for up and down counter. For truncated counter suppose we want up counter 0000 to 0111 then just connect 1 of Q3 connect to pl this gives MOD8 UP For truncated counter suppose we want up counter 1111 to 0111 then just connect 0 of Q3 connect to cp this gives MOD7 down MOD 11 counter 74191

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Preset Count

CLOCK

D3

D2

D1 74191

D0 RC TC

updown

Q3

Q2

Q1

Q0

PL

## Presettable up/down counter

Combinational Circuit Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0 Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 K-Map

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0 1 1 1

0 1 1 1

1 1 0 1

0 1 0 1

PL=Y=Q3Q1Q0+Q3Q2+Q3Q1+Q3Q2 1 1 vcc

Updown

D3

D2 74LS191

D1

D0 PL

CLOCK

Q3

Q2

Q1

Q0

Q3

Q2

Q1

Q0

CONCLUSION: All the given Mod counters are successfully implemented and are correctly verified with the help of IC 7490.

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FAQs:
1. What do you mean modulus counter? 2..How will you use the 7490 IC to design symmetrical divide by 10 frequency counter? 3. Where counters are used? Give real life example of counter.

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ASSIGNMENT NO 10 SEQUENCE GENERATOR AIM: To design and implement sequence generator with and without bushing using IC 7476.. ICs USED: Digital Trainer Kit, IC 7476(Dual JK), 7408 (AND-gate), 7432 (OR-gate). THEORY: A sequential circuit which generates a prescribed sequence of bits in synchronism with a clock is referred to as a sequence generator. These pulse trains or sequence of bits can be used to open valves, close gates, turn on lights, turn off machines and other variety of jobs. For the design of sequence generator, we first determine the required no. of flip flops and the logic circuit for the next state decoder. No. of flip flops required to generate particular sequence can be determined as follows. Find the no. of 1s in the sequence. Find the no. of 0s in the sequence. Take the maximum out of two. If N is the required no. of flip flops, choose minimum value of n to satisfy equation given below. Max(0s , 1s) 2n-1 The sequence generator can be classified as sequence generator without bushing and sequence generator with bushing. The aim in this experiment is to design a sequence generator to generate a sequence of bit i.e. 10101. For the given sequence no. of 1s=3 no. of 0s=2, so minimum value of n which satisfies above relation is 3. Once the no. of flip flops are decided we have to assign unique states corresponding to each bit in the given sequence such that flip flop representing least significant bit generates the given sequence (usually the o/p of flip flop representing the least significant bit is used to generate the given sequence) DESIGN: For the sequence of bits 10101 we require three flip flops as calculated above. The State Diagram, state assignment for this problem is shown below. Where we will use the o/p c i.e. o/p of first flip flop c as a sequence of bits & assign unique states corresponding to each bit in the sequence as shown in state assignment table. A) Sequence Generator Without Bushing: i) State assignment table QA QB QC 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 ii) State Diagram

STATES 1 0 3 2 5

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1 5 0

## Present states QA QB QC 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 iii) State table

Next states QA QB QC 0 1 1 0 0 0 1 0 1 0 1 0 X X X 0 0 1 X X X X X X

JA 0 0 1 0 X X X X

## Flip flop input KA JB KB JC X 1 X 1 X 0 X X X X 1 1 X X 0 X X X X X 1 0 X X X X X X X X X X

KC X 1 X 1 X 0 X X

v) Logic Diagram

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Cr

J1

Pr Q1 F/F-2

J2

Pr Q2 F/F-3

Clk

Q0

K1
Cr

Q1

K2
Cr

Q2

## Q0(LSB) Hardware requirements: GATE JK F/F AND ICs 7476 7408

Q1

Q2(MSB)

Quantity 2 1

B) Sequence Generator with Bushing :The state assignment for this is shown below as we have seen during designing of sequence generator without using bushing we will have the output C i.e. the output of first Flip-Flop is a sequence generator of bits and assign unique states corresponding to each bit in the sequence out with bushing means we have to use unassigned states also that is 4,6,7. i) State Assignment Table QA 0 0 0 0 1 QB 0 0 1 1 0 QC 1 0 1 0 1 STATES 1 0 3 2 5

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4 6 7

## iv) K Map : Present state Q2 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 Next state Q2 0 0 1 0 0 0 0 0 Q1 1 0 0 1 0 0 0 0 Q0 1 0 1 0 0 1 0 0 Flip flop inputs J0 1 X 1 X 0 X 0 X K0 X 1 X 1 X 0 X 1 J1 1 0 X X 0 0 X X K1 X X 1 0 X X 1 1 J2 0 0 1 0 X X X X K2 X X X X 1 1 1 1

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J0 = Q2 J1 = Q2Q0 J2 = Q1Q0

## K0 = Q2 + Q1 K1 = Q2 + Q0 K2=1 GATE JK F/F AND OR ICs 7476 7408 7432 Quantity 2 1 1

Hardware requirements:

CONCLUSION: In this way sequence generator with & without bushing is studied and implemented.

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FAQs with Answers : 1) What is sequential logic circuit? A sequential logic circuit consists of a memory elements in addition combinational circuits its output at any instant of time depends upon the present input as well as present state of memory element. 2) What is meant by delay line? It is used to introduce time delays in digital signals. 3) What is meant by following terms a) Synchronous preset b) Asynchronous preset c) Synchronous clear d) Asynchronous clear a) Preset operation is synchronized with the clock b) Preset operation is independent of the clock c) Clear is performed in synchronous with clock d) Clear is performed independent with clock 4) Is asynchronous counter faster than synchronous counter ? In a synchronous counter the time required for change of any state is same and is equal to delay time of one flip flop where as in asynchronous counter all flip flops are not clocked simultaneously, hence time required is not same. 5) What is mean by lockout in counter? In a counter design for a fewer state than the maximum possible state some time it may so happen that counter enters in unused state and goes from one unused state to another unused state and never comes to used state. 6) What is mean by state table and state diagram? It consists of complete information about present state and next state and outputs of a sequential system. The information available in a state table can be represented as graphically. the graphical representation is known as state diagram. 7) What is the advantage of state reduction in the design of sequential circuit? It reduces the number of flip flops 8) What is meant by excitation table? This gives information about what should be the flip flop inputs if outputs are specified before and after the clock pulse. 9) How many flip flop is a need to design sequence generator using Counters: max (0S,1S) in a given sequence <= 2N - 1 Where, N = Number of flip flops 10) How many flip flop is a need to design sequence generator using shift registers: S <= 2N-1 Where, N=Number of flip flops and S= Length of sequence 11) What is Lock out condition? How it is avoided?

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When counter enters into one of the invalid state and after application of pulses remains in invalid states only i. e. counter gets locked into invalid state & this is called as lock out. Lock out can be avoided by providing bushing to all the invalid states in such a way that after application of one or more clock pulses counter will fall into one of the valid state.

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ASSIGNMENT NO: 11 SEQUENCE DETECTOR AIM: To design & implement sequence detector to detect the given binary sequence. ICs Used: Digital Trainer Kit, IC 7476(Dual JK), 7408 (AND-gate), 7432 (OR-gate), IC 7404 THEORY: For designing a clocked sequential circuit, 2 models are most commonly used. Mealy Model and Moore Model.
External Inputs

## Next state logic

Excitation

Memory elements

Output logic

External Outputs

Fig. 1 Block diagram of clocked sequential circuit Mealy Model So for Mealy Model Next state = F1 (present state, External inputs) and Outputs = F2 (present state, External inputs). For Moore Model block diagram, signal path from the external inputs to the o/p. logic is not present. So for Moore Model, Next state = F1 (present state, External inputs) and Outputs = F2 (present state). For clocked sequential circuits, i.e. state Machines, sequence of inputs, present state, next State, outputs can be represented by a state table or a state diagram. Sequence detector is an example of a clocked sequential circuit which is used to detect desired binary sequence. Sequence detector is a state Machine with total no. of States = No. of bits in the binary sequence which is to be detected, one external input & one external output. General steps to design sequence Detector. Find no. of states, in turn number of flip flops required. To do this general rule is : Total no. of states (n) are total no. of bits in the binary sequence to be detected. Minimum number of flip flops required (m) is given by relation 2m <= n. To draw the state diagram, start from the first state, if the bit applied on the external input is the desired bit on the sequence to be detected, we have to go to the next state otherwise we have to go to the previous state from where we can continue the desired sequence. When complete sequence is detected, make external output high or otherwise low. Once complete sequence is detected, go to the initial state. Draw state table from state diagram. Get reduced Boolean expression for every flip flop input and external output in terms of external input and present state. Implement Boolean expression using logic gates and draw complete circuit diagram with flip flops and logic gates. Design sequence detector to detect sequence 1010 using JK flip flop IC 7476. No. of states = 4 (no. of bits in the sequence to be detected). Min. value of m to satisfy this relation is 2. State Assignment - Binary assignment and states will be assigned as M0 (00), M1 (01), M2 (10) & M3 (11). Start with initial state. If the bit applied on the external input is the desired bit in the

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length to be detected, we have to go the next state when complete sequence is detected output must go high and detector must go to the initial state otherwise the external output is low.
0/0 1/0 1/0

M0 00

1/00 0/0

M1 01

0/0

M2 10

1/0

M3 11

0/1

Fig. State Diagram State Table Sr. No. 1 2 3 4 5 6 7 8 Present State QB 0 0 1 1 0 0 1 1 QA 0 0 0 0 1 1 1 1 Ext. Input X 0 1 0 1 0 1 0 1 Next State QB 0 0 1 0 0 1 0 0 QA 0 1 0 1 0 1 0 1 Ext. Output Y 0 0 0 0 0 0 1 0 Flip Flop inputs JB 0 1 X X 0 1 X X KB X X 1 0 X X 1 0 JA 0 0 1 0 X X X X KB X X X X 1 0 1 1

Minimized Boolean expression for each flip flop input & external output with K-Map JA=X KA =QA + X JB = QAX KB = X + Q A Y = XQBQA Logic Diagram

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Fig. Logic Diagram of Sequence Detector Hardware Requirements Table: GATE / Flip Flop MS JK FF NOT AND OR IC 747 6 740 4 740 8 743 2 Quantity 1 1 1 1

CONCLUSION: Thus GPSS ( Greatest common Prefix Suffix Subsequence ) can be used to design sequence detector to get optimized state diagram with minimum hardware. Designed sequence detector is successfully implemented and tested for different input binary sequences.

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FAQs : 1) What is the state diagram? In this state is represented by a circle with the state indicated inside the circle. Directed lines connecting the states indicate the transition between the states when the input is applied and the circuit is clocked. Input and output conditions for a particular transition to take place are labelled with the directed lines, 1st binary number indicates input and 2nd binary number indicates output. In case, if input condition doesnt cause change of state, the fact is indicated by the directed line terminating on the same circle from which it is originated. 2) What do you mean by sequence detector? Sequence detector is an example of a clocked sequential circuit which is used to detect desired binary sequence. Sequence detector is a state Machine with total no. of States = No. of bits in the binary sequence which is to be detected, one external input & one external output. 3) Sequence detector is a combinational or sequential logic circuit? Sequence detector is an example of a clocked sequential circuit 4) How many flip-flops we need to design n bit sequence detector? Find no. of states, in turn number of flip flops required. To do this general rule is : Total no. of states (n) = Total no. of bits in the binary sequence to be detected. Minimum number of flip flops required ( m ) is given by relation 2m <= n. 5) What is state table? State table is a table which provides information about sequence of external inputs, present state, next State, external outputs of a state machine and its general format is Present Sr. No. External Inputs Next State External Outputs State

6) What do you mean by Moore model and Mealy model? for Mealy Model Next state = F1 (present state, External inputs), Outputs = F2 (present state, External inputs). For Moore Model block diagram, signal path from the external inputs to the o/p. logic is not present. so for Moore Model, Next state = F1 (present state, External inputs), Outputs = F2 (present state) 7) What is the advantage of state reduction in the design of sequential circuits? State reduction gives optimized state diagram & minimum hardware. 8) Which one is preferred in FSM design? Mealy or Moore model? Why? The option to include input in output generation logic gives certain advantage to Mealy Usually it requires less number of states and thereby less hardware to solve any problem. Also the output is generated one clock cycle earlier. 9) What are the disadvantages of Mealy model ? model.

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The input transients, glitches are directly conveyed to the output. Also if we want output be synchronized while input can change any time . Hence Mealy model is not preferred.

transitions to

10) What are the advantages of Moore model over Mealy model? In this model the output remains stable over entire clock period and changes only when there occurs a state change at clock trigger based on input available at that time. 11) Is there any difference in hardware requirement between Moore and Mealy machine? Yes. Comparatively less hardware is requirement in Mealy machine than Moore machines. 12) What are the disadvantages of state transition diagrams? Though state transition diagrams are more compact in representation, for relatively more complex problem where number of inputs and states are higher the state diagram space becomes so crowded that it is difficult to read. In such situations ASM charts are preferred References : 1) Digital principles & applications by D. Leach & A. Malvino, 6th edition, TMH

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ASSIGNMENT NO 12 ALGORITHMETIC STATE MACHINE AIM: Design 2 bit up counter using ASM chart and implement it using multiplexer controller method. APPARATUS: Digital trainer board, Power supply, connecting wires, ICs- 74151(8:1 Multiplexer) 7474 (D Flip flop) THEORY ASM chart: ASM chart means algorithmic state machine chart. It is a type of flowchart that can be used to represent the state transitions and generated outputs for finite state machine(FSM) ASM charts are similar to traditional flowcharts. Unlike a traditional flowchart, this also includes timing information. This chart specifies that the FSM flows from one state to another only after each active clock edge. Elements used in ASM Chart are State Box, Decision Box and Conditional output Box State Box is a rectangle represents a state of the FSM. It is equivalent to node in the state diagram or row in the state table. The name of the state should be indicated outside the box in left top corner. Moore type of outputs are listed inside the box. Decision Box is a diamond indicates that the stated condition expression has to be tested and exit paths has to be chosen accordingly. The condition expression consists of one or many inputs. Conditional output Box are oval type and denotes the output signals that are of Mealy type. These output depend on the values of state variables and the Inputs of FSM. The condition that determines whether such outputs are generated is specified in a decision box. Significance : It is an aid to design the complex circuits. ASM charts are used to describe complex circuits that include one or more FSMs and another circuitry such as registers, counters, adders, multipliers etc. ASM Block : It is a structure which consists of single state box and any decision and conditional output boxes that the state box may be connected to. It has one entrance and any number of exit paths. Each block describes the state of the system during the interval of one clock pulse. DESIGN A) 2 bit Up counter using multiplexer controller method 2 bit counter has 4 states i.e. 00,01,10,11. In the state diagram if mode control M =0, counter will be latched in the same state. and will start incrementing to the next state if M=1. By referring the state diagram, ASM chart is drawn.

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Fig. 1 State Diagram for 2 bit Up Counter Up counting takes place for M=1 and the counter progresses from states S0,S1,S2,S3. ASM chart of the above state diagram is as shown below in Fig.2

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## Fig.2 ASM Chart for 2-bit Up Counter

State transition table: Mode control i/p M 0 0 0 0 1 (Qn) QB 0 0 1 1 0 80 / 84 Present state QA 0 1 0 1 0 Next state (Qn+1) Qb+1 0 0 1 1 0 Q a+1 0 1 0 1 1

1 1 1

0 1 1

1 0 1

1 1 0

0 1 0

Excitation table for D Flip-flop returns state table. Mode control i/p Present state (Qn) M QB QA 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Next state (Qn+1) QB+1 QA+1 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 Input DB DA 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0

Multiplexer controller method of design has three levels of components as shown in the figure below:

The multiplexer outputs are applied to the input of the flip-flop forming the register at the second level to hold the present state inputs. The multiplexers decide the next state of the register as outputs of MUX has been connected to flip-flop inputs. Third level is the decoder which provides separate output for each control state. The decoder can be replaced by the combinational circuit.

Hardware Requirement: Name of the IC Description Quantity 74151 8:1 multiplexer 2 7474 D F/F 1

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Logic Diagram:

CONCLUSION

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ASM chart is drawn as per the state diagram and verified the functionality of given FSM using multiplexer controller method.

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FAQs: 1) What is meaning of ASM and FSM ASM is algorithmic state machine chart. It is a method to implement FSM. It is a type of flowchart that can be used to represent the state transitions and generated outputs for finite state machine(FSM). 2) What is the major difference between ASM chart and traditional flowchart A finite state machine (FSM) or finite state automaton (plural: automata) or simply a state machine, is a model of behavior composed of a finite number of states, transitions between those states, and actions. A finite state machine is an abstract model of a machine with a primitive internal memory. ASM charts are similar to traditional flowcharts. Unlike a traditional flowchart, this includes timing information. This chart specifies that the FSM flows from one state to another only after each active clock edge. 3) Write the significance of ASM chart in the design of FSM. It is an aid to design the complex circuits. ASM charts are used to describe complex circuits that include one or more FSMs and another circuitry such as registers, counters, adders, multipliers etc. Reference: 1) Fundamentals of Digital Logic with VHDL Design- Stephen Brown, Zvonko Vranesic.(TMH Publication)

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