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2011 MCQ 4.1

ONE MARK

In the circuit shown below, capacitors C1 and C2 are very large and are shorts at the input frequency. vi is a small signal input. The gain magnitude vo at 10 M rad/s is vi

**(A) maximum (B) minimum (C) unity (D) zero
**

MCQ 4.2

The circuit below implements a filter between the input current ii and the output voltage vo . Assume that the op-amp is ideal. The filter implemented is a

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Chap 4 Analog Circuits

(A) low pass filter (C) band stop filter

(B) band pass filter (D) high pass filter

2011

TWO MARKS

MCQ 4.3

In the circuit shown below, for the MOS transistors, μn Cox = 100 μA/V 2 and the threshold voltage VT = 1 V . The voltage Vx at the source of the upper transistor is

(A) 1 V (C) 3 V

MCQ 4.4

(B) 2 V (D) 3.67 V

For a BJT, the common base current gain α = 0.98 and the collector base junction reverse bias saturation current ICO = 0.6 μA . This BJT is connected in the common emitter mode and operated in the active region with a base drive current IB = 20 μA . The collector current IC for this mode of operation is (A) 0.98 mA (C) 1.0 mA

Page 174

(B) 0.99 mA (D) 1.01 mA

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Chap 4 Analog Circuits

MCQ 4.5

For the BJT, in the circuit shown below, Q1 β = 3, VBEon = 0.7 V, VCEsat = 0.7 V . The switch is initially closed. At time t = 0 , the switch is opened. The time t at which Q1 leaves the active region is

(A) 10 ms (C) 50 ms

(B) 25 ms (D) 100 ms

**Statement for Linked Answer Questions: 4.6 & 4.7
**

In the circuit shown below, assume that the voltage drop across a forward biased diode is 0.7 V. The thermal voltage Vt = kT/q = 25 mV . The small signal input vi = Vp cos ^ωt h where Vp = 100 mV.

MCQ 4.6

**The bias current IDC through the diodes is (A) 1 mA (B) 1.28 mA (C) 1.5 mA (D) 2 mA
**

Page 175

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gatehelp.nodia.co. If CE is disconnected from the circuit.com Chap 4 Analog Circuits MCQ 4.www.in . The capacitors CC and CE can be assumed to be short at signal frequency and effect of output resistance r0 can be ignored.25 cos ^ωt h mV (C) 2 cos (ωt) mV 2010 (B) 1 cos (ωt) mV (D) 22 cos (ωt) mV ONE MARK MCQ 4. which one of the following statements is true (A) The input resistance Ri increases and magnitude of voltage gain AV decreases (B) The input resistance Ri decreases and magnitude of voltage gain AV increases (C) Both input resistance Ri and magnitude of voltage gain AV decreases (D) Both input resistance Ri and the magnitude of voltage gain AV increases MCQ 4.7 The ac output voltage vac is (A) 0.9 In the silicon BJT circuit shown below. assume that the emitter area of transistor Q1 is half that of transistor Q2 Page 176 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.8 The amplifier circuit shown below uses a silicon transistor.

3 mA MCQ 4.com Chap 4 Analog Circuits The value of current Io is approximately (A) 0.nodia.7 μF Page 177 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.5 mA (C) 9. C1 = 3 and C2 = 4. gm = 0.co. RC = 250 kΩ.gatehelp.11 & 4. RB = 93 kΩ.www. RL = 1 kΩ. r0 = 259 Ω. RS = 1 kΩ.in .3861 A/V. the voltage gain of the amplifier shown below is (A) − R2 R1 (C) − R2 || R 3 R1 (B) − R 3 R1 (D) −b R2 + R 3 l R1 TWO MARKS 2010 Common Data Questions: 4.12 : Consider the common emitter amplifier shown below with the following circuit parameters: β = 100.10 (B) 2 mA (D) 15 mA Assuming the OP-AMP to be ideal.

13 The transfer characteristic for the precision rectifier circuit shown below is (assume ideal OP-AMP and practical diodes) Page 178 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.com Chap 4 Analog Circuits MCQ 4.www.co.gatehelp.12 The lower cut-off frequency due to C2 is (A) 33.nodia.9 Hz MCQ 4.in .1 Hz (D) 16.11 The resistance seen by the source vS is (A) 258 Ω (C) 93 k Ω (B) 1258 Ω (D) 3 MCQ 4.6 Hz (B) 27.9 Hz (C) 13.

nodia. 1) (D) max (− Vi. 1) MCQ 4.15 In the following a stable multivibrator circuit.14 In the circuit below.co.in . 1) (C) min (− Vi. 1) (B) max (Vi.com Chap 4 Analog Circuits 2009 TWO MARKS MCQ 4. the diode is ideal.www. The voltage V is given by (A) min (Vi.gatehelp. which properties of v0 (t) depend on R2 ? Page 179 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.

com Chap 4 Analog Circuits (A) Only the frequency (B) Only the amplitude (C) Both the amplitude and the frequency (D) Neither the amplitude nor the frequency Statement for Linked Answer Question 4. Assume. where the gate voltage v0 of the n-MOSFET is increased from zero. V .MOSFET is in saturation and p −MOSFET is in triode region Page 180 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. while the gate voltage of the p − MOSFET is kept constant at 3 V.16 For small increase in VG beyond 1V.2 MCQ 4. for both transistors.gatehelp. which of the following gives the correct description of the region of operation of each MOSFET (A) Both the MOSFETs are in saturation region (B) Both the MOSFETs are in triode region (C) n-MOSFETs is in triode and p −MOSFET is in saturation region (D) n.co.17 Consider for CMOS circuit shown.www. that.16 and 4.in . the magnitude of the threshold voltage is 1 V and the product of the trans-conductance parameter is 1mA.nodia.

16] (A) 4 − 1 2 (C) 4 − 3 2 (B) 4 + 1 2 (D) 4 + 3 2 MCQ 4.nodia.17 Estimate the output voltage V0 for VG = 1.in . [Hints : Use the appropriate current-voltage equation for each MOSFET.co.gatehelp. The transistor has β = 150 and hie = 3Ω . based on the answer to Q.www.19 A small signal source Vi (t) = A cos 20t + B sin 106 t is applied to a transistor amplifier as shown below. V = 5 V (D) Negative feedback. V = 2 V MCQ 4.6 V and β = 150 . (A) Positive feedback. Which expression best approximate V0 (t) Page 181 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.4. V = 10 V. V = 0 V (C) Negative feedback.com Chap 4 Analog Circuits MCQ 4. Decide whether the feedback in the circuit is positive or negative and determine the voltage V at the output of the op-amp.5 V. (B) Positive feedback.18 In the circuit shown below. the transistor has VBE = 0. the op-amp is ideal.

When it is forward biased.20 In the following limiter circuit.8 V The maximum and minimum values of the output voltage respectively are (A) 6. The zener breakdown voltage is 6.7 V when it is forward biased. − 0.1 V.in .7 V Page 182 (B) 0. − 7.co.7 V (C) 7. − 0.5 V GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.gatehelp.7 V.5 V.5 V (D) 7. − 7.com Chap 4 Analog Circuits (A) V0 (t) =− 1500 (A cos 20t + B sin 106 t) (B) V0 (t) = − 1500( A cos 20t + B sin 106 t) (C) V0 (t) =− 1500B sin 106 t (D) V0 (t) =− 150B sin 106 t 2008 ONE MARK MCQ 4.nodia. Assume that the diode drop is 0.5 V. an input voltage Vi = 10 sin 100πt is applied.www.

23 (B) 0.www.nodia. The current Ix is related to Ibias as (A) Ix = Ibias + Is (C) Ix = Ibias − cVDD − Vout m RE MCQ 4.7 V MCQ 4.co.gatehelp. The I-V (A) 0 V (C) 0. the output voltage V0 is V t Consider the following circuit using an ideal OPAMP. Assume the M2 is in saturation and the output is unloaded. For an input voltage Vi =− 1 V .in .1 V The OPAMP circuit shown above represents a Page 183 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.com Chap 4 Analog Circuits 2008 MCQ 4.22 (B) Ix = Ibias (D) Ix = Ibias − Is characteristic of the diode is described by the relation I = I 0 _eV − 1i where VT = 25 mV. I0 = 1μ A and V is the voltage across the diode (taken as positive for forward bias).21 TWO MARSK For the circuit shown in the following figure.1 V (D) 1. transistor M1 and M2 are identical NMOS transistors.

The equivalent gm of the pair is defied to be 2Iout at constant Vout 2Vi The equivalent gm of the pair is (A) the sum of individual gm ' s of the transistors (B) the product of individual gm ’s of the transistors (C) nearly equal to the gm of M1 (D) nearly equal to MCQ 4.25 gm of M2 g0 Consider the Schmidt trigger circuit shown below A triangular wave which goes from -12 to 12 V is applied to the inverting input of OPMAP.gatehelp. Assume that the output of the OPAMP swings from +15 V to -15 V. Vbias is chosen so that both transistors are in saturation.com Chap 4 Analog Circuits (A) high pass filter (C) band pass filter MCQ 4.24 (B) low pass filter (D) band reject filter Two identical NMOS transistors M1 and M2 are connected as shown below.www.in .nodia.co. The voltage at the non-inverting input switches between Page 184 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.

gatehelp.in . r3 = 25 mV/IE .com Chap 4 Analog Circuits (A) − 12V to +12 V (C) -5 V to +5 V (B) -7.5 V (D) 0 V and 5 V Statement for Linked Answer Question 3. VBE = 0.co.www.nodia.27: In the following transistor circuit.26 The value of DC current IE is (A) 1 mA (C) 5 mA (B) 2 mA (D) 10 mA MCQ 4.27 The mid-band voltage gain of the amplifier is approximately (A) -180 (C) -90 (B) -120 (D) -60 Page 185 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. and β and all the capacitances are very large MCQ 4.5 V to 7.26 and 3.7 V.

com Chap 4 Analog Circuits 2007 MCQ 4.nodia.5 V Page 186 (B) -1 V (D) 0.29 In a transconductance amplifier.28 ONE MARK The correct full wave rectifier circuit is MCQ 4.30 TWO MARKS For the Op-Amp circuit shown in the figure.in .gatehelp. V0 is (A) -2 V (C) -0.co.www. it is desirable to have (A) a large input resistance and a large output resistance (B) a large input resistance and a small output resistance (C) a small input resistance and a large output resistance (D) a small input resistance and a small output resistance 2007 MCQ 4.5 V GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.

7 V.com Chap 4 Analog Circuits MCQ 4. and for Vi = 4V.www. For Vi = 2V. The relationship between V01 and V02 is (A) V02 = 2 Vo1 (B) Vo2 = e2 Vo1 (D) Vo1 − Vo2 = VT 1n2 (C) Vo2 = Vo1 1n2 MCQ 4.33 In the CMOS inverter circuit shown. V0 = V02 .nodia.32 In the Op-Amp circuit shown. V0 = V01. assume that the β of the transistor is very large and VBE = 0.in .gatehelp.co. if the trans conductance parameters of the NMOS and PMOS transistors are W kn = kp = μn Cox Wn = μCox p = 40μA/V2 Ln Lp and their threshold voltages ae VTHn = VTHp = 1 V the current I is Page 187 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. assume that the diode current follows the equation I = Is exp (V/VT ).31 For the BJT circuit shown. The mode of operation of the BJT is (A) cut-off (C) normal active (B) saturation (D) reverse active MCQ 4.

gatehelp.co. If the input voltage (Vi) range is from 10 to 16 V.com Chap 4 Analog Circuits (A) 0 A (C) 45 μ A MCQ 4.35 The transfer function V0 (s)/ Vi (s) is (A) 1 − sRC (B) 1 + sRC 1 + sRC 1 − sRC Page 188 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.43 V Statement for Linked Answer Questions 4.14 to 7.29 V (D) 7.29 V (C) 7.29 to 7. the output voltage (V0) ranges from (A) 7.nodia. the Zener voltage at knee is 7 V.34 (B) 25 μ A (D) 90 μ A For the Zener diode shown in the figure.36: Consider the Op-Amp circuit shown in the figure.14 to 7. the knee current is negligible and the Zener dynamic resistance is 10 Ω .43 V (B) 7.www.in .35 & 4. MCQ 4.00 to 7.

38 (B) Zi = 0. then the minimum and maximum values of φ (in radians) are respectively (A) − π and π (B) 0 and π 2 2 2 (C) − π and 0 (D) − π and 0 2 2006 MCQ 4.www.37 ONE MARK The input impedance (Zi) and the output impedance (Z0) of an ideal trans-conductance (voltage controlled current source) amplifier are (A) Zi = 0.gatehelp. At t = 0 the switch S is closed. Z0 = 3 (D) Zi = 3. Z0 = 0 MCQ 4. the capacitor C is initially uncharged.36 If Vi = V1 sin (ωt) and V0 = V2 sin (ωt + φ).nodia.39 (B) VGS =− 3 Volts (D) VGS = 3 Volts TWO MARKS For the circuit shown in the following figure.in .co. Z0 = 0 (C) Zi = 3.com Chap 4 Analog Circuits (C) 1 1 − sRC (D) 1 1 + sRC MCQ 4. Z0 = 3 An n-channel depletion MOSFET has following two points on its ID − VGs curve: (i) VGS = 0 at ID = 12 mA and (ii) VGS =− 6 Volts at ID = 0 mA Which of the following Q point will given the highest trans conductance gain for small signals? (A) VGS =− 6 Volts (C) VGS = 0 Volts 2006 MCQ 4. The Vc across the capacitor at t = 1 millisecond is Page 189 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.

assume that the zener diode is ideal with a breakdown voltage of 6 volts.gatehelp.42 and 4. the OP-AMP is supplied with ! 15V .www. (A) 0 Volt (C) 9. 4.com Chap 4 Analog Circuits In the figure shown above.43 : In the transistor amplifier circuit shown in the figure below. The waveform observed across R is Common Data for Questions 4.co.nodia. the Page 190 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.41.in .45 Volts MCQ 4.40 (B) 6.3 Volt (D) 10 Volts For the circuit shown below.

42 (B) 5.8 Volts (C) 6.41 Under the DC conditions.45: A regulated power supply. the collector-or-emitter voltage drop is (A) 4.3 (C) 5.7V. the collector-to-emitter voltage drop (A) increases by less than or equal to 10% (B) decreases by less than or equal to 10% (C) increase by more than 10% (D) decreases by more than 10% MCQ 4. has an unregulated input (UR) of 15 Volts and generates a regulated output Vout . the ground has been shown by the symbol 4 MCQ 4. In the figure above. Page 191 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.nodia.43 The small-signal gain of the amplifier vc is vs (A) -10 (B) -5.gatehelp. VBE = 0.co.6 Volts If βDC is increased by 10%.com Chap 4 Analog Circuits transistor has the following parameters: βDC = 60 . shown in figure below.3 Volts (D) 6.in .44 & 4. hie " 3 The capacitance CC can be assumed to be infinite.0 Volts MCQ 4. Use the component values shown in the figure.www.3 (D) 10 Common Data for Questions 4.

co.45 (B) 5.com Chap 4 Analog Circuits MCQ 4.in .44 The power dissipation across the transistor Q1 shown in the figure is (A) 4.0 Watts (D) 6.8 Watts (C) 5.0 Watts If the unregulated voltage increases by 20%.www.4 Watts MCQ 4.gatehelp.nodia.46 The input resistance Ri of the amplfier shown in the figure is (A) 30 kΩ 4 (C) 40 kΩ Page 192 (B) 10 kΩ (D) infinite GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. the power dissipation across the transistor Q1 (A) increases by 20% (C) remains unchanged (B) increases by 50% (D) decreases by 20% 2005 ONE MARK MCQ 4.

50 For an npn transistor connected as shown in figure VBE = 0.47 The effect of current shunt feedback in an amplifier is to (A) increase the input resistance and decrease the output resistance (B) increases both input and output resistance (C) decrease both input and output resistance (D) decrease the input resistance and increase the output resistance MCQ 4.gatehelp.48 The cascade amplifier is a multistage configuration of (A) CC − CB (C) CB − CC (B) CE − CB (D) CE − CC 2005 TWO MARKS MCQ 4.www. Given that reverse saturation current of the junction at room temperature 300 K is 10 . (D) decreases the common mode gain only. the emitter current is (A) 30 mA (C) 49 mA (B) 39 mA (D) 20 mA Page 193 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.mode gains. a large value of (RE ).in .13 A. (C) decreases the differential mode gain only.com Chap 4 Analog Circuits MCQ 4.7 volts. (A) increase both the differential and common .co.nodia. MCQ 4. (B) increases the common mode gain only.49 In an ideal differential amplifier shown in the figure.

1000 rad/sec.co. Which of the following can be calculated ? (A) Bias current of the inverting input only (B) Bias current of the inverting and non-inverting inputs only (C) Input offset current only (D) Both the bias currents and the input offset current MCQ 4.com Chap 4 Analog Circuits MCQ 4. (C) high pass.52 The Op-amp circuit shown in the figure is filter.51 The voltage e0 is indicated in the figure has been measured by an ideal voltmeter.www.7V is shown in the figure. 10000 rad/sec The circuit using a BJT with β = 50 and VBE = 0. 1000 rad/sec MCQ 4. The type of filter and its cut.gatehelp.nodia. The base current IB and collector voltage by VC and respectively Page 194 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. Off frequency are respectively (A) high pass.53 (B) Low pass. 1000 rad/sec (D) low pass.in .

55 (B) 14. 36 μA/V2 and 9 μ A/V 2 . The output voltage Vo i s (A) 1 V (C) 3 V (B) 2 V (D) 4 V Page 195 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.7 mA MCQ 4. The maximum load current drawn from this current ensuring proper functioning over the input voltage range between 20 and 30 volts.8 volts and a zener knee current of 0.in .nodia.www.2 mA Both transistors T1 and T2 show in the figure. have a β = 100 . threshold voltage of 1 Volts.54 (B) 40 μ A and 16 Volts (D) 50 μ A and 10 Volts The Zener diode in the regulator circuit shown in the figure has a Zener voltage of 5. The device parameters K1 and K2 of T1 and T2 are.co.5 mA. respectively. is (A) 23.2 mA (D) 24.com Chap 4 Analog Circuits (A) 43 μ A and 11.4 Volts (C) 45 μ A and 11 Volts MCQ 4.gatehelp.7 mA (C) 13.

625 mA and 8.56 Zi and Z0 of the circuit are respectively (A) 2 M Ω and 2 k Ω (C) infinity and 2 M Ω MCQ 4.co.58.41 (D) 3.875 mA and 5.00 V (D) 6.50 V Transconductance in milli-Siemens (mS) and voltage gain of the amplifier are respectively (A) 1.59 (B) 1.500 mA and 11. 4.in . Vp =− 8 V MCQ 4.00 V MCQ 4.nodia.60 : Given.250 mA and 7.www.59 and 4.57 (B) 2 M Ω and 20 k Ω 11 (D) infinity and 20 k Ω 11 ID and VDS under DC conditions are respectively (A) 5.875 ms and -3.com Chap 4 Analog Circuits Common Data Questions 4.875 mS and 3. Page 196 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.gatehelp. rd = 20kΩ .3 mS and -6 MCQ 4.75 V (C) 4.58 (B) 1. IDSS = 10 mA.41 (C) 3.3 mS and 6 Given the ideal operational amplifier circuit shown in the figure indicate the correct transfer characteristics assuming ideal diodes with zero cut-in voltage.

61 Voltage series feedback (also called series-shunt feedback) results in (A) increase in both input and output impedances Page 197 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.in .60 An ideal op-amp is an ideal (A) voltage controlled current source (B) voltage controlled voltage source (C) current controlled current source (D) current controlled voltage source MCQ 4.nodia.www.gatehelp.com Chap 4 Analog Circuits 2004 ONE MARK MCQ 4.co.

com Chap 4 Analog Circuits (B) decrease in both input and output impedances (C) increase in input impedance and decrease in output impedance (D) decrease in input impedance and increase in output impedance MCQ 4.5 k Ω (D) gm = 40 mA/V and rπ = 2.5 k Ω MCQ 4.co.62 The circuit in the figure is a (A) low-pass filter (C) band-pass filter (B) high-pass filter (D) band-reject filter 2004 TWO MARKS MCQ 4. Assuming that the β of the transistor is 100 and the thermal voltage (VT ) is 25 mV.63 A bipolar transistor is operating in the active region with a collector current of 1 mA. the transconductance (gm) and the input resistance (rπ) of the transistor in the common emitter configuration.0 k Ω (C) gm = 25 mA/V and rπ = 2. are (A) gm = 25 mA/V and rπ = 15.in .nodia.625 kΩ (B) gm = 40 mA/V and rπ = 4.64 The value of C required for sinusoidal oscillations of frequency 1 kHz in the circuit of the figure is Page 198 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.www.gatehelp.

66 In the voltage regulator shown in the figure.www.gatehelp.e. Assuming that the Zener diode is ideal (i. the value of R is Page 199 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www..co. the Zener knee current is negligibly small and Zener resistance is zero in the breakdown region).65 In the op-amp circuit given in the figure.com Chap 4 Analog Circuits (A) 1 μF 2π (C) 1 μF 2π 6 (B) 2π μF (D) 2π 6 μF MCQ 4. the load current iL is (A) − Vs R2 (C) − Vs RL (B) Vs R2 (D) Vs R1 MCQ 4.nodia. the load current can vary from 100 mA to 500 mA.in .

VCE = 3. PIV = 2Vm π (D) Vdc Vm .67 (B) 70 Ω (D) 14 Ω In a full-wave rectifier using two ideal diodes.in .9 V GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.nodia. VCE = 4.7V. If PIV is the peak inverse voltage of the diode.com Chap 4 Analog Circuits (A) 7 Ω (C) 70 Ω 3 MCQ 4. then the appropriate relationships for this rectifier are (A) Vdc = Vm .5 V Page 200 (B) IC = 0.68 Assume that the β of transistor is extremely large and VBE = 0. VCE = 2. VCE = 3. PIV = Vm π (B) Idc = 2 Vm .75 V (D) IC = 0.7 V (C) IC = 1 mA.co.5 mA. Vdc and Vm are the dc and peak values of the voltage respectively across a resistive load.www. PIV = Vm π MCQ 4. PIV = 2Vm π (C) Vdc = 2 Vm .gatehelp.5 mA. IC and VCE in the circuit shown in the figure (A) IC = 1 mA.

then the output of the comparators has a duty cycle of (A) 1/2 (C) 1/6 (B) 1/3 (D) 1/2 Page 201 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.com Chap 4 Analog Circuits 2003 ONE MARK MCQ 4.www. CC − HI.co.in .70 The circuit shown in the figure is best described as a (A) bridge rectifier (C) frequency discriminator MCQ 4.gatehelp. CC − HI.71 (B) ring modulator (D) voltage double If the input to the ideal comparators shown in the figure is a sinusoidal signal of 8 V (peak to peak) without any DC component. CE − HI (B) CB − LO.69 Choose the correct match for input resistance of various amplifier configurations shown below : Configuration CB : Common Base CC : Common Collector CE : Common Emitter Input resistance LO : Low MO : Moderate HI : High (A) CB − LO. CC − LO. CC − MO.nodia. CE − MO (C) CB − MO. CE − MO MCQ 4. CE − LO (D) CB − HI.

2.5 k Ω .in . For a transistor with β of 200.www. input resistance of 1 k Ω and output resistance of 2. The input resistance of the current-shunt negative feedback amplifier using the above amplifier with a feedback factor of 0. the gain of a transistor amplifier falls at high frequencies due to the (A) internal capacitances of the device (B) coupling capacitor at the input (C) skin effect (D) coupling capacitor at the output 2003 TWO MARKS MCQ 4. then common mode rejection ratio is (A) 23 dB (C) 46 dB (B) 25 dB (D) 50 dB MCQ 4.5 mA when its β is 150. the values of R1 and R2 are such that the transistor is operating at VCE = 3 V and IC = 1. IC ) is Page 202 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.74 An amplifier without feedback has a voltage gain of 50.72 If the differential voltage gain and the common mode voltage gain of a differential amplifier are 48 dB and 2 dB respectively.co.75 (B) 1 kΩ 5 (D) 11 kΩ In the amplifier circuit shown in the figure.gatehelp. the operating point (VCE .nodia.73 Generally. is (A) 1 kΩ 11 (C) 5 kΩ MCQ 4.com Chap 4 Analog Circuits MCQ 4.

gatehelp. 2 mA) MCQ 4. 2 mA) (D) (4 V. 1 mA) The oscillator circuit shown in the figure has an ideal inverting amplifier.76 (B) (3 V.www.com Chap 4 Analog Circuits (A) (2 V.co. Its frequency of oscillation (in Hz) is (A) (C) 1 (2π 6 RC) 1 ( 6 RC) (B) (D) 1 (2πRC) 6 (2πRC) MCQ 4. 2 mA) (C) (4 V.in .77 The output voltage of the regulated power supply shown in the figure is Page 203 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.nodia.

co.www.gatehelp. the output voltage Vout will be equal to (A) 1 V (C) 14 V (B) 6 V (D) 17 V MCQ 4.nodia.in . input resistance of 1 k Ω and output resistance of 250 Ω are cascaded. The charging requires (A) Constant voltage source of 3 V for 1 ms (B) Constant voltage source of 3 V for 2 ms (C) Constant voltage source of 1 mA for 1 ms (D) Constant voltage source of 3 mA for 2 ms Page 204 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.80 An ideal sawtooth voltages waveform of frequency of 500 Hz and amplitude 3 V is generated by charging a capacitor of 2 μ F in every cycle. The opened circuit voltages gain of the combined amplifier is (A) 49 dB (C) 98 dB (B) 51 dB (D) 102 dB MCQ 4.78 If the op-amp in the figure is ideal.79 Three identical amplifiers with each one having a voltage gain of 50.com Chap 4 Analog Circuits (A) 3 V (C) 9 V (B) 6 V (D) 12 V MCQ 4.

com Chap 4 Analog Circuits 2002 ONE MARK MCQ 4. the overall frequency response is as given in Page 205 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.in .83 (B) 100 kHz (D) 1000 kHz 7. A noninverting amplifier suing this opamp and having a voltage gain of 20 dB will exhibit a -3 dB bandwidth of (A) 50 kHz (C) 1000 kHz 17 MCQ 4.82 A 741-type opamp has a gain-bandwidth product of 1 MHz. (A) Ri decreases and R0 decreases (B) Ri decreases and R0 increases (C) Ri increases and R0 decreases (D) Ri increases and R0 increases (Ri and R0 denote the input and output resistance respectively) MCQ 4. voltagesampling.www.co.81 In a negative feedback amplifier using voltage-series (i.gatehelp.e.nodia. If each of the amplifiers has a frequency response as shown in the figure.07 Three identical RC-coupled transistor amplifiers are cascaded. series mixing) feedback.

85 An amplifier using an opamp with a slew-rate SR = 1 V/μ sec has Page 206 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.84 The circuit in the figure employs positive feedback and is intended to generate sinusoidal oscillation. then to sustain oscillation at this frequency V0 (f) 6 (A) R2 = 5R1 (C) R2 = R1 6 (B) R2 = 6R1 (D) R2 = R1 5 MCQ 4.nodia. B (f) = 3 f = +0c.com Chap 4 Analog Circuits 2002 TWO MARKS MCQ 4.co.gatehelp.in . If at a frequency V (f) 1 f0.www.

nodia. The zener diode has Vz = 10 V and Izk (knee current) =1 mA.co.in .www. For satisfactory operation (A) R # 1800Ω (C) 3700Ω # R # 4000Ω MCQ 4.86 (B) 395 mV (D) 39.5 mV A zener diode regulator in the figure is to be designed to meet the specifications: IL = 10 mA V0 = 10 V and Vin varies from 30 V to 50 V.com Chap 4 Analog Circuits a gain of 40 dB. (A) 795 mV (C) 79.5 mV MCQ 4. If this amplifier has to faithfully amplify sinusoidal signals from dc to 20 kHz without introducing any slew-rate induced distortion. then the input signal level must not exceed.87 (B) 2000Ω # R # 2200Ω (D) R $ 4000Ω The voltage gain Av = v0 of the JFET amplifier shown in the figure vt is IDSS = 10 mA Vp =− 5 V(Assume C1. C2 and Cs to be very large (A) +16 (C) +8 (B) -16 (D) -6 Page 207 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.gatehelp.

47 # 1010 Hz and fβ = 1. C π = 4 # 10−13 F. R0 = 3 MCQ 4.nodia. A = 3.gatehelp.co.www.89 Thee ideal OP-AMP has the following characteristics. (A) Only statement 1 is correct (B) Only statement 2 is correct (C) Both the statements 1 and 2 are correct (D) Both the statements 1 and 2 are incorrect 2001 MCQ 4.90 (B) Ri = 0.47 # 1010 Hz (D) fT = 1. (A) Ri = 3. R0 = 3 Consider the following two statements : Statement 1 : A stable multi vibrator can be used for generating square wave. and DC current gain β0 = 90 . A = 3. C μ = 10−14 F.64 # 108 Hz (C) fT = 1.47 # 1010 Hz and fβ = 1. R0 = 0 (D) Ri = 0. A = 3. For this transistor fT and fβ are (A) fT = 1.33 # 1012 Hz and fβ = 1.com Chap 4 Analog Circuits 2001 MCQ 4. R0 = 0 (C) Ri = 3.91 TWO MARKS An npn BJT has gm = 38 mA/V. A = 3.88 ONE MARK The current gain of a BJT is (A) gm r0 (C) gm rπ (B) (D) gm r gm rπ MCQ 4.47 # 1010 Hz (B) fT = 1.64 # 108 Hz and fβ = 1. Statement 2: Bistable multi vibrator can be used for storing binary information.33 # 1012 Hz Page 208 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.in .

PT = 9.com Chap 4 Analog Circuits MCQ 4. when the input varies from 20 V to 30 V. Neglect the current through RB .9 W (D) Pz = 115 mW.3 V. VBE = 0.in .3 MHz (C) Hartley oscillator with foscillation = 159.92 The transistor shunt regulator shown in the figure has a regulated output voltage of 10 V. PT = 11.5 .6 MHz (B) Colpitts oscillator with foscillation = 50.gatehelp. β = 99 .2 MHz (D) Colpitts oscillator with foscillation = 159.co.9 W (C) Pz = 95 mW.3 MHz Page 209 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.nodia.www. The relevant parameters for the zener diode and the transistor are : Vz = 9. Then the maximum power dissipated in the zener diode (Pz ) and the transistor (PT ) are (A) Pz = 75 mW.9 W MCQ 4.9 W (B) Pz = 85 mW.93 The oscillator circuit shown in the figure is 4 (A) Hartely oscillator with foscillation = 79. PT = 7. PT = 8.

nodia.4 cos (100τ) dτ # 0 t (B) 10 cos (100τ) dτ # 0 t (D) 10 .in .96 In the differential amplifier of the figure.95 (B) − 9 (D) − 11 In the figure assume the OP-AMPs to be ideal. if the source resistance of the current source IEE is infinite.www.com Chap 4 Analog Circuits MCQ 4. then the common-mode gain is Page 210 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.4 d cos (100t) dt ONE MARK 2000 MCQ 4.94 The inverting OP-AMP shown in the figure has an open-loop gain of 100.gatehelp.co. The closed-loop gain V0 is Vs (A) − 8 (C) − 10 MCQ 4. The output v0 of the circuit is (A) 10 cos (100t) (C) 10 .

www. V0 is (A) -1 V (C) +1 V MCQ 4.99 (D) none of the above The current gain of a bipolar transistor drops at high frequencies because of (A) transistor capacitances (B) high current effects in the base (C) parasitic inductive elements (D) the Early effect Page 211 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.com Chap 4 Analog Circuits (A) zero (C) indeterminate MCQ 4.co.nodia.98 (B) 2 V (D) +15 V Introducing a resistor in the emitter of a common amplifier stabilizes the dc operating point against variations in (A) only the temperature (B) only the β of the transistor (C) both temperature and β MCQ 4.97 (B) infinite (D) Vin1 + Vin2 2VT In the circuit of the figure.in .gatehelp.

102 Assume that the op-amp of the figure is ideal. then v0 is (A) zero (C) − (V1 + V2) sin ωt MCQ 4.www. is ideal.in .com Chap 4 Analog Circuits MCQ 4.nodia. If vi is a triangular wave.101 (B) (V1 − V2) sin ωt (D) (V1 + V2) sin ωt The configuration of the figure is a (A) precision integrator (B) Hartely oscillator (C) Butterworth high pass filter (D) Wien-bridge oscillator MCQ 4. then v0 will be (A) square wave (C) parabolic wave Page 212 (B) triangular wave (D) sine wave GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.100 If the op-anp in the figure.gatehelp.co.

then v0 will be (A) 0 V (C) + 15 V or -15 V (B) 5 mV (D) +50 V or -50 V Page 213 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.105 (D) 10 mA If the op-amp in the figure has an input offset voltage of 5 mV and an open-loop voltage gain of 10000.104 TWO MARKS In the circuit of figure. The value of Ic is (A) Indeterminate since Rc is not given (B) 1 mA (C) 5 mA MCQ 4.nodia.7 V.co.in .com Chap 4 Analog Circuits MCQ 4.103 The most commonly used amplifier is sample and hold circuits is (A) a unity gain inverting amplifier (B) a unity gain non-inverting amplifier (C) an inverting amplifier with a gain of 10 (D) an inverting amplifier with a gain of 100 2000 MCQ 4.gatehelp. assume that the transistor is in the active region.www. It has a large β and its base-emitter voltage is 0.

gatehelp.106 The first dominant pole encountered in the frequency response of a compensated op-amp is approximately at (A) 5 Hz (C) 1 MHz MCQ 4. then the overall transconductance g (= i 0 /vi) of the cascade amplifier is (A) gm1 (C) gm1 2 (B) gm2 (D) gm2 2 MCQ 4.com Chap 4 Analog Circuits 1999 ONE MARK MCQ 4.108 In the cascade amplifier shown in the given figure.109 Crossover distortion behavior is characteristic of (A) Class A output stage (C) Class AB output stage Page 214 (B) Class B output stage (D) Common-base output stage GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.nodia.107 (B) 10 kHz (D) 100 MHz Negative feedback in an amplifier (A) reduces gain (B) increases frequency and phase distortions (C) reduces bandwidth (D) increases noise MCQ 4. if the commonemitter stage (Q1) has a transconductance gm1 . and the common base stage (Q2) has a transconductance gm2 .co.in .www.

are (B) 25 Ω and 20% (A) 5 Ω and 20% (C) 5 Ω and 16. The new input and output impedances.com Chap 4 Analog Circuits 1999 MCQ 4.7% 1998 MCQ 4.111 (D) 100 kΩ and 1 kΩ A dc power supply has a no-load voltage of 30 V.www.7% ONE MARK The circuit of the figure is an example of feedback of the following type (A) current series (C) voltage series MCQ 4.nodia.in .110 TWO MARK An amplifier has an open-loop gain of 100. CMRR can be improved by using an increased (A) emitter resistance (B) collector resistance (C) power supply voltages (D) source resistance Page 215 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. are (B) 10 Ω and 10 kΩ (A) 10 Ω and 1Ω (C) 100 kΩ and 1 Ω MCQ 4.113 (B) current shunt (D) voltage shunt In a differential amplifier.co. an input impedance of 1 kΩ .99 is connected to the amplifier in a voltage series feedback mode. respectively.112 (D) 25 Ω and 16.gatehelp. and a full-load voltage of 25 V at a full-load current of 1 A. Its output resistance and load regulation. A feedback network with a feedback factor of 0. respectively.and an output impedance of 100 Ω .

as compared to the basic amplifier (A) both. where α is (A) 4 (B) 3 (C) 2 MCQ 4. The Page 216 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. input and output impedances.decrease (B) input impedance decreases but output impedance increases (C) input impedance increase but output (D) both input and output impedances increases.gatehelp.in .114 From a measurement of the rise time of the output pulse of an amplifier whose is a small amplitude square wave.118 (D) B = 2 2 ω1 + ω2 2 + ω3 One input terminal of high gain comparator circuit is connected to ground and a sinusoidal voltage is applied to the other input. The approximate overall bandwidth B of the amplifier will be given by (A) B = ω1 + ω2 + ω3 (B) 1 = 1 + 1 + 1 ω1 ω2 ω3 B (C) B = (ω1 + ω2 + ω3) 1/3 MCQ 4.117 TWO MARKS A multistage amplifier has a low-pass response with three real poles at s =− ω1 − ω2 and ω3 . one can estimate the following parameter of the amplifier (A) gain-bandwidth product (B) slow rate (C) upper 3–dB frequency MCQ 4.com Chap 4 Analog Circuits MCQ 4.www. 1998 MCQ 4.nodia.116 (D) 1 In a shunt-shunt negative feedback amplifier.co.115 (D) lower 3–dB frequency The emitter coupled pair of BJT’s given a linear transfer relation between the differential output voltage and the differential output voltage and the differential input voltage Vid is less α times the thermal voltage.

120 (D) Av << 1 For full wave rectification.119 (B) a full rectified sinusoid (D) a square wave In a series regulated power supply circuit.www. 1 MCQ 4. (2) as well as (3) are true MCQ 4.nodia.com Chap 4 Analog Circuits output of comparator will be (A) a sinusoid (C) a half rectified sinusoid MCQ 4. Of these.gatehelp.in . a four diode bridge rectifier is claimed to have the following advantages over a two diode circuit : (A) less expensive transformer.co. (B) smaller size transformer. (A) only (1) and (2) are true (B) only (1) and (3) are true (C) only (2) and (3) are true (D) (1). and (C) suitability for higher voltage application. the voltage gain Av of the ‘pass’ transistor satisfies the condition (A) Av " 3 (B) 1 << Av < 3 (C) Av .121 In the MOSFET amplifier of the figure is the signal output V1 and V2 obey the relationship (A) V1 = V2 2 (C) V1 = 2V2 (B) V1 =−V2 2 (D) V1 =− 2V2 Page 217 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.

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Chap 4 Analog Circuits

MCQ 4.122

For small signal ac operation, a practical forward biased diode can be modelled as (A) a resistance and a capacitance in series (B) an ideal diode and resistance in parallel (C) a resistance and an ideal diode in series (D) a resistance

1997 MCQ 4.123

ONE MARK

In the BJT amplifier shown in the figure is the transistor is based in the forward active region. Putting a capacitor across RE will

(A) decrease the voltage gain and decrease the input impedance (B) increase the voltage gain and decrease the input impedance (C) decrease the voltage gain and increase the input impedance (D) increase the voltage gain and increase the input impedance

MCQ 4.124

A cascade amplifier stags is equivalent to (A) a common emitter stage followed by a common base stage (B) a common base stage followed by an emitter follower (C) an emitter follower stage followed by a common base stage (D) a common base stage followed by a common emitter stage

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Chap 4 Analog Circuits

MCQ 4.125

In a common emitter BJT amplifier, the maximum usable supply voltage is limited by (A) Avalanche breakdown of Base-Emitter junction (B) Collector-Base breakdown voltage with emitter open (BVCBO) (C) Collector-Emitter breakdown voltage with base open (BVCBO) (D) Zener breakdown voltage of the Emitter-Base junction

1997 MCQ 4.126

TWO MARKS

In the circuit of in the figure is the current iD through the ideal diode (zero cut in voltage and forward resistance) equals

(A) 0 A (C) 1 A

MCQ 4.127

(B) 4 A (D) None of the above

The output voltage V0 of the circuit shown in the figure is

(A) − 4 V (C) 5 V

(B) 6 V (D) − 5.5 V

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Chap 4 Analog Circuits

MCQ 4.128

A half wave rectifier uses a diode with a forward resistance Rf . The voltage is Vm sin ωt and the load resistance is RL . The DC current is given by Vm (A) Vm (B) π ( R f + R L) 2 RL (C) 2Vm π

1996

(D) Vm RL

ONE MARK

MCQ 4.129

In the circuit of the given figure, assume that the diodes are ideal and the meter is an average indicating ammeter. The ammeter will read

(A) 0.4 2 A (C) 0.8 A π

MCQ 4.130

(B) 0.4 A (D) 0.4 mamp π

The circuit shown in the figure is that of

**(A) a non-inverting amplifier (C) an oscillator
**

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(B) an inverting amplifier (D) a Schmitt trigger

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a very large input impedance.nodia.131 In the circuit shown in the given figure N is a finite gain amplifier with a gain of k .co.5 gm2 Value of R in the oscillator circuit shown in the given figure. The value of ω and the required value of R will respectively be Page 221 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.com Chap 4 Analog Circuits 1996 TWO MARKS MCQ 4. If the transconductance of c Q1 is gm1 and Q2 is gm2 .5 gm1 (D) 0. and a very low output impedance. The input impedance of the feedback amplifier with the feedback impedance Z connected as shown will be (A) Z b1 − 1 l k Z (C) (k − 1) MCQ 4.in . then the overall transconductance gmc . T ic c E vbe is given by (A) gm1 (C) gm2 MCQ 4.132 (B) Z (1 − k) (D) Z (1 − k) A Darlington stage is shown in the figure.www. so chosen that it just oscillates at an angular frequency of ω .gatehelp.133 (B) 0.

gatehelp.nodia.com Chap 4 Analog Circuits (A) 105 rad/ sec. 2 # 10 4 Ω (D) 105 rad/ sec.www. keeping the output voltage V0 constant at 6 V? (A) 0 mA.co. 180 mA (C) 10 mA. What are the minimum and maximum load currents that can be drawn safely from the circuit. 110 mA (D) 60 mA. 55 mA (B) 5 mA. and a maximum allowed power dissipation of 300 mW.134 (B) 2 # 10 4 rad/ sec. 180 mA *********** Page 222 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. 105 Ω A zener diode in the circuit shown in the figure is has a knee current of 5 mA.in . 2 # 10 4 Ω (C) 2 # 10 4 rad/ sec. 105 Ω MCQ 4.

com Chap 4 Analog Circuits SOLUTIONS SOL 4. Hence (D) is correct option. 1 ωr = 1 = = 10 M rad/s −6 LC 10 # 10 # 1 # 10−9 Thus given frequency is resonance frequency and parallel RLC circuit has maximum impedance at resonance frequency Gain of the amplifier is gm # (ZC RL) where ZC is impedance of parallel RLC circuit. Hence (A) is correct option.co.in .1 For the parallel RLC circuit resonance frequency is.gatehelp. Page 223 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.nodia. r SOL 4. ZC = R = 2 kΩ = ZC max . Hence HPF. gain is which is Gain ω = ω = gm (ZC RL) = gm (2k 2k) = gm # 103 maximum. Therefore gain is maximum at ωr = 10 M rad/ sec .2 The given circuit is shown below : From diagram we can write Ii = Vo + Vo R1 sL1 Transfer function H (s) = Vo = sR1 L1 I1 R1 + sL1 jω R 1 L 1 or H (jω) = R 1 + jω L 1 At ω = 0 H (jω) = 0 At ω = 3 H (jω) = R1 = constant . At ω = ωr . Hence at this frequency (ωr ).www.

By assuming M1 to be in saturation we have IDS (M ) = IDS (M ) μn C 0x μ C (4) (5 − Vx − 1) 2 = n 0x 1 (Vx − 1) 2 2 2 1 2 4 (4 − Vx ) 2 = (Vx − 1) 2 or 2 (4 − Vx ) = ! (Vx − 1) Taking positive root. for common emitter amplifier. 8 − 2Vx = Vx − 1 Vx = 3 V At Vx = 3 V for M1.98 β = α = 4. SOL 4.(1) IC = βIB + (1 + β) ICO Substituting ICO = 0. VGS = VG − VS = Vx − 0 = Vx VDS = VD − VS = Vx − 0 = Vx Since VGS − VT = Vx − 1 < VDS .4 We have Now α = 0. . Page 224 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.nodia.gatehelp.VGS = 5 − 3 = 2 V < VDS . Thus our assumption is true and Vx = 3 V ..01 mA Hence (D) is correct option.co.in . For transistor M2 . thus M2 is in saturation.3 Given circuit is shown below. IC = 1.www..6 μA and IB = 20 μA in above eq we have.com Chap 4 Analog Circuits SOL 4. Hence (C) is correct option.9 1−α In active region.

co.7 − (− 10) IE = E = = 1 mA 4.5 # 10−3 Hence (C) is correct option.gatehelp.7 − 4 (0.3k Now IC .in .7 V drop across each diode.7 V VE = VB − VBEon =− 5.. SOL 4.5 mA Since i1 = C dVC dt or VC = 1 C i1 t # i1 dt = C .nodia. In forward biased there will be 0.5 In active region Emitter voltage Emitter Current VBEon = 0.7 & VC =+ 5 V (across capacitor) Thus from (1) we get.VCE = 0. 12.(1) with time. IE = 1 mA Applying KCL at collector i1 = 0.www. + 5 = 0. When saturation starts.7) Thus IDC = = 1 mA 9900 Hence (A) is correct option. Page 225 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www..5 mA T 5 μA −6 or T = 5 # 5 # 10 = 50 m sec 0.7 V V − (− 10) − 5. the capacitor charges and voltage across collector changes from 0 towards negative.6 The current flows in the circuit if all the diodes are forward biased.3k 4.com Chap 4 Analog Circuits SOL 4.

gatehelp. SOL 4.7 The forward resistance of each diode is r = VT = 25 mV = 25 Ω IC 1 mA 4 (r) Thus Vac = Vi # e 4 (r) + 9900 o = 100 mV cos (ωt) 0. AV = 1 + gm R E Hence (A) is correct option.01 = 1 cos (ωt) mV Hence (B) is correct option.www. emitter area of transistor Q1 is half of transistor Q2 .com Chap 4 Analog Circuits SOL 4.8 The equivalent circuit of given amplifier circuit (when CE is connected. resistance RE appears in the circuit Input impedance R in = RB || [rπ + (β + 1)] RE Input impedance increases gm RC Voltage gain Voltage gain decreases.in . so current IE = 1 IE and IB = 1 IB 2 2 1 2 1 2 Page 226 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.nodia.co. SOL 4. if CE is disconnected. RE is short-circuited) Input impedance Ri = RB || r π Voltage gain AV = gm RC Now.9 Since.

co.com Chap 4 Analog Circuits The circuit is as shown below : VB =− 10 − (− 0.in . 2 702 2 I 0 = IC = β 2 : IB = 715 # 2 . IE Applying KCL at base we have 1 − IE = IB + IB 1 − (β 1 + 1) IB = IB + IB I 1 = (700 + 1 + 1) B + IB 2 1 2 1 1 2 2 2 IB .nodia.gatehelp.3 V Collector current I1 = 0 − (− 9.www.7) =− 9. 2 mA 702 2 2 Hence (B) is correct option. 0 − Vi + 0 − Vo = 0 R1 R2 Page 227 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. SOL 4.3 kΩ) 1 β 1 = 700 (high).10 The circuit is as shown below : So.3) = 1 mA (9. So IC .

14 # 1250 # 4.gatehelp. SOL 4.com Chap 4 Analog Circuits or Vo =− R2 Vi R1 Hence (A) is correct option. SOL 4. SOL 4.nodia.www.1 Hz 10 10 Hence (B) is correct option.12 Cut-off frequency due to C2 1 fo = 2π (RC + RL) C2 1 fo = = 271 Hz 2 # 3.co. o = 271 = 27.13 The circuit is as shown below Page 228 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.11 By small signal equivalent circuit analysis Input resistance seen by source vs R in = vs = Rs + Rs || rs is = (1000 Ω) + (93 kΩ || 259 Ω) = 1258 Ω Hence (B) is correct option.7 # 10−6 Lower cut-off frequency f fL .in .

www. D2 conducts 2 Equivalent circuit is shown below Output is Vo = 0 .V Diode is off.gatehelp.nodia. SOL 4. Vo = 0 At Vi =− 10 V. diode D2 will be off 5 + VI < 0 & V < − 5. Vo = 5 V Hence (B) is correct option.14 Let diode be OFF.co.in . diode D2 conducts So. If I < 0 . for 5 + VI > 0 & VI > − 5. therefore Vi − 1 > 0 " Vi > 1 Thus for Vi > 1 diode is off and V = 1V Page 229 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.com Chap 4 Analog Circuits Current I = 20 − 0 + Vi − 0 = 5 + Vi 4R R R If I > 0. it must be in reverse biased. In this case 1 A current will flow in resistor and voltage across resistor will be V = 1. D is off I 2 R The circuit is shown below 0 − Vi + 0 − 20 + 0 − Vo = 0 R 4R R or Vo =− Vi − 5 At Vi =− 5 V.

1) Hence (A) is correct option.www.4V = 0. Let Vi < 1.gatehelp. In this case diode will be on and voltage across diode will be zero and V = Vi Thus V = min (Vi. SOL 4.15 The R2 decide only the frequency.4k = 1.nodia.16 For small increase in VG beyond 1 V the n − channel MOSFET goes into saturation as VGS " + ive and p − MOSFET is always in active region or triode region.6 + 1.18 The circuit is shown in fig below The voltage at non inverting terminal is 5 V because OP AMP is ideal and inverting terminal is at 5 V.in .17 Hence (C) is correct option. Hence (A) is correct option SOL 4.co.4 = 2V Page 230 IE = IC GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. Hence (D) is correct option. Thus IC = 10 − 5 = 1 mA 5k VE = IE RE = 1m # 1. SOL 4.com Chap 4 Analog Circuits Option (B) and (C) doesn’t satisfy this condition. SOL 4.

− 150 # 3k Vi 3k .7 V Hence (C) is correct option. SOL 4.20 For the positive half of Vi . D2 is reverse bias and the zener diode is in breakdown state because Vi > 6. W W Thus b L l =b L l 2 2 W Ix = Hence Ix = Ibias Hence (B) is correct option. SOL 4.gatehelp. Thus output voltage is V0 = 0. Page 231 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. SOL 4. ^ L h2 Ibias W ^ L h1 Since MOSFETs are identical.in . D2 is forward bias thus Then V0 =− 0.co. thus inverting terminal is also at virtual ground. − 150B sin 106 t Hence (D) is correct option.5 V For the negative half of Vi.www. − 150 (A cos 20t + B sin 106 t) Since coupling capacitor is large so low frequency signal will be filtered out. the diode D1 is forward bias.com Chap 4 Analog Circuits Thus the feedback is negative and output voltage is V = 2V .21 By Current mirror. Hence (D) is correct option. and best approximation is V0 . − hfe RC Vi hie Here RC = 3 Ω and hie = 3 kΩ Thus V0 .22 The circuit is using ideal OPAMP.nodia.7 + 6.8 = 7. The non inverting terminal of OPAMP is at ground.8 . SOL 4.19 The output voltage is V0 = Ar Vi .

SOL 4.06 V V0 = I # 4k + V = 1 # 4k + 0. Thus the current I is 0 − (− 1) I = = 1 100k 100k The current through diode is V t I = I 0 _eV − 1i Now VT = 25 mV and I0 = 1 μA Thus or Now V I = 10−6 8e 25 # 10 − 1B = 1 5 10 −3 V = 0.1 V 100k Hence (B) is correct option.06 = 0.co. The non inverting terminal of OPAMP is at ground.com Chap 4 Analog Circuits Thus current will flow from -ive terminal (0 Volt) to -1 Volt source.in .F.gatehelp.nodia.23 The circuit is using ideal OPAMP. of low pass filter Page 232 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.www. Thus we can write vi v = − R R1 + sL sR C + 1 v R2 0 or =− vi (R1 + sL)( sR2 C2 + 1) 2 2 2 and from this equation it may be easily seen that this is the standard form of T. thus inverting terminal is also at virtual ground.

SOL 4.com Chap 4 Analog Circuits H (s) = K (R1 + sL)( sR2 C2 + 1) and form this equation it may be easily seen that this is the standard form of T.www. SOL 4. Hence (C) is correct option.F.co.67 k Ω 10k + 20k Page 233 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.24 The current in both transistor are equal. Thus gm is decide by M1.in .gatehelp. SOL 4. of low pass filter H (s) = 2 K as + bs + b Hence (B) is correct option.25 Let the voltage at non inverting terminal be V1. then after applying KCL at non inverting terminal side we have 15 − V1 + V0 − V1 = V1 − (− 15) 10 10 10 or V1 = V0 3 If V0 swings from -15 to +15 V then V1 swings between -5 V to +5 V. Hence (C) is correct option.nodia.26 For the given DC values the Thevenin equivalent circuit is as follows The thevenin resistance and voltage are VTH = 10 # 9 = 3 V 10 + 20 and total RTH = 10k # 20k = 6.

gatehelp.7 = 1 mA RE 2.27 The small signal model is shown in fig below gm = IC = 1m = 1 A/V VT 25m 25 IC . Page 234 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.5k) 25 or =− 60Vin Am = Vo =− 60 Vin Hence (D) is correct option.nodia.co. Hence (A) is correct option. SOL 4.3k Hence (A) is correct option.28 The circuit shown in (C) is correct full wave rectifier circuit. Hence (C) is correct option. IE Vπ = Vin Vo =− gm Vπ # (3k 3k ) =− 1 Vin (1.www.in .com Chap 4 Analog Circuits Since β is very large. therefore IB is small and can be ignored Thus IE = VTH − VBE = 3 − 0. SOL 4. SOL 4.29 In the transconductance amplifier it is desirable to have large input resistance and large output resistance.

co.5 mA 1k i = 0.3 mA 1k RE Since β is very large.5 − v0 = 0.5 V i = 1 − 0.gatehelp.www.in .5 − 1 =− 0. VBE = 0.5 V We know that Thus Now and or v+ = vv. Hence (B) is correct option.5 = 0.= 0.3) = 5 V Since VBC > 0. Applying voltage division rule v+ = 0.5 V Hence (C) is correct option.nodia.com Chap 4 Analog Circuits SOL 4.7 V.31 If we assume β very large.7 = 1. so applying KVL in Base-emitter loop IE = 2 − VBE = 2 − 0. then IB = 0 and IE = IC .30 We redraw the circuit as shown in fig. We assume that BJT is in active.7 V. SOL 4.3 mA Now applying KVL in collector-emitter loop 10 − 10IC − VCE − IC = 0 or Now VCE =− 4.3 V VBC = VBE − VCE = 0. thus IC = 1. thus transistor in saturation.7 − (− 4. we have IE = IC .5 mA 2k v0 = 0. Page 235 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.

34 We have VZ = 7 volt.5 V μA Thus ID = K (Vas − VT ) 2 = 40 2 (2.33 We have and Vthp = Vthp = 1 V WP W = N = 40μA/V2 LP LN From figure it may be easily seen that Vas for each NMOS and PMOS is 2.in .e.nodia. RZ = 10Ω Circuit can be modeled as shown in fig below Page 236 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.32 Here the inverting terminal is at virtual ground and the current in resistor and diode current is equal i. SOL 4. IR = ID Vi = I eV /V or s R or VD = VT 1n Vi Is R D T For the first condition VD = 0 − Vo1 = VT 1n 2 Is R For the first condition VD = 0 − Vo1 = VT 1n 4 Is R Subtracting above equation Vo1 − Vo2 = VT 1n 4 − VT 1n 2 Is R Is R Vo1 − Vo2 = VT 1n 4 = VT 1n2 2 or Hence (D) is correct option. VK = 0.co.gatehelp.5 − 1) 2 = 90 μ A V Hence (D) is correct option.com Chap 4 Analog Circuits SOL 4. SOL 4.www.

15 V to 45m # RZ = 0.36 V0 = H (s) = 1 − sRC Vi 1 + sRC H (jω) = 1 − jωRC 1 + jωRC +H (jω) = φ =− tan .= V+ = 1 V 1 + sCR i Applying voltage division rule (V + Vi) V+ = R1 (V0 + Vi) = o R1 + R1 2 or or (V + Vi) 1 Vi = o 1 + sCR 2 Vo =− 1 + 2 Vi 1 + sRC V0 = 1 − sRC Vi 1 + sRC Hence (A) is correct option.com Chap 4 Analog Circuits Since Vi is lies between 10 to 16 V. φmax = 0( at ω = 0) Hence (C) is correct option.35 The voltage at non-inverting terminal is V+ = Now R+ 1 sC 1 sC Vi = 1 V 1 + sCR i V.2 ωRC Minimum value. SOL 4.gatehelp.nodia. Page 237 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.co.www. the range of voltage across 200 k Ω V200 = Vi − VZ = 3 to 9 volt The range of current through 200 k Ω is 3 = 15 mA to 9 = 45 mA 200k 200k The range of variation in output voltage 15m # RZ = 0. SOL 4.in .45 Volt Hence (C) is correct option.1 ωRC =− 2 tan .45 Thus the range of output voltage is 7. φmin = − π (at ω " 3) Maximum value.15 Volt to 7.1 ωRC − tan .

39 The voltage at inverting terminal is V− = V+ = 10 V Here note that current through the capacitor is constant and that is I = V− = 10 = 10 mA 1k 1k Thus the voltage across capacitor at t = 1 msec is 1m 1m VC = 1 Idt = 1 10mdt = 10 4 C 0 1μ 0 # # dt = 10 V # 0 Im Hence (D) is correct option.in . Thus voltage across is resistor is VR = Vin − 6 Only option (B) satisfy this condition.www.38 Hence (C) is correct option. Hence (D) is correct option.40 In forward bias Zener diode works as normal diode. SOL 4. Thus for negative cycle of input Zener diode is forward biased and it conducts giving VR = Vin .37 In the transconductance amplifier it is desirable to have large input impedance and large output impedance. SOL 4. For positive cycle of input Zener diode is reversed biased when 0 < Vin < 6 .nodia. SOL 4.gatehelp. SOL 4.co. Diode is OFF and VR = 0 when Vin > 6 Diode conducts and voltage across diode is 6 V.41 The circuit under DC condition is shown in fig below Page 238 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.com Chap 4 Analog Circuits SOL 4. Hence (A) is correct option.

.(2) . SOL 4.95 V 53 1+ 1 + (1 + 60) Hence (C) is correct option.(1) .gatehelp.42 .nodia.www..43 Hence (A) is correct option.in .44 The Zener diode is in breakdown region.com Chap 4 Analog Circuits Applying KVL we have VCC − RC (IC + IB) − VCE = 0 and VCC − RB IB − VBE = 0 Substituting IC = βIB in (1) we have VCC − RC (βIB + IB) − VCE = 0 Solving (2) and (3) we get VCE = VCC − VCC − VBE RB 1+ RC (1 + β) Now substituting values we get 12 − 0.95 Hence (B) is correct option.co. SOL 4.5 # 100 =− 4.7 VCE = 12 − = 5.29 − 59...3% 5.. SOL 4. thus V+ = VZ = 6 V = Vin Page 239 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www..(4) We have β' = 110 # 60 = 66 100 Substituting β' = 66 with other values in (iv) in previous solutions 12 − 0.(3) ...7 VCE = 12 − = 5.29 V 53 1+ 1 + (1 + 66) Thus change is = 5.

9 A RL 10 Now VCE = 15 − 9 = 6 V The power dissipated in transistor is P = VCE IC = 6 # 0.nodia. SOL 4.1 − 5. the current flowing through the voltage source is Is = Vs 10k Vs = 10 kΩ = R or in Is Hence (B) is correct option. Thus Current IC .9 = 8.1 W Thus % increase in power is 8.4 Hence (B) is correct option.4 # 100 = 50% 5. IE .46 Since the inverting terminal is at virtual ground. VCE − 18 − 9 = 9 V IC = 0.co. There will be change in VCE Thus.www.47 The effect of current shunt feedback in an amplifier is to decrease the input resistance and increase the output resistance as : Rif = Ri 1 + Aβ Page 240 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.gatehelp.45 If the unregulated voltage increase by 20%. = Vout = 9 = 0.4 W Hence (C) is correct option. SOL 4.in . SOL 4.com Chap 4 Analog Circuits We know that or Vo = Vin c1 + Vout Rf R1 m = Vo = 6`1 + 12k j = 9 V 24k The current in 12 k Ω branch is negligible as comparison to 10 Ω .9 = 5.9 A Power dissipation P = VCE IC = 9 # 0. but the VZ = Vin = 6 remain same and hence Vout and IC remain same. them the unregulated voltage is 18 V.

49 Common mode gain ACM =− RC 2RE And differential mode gain ADM =− gm RC Thus only common mode gain depends on RE and for large value of RE it decreases.com Chap 4 Analog Circuits Rof = R0 (1 + Aβ) where Ri " Input resistance without feedback Rif " Input resistance with feedback. SOL 4. SOL 4.gatehelp.7 − 1m = 49 mA e1 # 26 # 10 -3 Hence (C) is correct option.50 IE = Is `e nV − 1j = 10 . It is used as last step to match a very low impedance source and to drain a high impedance load Thus cascade amplifier is a multistage configuration of CE-CB Hence (B) is correct option SOL 4. SOL 4. It performs basic function of amplifications. Hence (D) is correct option. Hence (D) is correct option.www.13 c VBE T 0. The CB configuration has lowest Ri and highest Ro .nodia.51 The circuit is as shown below Page 241 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.co.in .48 The CE configuration has high voltage gain as well as high current gain.

At high frequency capacitor act as short circuit and all input voltage appear at non-inverting terminal.. SOL 4..(2) V+ = − I+ (1M) Since for ideal OPAMP V+ = V. Thus.com Chap 4 Analog Circuits Writing equation for I− have e 0 − V− = I 1M or e0 = I− (1M) + V− Writing equation for I+ we have 0 − V+ = I+ 1M .nodia. this is high pass circuit..52 At low frequency capacitor is open circuit and voltage acr s noninverting terminal is zero.www. we can calculate input offset current IOS only. from (1) and (2) we have e0 = I− (1M) − I + (1M) = (I− − I+) (1M) = IOS (1M) Thus if e0 has been measured. The frequency is given by 1 = 1000 rad/sec ω = 1 = 3 RC 1 # 10 # 1 # 10 .6 Hence (C) is correct option.(1) or ..in .53 The circuit under DC condition is shown in fig below Applying KVL we have VCC − RB IB − VBE − RE IE = 0 or VCC − RB IB − VBE − RE (β + 1) IB = 0 Page 242 Since IE = IB + βIB GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. Hence (C) is correct option. SOL 4.gatehelp..co.

2 − 0.56 The small signal model is as shown below From the figure we have Zin = 2 MΩ and Z0 = rd RD = 20k 2k = 20 kΩ 11 Page 243 Hence (B) is correct option.nodia.e. Vmax = 30 V i.54 The maximum load current will be at maximum input voltage i.in . SOL 4.www.8 = I = 0. Vmax − VZ = I + I L Z 1k or 30 − 5.7 mA Hence (A) iscorrect option. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.com Chap 4 Analog Circuits or IB = = VCC − VBE RB + (β + 1) RE 20 − 0. SOL 4.55 Hence (D) is correct option.5 = 23.e.co. SOL 4.gatehelp.5 m L 1k or IL = 24.7 = 40μ A 430k + (50 + 1)1 k Now IC = βIB = 50 # 40μ = 2 mA VC = VCC − RC IC = 20 − 2m # 2k = 16 V Hence (B) is correct option.

625 mA (− 8) m VP Now VDS = VDD − ID RD = 20 − 5.gatehelp.625 m # 2 k = 8. The gain is So. VP = 2 5.41 11 Hence (B) is correct option.in .59 Only one diode will be in ON conditions When lower diode is in ON condition.875 mS 8 2 ID IDSS A =− gm (rd RD) = 1.58 The transconductance is gm = or.625mA # 10mA = 1.875ms # 20 K =− 3.5k 4 Hence (B) is correct option.co. then Vu = 2k Vsat = 2 10 = 8 V 2.com Chap 4 Analog Circuits SOL 4. FET is operating in active region 2 (− 2) 2 Now ID = IDSS c1 − VGS m = 10 c1 − = 5.nodia.57 The circuit in DC condition is shown below Since the FET has high input resistance.5k 2. SOL 4. Page 244 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.75 V Hence (A) is correct option. SOL 4.www.5 when upper diode is in ON condition Vu = 2k Vsat = 2 (− 10) =− 5 V 2. gate current can be neglect and we get VGS =− 2 V Since VP < VGS < 0 .

www. The frequency of oscillation is 2πf = 1 RC 1 = 1 = 1 μ 3 3 2πRf 2π 2π # 10 # 10 Hence (A) is correct option. Hence (B) is correct option.co.5 k Ω gm 40 # 10 Hence (D) is correct option. SOL 4. Rif = Ri (1 + Aβ) Ro Rof = (1 + Aβ) Hence (C) is correct option. or C = Page 245 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.nodia.64 The given circuit is wein bridge oscillator.gatehelp. SOL 4.60 An ideal OPAMP is an ideal voltage controlled voltage source.in . SOL 4. SOL 4.63 When IC >> ICO gm = rπ = IC = 1mA = 0.61 In voltage series feed back amplifier. because V0 = 0 At ω = 3 Vin and at ω = 0 V0 = 1 Vin Hence (A) is correct option.com Chap 4 Analog Circuits SOL 4. input impedance increases by factor (1 + Aβ) and output impedance decreases by the factor (1 + Aβ).04 = 40 mA/V VT 25mV β = 100 .3 = 2.62 This is a Low pass filter.

− Vo = Vs Applying KCL at non-inverting terminal V+ V − Vo =0 + IL + + R2 R2 or 2V+ − Vo + IL R2 = 0 Since V.= V+ Applying KCL at inverting terminal V.66 .(1) .65 The circuit is as shown below We know that for ideal OPAMP V.= V+ .gatehelp.nodia.. SOL 4.in .www.− V0 = 0 R1 R1 or 2V..com Chap 4 Analog Circuits SOL 4.− Vs + V. from (1) and (2) we have Vs + IL R2 = 0 or IL =− Vs R2 Hence (A) is correct option.(2) If IZ is negligible the load current is 12 − Vz = I L R as per given condition 100 mA # 12 − VZ # 500 mA R At IL = 100 mA 12 − 5 = 100 mA R R = 70Ω At IL = 500 mA 12 − 5 = 500 mA R or or Page 246 VZ = 5 V VZ = 5 V R = 14 Ω GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www...co.

www. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. IC .69 For the different combinations the table is as follows CE Ai Av Ri Ro CE High High Medium Medium CC High Unity High Low CB Unity High Low High Page 247 Hence (B) is correct option.7 = 3 mA RE 300 VCE = 5 − 2.com Chap 4 Analog Circuits Thus taking minimum we get R = 14 Ω Hence (D) is correct option.nodia. IE . IB .2kIC − 300IE = 5 − 2.2k # 1m − 300 # 1m = 2. 0 and IE = VT − VBE = 1 − 0.68 The thevenin equivalent is shown below VT = R1 V = 1 #5 = 1 R1 + R2 C 4+1 V Since β is large is large.co. SOL 4.5 V Hence (C) is correct option Now SOL 4.in .67 Hence (B) is correct option.gatehelp. SOL 4.

SOL 4.in .71 If the input is sinusoidal signal of 8 V (peak to peak) then Vi = 4 sin ωt The output of comparator will be high when input is higher than Vref = 2 V and will be low when input is lower than Vref = 2 V.gatehelp. Hence (D) is correct option.com Chap 4 Analog Circuits SOL 4.www.nodia.70 This circuit having two diode and capacitor pair in parallel. first crossover is at ωt1 and second crossover is at ωt2 where 4 sin ωt1 = 2V Thus ωt1 = sin . SOL 4.co. 3 Hence (B) is correct option.1 1 = π 2 6 ωt2 = π − π = 5π 6 6 Duty Cycle = 5π 6 − 2π π 6 =1 3 Thus the output of comparators has a duty cycle of 1 . Thus the waveform for input is shown below From fig.72 CMMR = Ad Ac or Page 248 20 log CMMR = 20 log Ad − 20 log Ac = 48 − 2 = 46 dB GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. works as voltage doubler.

01 mA β1 150 In second case IB2 will we equal to IB1 as there is no in R1. Rif = = 1 kΩ (1 + Aβ) 11 Hence (A) is correct option.com Chap 4 Analog Circuits Where Ad " Differential Voltage Gain and AC " Common Mode Voltage Gain Hence (C) is correct option. In first case VCC − IC1 R2 − VCE1 = 0 or 6 − 1.74 We have Ri = 1kΩ. This is fixed bias circuit operating in active region. SOL 4.5mR2 − 3 = 0 or R2 = 2kΩ IB1 = IC1 = 1.5m = 0. SOL 4.nodia. A = 50 Ri Thus.75 The DC equivalent circuit is shown as below.in . β = 0. Thus IC2 = β2 IB2 = 200 # 0.73 The gain of amplifier is Ai = − gm gb + jωC Thus the gain of a transistor amplifier falls at high frequencies due to the internal capacitance that are diffusion capacitance and transition capacitance.gatehelp.co. SOL 4.www. Page 249 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.01 = 2 mA VCE2 = VCC − IC2 R2 = 6 − 2m # 2 kΩ = 2 V Hence (A) is correct option.2. Hence (B) is correct option.

Thus Vo can be get by applying voltage division rule. SOL 4.− 10 = 6 # 8 − 10 = 6 V 3 Hence (B) is correct option.− 2 + V.= 8 V 3 Now applying KCL at inverting terminal we get V.78 The circuit is as shown below V+ = 8 (3) = 8 kΩ 1+8 3 V+ = V. i.− Vo = 0 1 5 or Vo = 6V.76 The given circuit is a R − C phase shift oscillator and frequency of its oscillation is 1 f = 2π 6 RC Hence (A) is correct option.com Chap 4 Analog Circuits SOL 4.co. Page 250 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. SOL 4.gatehelp.e.nodia.77 If we see th figure we find that the voltage at non-inverting terminal is 3 V by the zener diode and voltage at inverting terminal will be 3 V. 20 V = 3 20 + 40 o or V0 = 9 V Hence (C) is correct option.in .www.

www. Hence (D) is correct option.79 The equivalent circuit of 3 cascade stage is as shown in fig.co. Page 251 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.in .25k V3 = 40 # 40V1 Vo = 50V3 = 50 # 40 # 40V1 AV = Vo = 50 # 40 # 40 = 8000 V1 20 log AV = 20 log 8000 = 98 dB Hence (C) is correct option.com Chap 4 Analog Circuits SOL 4.6 i = 3 mA idt # 0 20 # 10.3 Thus the charging require 3 mA current source for 2 msec.nodia.25k 1k 50V2 = 40V2 1k + 0.3 − 0) = 6 # 10 . SOL 4.gatehelp. the output voltage is integration of input current and that is sawtooth waveform as below : VC = 1 C idt # 0 t The time period of wave form is T = 1 = 1 = 2 m sec f 500 Thus or or 1 3= 2 # 106 i (2 # 10 . V2 = Similarly or or or V3 = 1k 50V1 = 40V1 1k + 0.80 If a constant current is made to flow in a capacitor.

com Chap 4 Analog Circuits SOL 4. 40 Hz Ln 1 23 − 1 1 fHn = fH 2 2 − 1 = 0. SOL 4. From bandwidth point of view only options (A) may be correct because lower cutoff frequency must be increases and higher must be decreases.83 2n − 1 The higher cutoff frequency is 1 In multistage amplifier bandwidth decrease and overall gain increase.gatehelp. V (f) Now from circuit A = O = 1 + R2 Vf (f) R1 V (f) β (f) = 1 +0 = f 6 VO (f) Thus from above equation for sustained oscillation Page 252 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. therefore 20 log x = 20 or x = 10 Since Gain band width product is 106 Hz.in .nodia. SOL 4.2 . the Ri increase and Ro decrease because Rif = Ri (1 + Aβ) Ro Rof = (1 + Aβ) Hence (C) is correct option.84 As per Barkhousen criterion for sustained oscillations Aβ $ 1 and phase shift must be or 2πn .82 Let x be the gain and it is 20 db. From following calculation we have We have fL = 20 Hz and fH = 1 kHz For n stage amplifier the lower cutoff frequency is fL 20 f = = = 39. thus 6 6 So.5 kHz Hence (A) is correct option. bandwidth is BW = 10 = 10 = 105 Hz = 100 kHz 10 Gain Hence (B) is correct option.www.81 In voltage-amplifier or voltage-series amplifier. SOL 4.co.

com Chap 4 Analog Circuits 6 = 1 + R2 R1 or R2 = 5R1 Hence (A) is correct option.5 mV Hence (C) is correct option.nodia.in .co. SOL 4.www. SOL 4.gatehelp.85 Let the gain of OPAMP be AV then we have 20 log AV = 40 dB or AV = 100 Let input be Vi = Vm sin ωt then we have VO = VV Vi = Vm sin ωt dV O Now = AV Vm ω cos ωt dt Slew Rate c dVO m = AV Vm ω = AV Vm 2πf dt max 1 or = -6 Vm = SR AV V2πf 10 # 100 # 2π # 20 # 103 or VM = 79. 30 − 10 $ (10 + 1) mA R 20 $ 11 mA or R or when Vin = 50 V R # 1818 Ω [IZ + IL = I] Page 253 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.86 The circuit is shown as below I = IZ + IL For satisfactory operations Vin − V0 > I Z + IL R When Vin = 30 V.

5 jB = 2 mS VP −5 AV = V0 =− gm RD Vi So.5 V = VG − VS = 0 − 2. SOL 4. =− 2ms # 3k =− 6 Hence (D) is correct option. SOL 4.87 We have Now and Thus Now IDSS VG VS VGS = 10 mA and VP =− 5 V =0 = ID RS = 1 # 2.www.5 V gm = 2IDSS 81 − ` − 2.88 The current gain of a BJT is hfe = gm rπ Hence (C) is correct option.in .5 =− 2. SOL 4. because of its characteristic (2) Bi-stable multivibrator can store binary information.3 R or R # 3636Ω Thus R # 1818Ω Hence (A) is correct option. SOL 4.co.90 Both statements are correct because (1) A stable multivibrator can be used for generating square wave.nodia.com Chap 4 Analog Circuits 50 − 10 $ (10 + 1) mA R 40 $ 11 # 10 .89 The ideal op-amp has following characteristic : Ri " 3 R0 " 0 and A"3 Hence (A) is correct option.gatehelp. and this Page 254 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.5Ω = 2.

nodia.co.47 # 1010 Hz If fB is bandwidth then we have 10 f fB = T = 1. SOL 4.47 # 10 = 1.92 If we neglect current through RB then it can be open circuit as shown in fig.14 + 4 # 10 .64 # 108 Hz β 90 Hence (B) is correct option.com Chap 4 Analog Circuits multivibrator also give help in all digital kind of storing.3 = fT = 2π (Cμ + Cπ) 2π # (10 .99 = 9.01 = 95 mW IC = βIZ = 99 # 0.in . Hence (C) is correct option.www.5 # 0.gatehelp.13) or = 1.9 W Hence (C) is correct option.91 If fT is the frequency at which the short circuit common emitter gain attains unity magnitude then gm 38 # 10 .99 A VCE = Vo = 10 V Power dissipated in transistor is PT = VC IC = 10 # 0.01 A β+1 99 + 1 Since IC = βIB since IB = IZ or Power dissipated in zener diode is PZ = VZ IZ = 9. Maximum power will dissipate in Zener diode when current through it is maximum and it will occur at Vin = 30 V I = Vin − Vo = 30 − 10 = 1 A 20 20 I IC + IZ = βIB + IZ = βIZ + IZ = (β + 1) IZ IZ = I = 1 = 0. SOL 4. Page 255 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.1 = 0.

www.nodia..(2) R1 R2 From (1) and (2) we have VO = A = − R2 CL Vs R − R2 + R1 ROL Substituting the values we have − 10k =− 1000 . the output voltage is .3 MHz = 2π 10 2π 10 # 10 .− V0 = 0 ...− Vs + V.95 The first OPAMP stage is the differentiator and second OPAMP stage is integrator. − 11 ACL = 10 k 1 k 89 + 1k − 100k Hence (D) is correct option.94 The circuit is as shown below Let V.. f = SOL 4. SOL 4. since non inverting terminal a at ground.co.93 From the it may be easily seen that the tank circuit is having 2-capacitors and one-inductor.6 # 10 . so it is colpits oscillator and frequency is 1 f = 2π LCeq Ceq = C1 C2 = 2 # 2 = 1 pF 4 C1 + C2 1 1 # 109 = 50. Thus if input is cosine term.com Chap 4 Analog Circuits SOL 4.in .gatehelp.(1) Vo = AOL VNow applying KCL at inverting terminal we have V.be the voltage of inverting terminal. output will be also Page 256 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.12 Hence (B) is correct option.

6 # 100 V0 = j10V2 = j10 (− j cos 100t) V0 = 10 cos 100t Hence (A) is correct option. However we can calculate as follows. SOL 4. The circuit is shown in fig Applying KCL at inverting terminal of first OP AMP we have V1 = − ωjL = − 100 # 10 # 10 .co.com Chap 4 Analog Circuits cosine term. common mode gain AC = 0 Hence (A) is correct option.nodia.gatehelp.3 = − 1 R 10 10 VS or V1 = − jVS = j cos 100t 10 Applying KCL at inverting terminal of second OP AMP we have VO = − 1/jωC 100 V1 =− or 1 = j10 j100 # 10 # 10 .97 In positive feed back it is working as OP-AMP in saturation region. SOL 4. So. and the input applied voltage is +ve. V0 =+ Vsat = 15 V Hence (D) is correct option. Only option (A) is cosine term. Page 257 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.in .96 Common mode gain is AC = αRC REE Since source resistance of the current source is infinite REE = 3 . Other are sine term.www.

nodia. SOL 4.in . Page 258 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. series connection in parallel with parallel R − C combination.99 At high frequency gm + jω (C) 1 Ai \ Capacitance Ai =− or. and ' gbc Ai α 1 frequency Thus due to the transistor capacitance current gain of a bipolar transistor drops. Hence (A) is correct option.101 There is R − C . Hence (A) is correct option.gatehelp. Hence (C) is correct option.www. the inverting terminal at virtual ground due to ground at non-inverting terminal. it is a wein bridge oscillator because two resistors R1 and R2 is also in parallel with them.100 As OP-AMP is ideal. so the output of triangular wave will be square wave.98 With the addition of RE the DC abis currents and voltages remain closer to the point where they were set by the circuit when the outside condition such as temperature and transistor parameter β change.com Chap 4 Analog Circuits SOL 4.co. SOL 4. SOL 4. SOL 4. So. Hence (D) is correct option.102 The given circuit is a differentiator. Applying KCL at inverting terminal sC (v1 sin ωt − 0) + sC (V2 sin ωt − 0) + sC (Vo − 0) = 0 or Vo =− (V1 + V2) sin ωt Hence (C) is correct option.

3 = 5 − 0.com Chap 4 Analog Circuits SOL 4. 000 = 50 V But V0 = ! 15 V in saturation condition So.co.www.105 The output voltage will be input offset voltage multiplied by open by open loop gain.103 In sampling and hold circuit the unity gain non-inverting amplifier is used.106 Hence (A) is correct option.430KΩ Hence (D) is correct option. 0 and IE = VT − VBE RE 4.gatehelp. V0 = ! Vset = ! 15V Hence (C) is correct option.7 = = 10 mA 0. IC . Hence (B) is correct option. SOL 4.430kΩ 0. SOL 4. Thus So V0 = 5mV # 10. SOL 4. Page 259 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.nodia. IE . IB . it can never be exceeds ! 15 V So.104 The thevenin equivalent is shown below VT = R1 V = 5 # 15 = 5 V 10 + 5 R1 + R2 C Since β is large is large.in .

108 By drawing small signal equivalent circuit by applying KCL at E2 V gm1 Vπ − π = gm2 Vπ rπ at C2 i 0 =− gm2 Vπ from eq (1) and (2) gm1 Vπ + i 0 =− i 0 gm2 rπ 2 1 2 2 1 2 1 2 gm1 Vπ =− i 0 :1 + gm2 rπ = β >> 1 gm1 Vπ =− i 0 i 0 =− g m1 Vπ 2 1 1 1 gm2 rπ D 2 so i0 = g m1 Vi Hence (A) is correct option.com Chap 4 Analog Circuits SOL 4. Hence (B) is correct option. SOL 4.nodia.gatehelp. Page 260 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.co.in .109 a Vπ = Vi 1 Crossover behavior is characteristic of calss B output stage. Hence (A) is correct option.107 Negative feedback in amplifier reduces the gain of the system. Here 2 transistor are operated one for amplifying +ve going portion and other for -ve going portion. SOL 4.www.

111 Regulation = Vno − load − Vfuel − load Vfull − load = 30 − 25 # 100 = 20% 25 Output resistance = 25 = 25 Ω 1 Hence (B) is correct option.gatehelp.99 # 100) = 100 kΩ Similarly output impedance is given by R0 ROUT = R 0 = output impedance (1 + βv Av) Thus ROUT = 100 = 1Ω (1 + 0. Page 261 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.113 In a differential amplifier CMRR is given by (1 + β) IQ R 0 CMRR = 1 . R in = 1 # 103 (1 + 0.1 + E 2 VT β So where R 0 is the emitter resistance. SOL 4.www.com Chap 4 Analog Circuits SOL 4. Av = openloop gain and Ri = Input impedance So.co. SOL 4.112 This is a voltage shunt feedback as the feedback samples a portion of output voltage and convert it to current (shunt). So CMRR can be improved by increasing emitter resistance.110 In Voltage series feedback mode input impedance is given by R in = Ri (1 + βv Av) where βv = feedback factor . Hence (D) is correct option.nodia. Hence (A) is correct option. SOL 4.99 # 100) Hence (C) is correct option.in .

So output is a square wave. R in < Ri Similarly R0 ROUT = (1 + βA) ROUT < R 0 Thus input & output impedances decreases.114 We know that rise time (tr ) is tr = 0. SOL 4. Input impedance Ri R in = (1 + βA) where Ri = input impedance of basic amplifier β = feedback factor A = open loop gain So.gatehelp.com Chap 4 Analog Circuits SOL 4.116 In a shunt negative feedback amplifier.35 fH where fH is upper 3 dB frequency. SOL 4. Hence (D) is correct option. Page 262 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.118 Comparator will give an output either equal to + Vsupply or − Vsupply .co. SOL 4.www.117 Hence (A) is correct option.in . Thus we can obtain upper 3 dB frequency it rise time is known. SOL 4.nodia. Hence (C) is correct option. Hence (D) is correct option.115 In a BJT differential amplifier for a linear response Vid < VT . Hence (D) is correct option.

if CE is disconnected. SOL 4. SOL 4.com Chap 4 Analog Circuits SOL 4. Hence (D) is correct option.120 In bridge rectifier we do not need central tap transformer.123 The equivalent circuit of given amplifier circuit (when CE is connected.119 In series voltage regulator the pass transistor is in common collector configuration having voltage gain close to unity. SOL 4. SOL 4.122 Hence (C) is correct option.in .co. so its less expensive and smaller in size and its PIV (Peak inverse voltage) is also greater than the two diode circuit. resistance RE appears in the circuit Page 263 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. RE is short-circuited) Input impedance Ri = RB || r π Voltage gain AV = gm RC Now.www.121 In the circuit we have V2 = IS # RD 2 and V1 = IS # RD V2 = 1 2 V1 V1 = 2V2 Hence (C) is correct option.gatehelp. so it is also suitable for higher voltage application.nodia. Hence (C) is correct option.

BVCEO < BVCBO both avalanche and zener break down.www.124 In common emitter stage input impedance is high.So BVCEO limits the power supply. SOL 4. Hence (A) is correct option.co.nodia.com Chap 4 Analog Circuits Input impedance R in = RB || [rπ + (β + 1)] RE Input impedance increases gm RC Voltage gain decreases. VP < Vn by calculating Page 264 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www. SOL 4. Hence (C) is correct option. SOL 4.125 We know that collect-emitter break down voltage is less than compare to collector base breakdown voltage.gatehelp.in .126 If we assume consider the diode in reverse bias then Vn should be greater than VP . Voltage gain AV = 1 + gm R E Hence (C) is correct option. so in cascaded amplifier common emitter stage is followed by common base stage. Voltage are higher than BVCEO .

SOL 4.com Chap 4 Analog Circuits VP = 10 # 4 = 5 Volt 4+4 Vn = 2 # 1 = 2 Volt here VP > Vn (so diode cannot be in reverse bias mode).www.co.in .nodia.127 By applying node equation at terminal (2) and (3) of OP -amp Va − Q Va − V0 =0 + 5 10 2Va − 4 + Va − V0 = 0 V0 = 3Va − 4 Va − V0 + Va − 0 = 0 100 10 Va − V0 + 10Va = 0 Page 265 GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia Published by: NODIA and COMPANY ISBN: 9788192276236 Visit us at: www.gatehelp. apply node equation at node a Va − 10 + Va + Va = 2 1 4 4 6Va − 10 = 8 Va = 3 Volt Ib = 0 − 3 + 10 − 3 4 4 Ib = 10 − 6 = 1 amp 4 so current Hence (C) is correct option.

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**

Chap 4 Analog Circuits

**11Va = V0 Va = V0 11 So V0 = 3V0 − 4 11 8V0 =− 4 11 V0 =− 5.5 Volts Hence (D) is correct option.
**

SOL 4.128

Circuit with diode forward resistance looks

So the DC current will IDC = Vm π (R f + RL)

**Hence (B) is correct option.
**

SOL 4.129

For the positive half cycle of input diode D1 will conduct & D2 will be off. In negative half cycle of input D1 will be off & D2 conduct so output voltage wave from across resistor (10 kΩ) is –

**Ammeter will read rms value of current so I rms = Vm (half wave rectifier) πR =
**

Page 266

4 = 0.4 mA π (10 kΩ) π

**Hence (D) is correct option. GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia
**

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Chap 4 Analog Circuits

SOL 4.130

In given circuit positive feedback is applied in the op-amp., so it works as a Schmitt trigger. Hence (D) is correct option.

SOL 4.131

Gain with out feedback factor is given by V0 = kVi after connecting feedback impedance Z

given input impedance is very large, so after connecting Z we have Ii = Vi − V0 V0 = kVi Z Ii = Vi − kVi Z input impedance Zin = Vi = Z Ii (1 − k) Hence (D) is correct option

SOL 4.132

**Hence (A) is correct option.
**

SOL 4.133

For the circuit, In balanced condition It will oscillated at a frequency 1 ω= 1 = = 105 rad/ sec −3 −6 LC 10 # 10 # .01 # 10 In this condition R1 = R 3 R2 R4 5 =R 100 1 R = 20 kΩ = 2 # 10 4 Ω Hence (A) is correct option.

Page 267

**GATE Previous Year Solved Paper By RK Kanodia & Ashish Murolia
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Chap 4 Analog Circuits

SOL 4.134

V0 kept constant at so current in 50 Ω resistor

V0 = 6 volt I = 9−6 50 Ω

I = 60 m amp Maximum allowed power dissipation in zener PZ = 300 mW Maximum current allowed in zener PZ = VZ (IZ ) max = 300 # 10−3 & = 6 (IZ ) max = 300 # 10−3 & = (IZ ) max = 50 m amp Given knee current or minimum current in zener (IZ ) min = 5 m amp In given circuit I = IZ + I L I L = I − IZ (IL) min = I − (IZ ) max = (60 − 50) m amp = 10 m amp (IL) max = I − (IZ ) min = (60 − 5) = 55 m amp Hence (C) is correct option.

***********

Page 268

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