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Dept. of Electronics and Communications Engg. CITY ENGINEERING COLLEGE BANGALORE – 62.

Manual Prepared by: Mr. Vishvakiran RC, Asst. Prof., CEC

Logic Design Lab

2013

10ESL38

TABLE OF CONTENTS

Experiments

IC Pin Configurations 1. 2. 3. Boolean Expression realization using Logic gates Half/Full Adder and Subtractor a. Parallel Adder/ Subtractor b. BCD to Excess-3 and Vice-versa 4. 5. 6. 7. 8. 9. Binary to Gray Conversion and vice versa MUX/DEMUX for arithmetic circuits Comparators Decoder Chip for LED Display Priority Encoder Flip-Flop verification

Page No.

2 4 7 10 14 16 21 27 31 33 35 38 50 55 57 59 60

10. Counters 11. Shift Registers 12. Ring Counter/ Johnson Counter 13. Sequence Generator Logic Design Lab Syllabus – 10ESL38 Possible Viva Questions

3rdSem, E&C Dept.

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Logic Design Lab

2013

10ESL38

**IC Pin configurations
**

Inverter (NOT Gate) - 7404LS 2-Input AND Gate - 7408LS

2-Input OR Gate - 7432LS

2-Input NAND Gate - 7400LS

2-Input NOR Gate - 7402LS

2-Input EX-OR Gate - 7486LS

3-Input NAND Gate - 7410LS

4-bit Binary Full Adder74LS83

3rdSem, E&C Dept.

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Logic Design Lab 2013 10ESL38 Dual 4-Input NAND Gate . E&C Dept.7495 Synchronous Up/Down Counter– 74192 Decimal scalar .7485 Decoders/Demultiplexer 74139 Shift Register . 3 VK .7420LS Dual 4-input Multiplexer74153 4-Bit Magnitude Comparator .7490 DualJKFlip-flop– 7476 3rdSem.

Components Required: - IC 7408 (AND). E&C Dept. Construct a truth table for the given problem. Simplify the given Boolean expression manually using the Karnaugh Map. Apply the different combinations of input according to the truth tables. apply inputs according to the truth table and verify the results. Convert the AND-OR logic into NAND-NAND and NOR-NOR logic. 9. 3. Draw a Karnaugh Map corresponding to the given truth table. IC 7402 (NOR). 1 BOOLEAN EXPRESSION REALIZATION USING LOGIC GATES Aim: – To Simplify and Realize Boolean expressions using logic gates/Universal gates. Verify that the results are correct.IC 7486 (EX-OR) Procedure – 1. 10. 13. 8. 6. 12. IC 7404 (NOT). A: Implementation Using Logic Gates 5. 3rdSem. and then using only NOR gates. Realize the simplified expression using logic gates. Make connections as per the logic gate diagram. 7. 4.IC 7400 (NAND). Implement the simplified Boolean expressions using only NAND gates. Verify that the gates are working. Implementation Using Universal Gates 11. 4 VK . Connect VCC and ground as shown in the pin diagram. B. check them against the truth tables.Logic Design Lab 2013 10ESL38 Experiment No. 2. IC 7432 (OR). Connect the circuits according to the circuit diagrams. Check the output readings for the given circuits.

C.D)=B(C+D) 3rdSem.D)=BC+BD POS form Y=f(A.Logic Design Lab 2013 10ESL38 Given Problem: Truth Table: A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 Switching Expression: ∑ π Karnaugh Map Simplification: K-Map for SOP CD AB 00 01 11 10 BD 00 01 1 1 11 1 1 10 1 1 BC C+D AB 00 01 11 10 CD 00 0 0 0 0 01 0 11 0 10 0 B 0 0 0 K-Map for POS Simplified Boolean Expression: SOP form Y=f(A.C. 5 VK .B. E&C Dept.B.

6 VK . E&C Dept.Logic Design Lab 2013 10ESL38 Expression Realization using Basic Gates: C B D 1 7408 2 4 7408 5 3 1 7432 2 6 3 Y=BC+BD B C D 1 1 7432 2 7408 3 2 3 Y=B(C+D) Realization using only NAND gates: Realization using only NOR gates: 2 1 5 7402 6 8 7402 9 10 C B D 1 7400 2 4 7400 5 3 9 7400 6 10 8 B 7402 3 4 Y=B(C+D) Y=BC+BD C D Realization using only NOR gates: C B D 2 7402 3 5 7402 6 8 7402 9 10 1 11 7402 12 4 2 7402' 3 1 13 5 7402' 6 8 7402' 9 4 10 Y=BC+BD Realization using only NAND gates: B C D 1 7400 2 4 7400 5 10 6 3 9 7400 8 11 7400 12 13 1 7400' 2 3 Y=B(C+D) 3rdSem.

Verify that the sum/difference and carry/borrow bits are according to the expected values. Switch on the VCC power supply and apply the various combinations of the inputs according to the respective truth tables. 4. IC 7404. etc. 2.Logic Design Lab 2013 10ESL38 Experiment No. on the trainer kit. Repeat the procedure for the full adder circuit. 3. Verify that the outputs are according to the expected results. 6. 3rdSem. Verify that the gates are working. the half subtractor and full subtractor circuits. 5. 2 HALF/FULL ADDER AND HALF/FULL SUBTRACTOR Aim: – To realize half/full adder and half/full subtractor using Logic gates Components Required: - IC 7408. Procedure: - 1. 7. IC 7486. E&C Dept. IC 7432. Make the connections as per the circuit diagram for the half adder circuit. Note down the output readings for the half adder circuit for the corresponding combination of inputs. 7 VK .

E&C Dept. Half Adder using Logic Gates: Half Adder Using Basic Gates A B 1 7486 2 1 7408 2 3 A 0 B 0 1 0 1 S 0 1 1 0 C 0 0 0 1 3 0 1 1 B. 8 VK .Logic Design Lab 2013 10ESL38 A. Full Adder Using Logic Gates Full Adder Using Basic Gates A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cn-1 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 C 0 0 0 1 0 1 1 1 3rdSem.

Half Subtractor Using Logic Gates Half Subtractor Using Basic Gates A 0 0 1 1 B 0 1 0 1 D 0 1 1 0 Bo 0 1 0 0 D.Logic Design Lab 2013 10ESL38 C. E&C Dept. Full Subtractor Using Logic Gates Full Subtractor Using Basic Gates A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cn-1 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 B 0 1 1 1 0 0 0 1 3rdSem. 9 VK .

Connect one set of inputs from A1 to A4 pins and the other set from B1 to B4. Verify that the outputs match with the expected results. In order to Perform Addition take S=0. IC 7486. 2.Logic Design Lab 2013 10ESL38 Experiment No. etc. 7. 3 PARALLEL ADDER AND SUBTRACTOR USING 7483 Aim: –i. 10 VK . on the IC 7483. Procedure: 1. To realize Parallel Adder and Subtractor Circuits using IC 7483 ii. 4. Check the outputs and note them down in the table for the corresponding inputs. 5. E&C Dept. 6. Apply the B input through XOR gates (essentially taking complement of B). Apply the inputs to the adder/ subtractor circuits as shown in the truth tables.Connect the pins from S1 to S4 to output terminals. In order to implement the IC 7483 as a subtractor. IC 7483 Pin Diagram 7483 3rdSem. 8. Take S=1. Short S. 3.C0 to XOR gate 1 input and other input take from C4 and obtain the Output Carry Cout (Output Borrow Bout). BCD to Excess-3 Code conversion and Vice Versa using IC7483 Components Required: - IC 7483.

IC 7483 as a Parallel Adder Circuit Diagram: VCC A4 A3 1 3 8 10 16 4 5 14 C4 2 1 Output Carry 7486' S4 S3 S2 S1 3 Cout Input Data A A2 A1 1 15 2 6 9 B4 B3 B2 B1 7486 2 4 3 Data Output Input Data B 7486 5 9 6 7483 7486 10 12 8 7 11 13 C0 12 GND 7486 13 11 S=0 Truth Table:Input Data A A4 1 1 0 0 1 0 1 1 A3 0 0 0 0 0 1 1 0 A2 0 0 1 0 1 1 1 1 A1 0 0 0 1 0 0 0 0 4-BIT Parallel Adder Using 7483 where S=0 Input Data B B4 0 1 1 0 1 0 1 1 B3 0 0 0 1 0 0 1 1 B2 1 0 0 1 1 1 1 0 B1 0 0 0 1 1 1 1 1 Cout 0 1 0 0 1 0 1 1 S4 1 0 1 1 0 1 1 0 Addition S3 0 0 0 0 1 0 1 1 S2 1 0 1 0 0 0 0 1 S1 0 0 0 0 1 1 1 1 3rdSem. E&C Dept.Logic Design Lab 2013 10ESL38 A. 11 VK .

Bout = 0 for A>B.Logic Design Lab 2013 10ESL38 B. 12 VK . 3rdSem. IC 7483 as a Parallel Subtractor VCC Circuit Diagram: A4 A3 1 3 8 10 16 4 5 14 C4 Output Carry 1 7486' 2 3 Bout Input Data A A2 A1 1 15 2 6 9 S4 S3 S2 S1 B4 B3 B2 B1 7486 2 4 3 Data Output Input Data B 7486 5 9 6 7483 7486 10 12 8 7 11 13 C0 12 GND 7486 13 11 S=1 4-BIT Parallel Subtractor Using 7483 Where S=1 Truth Table: Subtraction Input Data A A4 A3 A2 A1 B4 Input Data B B3 B2 B1 Bout S4 S3 S2 S1 1 1 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 Note: Bout = 1 for A<B. E&C Dept.

A4 _ A3_ A2_ A1= _ B4 B3 B2 B1= 1001 1100→(1's complement) of +3 = 0011 +1 ←C0=1(S&C0 shorted) 2‟s Complement of B input = -B The end around carry is disregarded 1 0110 C0 C4 = Bout = 0 +6 4 bit subtraction operation using 7483 for A<Bhere S=1 _ A4 _ A3_ A2_ A1= B4 B3 B2 B1= 1110 0000→(1's complement) of +15=1111 2‟s Complement of B input = -B The end around carry is disregarded 0 1111 →(2's complement) of +1=0001 C0 C4 = Bout = 1 +1 ← C0=1(S&C0 shorted) -1 3rdSem. Consider the above Example A4 A_ 1001 and B4 B3 B2 B1= 0011 3A 2A 1= _ _ _ 1‟s Complement of B4 B3 B2 B1is B4 B3 B2 B1= 1100 .e. 4 bit subtraction operation using 7483 for A>B here S=1 A4 A3 A2 A1= 1001 B4 B3 B2 B1= 1101 (2's complement) of +3=0011 The end around carry is disregarded 1 0110 C0 C4 = Bout = 0 Difference. C0=1).Logic Design Lab 2013 10ESL38 Example 4bit adder operation using 7483 if control input S=0. 13 VK .S4 S3 S2 S1 =1111 and C0C4 = Cout.addition can be performed Ex:If ↓C0=0 A4 A3 A2 A1=1100 B4 B3 B2 B1=0011 then Sum. E&C Dept. S4 S3 S2 S1 = 0110 2's complement method of subtraction can be performed.if S=1(i.

A2. BCD TO EXCESS-3 CONVERTER VCC A3 A2 A1 A0 1 Note: S = 0 and B3.B0 = 0011 vary the BCD input at A3.B2. E&C Dept.B1.Logic Design Lab 2013 10ESL38 C. 14 VK . Circuit Diagram: 1 3 8 10 16 4 5 14 C4 E3 E2 E1 E0 X NC Input Data A 15 2 6 9 B3 = 0 7486 2 4 3 Data Output Input Data B B2 = 0 B1 = 1 B0 = 1 7486 5 9 6 7483 7486 10 12 8 7 11 13 C0 12 GND 7486 13 11 S=0 Truth Table : BCD to XCS3 using 7483 Consider Constant Value for B3B2B1B0 = 0011 and S=0 BCD Inputs A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 E3 0 0 0 0 0 1 1 1 1 1 X X X X X X Excess – 3 Outputs E2 0 1 1 1 1 0 0 0 0 1 X X X X X X E1 1 0 0 1 1 0 0 1 1 0 X X X X X X E0 1 0 1 0 1 0 1 0 1 0 X X X X X X 3rdSem.A1. BCD To Excess-3 And Vice-Versa Conversion Using 7483 Chip I.A0.

E&C Dept.B2. Circuit Diagram: A3 A2 A1 A0 1 VCC 1 3 8 10 16 4 5 14 C4 D C B A X NC Input Data A 15 2 6 9 B3 = 0 7486 2 4 3 Data Output Input Data B B2 = 0 B1 = 1 B0 = 1 7486 5 9 6 7483 7486 10 12 8 7 11 13 C0 12 GND 7486 13 11 S=1 Truth Table : XCS3 to BCD using 7483 Consider Constant Value for B3B2B1B0 = 0011 and S=1 Excess-3 Inputs E3 0 0 0 0 0 1 1 1 1 1 E2 0 1 1 1 1 0 0 0 0 1 E1 1 0 0 1 1 0 0 1 1 0 E0 1 0 1 0 1 0 1 0 1 0 A 0 0 0 0 0 0 0 0 1 1 BCD Outputs B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 3rdSem.Logic Design Lab 2013 10ESL38 II.A0(E0).A1(E1).B0 = 0011 vary the Excess-3 input at A3(E3).B1. 15 VK .A2(E2). EXCESS-3 to BCD CONVERTER Note: S=1 andB3.

Gray to Binary Converter using logic gates. etc. 4. 3.Logic Design Lab 2013 10ESL38 Experiment No. Check the outputs at the G3-G0 pins and note them down in the table for the corresponding inputs. ii. Make connections on the trainer kit as shown in the circuit diagram for the Binary to Gray converter. 5. Components Required: - IC 7486. 16 VK . E&C Dept. test and verify the working of a Grey to Binary Converter. 2. 6. Procedure: - 1. i. Verify that the outputs match with the expected results. 4 BINARY TO GRAY CONVERTER AND VICE VERSA Aim: – To realize:. Write the proper truth table for the given Binary to Gray converter. 8.Verify that the gates are working properly. 3rdSem. according to the truth table. 7. Binary to Gray Converter using logic gates. Repeat the procedure to design. Simplify the Karnaugh maps to get simplified Boolean Expressions. Apply the Binary inputs at B3-B0 pins. Draw Karnaugh maps for each bit of output.

17 VK . Truth Table: Binary Input B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Gray Code Output G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Karnaugh Maps: For G3: For G2: G3 = B3 3rdSem. Binary to Gray Converter.Logic Design Lab 2013 10ESL38 A. E&C Dept.

Logic Design Lab 2013 10ESL38 For G1: For G0: Circuit: 3rdSem. E&C Dept. 18 VK .

Logic Design Lab 2013 10ESL38 B. Gray to Binary Converter Truth Table Gray Code Input G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Binary Output B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Karnaugh Maps: For B3: For B2: B3 = G3 3rdSem. 19 VK . E&C Dept.

E&C Dept. 20 VK .Logic Design Lab 2013 10ESL38 For B1: For B0: Circuit: 3rdSem.

9. I1a. 7. I1b.etc. Verify outputs. the inputs are applied at Cn-1.The corresponding values of select input lines. 4. the inputs are applied at Cn-1. I3a)and(I0b. connections are made according to the circuit. The inputs are applied either to ‘A’ input or ‘B’ input. I2b and I3b) as shown. and thus the truth table is verified.In case of half adder using MUX.In case of Half Subtractor. and outputs are taken at Za (Difference) and Zb (Borrow). A and B (S1 and S0) are changed as per table and the output is taken at Za as sum and Zb as carry. I2a. IC 74139. the inputs A and B are varied. Based on the selection lines one of the inputs will be selected at the output. and Zb. 2. 5. 3. 6. 8. An and Bn according to the truth table.Logic Design Lab 2013 10ESL38 Experiment No. Making Ea and Eb zero andthe output is taken at Za. 10. IC 7400. In full subtractor using MUX. 1. EB is made low. EA is made low and if MUX ‘B’ has to be initialized. IC 7404. Inputs are applied at A and B as shown. IC 7420. 3rdSem. An and Bn according to the truth table. 5 MUX/DEMUX FOR ARITHMETIC CIRCUITS Aim: – To study IC 74153 and 74139 and to implement arithmetic circuits with them.In full adder using MUX. E&C Dept. 21 VK .If MUX ‘A’ has to be initialized. The corresponding outputs are taken at pin Za(Difference) and pin Zb(Borrow) and are verified according to the truth table. Components Required: Procedure – A.The Pin [16] is connected to + Vcc and Pin [8] is connected to ground.In this case. apply constant inputs at (I0a. The corresponding outputs are taken at Sn (pin Za) and Cn (pin Zb) and are verified according to the truth table. For MUX IC 74153 IC 74153.

22 VK . E&C Dept.Logic Design Lab 2013 10ESL38 Half Adder Using 74153 Half Subtractor using 74153 Truth Table: Inputs A 0 0 1 1 B 0 1 0 1 Half Adder Outputs Sum 0 1 1 0 Carry 0 0 0 1 Half Subtractor Outputs Diff 0 1 1 0 Borrow 0 1 0 0 Full Adder Using 74153 Full Subtractor using 74153 3rdSem.

8.Logic Design Lab 2013 10ESL38 Truth Tables for Full Adder/Subtractor using 74153 Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin/Bin 0 1 0 1 0 1 0 1 Full Adder Outputs S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1 Full Subtractor Outputs D 0 1 1 0 1 0 0 1 Bout 0 1 1 1 0 0 0 1 Procedure – B. The corresponding outputs are taken at Sum and Carry. 6. In case of Half Subtractor. E&C Dept. and thus the truth table is verified. 7. The inputs are applied either to ‘A’ input or ‘B’ input. 3rdSem. Verify outputs. Verify outputs. For DEMUX IC 74139 1. A and B (S1a and S0a) are changed as per table and the output is taken at Sum and Carry. and outputs are taken at Differenceand Borrow.Ea is set to 0. In full subtractor using DEMUX. 4. The Pin [16] is connected to + Vcc and Pin [8] is connected to ground. An and Bn according to the truth table. and are verified according to the truth table. The corresponding outputs are taken at Difference and Borrow as shown. Based on the selection lines one of the inputs will be selected at the set of outputs. In full adder using DEMUX. connections are made according to the circuit. Inputs are applied at A and B as shown. 2. 3. the corresponding values of select input lines. the inputs are applied at Cn-1. If DEMUX ‘A’ has to be initialized. 23 VK . EA is made low and if DEMUX ‘B’ has to be initialized. An and Bn according to the truth table. In case of half adder using DEMUX. the inputs are applied at Cn-1. and are verified according to the truth table. EB is made low. 5.

24 VK .Logic Design Lab 2013 10ESL38 Half Adder Using 74139 Half Subtractor Using 74139 Truth Tables: Inputs A 0 0 1 1 B 0 1 0 1 Half Adder Outputs Sum 0 1 1 0 Carry 0 0 0 1 Half Subtractor Outputs Diff 0 1 1 0 Borrow 0 1 0 0 3rdSem. E&C Dept.

E&C Dept. 25 VK .Logic Design Lab 2013 10ESL38 Full Adder Using 74139 Full Subtractor Using 74139 3rdSem.

26 VK .Logic Design Lab 2013 10ESL38 Truth Tables: Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin/Bin 0 1 0 1 0 1 0 1 Full Adder Outputs S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1 Full Subtractor Outputs D 0 1 1 0 1 0 0 1 Bout 0 1 1 1 0 0 0 1 3rdSem. E&C Dept.

and to study the working of IC 7485. 3. Study of IC 7485: 1. IC 7486. making sure that the MSB and LSB is correctly connected.Logic Design Lab 2013 10ESL38 Experiment No. A.Check the outputs and verify that they are according to the truth tables. IC 7404.Make the connections as per the respective circuit diagrams.Apply the two inputs as shown.Verify the working of the logic gates.Switch on Vcc. 2. Components Required: Procedure – A. IC 7485. Connect pin 16 to Vcc and pin 8 to GND for the ICs. pin 4 (A>B). etc. 6 ONE/TWO BITCOMPARATOR AND IC 7485 Aim: – To verify the truth tables for one bit and two bit comparators after constructing them with basic logic gates. E&C Dept. 2. IC 7432. Two-Bit Comparator: 3rdSem. 4. Comparators Using Logic Gates: 1. pin 3 (A=B) pins and are verified as being according to the truth table. IC 7408. 4.Write the truth table for an4-bit comparator.Apply the inputs as per the truth tables. 5. 3. B. 27 VK Outputs A>B 0 0 1 0 A=B 1 0 0 1 A<B 0 1 0 0 B 0 1 0 1 . Outputs are recorded at pin 2 (A<B). One-Bit Comparator: Circuit : Truth Table: 1bit Comparator Inputs A 0 0 1 1 B.

E&C Dept.Logic Design Lab 2013 10ESL38 Truth Table : 2bit Comparator A1 A0 B1 B0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 Karnaugh Maps: For A>B: For A<B For A=B 3rdSem. 28 VK .

E&C Dept.Logic Design Lab 2013 10ESL38 Circuit: C. 29 VK . 4-Bit comparator using IC 7485 Pin Diagram: 3rdSem.

Logic Design Lab 2013 10ESL38 Truth Table: 4bit Comparator Input A A3 0 0 1 0 0 1 0 1 A2 0 1 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 B3 0 0 1 0 1 1 0 1 Input B B2 0 0 0 1 0 0 1 1 B1 0 1 1 1 0 1 1 1 B0 1 1 0 0 0 1 0 0 A>B 0 1 0 0 0 1 0 1 Output A<B 1 0 0 1 1 0 0 0 A=B 0 0 1 0 0 0 1 0 3rdSem. 30 VK . E&C Dept.

7 DECODER CHIP FOR LED DISPLAY Aim: – Tostudy the use of a Decoder Chip (IC 7447) to drive a LED Display. and observe the Decimal outputs displayed on the 7-segment LCD Display. 3. 7-segment LED Display. Components required: - IC 7447. Test and verify that all the segments of the LED Display are working. Verify that the outputs match the expected results in the truth tables. 31 VK . 6. Give the different BCD inputs according to the truth table. Procedure: - 1. 2.Logic Design Lab 2013 10ESL38 Experiment No. 4. 5. Connect Pin 16 to Vcc and Pin 8 to GND. etc. Connect the input pinsof the 7-segment LED Display to the respective pins (A3-A0) of the 7447 BCD to 7-Segment decoder driver chip. IC 7447 Pin Diagram 3rdSem. E&C Dept. Make the circuit connections as shown in the circuit diagram.

E&C Dept. 32 VK .Logic Design Lab 2013 10ESL38 Circuit Diagram: Output Table: BCD inputs segment outputs display D C B A a b c d e f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 7-segment LED Display Schematic 3rdSem.

Logic Design Lab 2013 10ESL38 Experiment No. B. C. 5. Components Required: - IC 74147. Observe the outputs on the LED indicators. Provide the inputs to the encoder chip as shown in the truth table. 8 PRIORITY ENCODER Aim: – Tostudy the use of a 10-line-to-4-Line Priority Encoder Chip (IC 74147). 3. Connect the pins designated Inputs 1 through 9. IC 74147 Pin Diagram 3rdSem. 7. E&C Dept. to the input switches of the trainer kit. D to the LED indicators of the trainer kit. and note down the results for the respective inputs. 2. Connect Pin 16 of the IC to Vcc and Pin 8 to GND. etc. 6. 33 VK . Procedure: - 1. Connect the Output pins designated A. Make the connections as shown in the circuit diagram. 4. Verify that the outputs are as shown in the truth table.

E&C Dept.Logic Design Lab 2013 10ESL38 Truth Table: 1 1 0 X X X X X X X X 2 1 1 0 X X X X X X X 3 1 1 1 0 X X X X X X Decimal Input 4 5 6 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 X 0 1 X X 0 X X X X X X X X X 7 1 1 1 1 1 1 1 0 X X 8 1 1 1 1 1 1 1 1 0 X 9 1 1 1 1 1 1 1 1 1 0 BCD Output D C B A 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 Decimal Value 0 1 2 3 4 5 6 7 8 9 3rdSem. 34 VK .

Procedure: 1. A.Logic Design Lab 2013 10ESL38 Experiment No. 2. verify that they match that of the respective truth tables. 3. IC 7400. etc. Make the connections as shown in the respective circuit diagrams. Apply inputs as shown in the respective truth tables. Clear 1 0 1 1 1 1 J X X 0 0 1 1 K X X 0 1 0 1 35 Clock X X 1 0 0 1 Status Set Reset No Change 0 1 1 0 Reset Set Toggle VK . Components Required: - IC 7410. Check the outputs of the circuits. J-K Master-Slave Flip-Flop Circuit: Truth Table : Preset 0 1 1 1 1 1 3rdSem. E&C Dept. T-type and DType Flip-Flops. for each of the flip-flop circuits. 9 STUDY OF FLIP-FLOPS Aim: – To study and verify the truth tables for J-K Master Slave Flip Flop.

Logic Design Lab 2013 10ESL38 B. T-Type Flip-Flop Circuit: Truth Table : Preset 1 1 Clear 1 1 T 0 1 Clock 3rdSem. 36 VK . E&C Dept.

D-Type Flip-Flop Circuit: Truth Table: Preset 1 1 Clear 1 1 D 0 1 Clock 0 1 1 0 3rdSem. E&C Dept. 37 VK .Logic Design Lab 2013 10ESL38 C.

Logic Design Lab

2013

10ESL38

Experiment No. 10

STUDY OF COUNTERS

Aim: – Realization of 3-bit counters as a sequential circuit and Mod-N counter Design (7476, 7490, 74192, 74193)

Components Required: -

IC 7476, IC 7490, IC 74192, IC 74193, IC 7400, IC 7408, IC 7416, IC 7432, etc.

Procedure: A. Counter Circuits using IC 7476 1. Make the connections as shown in the respective circuit diagrams. 2. Clock inputs are applied one by one at the clock I/P, and the outputs are observed at QA, QB and QC pins of the 7476 ICs. 3. Verify that the circuit outputs match those indicated by the truth tables. B. Study of Counters IC 74192, IC 74193 1. Connections are made as shown in the respective circuit diagrams, except for the connection from the output of the NAND gate to the load input. 2. The data (0011) = 3 is made available at the data input pins designated A, B, C and D respectively. 3. The Load pin is made LOW so that the data 0011 appears at QD, QC, QB and QA respectively. 4. Now, the output of the NAND gate is connected to the Load input pin. 5. Clock pulses are applied to the “Count Up” pin, and truth table is verified for that condition. 6. Next, the data (1100) =12 (for 12 to 5 counter) is applied at A, B, C and D and the same procedure as explained above, is performed. 7. IC 74192 and IC 74193 have the same pin configurations. 74192 can be configured to count between 0 and 9 in either direction. Starting value can be any number between 0 and 9.

3rdSem, E&C Dept.

38

VK

Logic Design Lab

2013

10ESL38

A. 3-bit Asynchronous Up Counter

Circuit Diagram:

Timing Diagram:

**Truth Table: Clock 0 1 2 3 4 5 6 7 8 9
**

3rdSem, E&C Dept.

QC 0 0 0 0 1 1 1 1 0 0

39

QB 0 0 1 1 0 0 1 1 0 0

QA 0 1 0 1 0 1 0 1 0 1

VK

Logic Design Lab

2013

10ESL38

B. 3-bit Asynchronous Down Counter

Circuit Diagram:

Timing Diagram:

**Truth Table: Clock 0 1 2 3 4 5 6 7 8 9
**

3rdSem, E&C Dept.

QC 1 1 1 1 0 0 0 0 1 1

40

QB 1 1 0 0 1 1 0 0 1 1

QA 1 0 1 0 1 0 1 0 1 0

VK

Mod-5 Asynchronous Counter Circuit: Timing Diagram: Truth Table: Clock 0 1 2 3 4 5 QC 0 0 0 0 1 0 QB 0 0 1 1 0 0 QA 0 1 0 1 0 0 3rdSem. 41 VK .Logic Design Lab 2013 10ESL38 C. E&C Dept.

Mod-3 Asynchronous Counter Circuit: Timing Diagram: Truth Table: Clock 0 1 2 3 4 5 QC 0 0 0 0 0 0 QB 0 0 1 0 0 1 QA 0 1 0 0 1 0 3rdSem.Logic Design Lab 2013 10ESL38 D. E&C Dept. 42 VK .

3-bit Synchronous Counter Circuit: Timing Diagram: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 QC 0 0 0 0 1 1 1 1 0 0 QB 0 0 1 1 0 0 1 1 0 0 QA 0 1 0 1 0 1 0 1 0 1 3rdSem. E&C Dept. 43 VK .Logic Design Lab 2013 10ESL38 E.

QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 44 QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VK .Logic Design Lab 2013 10ESL38 F. E&C Dept. 4-bit Ripple Counter Circuit: Truth Table: CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3rdSem.

Logic Design Lab 2013 10ESL38 G. Mod-10 Ripple Counter Circuit: Truth Table CLK 0 1 2 3 4 5 6 7 8 9 10 QD 0 0 0 0 0 0 0 0 1 1 0 QC 0 0 0 0 1 1 1 1 0 0 0 QB 0 0 1 1 0 0 1 1 0 0 0 QA 0 1 0 1 0 1 0 1 0 1 0 3rdSem. E&C Dept. 45 VK .

Logic Design Lab 2013 10ESL38 H. Decade Counter (using IC 7490) Circuit: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 10 QD 0 0 0 0 0 0 0 0 1 1 0 QC 0 0 0 0 1 1 1 1 0 0 0 QB 0 0 1 1 0 0 1 1 0 0 0 QA 0 1 0 1 0 1 0 1 0 1 0 3rdSem. E&C Dept. 46 VK .

E&C Dept. Mod-8 Counter (Using IC 7490) Circuit: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 QD 0 0 0 0 0 0 0 0 0 0 QC 0 0 0 0 1 1 1 1 0 0 QB 0 0 1 1 0 0 1 1 0 0 QA 0 1 0 1 0 1 0 1 0 1 3rdSem.Logic Design Lab 2013 10ESL38 I. 47 VK .

Logic Design Lab 2013 10ESL38 J. 48 VK . Presettable counter using IC 74192/IC 74193 to count up from 3 to 8 Circuit: Truth Table: Clock 0 1 2 3 4 5 6 7 QD 0 0 0 0 0 1 0 0 QC 0 1 1 1 1 0 0 1 QB 1 0 0 1 1 0 1 0 QA 1 0 1 0 1 0 1 0 Decimal 3 4 5 6 7 8 3 4 3rdSem. E&C Dept.

Logic Design Lab 2013 10ESL38 K. Presettable counter using IC 74192/74193 to count down from 5 to 12 Circuit: Implementation of 4-Input OR gate: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 QD 0 0 0 1 1 1 1 1 0 0 QC 1 1 1 0 0 0 0 1 1 1 QB 0 1 1 0 0 1 1 0 0 1 QA 1 0 1 0 1 0 1 0 1 0 Decimal 5 6 7 8 9 10 11 12 5 6 3rdSem. 49 VK . E&C Dept.

Apply the first data at pin 1 (SD1) and apply one clock pulse. we notice that all 4 bits are available at the parallel output pins QA through QD. and connect clock input to Pin 8 (Clk 2). Apply a clock pulse. 7. At the end of the 4th clock pulse. QC. Serial In-Parallel Out (Left Shift): 1. QB. apply the second data at SD1. 2. Components Required: Procedure: A. 4. Enter more bits to see there is a right shifting of bits with each succeeding clock pulse. we notice that all 4 bits are available at the parallel output pins QA (MSB). 6. Make the connections as shown in the respective circuit diagram. until all bits are entered one by one. Enter more bits to see there is a left shifting of bits with each succeeding clock pulse. 5. Apply the first data at pin 5 (D) and apply one clock pulse. 7. Now. We now observe that the earlier data is shifted from QD to QC. Shift right. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode M) is set to LOW. We observe that this data appears at pin 10 (QD). Make the connections as shown in the respective circuit diagram. B. and the realization of Shift left. 3. Serial In-Parallel Out (Right Shift): 1. . and the new data appears at QD. Make sure the 7495 is operating in Parallel mode by ensuring Pin 6 (Mode M) is set to HIGH. and the new data appears at QA. and connect clock input to Pin 9 (Clk 1). 5. 4. SISO. E&C Dept. 6. PISO. Repeat the earlier step to enter data. 3. We now observe that the earlier data is shifted from QA to QB. At the end of the 4th clock pulse. 50 VK IC 7495. Apply a clock pulse.Logic Design Lab 2013 10ESL38 Experiment No. We observe that this data appears at pin 13 (QA). Now. etc. 3rdSem. apply the second data at D. 2. 11 STUDY OF SHIFT REGISTERS Aim: – To study IC 74S95. until all bits are entered one by one. SIPO. PIPO operations using the same. Repeat the earlier step to enter data. QD (LSB).

B. Apply one clock pulse at Clk 2 (Pin 8). and apply clock pulses one by one. 4. Set Mode Control M to HIGH to enable Parallel transfer. the first data bit. C. QB. one by one. 3. D. B. E&C Dept. 5. D appears at the parallel output pins QA. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode) is set to LOW. 6. Serial In-Serial Out Mode: 1. QDrespectively. with a clock pulse in between each pair of inputs to load the bits into the IC. 2. QC. The data applied at the parallel input pins A. 4. 51 VK . to get the second data bit „d1‟ at QD. Connections are made as shown in the SISO circuit diagram. B. Observe the data coming out in a serial mode at QD. At the end of the 4th clock pulse. 5. QB. E. D (pins 2 through 5). Thus we see the IC 7495 operating in SISO mode. 2. Parallel In-Serial Out Mode: 1. C. The 4 bits are applied at the Serial Input pin (Pin 1). 4. D will appear at the parallel output pins QA. with serially applied inputs appearing as serial outputs. C. apply one clock pulse. 3rdSem. Keeping the mode control M on HIGH. „d0‟ appears at the output pin QD. and connect clock input to Clk 1(Pin 9). Now set the Mode Control M to LOW. QDrespectively. B. Apply the 4 data bits as input to pins A. Apply another clock pulse. Parallel In-Parallel Out Mode: 1. QC. We observe now that the IC operates in PISO mode with parallel inputs being transferred to the output side serially. Connections are made as shown in the PISO circuit diagram. 3. 2. and so on. Note that the 4 bit data at parallel inputs A. 3. C. Applying yet another clock pulse gets the third data bit „d2‟ at QD. Now apply the 4-bit data at the parallel input pins A.Logic Design Lab 2013 10ESL38 C. Connections are made as shown in the PIPO mode circuit diagram. D. 5.

E&C Dept.Logic Design Lab 2013 10ESL38 IC 7495 Pin Diagram: A. SIPO MODE (Right Shift) Circuit: Truth Table: Clock 1 2 3 4 Serial I/P 1 0 1 1 QA 1 0 1 1 QB X 1 0 1 QC X X 1 0 QD X X X 1 3rdSem. SIPO Mode (Left Shift) Circuit: Truth Table: Clock 1 1 Serial I/P 1 0 1 1 QA X X X 1 QB X X 1 0 QC X 1 0 1 QD 1 0 1 1 2 3 4 B. 52 VK .

PISO Mode Circuit: Truth Table: Mode Clk Parallel I/P A Parallel O/P B C D QA QB QC QD 0 1 1 1 X X X 0 1 X X 1 0 1 X 1 1 0 1 1 0 0 0 1 2 3 4 1 X X X X X X X X X X X X 3rdSem.Logic Design Lab 2013 10ESL38 C. SISO Mode Circuit: Truth Table: Clock 1 2 3 4 5 6 7 Serial I/P d0=0 d1=1 d2=1 d3=1 X X X QA QB Q C 0 1 1 1 X X X X 0 1 1 1 X X X X 0 1 1 1 X QD X X X 0=d0 1=d1 1=d2 1=d3 D. 53 VK . E&C Dept.

PIPO Mode Circuit: Truth Table: Clk Parallel I/P Parallel O/P A B C D QA QB QC QD 1 1 0 1 1 1 0 1 1 3rdSem. 54 VK . E&C Dept.Logic Design Lab 2013 10ESL38 E.

record the observations and verify that they match the expected outputs from the truth table. Repeat the same procedure as above for the Johnson Counter circuit and verify its operation. Make the connections as shown in the respective circuit diagram for the Ring Counter.Logic Design Lab 2013 10ESL38 Experiment No. B. 6. Select Mode = LOW (0) to switch to serial mode and apply clock pulses. 2. Keep Select Mode = HIGH (1) and apply one clock pulse. D pins respectively. 55 VK . E&C Dept. C. 4. IC 7404. Procedure: 1. Observe the output after each clock pulse. 12 RING COUNTER /JOHNSON COUNTER Aim: – To design and study the operation of a ring counter and a Johnson Counter. Apply an initial input (1000) at the A. Ring Counter Circuit: Truth Table: Mode Clock QA QB QC QD 1 0 0 0 0 0 1 2 3 4 5 6 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 3rdSem. etc. 3. Components Required: - IC 7495. 5. Next. A.

Logic Design Lab 2013 10ESL38 B. 56 VK . Johnson Counter Circuit: Truth Table: Mode Clock QA QB QC QD 1 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 1 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 3rdSem. E&C Dept.

and so on.Logic Design Lab 2013 10ESL38 Experiment No. in order to satisfy the condition . 2. 13 SEQUENCE GENERATOR Aim: – To design and study the operation of a Sequence Generator. it is necessary to use at least„N‟ number of Flip-flops. and Karnaugh maps are drawn in order to obtain a simplified Boolean expression for the circuit. 5. In order to generate a sequence of length „S‟. IC 7486. Components Required: Theory: - IC 7495. we need to use 5 flip-flops. Circuit: 3rdSem. E&C Dept. N = 4 Note: There is no guarantee that the given sequence can be generated by 4 flip-flops. Connections are made as shown in the circuit diagram. 3. The functioning of the circuit as a sequence generator is verified. Procedure:1. 57 VK . Clock pulses are applied at CLK 1 and the output values are noted. and checked against the expected values from the truth table. If the sequence is not realizable by 4 flip-flops. Truth table is constructed for the given sequence. 4. The given sequence length S = 15 Therefore. and clock pulses are fed through Clk 1 (pin 9). etc. Mode M is set to LOW (0).

58 VK .Logic Design Lab 2013 10ESL38 Truth Table: Karnaugh Map: Map Value 15 7 3 1 8 4 2 9 12 6 11 5 10 13 14 O/p Clock QA QB QC QD D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 3rdSem. E&C Dept.

LabView can be used for designing the gates along with the above. E&C Dept. 74139 for arithmetic circuits and code converter. Realization of Binary to Gray code conversion and vice versa 5.scribd.74193). Wiring and testing of Sequence generator.com/doc/62491691/Logic-Design-Lab-Manual-10ESL38-3rd-sem-2011 3rdSem. 7. 6. 2. Shift left. 59 VK . Simplification.Logic Design Lab 2013 10ESL38 Syllabus LOGIC DESIGN LAB (Common to EC/TC/EE/IT/BM/ML) Sub Code :10ESL38 Hrs/ Week : 03 Total Hrs. 10. http://www. SIPO. Use of Decoder chip to drive LED display. Realization of Half/Full adder and Half/Full Subtractors using logic gates. 11. PISO. 3. Use of IC 74147 as Priority encoder. 8. 74192. SISO. Truth table verification of Flip-Flops: (i) (ii) (iii) JK Master slave T type D type. Wiring and testing Ring counter/Johnson counter. Realization of 3 bit counters as a sequential circuit and MOD – N counter design (7476. MUX/DEMUX – use of 74153.: IA Marks : 25 Exam Hours : 03 Exam Marks : 50 NOTE: Use discrete components to test and verify the logic gates. 4. 1. Shift right. Realization of One/Two bit comparator and study of 7485 magnitude comparator. PIPO operations using 74S95. (i)Realization of parallel adder/Subtractors using 7483 chip (ii) BCD to Excess-3 code conversion and vice versausing 7483 chip. 9. realization of Boolean expressions using logic gates/Universal gates. 13. 7490. 12.

What are basic gates? 3. Give the block diagram of parallel adders 24. Why NAND and NOR gates are called as universal gates. What does LS stand for. Define LSI. 47. What is LCD and LED. What is a shift register? 40. 45. What is modulus of a number? 39. What is a truth table? 12. 60 VK . Define a logic gate. Explain AND and OR gate using diodes 8. What is an up counter and down counter? 43. Explain the working of 7483 adder chip. What is a priority encoder? 34. What is a half adder? 13. Give the applications of mux and demux 30. Compare synchronous and asynchronous counters 37. Give the applications of combinational and sequential circuits 17. MSI . How do you eliminate race around condition 23. 4. 49. What is common cathode and common anode LED? 44. Explain how it can be used as EX-3 to BCD conversion and vice versa 27. What is minterm and maxterm? 26. Differentiate between flip flop and latch 21. What is a Demultiplexer? 29. Explain how a shift register can be used as ring and johnson counter 41. in 74LS00? 48. Give the block diagram of sequential circuits 18. Give examples 16. Explain how transistor can be used as NOT gate 7. List the applications of EX-OR and EX~NOR gates 11. Mention the different logic families.Logic Design Lab 2013 10ESL38 Possible Viva Questions 1. List the types of LCD's and LED's. What is a encoder and decoder 31. Differentiate between combinational and sequential circuits. What is an excitation table/functional table 20. Give the applications of johnson and ring counters 42. 46. What is a code converter? 35. Realize logic gates using NAND and NOR gates only 9. State De-morgans theorem 5. What are counters? Give their applications 36. Which is the fastest logic? 3rdSem. E&C Dept. Define multiplexer/ data selector 28. What is race around condition? 22. What is a full adder? 15. Differentiate between half adder and half subtractor 14. Give examples for SOP and POS 6. 2. What is a static and a dynamic display. Compare mux and encoder 32. What are BCD Give their applications or uses 25. Define flip flop 19. What is a ripple counter? 38. SSI 10. Compare demux and decoder 33.

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