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RS-232 TRANSMITTER AND RECEIVER USING FPGA WITH VHDL CODE

Internal Guide by:Prof. Hardik .H .Patel Assistance professor, Department of EC, SRPEC, Unjha.

By:Ankita Patel(090780111007) Kinjal Prajapati(100783111004) Vidhi Patel(090780111001) 8th Semester, B.E (EC), SRPEC, Dabhi Unjha

External Guide by:Mr. Elesh Patel

CONTENTS
AIM MOTIVATION OVERVIEW OF PROJECT COMPONENT SPECIFICATION STATE DIAGRAM SIMULATION /RESULTS WORK PLAN CONCLUSION FUTURE WORK REFERENCES
RS-232 TX/RX USING FPGA WITH VHDL CODE

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AIM
Aim of this project is to transfer data from PC to FPGA and FPGA to PC using serial communication. For this Serial communication we are using RS-232 for interfacing of PC and FPGA and Using Code of data transfer with VHDL language we Transfer data between FPGA and PC. Hyper terminal is used for transferring data and for giving input for receiver section and showing output on hyper terminal for transmitting section.

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RS-232 TX/RX USING FPGA WITH VHDL CODE

MOTIVATION
Many more Data acquisition system are available in the market Based on DSP ,microcontroller and FPGA etcBut the Faster response, low Power Consumption, less time consuming of FPGA we are going though FPGA. Reason for Choosing FPGA based System: Faster Response. Low Power Consumption. Less Time Consuming. Data Security. Accuracy.
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RS-232 TX/RX USING FPGA WITH VHDL CODE

OVERVIEW OF PROJECT

Fig:1 general block diagram of our project

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RS-232 TX/RX USING FPGA WITH VHDL CODE

ALTERA MODEL[1]

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RS-232 TX/RX USING FPGA WITH VHDL CODE

BLOCK DIAGRAM OF RECEIVER

RX

RECIVER RECEIVR DATA DATA BLOCK BLOCK

8 BIT

DATA R (7 DOWN T0 0)

RST

CLK

Fig:2 BLOCK DIAGRAM OF RECEIVER


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RS-232 TX/RX USING FPGA WITH VHDL CODE

BLOCK DIAGRAM OF TRANSMITTER

TX
8 BIT DATA_TX (7 DOWN T0 0)

TRANSMITTER DATA BLOCK

RST

CLK

Fig:3 BLOCK DIAGRAM OF TRANSMITTER


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RS-232 TX/RX USING FPGA WITH VHDL CODE

HYPER TERMINAL
This is a built in interface in windows which sends and receives data through the serial port.it has the option of sending through port COM1 and COM2 and also has flexible baud rate.

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RS-232 TX/RX USING FPGA WITH VHDL CODE

Fig:4 snap of hiper terminal


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COMPONENTS
Altera kit(FPGA) RS-232 Power Supply Cyclone QUARTUS II software PC

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SPECIFICATION OF ALTERA KIT


5volt external supply. 9600 baud rate. 27 MHZ/25 MHZ frequency.

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DECIDING THE CLOCK AND BAUDRATE


In FPGA clock in not standard. That is ,in FPGA clock is use by 10MHZ,27MHZ,50MHZ etc.. Baud rate that we are using is 9600. Also there is miss match between clock and baudrate so calculate clock by:
Frequency/baud rate= new clock genereted that is used in FPGA

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DECIDING THE CLOCK AND BAUDRATE


Here, 27MHZ/9600=2812 cycle so,there is a 1406 clock cycle for upper cycle and similarly 1406 clock cycle for lower cycle. In this way clock and baud rate is decided

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STATE DIAGRAM

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STATE DIGRAM OF RECEIVER


RST Data_r(7)<=rx 0 S8 1 1 IDEAL S0 1 S2 S7 Data_r(6)<=rx Data_r(4)<=rx S6 Data_r(5)<=rx
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Fig:5 state diagram Data_r(0)<=rx 0 S1

Data_r(1)<=rx

S3 Data_r(2)<=rx S4 Data_r(3)<=rx
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S5

RS-232 TX/RX USING FPGA WITH VHDL CODE

STATE DIGRAM OF TRANSMITTER


1 RST 1 TX<=data_tx(6) S8 S2 S7 TX<=data_tx(5) S3 S6 TX<=data_tx(4)
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Fig:6 state diagram IDEAL S0 TX<=data_tx(0) 0 S1

TX<=data_tx(1)

TX<=data_tx(3)
S5 S4

TX<=data_tx(1)

TX<=data_tx(2)
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RS-232 TX/RX USING FPGA WITH VHDL CODE

SIMULATION/RESULT

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Design flow

Fig:7 design flow of simulation process[2]


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DESCRIPTION OF THE DESIGN FLOW


Design Entry. Synthesis. Functional Simulation. Fitting. Timing Analysis. Timing Simulation. Programming and Configuration.

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TESTING WITH HARDWARE

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Fig:8 Snap of result


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Fig:9 snap of result


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Fig:10 output waveform of the transmitter


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Fig:11 output waveform of the receiver


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WORK PLAN
Jul-12 Aug-12 Sep-12 Oct-12

Sr. No

Sr. No Selection of project (1) . Topic (2) . Introduction Detail study in project (3) . work To study the VHDL (4) . Language

W- WW-1 W-2 W-3 4 1 W-2 W-3 W-4 W-1 W-2 W-3 W-4 W-1 W-2 W-3 W-4

To study project (5) . by software


(6) . Programme practice
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WORK PLAN
Sr. No Sr. No (1) . Coding of receiver part (2) Implement receiver . code on altera kit (3) Coding of transmiter . part (4) Implement transmiter . part on altera kit Implement both code (5) on Xillinx spartan3 . code (6) Prepare a report and . presenatation
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Jan-13

Feb-13

Mar-13

Apr-13

W- WW-1 W-2 W-3 4 1 W-2 W-3 W-4 W-1 W-2 W-3 W-4 W-1 W-2 W-3 W-4

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CONCLUSION
The FPGA based Transmitter/Receiver data using serial communication are most of the high fidelity (hi-fi) are maintain using VHDL code design was successfully design by behavioral model. Here, we get particular output according input what we are given as and that output is unique for every input. So that we control many circuits by every unique output or we operate that many circuits by giving input.

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FUTURE WORK
We can also use this method, For transferring file and documents from one pc to another pc like one pc is data transmit to the FPGA and from FPGA to another pc. In the transmitter section, There is not stable output ,that means here we get continuous output on the hyper terminal. so we are trying to get the stable output or static output for transmitter section. In this session project was based on different code for TX/RX. So, code will be merged for TX and RX with help of logic loop.

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REFERENCES
[1] Cyclone II FPGA Starter Development Board Reference Manual [2]Stephen Brown and Jonathan Rose(for fpga)s Department of Electrical and Computer Engineering University of Toronto email: brown | jayar@eecg.toronto.edu

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THANK YOU

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