Pll

Phase detector

:
PD
K
Loop filter:
p
s
K
K
LPF
F
+
=
1
VCO:
s
K
VCO
F VCO PD
F VCO PD
data
clock
K K K
N
s
K K K
s H
1
) (
+
=
u
u
=
Phase Locked Loop (PLL) Design

by Akin Akturk and Zeynep Dilli
Figure 1: Basic PLL building blocks
Figure 2: Phase Frequency Detector and the Loop Filter
Figure 3: PD and Loop Filter responses to input transients
t
µ
t 2
74
2
A
I
K
pump
PDI
= =
Phase Detector Design
VDD NC
I
f
tot
D
OSC
=
Figure 4: The schematics of the VCO
Figure 5: Schematics of the Current Pumps
Voltage Controlled Oscillator
Figure 6: I-Vin for Current Pumps
50
100
150
200
250
0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3
Vin (V)
V
C
O
_
f

(
M
H
z
)
Figure 7: Vin-fosc Relation
(196 103)
(1.2 1.0)
VCO
MHz
K
V
÷
=
÷
Design Considerations for the VCO
Figure 8: The Schematics of the 10-Bit Input Counter
Ripple Carry Counter
15 . 0 2
125
87 . 1 , 5 . 0 , 5 ,
2 . 0
93
,
2
74
) (
) 1 (
) (
) (
1
1
) (
1
2
2
2 1
3
2 1
2 1 2 2 1
2 1 2 3
2 1
1
2 1 2 1
2
1
= ¬ = ¬ =
= ¬ =
= = O = = =
+ +
+
+
+
=
¬
+ +
+
=
+
=
u
u
=
ç e ç çe
e e
t
µ
RC
NC
K K
kHz
C NRC
K K
nF C nF C k R
V
MHz
K
A
K
C NRC
K K
NC
K K
s
C RC
C C
s s
C RC
sRC K K
s H
C C s C RC s
sRC
K
K K K
N
s
K K K
s H
n
VCO PDI
n
n
VCO PDI
n
VCO PDI
VCO PDI VCO PDI
VCO PDI
F
F VCO PDI
F VCO PDI
data
clock
PLL Building Blocks and Design Considerations Revisited
Figure 8: Overall PLL Schematics
Figure 10: Reference Clock and the Output of the Counter
Pspice Simulation Result I
Figure 11: Loop Filter and VCO Inputs
Pspice Simulation Result II
Figure 12: VCO Output at the Start and the End of the Simulation
Pspice Simulation Result III

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