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Hardware book

Hardware book

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Published by Sergey Sarmatov
Electronic reference guide
Electronic reference guide

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Published by: Sergey Sarmatov on Aug 28, 2013
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Sections

  • Connector Menu
  • ISA
  • ISA (Technical)
  • EISA
  • PCI
  • PCI (Technical)
  • VESA LocalBus (VLB)
  • CompactPCI
  • Miniature Card
  • NuBus
  • NuBus 90
  • Zorro II
  • Zorro II/III
  • Name Zorro III
  • Video Expansion (Amiga)
  • CardBus
  • PC Card
  • PC Card ATA
  • PCMCIA
  • CompactFlash
  • C-bus II
  • SSFDC
  • Unibus
  • Serial (PC 9)
  • Serial (PC 25)
  • Serial (Amiga 1000)
  • Serial (Amiga)
  • Serial (MSX)
  • Serial (Printer)
  • Mouse (PS/2)
  • Serial (15)
  • DEC Dual RS-232
  • Macintosh RS-422
  • Macintosh Serial
  • C64 RS232 User Port
  • DEC DLV11-J Serial
  • Cisco Console Port
  • RocketPort Serialport
  • CoCo Serial Printer
  • Conrad Electronics MM3610D
  • Parallel (PC)
  • Parallel (Amiga)
  • Parallel (Amiga 1000)
  • ECP Parallel
  • MSX Parallel
  • Parallel (Olivetti M10)
  • Amstrad CPC6128 Printer Port
  • Universal Serial Bus (USB)
  • C64/C16/C116/+4 Serial I/O
  • Atari ACSI DMA
  • VGA (VESA DDC)
  • VGA (15)
  • VGA (9)
  • MDA (Hercules)
  • VESA Feature
  • Macintosh Video
  • Amiga Video
  • CDTV Video Slot
  • PlayStation A/V
  • Commodore 1084 & 1084S (Analog)
  • Commodore 1084 & 1084S (Digital)
  • Commodore 1084d & 1084dS
  • Atari Jaguar A/V
  • SNES Video
  • NeoGeo Audio/Video
  • Amstrad CPC6128 Monitor
  • Amstrad CPC6128 Plus Monitor
  • Atari ST Monitor
  • Sun Video
  • ZX Spectrun 128 RGB
  • CM-8/CoCo RGB
  • AT&T 53D410
  • AT&T 6300 Taxan Monitor
  • AT&T PC6300
  • Vic 20 Video
  • C64 Audio/Video
  • C65 Video
  • C128 RGBI
  • C128/C64C Video
  • CBM 1902A
  • Spectravideo SVI318/328 Audio/Video
  • PC Gameport
  • PC Gameport+MIDI
  • Amiga Mouse/Joy
  • C64 Control Port
  • C16/C116/+4 Joystick
  • MSX Joystick
  • SGI Mouse (Model 021-0004-002)
  • Macintosh Mouse
  • Atari Mouse/Joy
  • Atari Enhanced Joystick
  • Atari 2600 Joystick
  • Atari 5200 Joystick
  • Atari 7800 Joystick
  • Amstrad Digital Joystick
  • NeoGeo Joystick
  • Keyboard (5 PC)
  • Keyboard (6 PC)
  • Keyboard (XT)
  • Keyboard (5 Amiga)
  • Keyboard (6 Amiga)
  • Keyboard (Amiga CD32)
  • Macintosh Keyboard
  • AT&T 6300 Keyboard
  • Internal Diskdrive
  • 8" Floppy Diskdrive
  • Amiga External Diskdrive
  • MSX External Diskdrive
  • Amstrad CPC6128 Diskdrive 2
  • Chapter 1: Connector Menu Amstrad CPC6128 Plus External Diskdrive Connector
  • Amstrad CPC6128 Plus External Diskdrive
  • Macintosh External Drive
  • Atari Floppy Port
  • SCSI Internal (Single-ended)
  • SCSI Internal (Differential)
  • Chapter 1: Connector Menu SCSI External Centronics 50 (Single-ended) Connector
  • SCSI External Centronics 50 (Single-ended)
  • SCSI External Centronics 50 (Differential)
  • Chapter 1: Connector Menu SCSI-II External Hi D-Sub (Single-ended) Connector
  • SCSI External D-Sub (Future Domain)
  • SCSI External D-Sub (PC/Amiga/Mac)
  • Novell and Procomp External SCSI
  • IDE Internal
  • ATA Internal
  • ATA (44) Internal
  • ESDI
  • ST506/412
  • Paravision SX-1 External IDE
  • Mitsumi CD-ROM
  • Panasonic CD-ROM
  • Sony CD-ROM
  • C64 Cassette
  • C16/C116/+4 Cassette
  • CoCo Cassette
  • MSX Cassette
  • Spectravideo SVI318/328 Cassette
  • Amstrad CPC6128 Tape
  • 30 pin SIMM
  • 72 pin SIMM
  • 72 pin ECC SIMM
  • 72 pin SO DIMM
  • 144 pin SO DIMM
  • 168 pin DRAM DIMM (Unbuffered)
  • 168 pin SDRAM DIMM (Unbuffered)
  • SmartCard AFNOR
  • SmartCard ISO 7816-2
  • SmartCard ISO
  • SCART
  • S-Video
  • DIN Audio
  • 3.5 mm Mono Telephone plug
  • 3.5 mm Stereo Telephone plug
  • 6.25 mm Mono Telephone plug
  • 6.25 mm Stereo Telephone plug
  • 5.25" Power
  • 3.5" Power
  • Motherboard Power
  • Turbo LED
  • AT Backup Battery
  • AT LED/Keylock
  • Motherboard IrDA
  • Motherboard CPU Cooling fan
  • Ethernet 100Base-T4
  • Atari 2600 Cartridge
  • Atari 5200 Cartridge
  • Atari 5200 Expansion
  • Atari 7800 Cartridge
  • Atari 7800 Expansion
  • Atari Cartridge Port
  • GameBoy Cartridge
  • MSX Expansion
  • Vic 20 Memory Expansion
  • C64 User Port
  • C128 Expansion Bus
  • C16/C116/+4 Expansion Bus
  • +4 User Port
  • CDTV Diagnostic Slot
  • CDTV Expansion Slot
  • PC-Engine Cartridge
  • SNES Cartridge
  • TG-16 Cartridge
  • ZX Spectrum AY-3-8912
  • ZX Spectrum ULA
  • Spectravideo SVI318/328 Expansion Bus
  • Spectravideo SVI318/328 Game Cartridge
  • MIDI Out
  • MIDI In
  • Minuteman UPS
  • Connector Top 10 Menu
  • Nullmodem (9-9) Cable
  • Nullmodem (9-25) Cable
  • Nullmodem (25-25) Cable
  • Mac to C64 Nullmodem Cable
  • Modem (9-25) Cable
  • Modem (25-25) Cable
  • Two-Wire Modem (9-25) Cable
  • Two-Wire Modem (25-25) Cable
  • Macintosh Modem (With DTR) Cable
  • Macintosh Modem (Without DTR) Cable
  • RocketPort Serial (25) Cable
  • Modem (9-15) Cable
  • Serial Printer (9-25) Cable
  • Serial Printer (25-25) Cable
  • C64 Centronics Printer Cable
  • LapLink/InterLink Parallel Cable
  • ParNet Parallel Cable
  • 64NET Cable
  • GEOCable Cable
  • Cisco Console (9) Cable
  • Cisco Console (25) Cable
  • Mac to HP48 Cable
  • Parallel Port Loopback (Norton)
  • Parallel Port Loopback (CheckIt)
  • Serial Port Loopback (9 Norton)
  • Serial Port Loopback (25 Norton)
  • Serial Port Loopback (9 CheckIt)
  • Serial Port Loopback (25 CheckIt)
  • Floppy Cable
  • IDE Cable
  • SCSI Cable (Amiga/Mac)
  • SCSI Cable (D-Sub to Hi D-Sub)
  • ST506/412 Cable
  • ESDI Cable
  • Paravision SX1 to IDE Cable
  • Video to TV SCART cable
  • Amiga to SCART cable
  • 9 to 15 pin VGA cable
  • Amiga to C1084 Monitor Cable
  • C128/C64C to CBM 1902A Monitor Cable
  • C128/C64C to SCART (S-Video) Cable
  • NeoGeo to SCART Cable
  • Ethernet 10/100Base-T Crossover Cable
  • Ethernet 10/100Base-T Straight Thru Cable
  • Ethernet 100Base-T4 Crossover Cable
  • ParaLoad Cable
  • X1541 Cable
  • MIDI Cable
  • Misc unsupported Cables
  • Nullmodem Adapter
  • 9 to 25 Serial Adapter
  • Centronics to LapLink Adapter
  • Mini-DIN to DIN Keyboard Adapter
  • DIN to Mini-DIN Keyboard Adapter
  • PS/2 Keyboard (Gateway) Y Adapter
  • PS/2 Keyboard (IBM Thinkpad) Y Adapter
  • PS/2 to Serial Mouse Adapter
  • Serial to PS/2 Mouse Adapter
  • Amiga 4 Joysticks adapter
  • PC 2 Joysticks adapter
  • A1000 to Amiga Parallel Adapter
  • SCSI Information
  • DCE
  • Table Menu
  • SI Prefixes
  • Wanted
  • About Hardware Book
  • Contacting the author HwB

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

It may not be modified and re-distributed without the authors permission.

The Hardware Book
by Joakim Ögren

Visit Cable City at <http://www.cablecity.com> Created and maintained by Joakim Ögren.

Contents:

Note: This PDF file may NOT be sold in printed form. (C) Joakim Ögren 1996,1997

PR EL IM IN

Connectors Connectors Top 10 Cables Adapters Circuits Misc Tables Download HwB-News Wanted About Comment

Pinouts for connectors, buses etc. Too many? These are the most common. How to build serial cables and many other cables. How to build adapters. Misc circuits (active filters etc). Misc information (encyclopaedia). Misc tables with info. (AWG..) Download a WinHelp or HTML version for offline viewing. Subscribe to the HwB Newsletter! Info about updates etc. Information I am currently looking for. Who did this? And why? Send your comments to the author.

BETA RELEASE

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Current version 1.3 BETA. Converted from HTML 1997-11-23.

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This is the PDF (Adobe Acrobat) version. It's converted from HTML to PDF so the result may sometimes look a bit strange. Please let me know if you find any major visual errors. You will find the online version and the latest PDF version at HwB <http://www.blackdown.org/~hwb/hwb.html>.

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Welcome to the Hardware Book. Your electronic reference guide.

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The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

Chapter 1
Connector Menu

What does the information that is listed for each connector mean? See the tutorial.

Buses:
- ISA - (Technical) - EISA - (Technical) - PCI - (Technical) - VESA LocalBus (VLB) - (Technical) - CompactPCI - (Technical) - IndustrialPCI - SmallPCI - Miniature Card - (Technical) - NuBus - NuBus 90 - Zorro II - Zorro II/III - CPU-port (A1200) - Ramex (A1000) - Video Expansion (Amiga) - CD32 Expansion - CardBus - PC Card - PC Card ATA - PCMCIA - CompactFlash - C-bus II - SSFDC - PC-104 - Unibus

Serial In/Out:

- RS-232 - Serial (PC 9) - Serial (PC 25) - Serial (Amiga 1000) - Serial (Amiga) - Serial (MSX)

PR EL IM IN

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Chapter 1: Connector Menu
- Serial (Printer) - Mouse (PS/2) - Serial (15) - DEC Dual RS-232 - Macintosh RS-422 - RS-422 - Macintosh Serial - C64 RS232 User Port - DEC DLV11-J Serial - Cisco Console Port - RocketPort Serialport - CoCo Serial Printer - Conrad Electronics MM3610D

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

Video:

- VGA (VESA DDC) - VGA (15) - VGA (9) - CGA - EGA - PGA - MDA (Hercules) - VESA Feature - Macintosh Video - Amiga Video - RF Monitor (Amiga 1000) - CDTV Video Slot - PlayStation A/V - Commodore 1084 & 1084S (Analog) - Commodore 1084 & 1084S (Digital) - Commodore 1084d & 1084dS - Atari Jaguar A/V - SNES Video - NeoGeo Audio/Video

PR EL IM IN

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- Universal Serial Bus (USB) - (Technical) - BeBox GeekPort - C64/C16/C116/+4 Serial I/O - Atari ACSI DMA

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Misc In/Out:

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- Parallel (PC) - Parallel (Amiga) - Parallel (Amiga 1000) - ECP Parallel - (Technical) - Centronics Printer - MSX Parallel - Parallel (Olivetti M10) - Amstrad CPC6128 Printer Port

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Parallel In/Out:

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Chapter 1: Connector Menu
- Amstrad CPC6128 Monitor - Amstrad CPC6128 Plus Monitor - Atari ST Monitor - Sun Video - ZX Spectrum 128 RGB - 3b1-7300 Video - CM-8/CoCo RGB - AT&T 53D410 - AT&T 6300 Taxan Monitor - AT&T PC6300 - Vic 20 Video - C64 Audio/Video - C65 Video - C128 RGBI - C128/C64C Video - C16/C116/+4 - CBM 1902A - Spectravideo SVI318/328 Audio/Video

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

Diskdrives:

- Internal Diskdrive - 8" Floppy Diskdrive - External Diskdrive (Amiga)

PR EL IM IN

- Keyboard (5 PC) - Keyboard (6 PC) - Keyboard (XT) - Keyboard (5 Amiga) - Keyboard (6 Amiga) - Keyboard (Amiga CD32) - Macintosh Keyboard - AT&T 6300 Keyboard

BETA RELEASE

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Keyboards:

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- PC Gameport - PC Gameport+MIDI - Amiga Mouse/Joy - C64 Control Port - C16/C116/+4 Joystick - MSX Joystick - SGI Mouse (Model 021-0004-002) - Macintosh Mouse - Atari Mouse/Joy - Atari Enhanced Joystick - Atari 2600 Joystick - Atari 5200 Joystick - Atari 7800 Joystick - Amstrad Digital/Joystick - NeoGeo Joystick

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Joysticks/Mice:

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Chapter 1: Connector Menu

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

Harddrives:
- SCSI Internal (Single-ended) - SCSI Internal (Differential) - SCSI External Centronics 50 (Single-ended) - SCSI External Centronics 50 (Differential) - SCSI-II External Hi D-Sub Connector (Single-ended) - SCSI-II External Hi D-Sub Connector (Differential) - SCSI External D-Sub (Future Domain) - SCSI External D-Sub (PC/Amiga/Mac) - Novell and Procomp External SCSI - IDE Internal - ATA Internal - ATA (44) Internal - ESDI - ST506/412 - Paravision SX-1 External IDE

Misc data storage:
- Mitsumi CD-ROM - Panasonic CD-ROM - Sony CD-ROM - C64 Cassette - C16/C116/+4 Cassette - CoCo Cassette - MSX Cassette - Spectravideo SVI318/328 Cassette - Amstrad CPC6128 Tape

Memories:

Home audio/video:
- SCART - S-Video

PR EL IM IN

- 30 pin SIMM - 72 pin SIMM - 72 pin ECC SIMM - 72 pin SO DIMM - 144 pin SO DIMM - 168 pin DRAM DIMM (Unbuffered) - 168 pin SDRAM DIMM (Unbuffered) - CDTV Memory Card - SmartCard AFNOR - SmartCard ISO 7816-2 - SmartCard ISO

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- MSX External Diskdrive - Amstrad CPC6128 Diskdrive 2 - Amstrad CPC6128 Plus External Diskdrive - Macintosh External Drive - Atari Floppy Port

Chapter 1: Connector Menu

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

PC motherboards:
- 5.25" Power - 3.5" Power - Motherboard Power - Turbo LED - AT Backup Battery - AT LED/Keylock - PC-Speaker - Motherboard IrDA - Motherboard CPU Cooling fan

Networking:
- Ethernet 10Base-T & 100Base-T - Ethernet 100Base-T4 - AUI

Cartridge/Expansion:

Misc:

- MIDI Out - MIDI In

PR EL IM IN

- Atari 2600 Cartridge - Atari 5200 Cartridge - Atari 5200 Expansion - Atari 7800 Cartridge - Atari 7800 Expansion - Atari Cartridge Port - GameBoy Cartridge - MSX Expansion - Vic 20 Memory Expansion - C64 Cartridge - C64 User Port - C128 Expansion Bus - C16/+4 Expansion Bus - +4 User Port - CDTV Diagnostic Slot - CDTV Expansion Slot - PC-Engine Cartridge - SNES Cartridge - TG-16 Cartridge - ZX Spectrum AY-3-8912 - ZX Spectrum ULA - Spectravideo SVI318/328 Expansion Bus - Spectravideo SVI318/328 Game Cartridge

BETA RELEASE

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- DIN Audio - 3.5 mm Mono Telephone plug - 3.5 mm Stereo Telephone plug - 6.25 mm Mono Telephone plug - 6.25 mm Stereo Telephone plug

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(C) Joakim Ögren 1996,1997

Last updated 1997-11-17.

PR EL IM IN YB ET A .N OT FO R RE DI

- Minuteman UPS - C64 Power Supply Connector - Amstrad CPC6128 Stereo Connector

Chapter 1: Connector Menu

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Chapter 1: Connector Menu

Connector Tutorial

Heading
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

First at each page there a short heading describing what the connector is.

(At the monitor cable)

Texts describing the connectors
5 PIN DIN 180° (DIN41524) at the computer.

Pin table
Pin 1 2 3 4 5

The pin table is perhaps the information you are looking for. Should be simple to read. Contains mostly the following three columns; Pin, Name & Description. Name CLOCK GND DATA VCC n/c Description Key Clock GND Key Data +5 VDC Not connected

Contributor & Source

PR EL IM IN

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Below the pictures there is texts that describes the connectors. Including the name of the physical connector.

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(At the videocard)

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Normally are one or more pictures. These are seen from the front, and NOT the soldside. Holes (female connectors usually) are darkened. Look at the example below. The first is a female connector and the second is a male. The texts insde parentheses will tell you at which kind of the device it will look like that.

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There may be some pictures I haven't drawn yet. I illustrate this with the following advanced picture:

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After that there is at each page there is one or more pictures of the connectors. Sometimes there is some question marks only. This means that I don't know what kind of connector it is or how it looks.

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Pictures of the connectors

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Short tutorial

N OT FO R RE DI ST RI BU TIO N. I must admit that I am bad at writing the source. The source of the information is perhaps a book or another site. It may not be modified and re-distributed without the authors permission. 9 . Contributor: Joakim Ögren Source: Amiga 4000 User's Guide from Commodore PR EL IM IN BETA RELEASE AR YB ET A . All persons that helped me or sent me information about the connector will be listed here. but I will try to fill in these in the future.Chapter 1: Connector Menu Connector Tutorial Example: The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

Chapter 1: Connector Menu ISA Connector ISA=Industry Standard Architecture The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. RE Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 Name Dir /I/O CH CK D7 D6 D5 D4 D3 D2 D1 D0 I/O CH RDY AEN A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 62+36 PIN EDGE CONNECTOR MALE at the card. 62+36 PIN EDGE CONNECTOR FEMALE at the computer. active low=parity error Data bit 7 Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 I/O Channel ready. 10 ISA . It may not be modified and re-distributed without the authors permission. pulled low to lengthen memory cycles Address enable.N OT FO R (At the computer) DI (At the card) ST RI BU TIO N. Description I/O channel check. active high when DMA controls bus Address bit 19 Address bit 18 Address bit 17 Address bit 16 Address bit 15 Address bit 14 Address bit 13 Address bit 12 Address bit 11 Address bit 10 Address bit 9 Address bit 8 Address bit 7 Address bit 6 Address bit 5 Address bit 4 Address bit 3 Address bit 2 Address bit 1 PR EL IM IN BETA RELEASE AR YB ET A .

50% duty cycle) Interrupt Request 7 Interrupt Request 6 Interrupt Request 5 Interrupt Request 4 Interrupt Request 3 DMA Acknowledge 2 Terminal count.31818 MHz. pulses high when DMA term. count reached Address Latch Enable +5 VDC High-speed Clock (70 ns.33 MHz. 16-bit memory cycle) I/O 16-bit chip select (1 wait.Chapter 1: Connector Menu A31 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 A0 GND RESET +5V IRQ2 -5VDC DRQ2 -12VDC /NOWS +12VDC GND /SMEMW /SMEMR /IOW /IOR /DACK3 DRQ3 /DACK1 DRQ1 /REFRESH CLOCK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 /DACK2 T/C ALE +5V OSC GND ISA Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 8-8. .N Address bit 0 Ground Active high to reset or initialize system logic +5 VDC Interrupt Request 2 -5 VDC DMA Request 2 -12 VDC No WaitState +12 VDC Ground System Memory Write System Memory Read I/O Write I/O Read DMA Acknowledge 3 DMA Request 3 DMA Acknowledge 1 DMA Request 1 Refresh System Clock (67 ns. 14. C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 SBHE LA23 LA22 LA21 LA20 LA18 LA17 LA16 /MEMR /MEMW SD08 SD09 SD10 SD11 SD12 SD13 SD14 SD15 /MEMCS16 /IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 /DACK0 DRQ0 System bus high enable (data available on SD8-15) Address bit 23 Address bit 22 Address bit 21 Address bit 20 Address bit 19 Address bit 18 Address bit 17 Memory Read (Active on all memory read cycles) Memory Write (Active on all memory write cycles) Data bit 8 Data bit 9 Data bit 10 Data bit 11 Data bit 12 Data bit 13 Data bit 14 Data bit 15 Memory 16-bit chip select (1 wait. 16-bit I/O cycle) Interrupt Request 10 Interrupt Request 11 Interrupt Request 12 Interrupt Request 15 Interrupt Request 14 DMA Acknowledge 0 DMA Request 0 11 PR EL IM IN BETA RELEASE AR YB ET A . 50% duty cycle) Ground OT FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission.

N OT FO R RE DI Sources: IBM PC/AT Technical Reference. Rob Gill <gillr@mailcity.ibm.answers/pc-hardware-faq/part1>.* FAQ Part 4 <ftp://rtfm. PR EL IM IN BETA RELEASE AR YB ET A .mit. maintained by Ralph Valentino <ralf@alum.sys. Note: Direction is Motherboard relative ISA-Cards.Chapter 1: Connector Menu D10 D11 D12 D13 D14 D15 D16 D17 D18 /DACK5 DRQ5 /DACK6 DRQ6 /DACK7 DRQ7 +5 V /MASTER GND ISA Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.pc. activated by cards in XT's slot J8 BU Used with DRQ to gain control of system Ground TIO N.com> Please send any comments to Joakim Ögren. pages 1-25 through 1-37 Sources: comp.edu> ST RI Note: B8 was /CARD SLCDTD on the XT.wpi. Card selected.hardware.edu/pub/usenet/news. It may not be modified and re-distributed without the authors permission. Contributor: Joakim Ögren . 12 DMA Acknowledge 5 DMA Request 5 DMA Acknowledge 6 DMA Request 6 DMA Acknowledge 7 DMA Request 7 .

BU This file is designed to give a basic overview of the bus found in most IBM clone computers. with an extension called the EISA (Extended ISA) bus also now as a standard. 8-bit cards only uses the first 62 pins and 16-bit cards uses all 98 pins. Physical Design: 8-bit card: ET A YB (At the computer) 16-bit card: PR EL IM IN BETA RELEASE AR . a more formal standard called the ISA bus (Industry Standard Architecture) has been created.Chapter 1: Connector Menu ISA (Tech) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. It is for informational purposes only. The EISA bus extensions will not be detailed here. DI ST RI This file is not intended to be a thorough coverage of the standard. In recent years. often referred to as the XT or AT bus. TIO N. The AT version of the bus is upwardly compatible. Some 8-bit cards uses some of the 16-bit extension pins to get more interrupts. This bus was produced for many years without any formal standard. and is intended to give designers and hobbyists sufficient information to design their own XT and AT compatible cards. ISA (Technical) 13 . which means that cards designed to work on an XT bus will work on an AT bus.N OT (At the card) FO R RE ISA cards can be either 8-bit or 16-bit.

6. The address bus is latched on the rising edge of this signal. 5. (At the computer) Power supplies. DMA request channels 0-3 are for 8-bit data transfer. -5. This signal is forced high during DMA cycles. -12 R Signal Descriptions: RE DI ST (At the card) RI BU TIO N. DRQx DMA Request. or just Address Latch Enable (ALE).3 MHz is specified as the maximum. DMA requests are serviced in the following priority sequence: High: DRQ 0. 3. but many systems allow this clock to be set to 12 MHz and higher. 7 Lowest PR EL IM IN Bus Clock. 33% Duty Cycle. 14 . 8. Memory devices should latch the LA bus on the falling edge of BALE.N Address Enable.Chapter 1: Connector Menu ISA (Tech) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. the DMA Controller has control of the address bus as the memory and I/O read/write command lines. This is asserted when a DMAC has control of the bus. Some references refer to this signal as Buffered Address Latch Enable. 4. ET A BALE . +12. The Buffered-Address Latch Enable is used to latch SA0-19 on the falling edge. DMA request channel 4 is used internally on the system board. 5-7. 2. It may not be modified and re-distributed without the authors permission. These signals are asynchronous channel requests used by I/O channel devices to gain DMA service. The active-low DMA Acknowledge 0 to 3 and 5 to 7 are the corresponding acknowledge signals for DRQ 0-3. OT AEN FO +5. Frequency Varies. DMA requests should be held high until the corresponding DACK line goes active. DAM request channels 5-7 are for 16-bit data transfer. This prevents an I/O device from responding to the I/O command lines during a DMA transfer. 1. BETA RELEASE AR BCLK YB Bus Address Latch Enable. When AEN is active.77 to 8 MHz typical. The address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle. DACKx DMA Acknowledge. -5 is often not implemented.

The I/O Write is an active-low signal which instructs the I/O device to read data from the data bus.7 . SD0-SD15. Combine with the lower address lines to form a 24 bit address space (16 MB) These unlatched address signals give the system up to 16 MB of address ability. This signal is pulled low by a memory or I/O device to lengthen memory or I/O read/write cycles. Generated by the ISA bus master when initiating a bus cycle.3. Holding this line low for too long (15 microseconds.5. YB LAxx ET A Interrupt Request. The I/O Channel Check is an active-low signal which indicates that a parity error exists in a device on the I/O channel. SD0-SD15.14.5 microseconds.4. the I/O processor may assert MASTER. This signal should not be asserted for more than 15 microseconds. This signal is called IOCHRDY (I/O Channel Ready) by some references. externally to the processor (of course). 16 bit data memory cycle. and upon receiving the corresponding DACK. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.6.10. and are higher priority than IRQ 3-7. or system memory may be corrupted du to the lack of memory refresh activity. This active-low signal is used in conjunction with a DRQ line by a processor on the I/O channel to gain control of the system. DI ST I/O CH RDY RI Channel Check. 12. IRQ2 has the highest priority. BETA RELEASE AR Latchable Address lines. MEMR PR EL IM IN 16 bit bus master.Chapter 1: Connector Menu IOCS16 ISA (Tech) Connector I/O size 16. typical) can prevent RAM refresh cycles on some systems. 15 . The active-low I/O Chip Select 16 indicates that the current transfer is a 1 wait state. The Interrupt Request signals which indicate I/O service attention. BU TIO N. Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach the cpu. The I/O processor first issues a DRQ. A low signal generates an NMI.N OT IOW FO R RE Channel Ready. data and control lines. Setting this low prevents the default ready timer from timing out. 16 bit I/O cycle. It may not be modified and re-distributed without the authors permission. The are valid when "BALE" is high. The slave device may then set it high again when it is ready to end the bus cycle. CHRDY and NOWS should not be used simultaneously.11. IRQx MASTER MEMCS16 The active-low Memory Chip Select 16 indicates that the current data transfer is a 1 wait state. I/O CH CK IOR The I/O Read is an active-low signal which instructs the I/O device to drive its data onto the data bus. The NMI signal can be masked on a PC. This may cause problems with some bus controllers. They are prioritized in the following sequence: Highest IRQ 9(2). Open Collector. It should only be held low for a minimum of 2. which will allow it to control the system address. IRQ 10-15 are only available on AT machines. Generated by a 16 bit slave when addressed by a bus master.

Chapter 1: Connector Menu

ISA (Tech) Connector

The Memory Read is an active-low signal which instructs memory devices to drive data onto the data bus SD0-SD15. This signal is active on all memory read cycles.

MEMW
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

The Memory Write is an active-low signal which instructs memory devices to store data present on the data bus SD0-SD15. This signal is active on all memory write cycles.

OSC

REFRESH

SA0-SA19

SBHE

System Bus High Enable, tristate. Indicates a 16 bit data transfer. The System Bus High Enable indicates high byte transfer is occurring on the data bus SD8-SD15. This may also indicate an 8 bit transfer using the upper half of the bus data (if an odd address is present).

SD0-SD16

System Data lines, or Standard Data Lines. They are bidrectional and tri-state. On most systems, the data lines float high when not driven. These 16 lines provide for data transfer between the processor, memory and I/O devices.

SMEMR

System Memory Read Command line. Indicates a memory read in the lower 1 MB area. This System Memory Read is an active-low signal which instructs memory devices to drive data onto the data bus SD0-SD15. This signal is active only when the memory address is within the lowest 1MB of memory address space.

PR EL IM IN

BETA RELEASE

AR

YB

System Address Lines, tri-state. The System Address lines run from bit 0 to bit 19. They are latched on to the falling edge of "BALE".

ET A

This signal goes low when the machine is powered up. Driving it low will force a system reset. This signal goes high to reset the system during powerup, low line-voltage or hardware reset. ??????????????

.N

RESET

OT

Refresh. Generated when the refresh logic is bus master. This active-low signal is used to indicate a memory refresh cycle is in progress. An ISA device acting as bus master may also use this signal to initiate a refresh cycle.

FO

Oscillator, 14.31818 MHz, 50% Duty Cycle. Frequency varies. This was originally divided by 3 to provide the 4.77 MHz cpu clock of early PCs, and divided by 12 to produce the 1.19 MHz system clock. Some references have placed this signal as low as 1 MHz (possibly referencing the system clock), but most modern systems use 14.318 MHz. This frequency (14.318 MHz) is four times the television colorburst frequency. Refresh timing on many PC's is based on OSC/18, or approximately one refresh cycle every 15 microseconds. Many modern motherboards allow this rate to be changed, which frees up some bus cycles for use by software, but also can cause memory errors if the system RAM cannot handle the slower refresh rates.

R

RE

DI

ST

RI

No Wait State. Used to shorten the number of wait states generated by the default ready timer. This causes the bus cycle to end more quickly, since wait states will not be inserted. Most systems will ignore NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers, and both signals should not be active simultaneously.

BU

NOWS

TIO N.

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Chapter 1: Connector Menu
SMEMW

ISA (Tech) Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

T/C

Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete. Terminal Count provides a pulse when the terminal count for any DMA channel is reached.

__ BCLK BALE ___| |___| __ _______|

__

|_______________________________________

AEN SA0-SA19

__________________________________________________ ______________________________________ ---------<______________________________________>-

Note: W1 through W4 indicate wait cycles.

NOWS is sampled at the midpoint of each wait cycle. If it is low, the transfer cycle terminates without further wait states. CHRDY is sampled during the first half of the clock cycle. If it is low, further wait cycles will be inserted. The default for 8 bit transfers is 4 wait states. Some computers allow the number of default wait states to be changed.

16 Bit Memory or I/O Transfer Timing Diagram (1 wait state shown)
__ __ __ __ __ __

PR EL IM IN

BETA RELEASE

AR

The command line is then pulled low (IORC or IOWC for I/O commands, SMRDSC or SMWTC for memory commands, read and write respectively). For write operations, the data remains on the SD bus for the remainder of the transfer cycle. For read operations, the data must be valid on the falling edge of the last cycle.

YB

BALE is placed high, and the address is latched on the SA bus. The slave device may safely sample the address during the falling edge of BALE, and the address on the SA bus remains valid until the end of the transfer cycle. Note that AEN remains low throughout the entire transfer cycle.

ET A

SD0-SD7 (WRITE)

___________________________________ ---------<___________________________________>----

.N

_____________ _____ Command Line |______________________________| (IORC,IOWC, SMRDC, or SMWTC) _____ SD0-SD7 ---------------------------------------<_____>---(READ)

OT

FO

R

RE

DI

__ __ __ __ __ |___| |__| |___| |___| |___| |__ W1 W2 W3 W4

ST

8 Bit Memory or I/O Transfer Timing Diagram (4 wait states shown)

RI

BU

TIO N.

System Memory Write Commmand line. Indicates a memory write in the lower 1 MB area. The System Memory Write is an active-low signal which instructs memory devices to store data preset on the data bus SD0-SD15. This signal is active only when the memory address is within the lowest 1MB of memory address space.

17

Chapter 1: Connector Menu
BCLK AEN [2] LA17-LA23
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

ISA (Tech) Connector
|___| |_

___|

|___|

|___|

|__|

|___|

__________________________________________ _____________ -------<_____________>-[1]----------------__ ______________| ________________ |________________________ _______ |__________________|

SBHE SA0-SA19 M16

__________________ ---------------<__________________>------_________________ ____________________ |____| * * [4] ___________ |_____________| * _________________ |____________|

_________________ IO16 [3]

SD0-SD7 (READ) SD0-SD7 (WRITE)

An asterisk (*) denotes the point where the signal is sampled. [1] The portion of the address on the LA bus for the NEXT cycle may now be placed on the bus. This is used so that cards may begin decoding the address early. Address pipelining must be active. [2] AEN remains low throughout the entire transfer cycle, indicating that a normal (non-DMA) transfer is occurring.

I/O adapter cards do not need to monitor the LA bus or BALE, since I/O addresses are always within the address space of the SA bus. SBHE will be pulled low by the system board, and the adapter card must respond with IO16 or M16 at the appropriate time, or else the transfer will be split into two separate 8 bit transfers. Many systems expect IO16 or M16 before the command lines are valid. This requires that IO16 or M16 be pulled low as soon as the address is decoded (before it is known whether the cycle is I/O or Memory). If the system is starting a memory cycle, it will ignore IO16 (and vice-versa for I/O cycles and M16). 18

PR EL IM IN

16 bit transfers follow the same basic timing as 8 bit transfers. A valid address may appear on the LA bus prior to the beginning of the transfer cycle. Unlike the SA bus, the LA bus is not latched, and is not valid for the entire transfer cycle (on most computers). The LA bus should be latched on the falling edge of BALE. Note that on some systems, the LA bus signals will follow the same timing as the SA bus. On either type of system, a valid address is present on the falling edge of BALE.

BETA RELEASE

AR

[4] M16 is sampled a second time, in case the adapter card did not active the signal in time for the first sample (usually because the memory device is not monitoring the LA bus for early address information, or is waiting for the falling edge of BALE).

YB

[3] Some bus controllers sample this signal during the same clock cycle as M16, instead of during the first wait state, as shown above. In this case, IO16 needs to be pulled low as soon as the address is decoded, which is before the I/O command lines are active.

ET A

.N

OT

______________ -----------------<______________>---------

FO

____ ---------------------------<____>---------

R

Command Line (IORC,IOWC, MRDC, or MWTC)

RE

___________

DI

ST

RI

BU

BALE

TIO N.

Chapter 1: Connector Menu

ISA (Tech) Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

Shortening or Lengthening the bus cycle:

BCLK W W W W _ __ __ __ __ __ __ __ __ __ __ __ |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__ |--Transfer 1-----|----Transfer 2---------|----Transfer 3---| BALE __ ________| SBHE _________ |______________| __

FO

R

RE

DI
__ |______________|

ST

It is also possible for an 8 bit bus cycle to use the upper portion of the bus. In this case, the timing will be similar to a 16 bit cycle, but an odd address will be present on the bus. This means that the bus is transferring 8 bits using the upper data bits (SD8-SD15).

RI

SMRDC/SMWTC follow the same timing as MRDC/MWTC respectively when the address is within the lower 1 MB. If the address is not within the lower 1 MB boundary, SMRDC/SMWTC will remain high during the entire cycle.

BU

The default for 16 bit transfers is 1 wait state. This may be shortened or lengthened in the same manner as 8 bit transfers, via NOWS and CHRDY. Many systems only allow 16 bit memory devices (and not I/O devices) to transfer using 0 wait states (NOWS has no effect on 16 bit I/O cycles).

|____________________|

OT

_______________________

|__________________|__________________| SA0-SA19

IO16 ___________

ET A

_________________ _____________________ _________________ ----------<_________________><_____________________><_________________>

___

.N

___________________________

CHRDY ________________________________

YB

|_____________| *

|_____________| * _______________________________ |______| * * [1] _____ |__________| * [2]

IORC ______________

PR EL IM IN

NOWS ______________________________________________________

AR

*

_______ |_______________|

_______ |_________|

|_________|

SD0-SD15

____ ____ ____ --------------------<____>------------------<____>------------<____>--* * *

An asterisk (*) denotes the point where the signal is sampled. W=Wait Cycle

BETA RELEASE

TIO N.

For read operations, the data is sampled on the rising edge of the last clock cycle. For write operations, valid data appears on the bus before the end of the cycle, as shown in the timing diagram. While the timing diagram indicates that the data needs to be sampled on the rising clock, on most systems it remains valid for the entire clock cycle.

__

____

19

Chapter 1: Connector Menu

ISA (Tech) Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

Port (hex) Port Assignments 000-00F DMA Controller 010-01F DMA Controller (PS/2) 020-02F Master Programmable Interrupt Controller (PIC) 030-03F Slave PIC 040-05F Programmable Interval Timer (PIT) 060-06F Keyboard Controller 070-071 Real Time Clock 080-083 DMA Page Register 090-097 Programmable Option Select (PS/2) 0A0-0AF PIC #2 0C0-0CF DMAC #2 0E0-0EF reserved 0F0-0FF Math coprocessor, PCJr Disk Controller 100-10F Programmable Option Select (PS/2) 110-16F AVAILABLE 170-17F Hard Drive 1 (AT) 180-1EF AVAILABLE 1F0-1FF Hard Drive 0 (AT) 200-20F Game Adapter 210-217 Expansion Card Ports 220-26F AVAILABLE 278-27F Parallel Port 3 280-2A1 AVAILABLE 2A2-2A3 clock 2B0-2DF EGA/Video 2E2-2E3 Data Acquisition Adapter (AT) 2E8-2EF Serial Port COM4 2F0-2F7 Reserved 2F8-2FF Serial Port COM2 300-31F Prototype Adapter, Periscope Hardware Debugger 320-32F AVAILABLE 330-33F Reserved for XT/370 340-35F AVAILABLE 360-36F Network 370-377 Floppy Disk Controller 378-37F Parallel Port 2 380-38F SDLC Adapter 390-39F Cluster Adapter 3A0-3AF reserved 3B0-3BF Monochrome Adapter 3BC-3BF Parallel Port 1 3C0-3CF EGA/VGA 3D0-3DF Color Graphics Adapter 3E0-3EF Serial Port COM3 3F0-3F7 Floppy Disk Controller

PR EL IM IN

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AR

YB

ET A

.N

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FO

R

RE

DI

ST

RI

Note: Only the first 10 address lines are decoded for I/O operations. This limits the I/O address space to address 3FF (hex) and lower. Some systems allow for 16 bit I/O address space, but may be limited due to some I/O cards only decoding 10 of these 16 bits.

BU

I/O Port Addresses

TIO N.

This timing diagram shows three different transfer cycles. The first is a 16 bit standard I/O read. This is followed by an almost identical 16 bit I/O read, with one wait state inserted. The I/O device pulls CHRDY low to indicate that it is not ready to complete the transfer (see [1]). This inserts a wait cycle, and CHRDY is again sampled. At this second sample, the I/O device has completed its operation and released CHRDY, and the bus cycle now terminates. The third cycle is an 8 bit transfer, which is shortened to 1 wait state (the default is 4) by the use of NOWS.

20

Chapter 1: Connector Menu
3F8-3FF Serial Port COM1 Soundblaster cards usually use I/O ports 220-22F. Data acquisition cards frequently use 300-31F.

ISA (Tech) Connector

DMA Read and Write
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

I/O Port 0000 DMA CH0 Memory Address Register Contains the lower 16 bits of the memory address, written as two consecutive bytes. 0001 DMA CH0 Transfer Count Contains the lower 16 bits of the transfer count, written as two consecutive bytes. 0002 DMA CH1 Memory Address Register 0003 DMA CH1 Transfer Count 0004 DMA CH2 Memory Address Register 0005 DMA CH2 Transfer Count 0006 DMA CH3 Memory Address Register 0007 DMA CH3 Transfer Count 0008 DMAC Status/Control Register Status (I/O read) bits 0-3: Terminal Count, CH 0-3 - bits 4-7: Request CH0-3 Control (write) - bit 0: Mem to mem enable (1 = enabled) - bit 1: ch0 address hold enable (1 = enabled) - bit 2: controller disable (1 = disabled) - bit 3: timing (0 = normal, 1 = compressed) - bit 4: priority (0 = fixed, 1 = rotating) - bit 5: write selection (0 = late, 1 = extended) - bit 6: DRQx sense asserted (0 = high, 1 = low) - bit 7: DAKn sense asserted (0 = low, 1 = high) 0009 Software DRQn Request - bits 0-1: channel select (CH0-3) - bit 2: request bit (0 = reset, 1 = set) 000A DMA mask register - bits 0-1: channel select (CH0-3) - bit 2: mask bit (0 = reset, 1 = set) 000B DMA Mode Register - bits 0-1: channel select (CH0-3) - bits 2-3: 00 = verify transfer, 01 = write transfer, 10 = read transfer, 11 = reserved - bit 4: Auto init (0 = disabled, 1 = enabled) - bit 5: Address (0 = increment, 1 = decrement) - bits 6-7: 00 = demand transfer mode, 01 = single transfer mode, 10 = block transfer mode, 11 = cascade mode 21

PR EL IM IN

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R

Slave DMA Controller

RE

Before a DMA transfer can take place, the DMA Controller (DMAC) must be programmed. This is done by writing the start address and the number of bytes to transfer (called the transfer count) and the direction of the transfer to the DMAC. After the DMAC has been programmed, the device may activate the appropriate DMA request (DRQx) line.

DI

The DMAC can be programmed for read transfers (data is read from memory and written to the I/O device), write transfers (data is read from the I/O device and written to memory), or verify transfers (neither a read or a write - this was used by DMA CH0 for DRAM refresh on early PCs).

ST

RI

The ISA bus uses two DMA controllers (DMAC) cascaded together. The slave DMAC connects to the master DMAC via DMA channel 4 (channel 0 on the master DMAC). The slave therefore gains control of the bus through the master DMAC. On the ISA bus, the DMAC is programmed to use fixed priority (channel 0 always has the highest priority), which means that channel 0-4 from the slave have the highest priority (since they connect to the master channel 0), followed by channels 5-7 (which are channel 1-3 on the master).

BU

TIO N.

Chapter 1: Connector Menu

ISA (Tech) Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

Master DMA Controller

I/O Port 00C0 DMA CH4 Memory Address Register Contains the lower 16 bits of the memory address, written as two consecutive bytes. 00C2 DMA CH4 Transfer Count Contains the lower 16 bits of the transfer count, written as two consecutive bytes. 00C4 DMA CH5 Memory Address Register 00C6 DMA CH5 Transfer Count 00C8 DMA CH6 Memory Address Register 00CA DMA CH6 Transfer Count 00CC DMA CH7 Memory Address Register 00CE DMA CH7 Transfer Count 00D0 DMAC Status/Control Register Status (I/O read) bits 0-3: Terminal Count, CH 4-7 - bits 4-7: Request CH4-7 Control (write)- bit 0: Mem to mem enable (1 = enabled) - bit 1: ch0 address hold enable (1 = enabled) - bit 2: controller disable (1 = disabled) - bit 3: timing (0 = normal, 1 = compressed) - bit 4: priority (0 = fixed, 1 = rotating) - bit 5: write selection (0 = late, 1 = extended) - bit 6: DRQx sense asserted (0 = high, 1 = low) - bit 7: DAKn sense asserted (0 = low, 1 = high) 00D2 Software DRQn Request - bits 0-1: channel select (CH4-7) - bit 2: request bit (0 = reset, 1 = set) 00D4 DMA mask register - bits 0-1: channel select (CH4-7) - bit 2: mask bit (0 = reset, 1 = set) 00D6 DMA Mode Register - bits 0-1: channel select (CH4-7) - bits 2-3: 00 = verify transfer, 01 = write transfer, 10 = read transfer, 11 = reserved - bit 4: Auto init (0 = disabled, 1 = enabled) - bit 5: Address (0 = increment, 1 = decrement) - bits 6-7: 00 = demand transfer mode, 01 = single transfer mode, 10 = block transfer mode, 11 = cascade mode 00D8 DMA Clear Byte Pointer Writing to this causes the DMAC to clear the pointer used to keep track of 16 bit data transfers into and out of the DMAC for hi/low byte sequencing. 00DA DMA Master Clear (Hardware Reset) 00DC DMA Reset Mask Register - clears the mask register 00DE DMA Mask Register - bits 0-3: mask bits for CH4-7 (0 = not masked, 1 = masked)

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000C DMA Clear Byte Pointer Writing to this causes the DMAC to clear the pointer used to keep track of 16 bit data transfers into and out of the DMAC for hi/low byte sequencing. 000D DMA Master Clear (Hardware Reset) 000E DMA Reset Mask Register - clears the mask register 000F DMA Mask Register - bits 0-3: mask bits for CH0-3 (0 = not masked, 1 = masked) 0081 DMA CH2 Page Register (address bits A16-A23) 0082 DMA CH3 Page Register 0083 DMA CH1 Page Register 0087 DMA CH0 Page Register 0089 DMA CH6 Page Register 008A DMA CH7 Page Register 008B DMA CH5 Page Register

RI

BU

TIO N.

22

Chapter 1: Connector Menu
Single Transfer Mode

ISA (Tech) Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

The DMAC is programmed for transfer. The DMA device requests a transfer by driving the appropriate DRQ line high. The DMAC responds by asserting AEN and acknowledges the DMA request through the appropriate DAK line. The I/O and memory command lines are also asserted. When the DMA device sees the DAK signal, it drops the DRQ line. The DMAC places the memory address on the SA bus (at the same time as the command lines are asserted), and the device either reads from or writes to memory, depending on the type of transfer. The transfer count is incremented, and the address incremented/decremented. DAK is de-asserted. The cpu now once again has control of the bus, and continues execution until the I/O device is once again ready for transfer. The DMA device repeats the procedure, driving DRQ high and waiting for DAK, then transferring data. This continues for a number of cycles equal to the transfer count. When this has been completed, the DMAC signals the cpu that the DMA transfer is complete via the TC (terminal count) signal.
__ BCLK DRQx AEN DAKx SA0-SA15 ___| _| ____| _______ |___| _______ __ |___| __ |__| __ |___| __

DI
|___|

|___________________________________

R

______________________________ |________ ________

|___________________________|

___________ Command Line (IORC, MRDC) SD0-SD7 (READ) SD0-SD7 (WRITE)

OT

____________________________ -------<____________________________>------____________

|___________________| _____________ ----------------------<_____________>------____________________________ -------<____________________________>-------

Block Transfer Mode
The DMAC is programmed for transfer. The device attempting DMA transfer drives the appropriate DRQ line high. The motherboard responds by driving AEN high and DAK low. This indicates that the DMA device is now the bus master. In response to the DAK signal, the DMA device drops DRQ. The DMAC places the address for DMA transfer on the address bus. Both the memory and I/O command lines are asserted (since DMA involves both an I/O and a memory device). AEN prevents I/O devices from responding to the I/O command lines, which would not result in proper operation since the I/O lines are active, but a memory address is on the address bus. The data transfer is now done (memory read or write), and the DMAC increments/decrements the address and begins another cycle. This continues for a number of cycles equal to the DMAC transfer count. When this has been completed, the terminal count signal (TC) is generated by the DMAC to inform the cpu that the DMA transfer has been completed. Note: Block transfer must be used carefully. The bus cannot be used for other things (like RAM refresh) while block mode transfers are being done.

Demand Transfer Mode

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TIO N.

23

it must assert MASTER16 to release AEN. An ISA device may take control of the bus. The software aspects of interrupts and interrupt handlers is intentionally omitted from this document. The device attempting DMA transfer drives the appropriate DRQ line high. IRQ0. most systems require bus cycles for DRAM refresh. but this must be done with caution. The DMAC sends a hold request to the cpu. The AT and later machines have a second interrupt controller. and so it is easily possible to crash the entire system by incorrectly taking control of the bus. the system RAM can become corrupted. To take control of the bus.1.2. This continues until the terminal count has been reached. The ISA adapter card can generate refresh cycles without relinquishing control of the bus by asserting REFRESH. There are no safety mechanisms involved. This indicates that the DMA device is now the bus master. the device first asserts its DRQ line. Interrupts on most systems may be either edge triggered or level triggered. Mem Refresh 8 8253 Channel 0 (System Timer) 9 Keyboard A Cascade from slave PIC B COM2 C COM1 D LPT2 E Floppy Drive Controller F LPT1 F Real Time Clock F Redirection to IRQ2 F Reserved F Reserved F Mouse Interface F Coprocessor F Hard Drive Controller F Reserved FO R RE DI ST RI Interrupts on the ISA bus BU The DMAC is programmed for transfer. it drops DRQ and the cpu once again has control of the bus. so if the device wishes to access I/O devices.N OT Name NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 InterruptDescription 2 Parity Error. The device is now the bus master.8. for example). The default is usually edge triggered. and when the DMAC receives a hold acknowledge. The DMA device transfers data in the same manner as for block transfers. If the ISA bus master does not relinquish control of the bus or generate its own DRAM refresh cycles every 15 microseconds. The IBM PC and XT had only a single 8259 interrupt controller. and the two are used in a master/slave combination. 24 . Control of the bus is returned to the system board by releasing PR EL IM IN Bus Mastering: BETA RELEASE AR YB ET A . The interrupt level must be held high until the first interrupt acknowledge cycle (two interrupt acknowledge bus cycles are generated in response to an interrupt request). MRDC can be then monitored to determine when the refresh cycle ends. and 13 are not available on the ISA bus. For example. the DMA device does not drop DRQ in response to DAK. The DMAC will continue to generate DMA cycles as long as the I/O device asserts DRQ. TIO N. Unlike single transfer and block transfer. It may not be modified and re-distributed without the authors permission. The motherboard responds by driving AEN high and DAK low. and active high (low to high transition). due to the numerous syntactical differences in software tools and the fact that adequate documentation of this topic is usually provided with developement software. and the TC signal informs the cpu that the transfer has been completed. it asserts the appropriate DAK line corresponding to the DRQ line asserted. Control is returned to the DMAC by once again asserting DRQ. IRQ2 and IRQ9 are the same pin on most ISA systems.Chapter 1: Connector Menu ISA (Tech) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. AEN is asserted. When the I/O device is unable to continue the transfer (if it no longer had data ready to transfer.

uni-frankfurt.edu/~msokos1/isa. PR EL IM IN BETA RELEASE AR YB ET A .de> 25 .N OT FO R RE DI ST RI BU Sources: Mark Sokos ISA page <http://www. It may not be modified and re-distributed without the authors permission.umbc. ISA (Tech) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Pieter Hollants <fxmts205@rz. OPTi 486. Niklas Edmundsson <nikke@ing. Please send any comments to Joakim Ögren. 3rd Edition" by Tom Shanley and Don Anderson ISBN 0-201-40996-8 Sources: "Eisa System Architecture. 82C495sx TIO N. Mark Sokos <msokos1@gl.gl.se> . by David Jurgens Sources: ZIDA 80486 Mother Board User's Manual.10 Quick Reference Utility.edu> .umu.M.Chapter 1: Connector Menu DRQ. 2nd Edition" by Tom Shanley and Don Anderson ISBN 0-201-40995-X Sources: "Microcomputer Busses" by R.txt> Sources: "ISA System Architecture.umbc. Cram ISBN 0-12-196155-9 Sources: HelpPC v2. Contributor: Joakim Ögren.

Chapter 1: Connector Menu EISA Connector EISA=Extended Industry Standard Architecture. (At the computer) 62+38 PIN EDGE CONNECTOR at the computer. AST.. Zenith. Tandy. Pin E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 F1 F2 F3 F4 F5 Name CMD# START# EXRDY EX32# GND KEY EX16# SLBURST# MSBURST# W/R# GND RES RES RES GND KEY BE1# LA31# GND LA30# LA28# LA27# LA25# GND KEY LA15 LA13 LA12 LA11 GND LA9 GND +5V +5V ----Description Command Phase Start Phase EISA Ready EISA Slave Size 32 Ground Access Key EISA Slave Size 16 Slave Burst Master Burst Write/Read Ground Reserved Reserved Reserved Ground Access Key Byte Enable 1 Latchable Addressline 31 Ground Latchable Addressline 30 Latchable Addressline 28 Latchable Addressline 27 Latchable Addressline 25 Ground Access Key Latchable Addressline 15 Latchable Addressline 13 Latchable Addressline 12 Latchable Addressline 11 Ground Latchable Addressline 9 Ground +5 VDC +5 VDC PR EL IM IN BETA RELEASE AR YB ET A .G=Component Side A. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.C.B. Developed by Compaq.N OT FO R RE DI ST +---------------------------------------------+ | (component side) | | | |___________ ISA-16bit __ ISA-8bit __| ||||||||||| ||||||||||||||||||| A1(front)/B1(back) | | | | | | | | | | | | | | EISA: E1(front)/F1(back) C1/D1 G1/H1 A.E.. 26 EISA . It may not be modified and re-distributed without the authors permission.F.H=Sold Side RI BU TIO N.

It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 KEY ----+12V M/IO# LOCK# RES GND RES BE3# KEY BE2# BE0# GND +5V LA29# GND LA26# LA24# KEY LA16 LA14 +5V +5V GND LA10 LA7 GND LA4 LA3 GND KEY D17 D19 D20 D22 GND D25 D26 D28 KEY GND D30 D31 MREQx LA8 LA6 LA5 +5V LA2 KEY D16 D18 GND D21 D23 D24 GND Access Key +12 VDC Memory/Input-Output Lock bus Reserved Ground Reserved Byte Enable 3 Access Key Byte Enable 2 Byte Enable 0 Ground +5 VDC Latchable Addressline 29 Ground Latchable Addressline 26 Latchable Addressline 24 Access Key Latchable Addressline 16 Latchable Addressline 14 +5 VDC +5 VDC Ground Latchable Addressline 10 Latchable Addressline 7 Ground Latchable Addressline 4 Latchable Addressline 3 Ground Access Key Data 17 Data 19 Data 20 Data 22 Ground Data 25 Data 26 Data 28 Access Key Ground Data 30 Data 31 Master Request Latchable Addressline 8 Latchable Addressline 6 Latchable Addressline 5 +5 VDC Latchable Addressline 2 Access Key Data 16 Data 18 Ground Data 21 Data 23 Data 24 Ground EISA Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI ST RI BU TIO N. 27 .

mit.txt> Sources: "Eisa System Architecture. 28 .Chapter 1: Connector Menu H14 H15 H16 H17 H18 H19 D27 KEY D29 +5V +5V MAKx Data 27 Access Key Data 29 +5 VDC +5 VDC Master Acknowledge EISA Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.edu> Please send any comments to Joakim Ögren.N OT FO R RE DI ST RI Sources: Mark Sokos EISA page <http://www.gl.wpi.edu/pub/usenet/news.answers/pc-hardware-faq/part1>. PR EL IM IN BETA RELEASE AR YB ET A .umbc.* FAQ Part 4 <ftp://rtfm.hardware. It may not be modified and re-distributed without the authors permission.pc. Contributor: Joakim Ögren.edu/~msokos1/eisa.edu> BU TIO N. ISBN 0-201-40995-X Sources: comp.ibm. 2nd Edition" by Tom Shanley and Don Anderson.sys. maintained by Ralph Valentino <ralf@alum. Mark Sokos <msokos1@gl.umbc.

but many systems allow this clock to be set to 10 MHz and higher. BE(x) CHCHK CHRDY Channel Ready. -5 is often not implemented.Chapter 1: Connector Menu EISA (Tech) Connector This section is currently based solely on the work by Mark Sokos. It is an extension of the ISA architecture. Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach the cpu. BETA RELEASE AR Byte Enable. The upper row is the same as a regular ISA slot. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. AEN BALE BCLK Bus Clock. -5. which means that cards originally designed for the 8 bit IBM bus (often referred to as the XT bus) and cards designed for the 16 bit bus (referred to as the AT bus. It may not be modified and re-distributed without the authors permission. for example. which is a standardized version of the bus originally developed by IBM for their PC computers. so that hobbyists and amateurs can design their own EISA compatible cards. and also as the ISA bus). -12 Power supplies. will work in an EISA slot. Memory devices should latch the LA bus on the falling edge of BALE. This prevents an I/O device from responding to the I/O command lines during a DMA transfer. CMD PR EL IM IN Channel Check. OT Address Enable. CHRDY and NOWS should not be used simultaneously. The address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle. A 16 bit transfer would assert BE0 and BE1. EISA is an acronym for Extended Industry Standard Architecture. This file is intended to provide a basic functional overview of the EISA Bus. externally to the processor (of course). The address bus is latched on the rising edge of this signal. The slot is keyed so that ISA cards cannot be inserted to the point where they connect with the EISA signals. +12. EISA specific cards will not work in an AT or an XT slot. Indicates to the slave device which bytes on the data bus contain valid data.33 MHz is specified as the maximum. FO R RE DI The EISA connector uses multiple rows of connectors. Signal Descriptions +5. Frequency Varies. 33% Duty Cycle. It is not intended to provide complete coverage of the EISA standard. 8. A low signal generates an NMI. but not BE2 or BE3. YB ET A . This is asserted when a DMAC has control of the bus. ST RI BU TIO N. Setting this low prevents the default ready timer from timing out. The slave device may then set it high again when it is ready to end the bus cycle. Holding this line low for too long can cause problems on some systems. This may cause problems with some bus controllers. The NMI signal can be masked on a PC. and the lower row contains the EISA extension.N Bus Address Latch Enable. EISA (Technical) 29 . EISA is upwardly compatible.

It may not be modified and re-distributed without the authors permission. the data is transferred during the CMD phase. 30 . EX16 EX32 EISA Slave Size 32. MAKx Master Acknowledge for slot x: Indicates that the bus master request (MREQx) has been granted. Interrupt Request. IORC I/O Read Command line. This is used by the slave device to inform the bus master that it is capable of 16 bit transfers. IRQ2 has the highest priority. CMD remains asserted from the falling edge of START until the end of the bus cycle.N OT IO16 FO EXRDY R RE DI EISA Slave Size 16. ST RI DRQx BU DAKx TIO N. DMA Acknowledge. After the start phase (see START). Generated by the ISA bus master when initiating a bus cycle. Command Phase. Asserting this signal prevents other bus masters from requesting control of the bus. I/O size 16. the cycle will end on the next rising edge of BCLK. EISA Ready. This signal indicates that the current bus cycle is in the command phase. They are bidrectional and tri-state.Chapter 1: Connector Menu EISA (Tech) Connector SD0-SD16 The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. DMA Request. If this signal is asserted. This is used by the slave device to inform the bus master that it is capable of 32 bit transfers. MASTER16 M/IO 16 bit bus master. The slave device drives this signal low to insert wait states. Generated by a 16 bit slave when addressed by a bus master. System Data lines. PR EL IM IN LOCK BETA RELEASE AR LAxx YB IRQx ET A . IOWC I/O Write Command line. Latchable Address lines.

The bus master will respond with MSBURST if it is also capable of burst cycles.N Oscillator. Indicates a memory write in the lower 1 MB area. This tells the slave device that the bus master is also capable of burst cycles. This is used to indicate whether the current bus cycle is a memory or an I/O operation.Chapter 1: Connector Menu EISA (Tech) Connector Memory/Input-Output. Generated when the refresh logic is bus master. PR EL IM IN BETA RELEASE AR System Address Lines. ST RI BU TIO N. and both signals should not be active simultaneously. SA0-SA19 SBHE SLBURST System Bus High Enable. this may cause problems with some bus controllers. MREQx Master Request for Slot x: This is a slot specific request for the device to become the bus master. It may not be modified and re-distributed without the authors permission. OSC REFRESH RESDRV Refresh. 16 bit The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. tri-state. FO R NOWS RE DI Master Burst. Most systems will ignore NOWS if CHRDY is active (low). The slave device uses this to indicate that it is capable of burst cycles. Indicates a 16 bit data transfer.318 MHz. SMWTC Standard Memory Write Commmand line. Indicates a memory read in the lower 1 MB area. Used to shorten the number of wait states generated by the default ready timer. The bus master asserts this signal in response to SLBURST. 14. This causes the bus cycle to end more quickly. since wait states will not be inserted. 31 . tristate. YB This signal goes low when the machine is powered up. Driving it low will force a system reset. MSBURST MWTC Memory Write Command line. 50% Duty Cycle. OT No Wait State. Frequency varies. ET A . However. M16 Memory Access. Slave Burst. MRDC Memory Read Command line. SMRDC Standard Memory Read Command line.

ST RI Write or Read. 32 .edu> Sources: Mark Sokos EISA page <http://www.umbc. This signal is low when the current bus cycle is in the start phase. Mark Sokos <msokos1@gl. TIO N. TC W/R Contributor: Joakim Ögren. Address and M/IO signals are decoded during this phase. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI Please send any comments to Joakim Ögren.edu/~msokos1/eisa.gl. Start Phase. Used to indicate if the current bus cycle is a read or a write operation.Chapter 1: Connector Menu START EISA (Tech) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. BU Terminal Count. ISBN 0-201-40995-X PR EL IM IN BETA RELEASE AR YB ET A . Notifies the cpu that that the last DMA data transfer operation is complete.umbc. Data is transferred during the command phase (indicated by CMD). 2nd Edition" by Tom Shanley and Don Anderson.txt> Sources: "Eisa System Architecture.

Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 +5V TRST +12V TMS TDI +5V INTA INTC +5V RESV01 +5V RESV03 GND03 GND05 RESV05 RESET +5V GNT GND08 RESV06 AD30 +3.3V Card 32/64 bit | optional | | ____ mandatory 32-bit pins 64-bit pins _____| |___| |||||||--||||||||||||||||||||||||||--|||||||||||||| DI ST RI BU TIO N.3 V) Grant PCI use Ground Reserved VDC Address/Data 30 +3. 33 PCI .3 VDC Address/Data 28 Address/Data 26 Ground Address/Data 24 Initialization Device Select +3. It may not be modified and re-distributed without the authors permission.3V01 AD28 AD26 GND10 AD24 IDSEL +3.3 VDC Address/Data 22 Address/Data 20 Ground Address/Data 18 +3.3 V) Reserved VDC (OPEN) (OPEN) Ground or Open (Key) (OPEN) (OPEN) Ground or Open (Key) Reserved VDC Reset +3.N OT FO (At the computer) R RE PCI Universal Card 32/64 bit ---------------------------------------------------------------| PCI Component Side (side B) | | | | | | optional | | ____ mandatory 32-bit pins 64-bit pins _____| |___| |||||||--|||||||||||||||||--|||||||--|||||||||||||| ^ ^ ^ ^ ^ ^ ^ ^ b01 b11 b14 b49 b52 b62 b63 b94 PCI 5V Card 32/64 bit | optional | | ____ mandatory 32-bit pins 64-bit pins _____| |___| ||||||||||||||||||||||||||--|||||||--|||||||||||||| PCI 3.3V Signal Rail +V I/O (+5 V or +3.3V Signal Rail +V I/O (+5 V or +3.3V PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu PCI Connector PCI=Peripheral Component Interconnect The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.3V03 AD22 AD20 GND12 AD18 Universal Description Test Logic Reset +12 VDC Test Mde Select Test Data Input +5 VDC Interrupt A Interrupt C +5 VDC Reserved VDC +3. 98+22 PIN EDGE CONNECTOR at the computer.

3 VDC Address/Data 6 Address/Data 4 Ground Address/Data 2 Address/Data 0 Signal Rail +V I/O (+5 V or +3.3 V) Parity 64 ??? Address/Data 62 Ground Address/Data 60 Address/Data 58 Ground Address/Data 56 Address/Data 54 Signal Rail +V I/O (+5 V or +3.3V10 AD13 AD11 GND19 AD9 C/BE0 +3.3V07 SDONE SBO GND17 PAR AD15 +3.Chapter 1: Connector Menu A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 AD16 +3.3 VDC Address or Data phase Ground Target Ready Ground Stop Transfer Cycle +3.3 V) Address/Data 40 Address/Data 38 Ground Address/Data 36 Address/Data 34 Ground Address/Data 32 Reserved PR EL IM IN BETA RELEASE AR YB ET A .3V AD52 AD50 GND AD48 AD46 GND AD44 AD42 +5V +3. Byte Enable 7 Command.3V11 AD6 AD4 GND21 AD2 AD0 +5V +3.3 V) Address/Data 52 Address/Data 50 Ground Address/Data 48 Address/Data 46 Ground Address/Data 44 Address/Data 42 Signal Rail +V I/O (+5 V or +3. Byte Enable 0 +3.3 VDC Address/Data 13 Address/Data 11 Ground Address/Data 9 Command.3V PAR64 AD62 GND AD60 AD58 GND AD56 AD54 +5V +3. 34 . Ground Command.3V REQ64 VCC11 VCC13 GND C/BE[7]# C/BE[5]# +5V +3. It may not be modified and re-distributed without the authors permission.3V AD40 AD38 GND AD36 AD34 GND AD32 RES PCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Byte Enable 5 Signal Rail +V I/O (+5 V or +3.3 VDC Snoop Done Snoop Backoff Ground Parity Address/Data 15 +3.N OT Address/Data 16 +3.3 V) Request 64 bit ??? +5 VDC +5 VDC FO R RE DI ST RI BU TIO N.3V05 FRAME GND14 TRDY GND15 STOP +3.

3V12 AD5 AD3 GND22 Ground Reserved PCI Connector -12 VDC Test Clock Ground Test Data Output +5 VDC +5 VDC Interrupt B Interrupt D Reserved +V I/O (+5 V or +3. Byte Enable 2 Ground Initiator Ready +3. 35 .3 V) Address/Data 31 Address/Data 29 Ground Address/Data 27 Address/Data 25 +3.3V AD17 C/BE2 GND13 IRDY +3. It may not be modified and re-distributed without the authors permission.3V09 C/BE1 AD14 GND18 AD12 AD10 GND20 (OPEN) (OPEN) AD8 AD7 +3.3 VDC Address/Data 5 Address/Data 3 Ground The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.3V C/BE3 AD23 GND AD21 AD19 +3.3 VDC Command.3V06 DEVSEL GND16 LOCK PERR +3.Chapter 1: Connector Menu A93 A94 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 GND RES -12V TCK GND TDO +5V +5V INTB INTD PRSNT1 RES PRSNT2 GND GND RES GND CLK GND REQ +5V AD31 AD29 GND AD27 AD25 +3.3 VDC System Error +3.3 VDC Device Select Ground Lock bus Parity Error +3. PR EL IM IN BETA RELEASE AR YB ET A . Byte Enable 1 Address/Data 14 Ground Address/Data 12 Address/Data 10 Ground GND (OPEN) Ground or Open (Key) GND (OPEN) Ground or Open (Key) Address/Data 8 Address/Data 7 +3.3VDC Command.N OT FO R RE DI ST RI BU TIO N.3V08 SERR +3.3V Signal Rail +V I/O (+5 V or +3.3 V) ?? (OPEN) (OPEN) Ground or Open (Key) (OPEN) (OPEN) Ground or Open (Key) Reserved VDC Reset Clock Ground Request +3.3 VDC Address/Data 17 Command. Byte Enable 3 Address/Data 23 Ground Address/Data 21 Address/Data 19 +3.

3V on 3.3V boards.com> YB Notes: Pin 63-94 exists only on 64 bit PCI implementations.3 V) Address/Data 47 Address/Data 45 Ground Address/Data 43 Address/Data 41 Ground Address/Data 39 Address/Data 37 Signal Rail +V I/O (+5 V or +3. 5V on 5V boards. Byte Enable 6 Command.3 V) Address/Data 59 Address/Data 57 Ground Address/Data 55 Address/Data 53 Ground Address/Data 51 Address/Data 49 Signal Rail +V I/O (+5 V or +3.3 V) Address/Data 35 Address/Data 33 Ground Reserved Reserved Ground .Chapter 1: Connector Menu B58 B59 B60 B61 B62 The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Source: ? PR EL IM IN Please send any comments to Joakim Ögren. PCI Connector +V I/O is 3. 36 AD1 VCC08 ACK64 VCC10 VCC12 Address/Data 1 +5 VDC Acknowledge 64 bit ??? +5 VDC +5 VDC .3V AD47 AD45 GND AD43 AD41 GND AD39 AD37 +5V +3. It may not be modified and re-distributed without the authors permission. Byte Enable 4 Ground Address/Data 63 Address/Data 61 Signal Rail +V I/O (+5 V or +3. ET A B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94 RES GND C/BE[6]# C/BE[4]# GND AD63 AD61 +5V +3.N OT FO R RE DI ST RI BU TIO N. and define signal rails on the Universal board.3V AD35 AD33 GND RES RES GND Reserved Ground Command. BETA RELEASE AR Contributor: Joakim Ögren.3V AD59 AD57 GND AD55 AD53 GND AD51 AD49 +5V +3. Phil Toms <ptoms@m4.

companies like Xilinx are offering PCI compliant designs which you can use as a starting point for your own projects.Chapter 1: Connector Menu PCI (Tech) Connector This section is currently based solely on the work by Mark Sokos. due to the higher clock speeds involved.N C/BE(x) OT CLK FO AD(x) R Signal Descriptions: RE DI ST RI This file is not intended to be a thorough coverage of the PCI standard. IDSEL INT(x) IRDY Initialization Device Select Interrupt Initiator Ready LOCK REQ Used to manage resource locks on the PCI bus. and. PR EL IM IN BETA RELEASE AR YB ET A . PCI (Technical) 37 . which will usually not be dealt with by an I/O card. Requests a PCI transfer. FRAME DEVSEL Device Select. Byte Enable. For a copy of the full PCI standard. Hobbyists are also warned that. Many companies are now making PCI prototyping cards. It is for informational purposes only. Clock. BU TIO N. contact: PCI Special Interest Group (SIG) PO Box 14070 Portland. are only briefly explained. Thus. 33 MHz maximum. It may not be modified and re-distributed without the authors permission. and is intended to give designers and hobbyists an overview of the bus so that they might be able to design their own PCI cards. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PCI cards are more difficult to design than ISA cards or cards for other slower busses. Used to indicate whether the cycle is an address phase or a data phase. OR 97214 1-800-433-5177 1-503-797-4207 Address/Data Lines. while memory operations. Request. I/O operations are explained in the most detail. for those fortunate enough to have access to FPGA programmers. Command.

38 Grant. . SERR STOP TCK Test Clock System Error. Requests the master to stop the current transfer cycle. SBO Snoop Backoff. This is done to reduce the overall number of pins on the PCI connector. Parity Error. indicates that permission to use PCI is granted. The Command lines (C/BE3 to C/BE0) indicate the type of bus transfer during the address phase. Snoop Done. The command lines are also used for byte enable lines. PCI (Tech) Connector Parity. Asserted by Target. Each cycle begins with an address phase followed by one or more data phases.N OT FO R RE SDONE DI ST RI RST BU PERR TIO N. Each device has its own timer (see the Latency Timer in the configuration space). This timer is set by the CPU as part of the configuration space. The same lines are used for address and data.Chapter 1: Connector Menu GNT PAR The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Reset. It may not be modified and re-distributed without the authors permission. Data phases may repeat indefinitely. Used for AD0-31 and C/BE0-3. TDI Test Data Input TDO Test Data Output TMS Test Mode Select TRDY Target Ready TRST Test Logic Reset The PCI bus treats all transfers as a burst operation. PR EL IM IN BETA RELEASE AR YB ET A . but are limited by a timer that defines the maximum amount of time that the PCI device may control the bus. Indicates an address parity error for special cycles or a system error.

no wait states. 39 .Chapter 1: Connector Menu C/BE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command Type Interrupt Acknowledge Special Cycle I/O Read I/O Write reserved reserved Memory Read Memory Write reserved reserved Configuration Read Configuration Write Multiple Memory Read Dual Address Cycle Memory-Read Line Memory Write and Invalidate PCI (Tech) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. and Configuration. Memory. AR PR EL IM IN ___ YB |________________________________| |_______________________________| ___ |___| CLK ___| |___| _______ FRAME |________________________________________________| AD A B C ______ ______________ ______ _____________ -------<______>---------<______________><______><_____________>--Address Data1 Data2 Data3 ______ ______________________________________________ -------<______><______________________________________________>--Command Byte Enable Signals C/BE BETA RELEASE ET A [1] ___ . PCI timing diagrams: ___ CLK FRAME AD ___| _______ |___| ___ |___| ___ ___ |___| R RE ___ The three basic types of transfers are I/O.N OT RI BU TIO N. FO |___| DI |___| ST ___ |___ _________ ___ ___ ___ ___ |___| [2] [3] ___ ___ ___ ___ |___| |___| |___| |___| |__ _________ |_________________________________| ______ _______ ______ ______ ______ -------<______><_______><______><______><______>--Address Data1 Data2 Data3 Data4 ______ _______________________________ -------<______><_______________________________>--Command Byte Enable Signals ____________ |_________________________________| _____________ C/BE IRDY TRDY DEVSEL ______________ PCI transfer cycle. Data is transferred on the rising edge of CLK. 4 data phases. It may not be modified and re-distributed without the authors permission.

B. . Address 00 04 08 0C 10-24 28 2C 30 Bit 32 16 15 0 Unit ID | Manufacturer ID Status | Command Class Code | Revision BIST | Header | Latency | CLS Base Address Register Reserved Reserved Expansion ROM Base Address PR EL IM IN BETA RELEASE AR A read or write to the system memory space. In the data phase. Memory Read (0110) and Memory Write (0111) Configuration Read (1010) and Configuration Write (1011) A read or write to the PCI device configuration space. ST Bus Cycles: RI BU |______________________________________________| TIO N. The AD lines contain a doubleword address. The AD lines contain a byte address (AD0 and AD1 must be decoded). |__________________________________| 40 .Chapter 1: Connector Menu ____________ IRDY PCI (Tech) Connector Wait _____ ___ |_______| ___ ___ Wait ______________________ TRDY The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. and the remaining AD lines are not used.N OT FO R RE DI The interrupt controller automatically recognizes and reacts to the INTA (interrupt acknowledge) command. The address port must be written first. the Intel CPU is limited to 16 bits of I/O space. and thus mirror themselves throughout the 16 bit I/O space). Data is transferred on the rising edge of CLK at points labelled A. which is 256 bytes in length. Interrupt Acknowledge (0000) Special Cycle (0001) AD15-AD0 0x0000 0x0001 0x0002 0x0003 to 0xFFFF Description Processor Shutdown Processor Halt x86 Specific Code Reserved I/O Read (0010) and I/O Write (0011) The PCI configuration space may also be accessed through I/O ports 0x0CF8 (Address) and 0x0CFC (Data). and C. AD8-10 are used for selecting the addressed unit a the malfunction unit. AD0 and AD1 do not need to be decoded. The Byte Enable lines (C/BE) indicate which bytes are valid. PCI allows 32 bits of address space. with wait states. it transfers the interrupt vector to the AD lines. YB ET A Input/Output device read or write operation. AD2-7 contain the doubleword address. which is further limited by some ISA cards that may also be installed in the machine (many ISA cards only decode the lower 10 bits of address space. PCI I/O ports may be 8 or 16 bits. It may not be modified and re-distributed without the authors permission. Wait ______ |_______| |_______________________| ______________ DEVSEL PCI transfer cycle. It is accessed in doubleword units. On IBM compatible machines. This limit assumes that the machine supports ISA or EISA slots in addition to PCI slots. AD0 and AD1 contain 0.

.txt> Sources: "Inside the PCI Local Bus" by Guy W.edu> Sources: Mark Sokos PCI page <http://www.edu/~msokos1/pci. Memory Write and Invalidate (1111) This indicates that a minimum of one cache line is to be transferred. followed by the most significant 32 bits. Byte. typically up to the end of a cache line. etc). but only a 32 bit physical address exists.N OT Bus Arbitration: FO R RE DI Two address cycles are necessary when a 64 bit address is used. TIO N. 41 . PCI BIOS: Contributor: Joakim Ögren. The least significant portion of the address is placed on the AD lines first. saving a cache write-back cycle. ISBN 0-201-8769-3 Please send any comments to Joakim Ögren. The second address cycle also contains the command for the type of transfer (I/O. 177-180 Sources: "The Indispensible PC Hardware Book" by Hans-Peter Messmer. which is beneficial for long sequential memory accesses. Mark Sokos <msokos1@gl. The PCI bus supports a 64 bit I/O address space.umbc. ST RI BU This is an extension of the memory read bus cycle. February 1994 v 19 p. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A This section is under construction. Memory.umbc.gl.Chapter 1: Connector Menu 34 38 3C 40-FF Reserved Reserved MaxLat|MnGNT | INT-pin | INT-line available for PCI unit PCI (Tech) Connector Multiple Memory Read (1100) The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. although this is not available on Intel based PCs due to limitations of the CPU. It is used to read large blocks of memory without caching. This allows main memory to be updated. Kendall. This section is under construction. Dual Address Cycle (1101) Memory-Read Line (1110) This cycle is used to read in more than two 32 bit data blocks. It is more efficient than normal memory read bursts for a long series of sequential memory accesses.

Chapter 1: Connector Menu VESA LocalBus (VLB) Connector VLB=VESA Local Bus. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT 58 PIN EDGE CONNECTOR MALE at the card. RE DI ST RI BU TIO N. (At the VESA LocalBus (VLB) card) FO R (At the computer) Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 Name D1 D3 GND D5 D7 D9 D11 D13 D15 GND D17 Vcc D19 D21 D23 D25 GND D27 D29 D31 A30 A28 A26 GND A24 A22 VCC A20 Description Data 1 Data 3 Ground Data 5 Data 7 Data 9 Data 11 Data 13 Data 15 Ground Data 17 +5 VDC Data 19 Data 21 Data 23 Data 25 Ground Data 27 Data 2 Data 31 Address 30 Address 28 Address 26 Ground Address 24 Address 22 +5 VDC Address 20 PR EL IM IN BETA RELEASE AR YB ET A . 58 PIN EDGE CONNECTOR FEMALE at the computer. VESA=Video Electronics Standards Association. 42 . It may not be modified and re-distributed without the authors permission.

Chapter 1: Connector Menu A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 A18 A16 A14 A12 A10 A8 GND A6 A4 WBACK# BE0# VCC BE1# BE2# GND BE3# ADS# LRDY# LDEV LREQ GND LGNT VCC ID2 ID3 ID4 LKEN# LEADS# D0 D2 D4 D6 D8 GND D10 D12 VCC D14 D16 D18 D20 GND D22 D24 D26 D28 D30 VCC A31 GND A29 A27 A25 A23 A21 A19 GND A17 Address 18 Address 16 Address 14 Address 12 Address 10 Address 8 Ground Address 6 Address 4 Write Back Byte Enable 0 +5 VDC Byte Enable 1 Byte Enable 2 Ground Byte Enable 3 Address Strobe Local Ready Local Device Local Request Ground Local Grant +5 VDC Identification 2 Identification 3 Identification 4 VESA LocalBus (VLB) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 43 . It may not be modified and re-distributed without the authors permission. Data 0 Data 2 Data 4 Data 6 Data 8 Ground Data 10 Data 12 +5 VDC Data 14 Data 16 Data 18 Data 20 Ground Data 22 Data 24 Data 26 Data 28 Data 30 +5 VDC Address 31 Ground Address 29 Address 27 Address 25 Address 23 Address 21 Address 19 Ground Address 17 PR EL IM IN BETA RELEASE AR YB ET A .N OT Local Enable Address Strobe FO R RE DI ST RI BU TIO N.

Chapter 1: Connector Menu B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 A15 VCC A13 A11 A9 A7 A5 GND A3 A2 n/c RESET# DC# M/IO# W/R# RDYRTN# GND IRQ9 BRDY# BLAST# ID0 ID1 GND LCLK VCC LBS16# Address 15 +5 VDC Address 13 Address 11 Address 9 Address 7 Address 5 Ground Address 3 Address 2 Not connected Reset Data/Command Memory/IO Write/Read Ready Return Ground Interrupt 9 Burst Ready Burst Last Identification 0 Identification 1 Ground Local Clock +5 VDC Local Bus Size 16 VESA LocalBus (VLB) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.edu> Please send any comments to Joakim Ögren.hardware. It may not be modified and re-distributed without the authors permission.* FAQ Part 4 <ftp://rtfm.answers/pc-hardware-faq/part1>.wpi. PR EL IM IN BETA RELEASE AR YB ET A .sys.pc. 44 .edu/pub/usenet/news.N OT FO R RE DI ST RI BU TIO N.ibm. Contributor: Joakim Ögren Source: comp.mit. maintained by Ralph Valentino <ralf@alum.

and does not need to connect to the ISA portion of the bus. Indicates the end of the current burst transfer. it multiplexes the existing pins. The 64 bit expansion of the bus (optional) does not add additional pins or connectors. ID0-ID4 Identification Signals. The VLB Burst cycle consists of an address phase followed by four data phases. It is not intended to provide complete coverage of the VLB standard. This file is intended to provide a basic functional overview of the Vesa Local Bus. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Signal Descriptions A2-A31 Address Bus ADS Address Strobe BE0-BE3 Byte Enable. so that hobbyists and amateurs can design their own VLB compatible cards.N Burst Last. ID0 ID1 ID4 CPU Bus WidthBurst 0 0 0 (res) PR EL IM IN BETA RELEASE AR Data/Command. Used with M/IO and W/R to indicate the type of cycle. INTA sequence Halt/Special (486) I/O Read I/O Write Instruction Fetch Halt/Shutdown (386) Memory Read Memory Write YB ET A BRDY . Indicates a VLB Burst Cycle. Instead. BLAST Burst Ready. OT FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission. the VLB is separate. Valid bytes are indicated by *BE(x) signals.Chapter 1: Connector Menu VESA LocalBus (VLB) (Tech) Connector This section is currently based solely on the work by Mark Sokos. so that adapter cards may use both. However. which will complete with *BRDY. Indicates that the 8 data lines corresponding to each signal will deliver valid data. D0-D31 D/C M/IO 0 0 0 0 1 1 1 1 D/C 0 0 1 1 0 0 1 1 W/R 0 1 0 1 0 1 0 1 Data Bus. VLB Connectors are usually inline with ISA connectors. The 32 bit VLB bus does not use the 64 bit signals shown in the above pinouts. VESA LocalBus (VLB) (Technical) 45 .

ID2 Indicates wait: IRQ9 Local Enable Address Strobe. Used by VLB Master to gain control of the bus. LREQ M/IO Local Request. May precede LRDY by one cycle.3 MHz 1 = less than 33. ST RI 0 = 1 wait cycle (min) 1 = no wait ID3 Indicates bus speed: 0 = greater than 33. OT LCLK FO R RE LEADS DI Interrupt Request.N Local Clock. Also used for cache invalidation signal. This allows standalone VLB adapters (not connected to ISA portion of the bus) to have one IRQ. up to 50 MHz.3 MHz BU TIO N. Connected to IRQ9 on ISA bus. LDEV Local Ready. the VLB device must pull this line low to indicate that it is a VLB device. Set low by VLB master (not CPU). and control is being transferred to the new VLB master. 66 MHz is allowed for on-board devices. Runs at the same frequency as the cpu. It may not be modified and re-distributed without the authors permission. BETA RELEASE AR LGNT YB LRDY ET A Local Device: When appropriate address and M/IO signals are present on the bus. See D/C for signal description. RDYRTN RESET Ready Return. . Used by slave device to indicate that it has a transfer width of only 16 bits. 46 . The VLB controller will then use the VLB bus for the transfer. This signal is only used for single cycle transfers. Indicates that an *LREQ signal has been granted. *BRDY is used for burst transfers.Chapter 1: Connector Menu 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 (res) 486 486 386 386 (res) 486 16/32 16/32 16/32 16/32 16/32/64 Burst Possible Read Burst None None Read/Write Burst VESA LocalBus (VLB) (Tech) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Indicates that the VLB device has completed the cycle. LBS16 Local Bus Size 16. PR EL IM IN Local Grant. Memory/IO. Indicates VLB cycle has been completed.

umbc. See D/C for signal description. Multiplexed with address bus. 64-bit Expansion Signals ACK64 Acknowledge 64 bit transfer. Indicates that the device can perform the requested 64 bit transfer cycle. Resets all VLB devices. Mark Sokos <msokos1@gl. ISBN 0-201-8769-3 Please send any comments to Joakim Ögren.gl. Local Bus Size 64 bits. W/R Data D32-33 _____________________________ _____________________________ PR EL IM IN ______ AR |_______________| |_______________| _____________________________ *ACK64 D0-D31 |______________| _______________ --------------------<_______________>------------- _____________________ _____________ LRDY |______________| Contributor: Joakim Ögren. BETA RELEASE ET A . It may not be modified and re-distributed without the authors permission. W/R M/IO. BE4-BE7 D32-D63 LBS64 W/R Write/Read. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. VESA LocalBus (VLB) (Tech) Connector Write Back.edu> Sources: Mark Sokos VLB page <http://www.Chapter 1: Connector Menu Reset. 47 WBACK . Indicates which bytes are valid (similar to BE0-BE3).umbc.edu/~msokos1/vlb. 64 Bit Data Transfer Timing Diagram: Address Phase _______ LCLK *ADS A2-A31 D34-D63 ___| ____ |_______| |_______| Data Phase _______ OT FO R ______________________________________ _______________ _______________ ----<_______________><_______________>------------Address Data D34-D63 _____ *LDEV *LBS64 _____ YB _______________ _______________ D/C ----<_______________><_______________>------------M/IO.N |_______| RE _______ |_______ DI ST RI BU TIO N. Byte Enable. Used by VLB Master to indicate that it desires a 64 bit transfer.txt> Sources: "The Indispensible PC Hardware Book" by Hans-Peter Messmer. Upper 32 bits of data bus.

It may not be modified and re-distributed without the authors permission. (At the backplane) Pin Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 Z9 Z10 Z11 Z12 Z13 Z14 Z15 Z16 Z17 Z18 Z19 Z20 Z21 Z22 Z23 Z24 Z25 Z26 Z27 Z28 Z29 Z30 Z31 Z32 Z33 Z34 Z35 Z36 Z37 Z38 Z39 Z40 Z41 Name GND GND GND GND GND GND GND GND GND GND GND KEY KEY KEY GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Description Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Keyed (no pin) Keyed (no pin) Keyed (no pin) Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu CompactPCI Connector PCI=Peripheral Component Interconnect. CompactPCI is a version of PCI adapted for industrial and/or embedded applications. 7x47 PIN (IEC917 and IEC1076-4-101) CONNECTOR at the device (card). ST (At the device (card)) RI BU TIO N.N OT FO R RE DI 7x47 PIN (IEC917 and IEC1076-4-101) CONNECTOR at the backplane. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. CompactPCI 48 .

3 VDC System Error +3. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .3V SERR# 3.3 VDC Address/Data 7) +3.N OT FO R RE DI ST RI BU TIO N.3 VDC or +5 VDC Command: Byte Enable Address/Data 63 Address/Data 59 Address/Data 56 Address/Data 52 Address/Data 49 Address/Data 45 Address/Data 42 Address/Data 38 Address/Data 35 Bused Reserved (don't use) Bused Reserved (don't use) Bused Reserved (don't use) User Defined User Defined User Defined User Defined User Defined -12 VDC +5 VDC Interrupt B Ground Bused Reserved (don't use) CompactPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.3 VDC Address/Data 1) +5 VDC Clock ?? MHz Clock ?? MHz Clock ?? MHz +3.3V AD(7) 3.3V DEVSEL# 3.3V AD(1) 5V CLK1 CLK2 CLK4 V(I/O) C/BE(5)# AD(63) AD(59) AD(56) AD(52) AD(49) AD(45) AD(42) AD(38) AD(35) BRSV BRSV BRSV USR USR USR USR USR -12V 5V INTB# GND BRSV Ground Ground Ground Ground Ground Ground +5 VDC Test Clock Interrupt A Bused Reserved (don't use) Bused Reserved (don't use) Request PCI transfer Address/Data 30 Address/Data 26 Command: Byte Enable Address/Data 21 Address/Data 18 Keyed (no pin) Keyed (no pin) Keyed (no pin) +3.Chapter 1: Connector Menu Z42 Z43 Z44 Z45 Z46 Z47 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 B1 B2 B3 B4 B5 GND GND GND GND GND GND 5V TCK INTA# BRSV BRSV REQ# AD(30) AD(26) C/BE(3)# AD(21) AD(18) KEY KEY KEY 3. 49 .3 VDC Address/Data 12 +3.3 VDC Device Select +3.3V AD(12) 3.

PR EL IM IN BETA RELEASE AR YB ET A .3 VDC or +5 VDC Snoop Backoff CompactPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.3V AD(28) V(I/O) AD(23) 3.3 VDC or +5 VDC Reset +3.3 VDC or +5 VDC Address/Data 23 +3. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N.Chapter 1: Connector Menu B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 GND AD(29) GND IDSEL GND AD(17) KEY KEY KEY FRAME# GND SDONE GND AD(15) GND AD(9) GND AD(4) 5V REQ64# GND CLK3 GND BRSV GND AD(62) GND AD(55) GND AD(48) GND AD(41) GND AD(34) GND BRSV GND USR USR USR USR USR TRST# TMS INTC# V(I/O) RST 3.3V AD(16) KEY KEY KEY IRDY# V(I/O) SBO# Ground Address/Data 29 Ground Initialization Device Select Ground Address/Data 17 Keyed (no pin) Keyed (no pin) Keyed (no pin) Address or Data phase Ground Snoop Done Ground Address/Data 15 Ground Address/Data 9) Ground Address/Data 4) +5 VDC Ground Clock ?? MHz Ground Bused Reserved (don't use) Ground Address/Data 62 Ground Address/Data 55 Ground Address/Data 48 Ground Address/Data 41 Ground Address/Data 34 Ground Bused Reserved (don't use) Ground User Defined User Defined User Defined User Defined User Defined Test Logic Reset Test Mode Select Interrupt C +3. 50 .3 VDC Address/Data 28 +3.3 VDC Address/Data 16 Keyed (no pin) Keyed (no pin) Keyed (no pin) Initiator Ready +3.

It may not be modified and re-distributed without the authors permission.3 VDC or +5 VDC Address/Data 33 Power Supply Status FAL (CompactPCI specific) Power Supply Status DEG (CompactPCI specific) Push Button Reset (CompactPCI specific) User Defined User Defined User Defined User Defined User Defined FO R RE DI ST RI BU TIO N.3V AD(3) V(I/O) BRSV REQ1# SYSEN# GNT3# C/BE(7) V(I/O) AD(61) V(I/O) AD(54) V(I/O) AD(47) V(I/O) AD(40) V(I/O) AD(33) FAL# DEG# PRST# USR USR USR USR USR +12V TDO 5V INTP GND CLK GND AD(25) GND AD(20) GND KEY KEY KEY GND STOP# GND PAR GND AD(11) M66EN AD(6) 5V AD(0) 3.3 VDC Grant Grant Request PCI transfer Ground 51 BETA RELEASE AR YB ET A .3 VDC Address/Data 14 +3.3 VDC or +5 VDC Address/Data 54 +3.N +12 VDC Test Data Output +5 VDC OT Grant Command: Byte Enable +3. .3V GNT1# GNT2# REQ4# GND +3.3 VDC or +5 VDC Bused Reserved (don't use) Request PCI transfer CompactPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.3 VDC or +5 VDC Address/Data 40 +3.3 VDC or +5 VDC Address/Data 47 +3.3 VDC Address/Data 3) +3.3 VDC or +5 VDC Address/Data 61 +3. Ground PR EL IM IN Ground Address/Data 25 Ground Address/Data 20 Ground Keyed (no pin) Keyed (no pin) Keyed (no pin) Ground Stop transfer cycle Ground Parity for AD0-31 & C/BE0-3 Ground Address/Data 11 Address/Data 6) +5 VDC Address/Data 0) +3.3 VDC or +5 VDC Address/Data 8) +3.3V AD(14) V(I/O) AD(8) 3.Chapter 1: Connector Menu C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 3.

N OT FO R RE DI ST RI BU TIO N.Chapter 1: Connector Menu D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 E41 C/BE(4)# GND AD(58) GND AD(51) GND AD(44) GND AD(37) GND REQ5# GND REQ6# USR USR USR USR USR 5V TDI INTD# INTS GNT# AD(31) AD(27) AD(24) AD(22) AD(19) C/BE(2)# KEY KEY KEY TRDY# LOCK# PERR# C/BE(1)# AD(13) AD(10) C/BE(0)# AD(5) AD(2) ACK64# 5V REQ2# REQ3# GNT4# C/BE(6)# PAR64 AD(60) AD(57) AD(53) AD(50) AD(46) AD(43) AD(39) AD(36) AD(32) GNT5# BRSV Command: Byte Enable Ground Address/Data 58 Ground Address/Data 51 Ground Address/Data 44 Ground Address/Data 37 Ground Request PCI transfer Ground Request PCI transfer User Defined User Defined User Defined User Defined User Defined +5 VDC Test Data Input Interrupt D Grant Address/Data 31 Address/Data 27 Address/Data 24 Address/Data 22 Address/Data 19 Command: Byte Enable Keyed (no pin) Keyed (no pin) Keyed (no pin) Target Ready Lock resource Parity Error Command: Byte Enable Address/Data 13 Address/Data 10 Command: Byte Enable Address/Data 5) Address/Data 2) +5 VDC Request PCI transfer Request PCI transfer Grant Command: Byte Enable Address/Data 60 Address/Data 57 Address/Data 53 Address/Data 50 Address/Data 46 Address/Data 43 Address/Data 39 Address/Data 36 Address/Data 32 Grant Bused Reserved (don't use) CompactPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 52 . It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .

umbc.compactpci.0 <http://www. Kendall.gl.N OT FO R RE DI ST RI BU TIO N.com/cspec. Contributor: Joakim Ögren Sources: CompactPCI specifications v1. February 1994 v 19 p. Byte. It may not be modified and re-distributed without the authors permission.com/> Sources: Mark Sokos PCI page <http://www.edu/~msokos1/pci.txt> Sources: "Inside the PCI Local Bus" by Guy W.htm> at CompactPCI's homepage <http://www. 53 . 177-180 PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu E42 E43 E44 E45 E46 E47 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 F44 F45 F46 F47 GNT6# USR USR USR USR USR GND GND GND GND GND GND GND GND GND GND GND KEY KEY KEY GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Grant User Defined User Defined User Defined User Defined User Defined Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Keyed (no pin) Keyed (no pin) Keyed (no pin) Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground CompactPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.compactpci.

Please send any comments to Joakim Ögren. 54 . It may not be modified and re-distributed without the authors permission.The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI Chapter 1: Connector Menu AR Sources: "The Indispensible PC Hardware Book" by Hans-Peter Messmer. PR EL IM IN YB ET A . ISBN 0-201-8769-3 BETA RELEASE ST RI BU CompactPCI Connector TIO N.

Since CompactPCI is based on PCI you should first refer to the PCI standard.INTA# .Chapter 1: Connector Menu CompactPCI (Tech) Connector This section does not currently contain so much in depth information as I would like.N OT The connector has 7 columns with 47 rows.ACK64# PR EL IM IN BETA RELEASE AR The following signals must be terminated: .Row 1-25: 32-bit PCI .REQ64# .PERR# .INTD# . contact: PCI Industrial Computer Manufacturers Group (PICMG) c/o Roger Communications 301 Edgewater place Suite 220 Wakewater MA01880 Phone: 1-617-224-1100 Fax: 1-617-224-1239 The following signals must be terminated if used: .Row 26-28 and 40-42: Primarily implemented on System Slot boards.C/BE4#-C/BE7# .STOP# . CompactPCI (Technical) 55 .Row 26-47: Additional pins for 64-bit PCI (System Slot boards must use it).INTC# . FO R A CompactPCI system is composed of up to eight CompactPCI card locations: .PAR .Up to seven Peripheral Slots RE Overview: DI ST RI BU TIO N.IDSEL .RST# YB ET A . . For a copy of the full CompactPCI standard.IRDY# .SB0# .LOCK# .AD0-31 .C/BE0#-C/BE3# . This only explains the extensions CompactPCI specifies.SERR# .TRDY# . They are divided into groups: . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.SDOBE .AD32-AD63 .One System Slot .FRAME# .INTB# .DEVSEL# . It may not be modified and re-distributed without the authors permission.

Chapter 1: Connector Menu .3V AD(16) KEY KEY KEY IRDY# V(I/O) SBO# 3.3V AD(3) V(I/O) BRSV REQ1# SYSEN# GNT3# C/BE(7 ) V(I/O) AD(61) V(I/O) AD(54) V(I/O) AD(47) V(I/O) AD(40) V(I/O) AD(33) FAL# 12V DO 5V INTP GND CLK GND AD(25) GND AD(20) GND KEY KEY KEY GND STOP# GND PAR GND AD(11) M66EN AD(6) 5V AD(0) 3.3V AD(7) 3.3V SERR# 3.ACK64# PR EL IM IN BETA RELEASE AR YB ET A .TMS . It may not be modified and re-distributed without the authors permission.PAR64# The following signals do no require a stub termination: .3V GNT1# GNT2# REQ4# GND C/BE(4)# GND AD(58) GND AD(51) GND AD(44) GND AD(37) GND REQ5# RE Connector: 5V TDI INTD# INTS GNT# AD(31) AD(27) AD(24) AD(22) AD(19) C/BE(2)# KEY KEY KEY TRDY# LOCK# PERR# C/BE(1)# AD(13) AD(10) C/BE(0)# AD(5) AD(2) ACK64# 5V REQ2# REQ3# GNT4# C/BE(6)# PAR64 AD(60) AD(57) AD(53) AD(50) AD(46) AD(43) AD(39) AD(36) AD(32) GNT5# DI The System Slot board must pullup the following signals (even if not used): .GNT# .CLK . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND GND GND GND GND GND GND GND GND GND GND KEY KEY KEY GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 5V TCK INTA# BRSV BRSV REQ# AD(30) AD(26) C/BE(3)# AD(21) AD(18) KEY KEY KEY 3.3V AD(14) V(I/O) AD(8) 3.TDO . 56 .REQ# .3V AD(1) 5V CLK1 CLK2 CLK4 V(I/O) C/BE(5)# AD(63) AD(59) AD(56) AD(52) AD(49) AD(45) AD(42) AD(38) AD(35) BRSV -12V 5V INTB# GND BRSV GND AD(29) GND IDSEL GND AS(17) KEY KEY KEY FRAME# GND SDONE GND AD(15) GND AD(9) GND AD(4) 5V REQ64# GND CLK3 GND BRSV GND AD(62) GND AD(55) GND AD(48) GND AD(41) GND AD(34) GND TRST# TMS INTC# V(I/O) RST 3.3V AD(28) V(I/O) AD(23) 3.TCK .TRST# CompactPCI (Tech) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.3V AD(12) 3.REQ64# .N OT FO R ST RI GND GND GND GND GND GND GND GND GND GND GND KEY KEY KEY GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND BU TIO N.3V DEVSEL# 3.TDI# .

edu/~msokos1/pci. Byte.umbc. Kendall.compactpci. 57 .Chapter 1: Connector Menu 41 42 43 44 45 46 47 GND GND GND GND GND GND GND Z BRSV BRSV USR USR USR USR USR A BRSV GND USR USR USR USR USR B DEG# PRST# USR USR USR USR USR C GND REQ6# USR USR USR USR USR D CompactPCI (Tech) Connector BRSV GNT6# USR USR USR USR USR E GND GND GND GND GND GND GND F The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.umbc.N Info: CompactPCI .com/vtc/pavj1/pavjp.htm> at CompactPCI's homepage <http://www. Mark Sokos <msokos1@gl.An Open Industrial Computer Standard <http://www. ISBN 0-201-8769-3 Please send any comments to Joakim Ögren.htm> article by Joseph S.com> OT FO R RE FAL DI ST RI BU TIO N. PR EL IM IN BETA RELEASE AR YB ET A . Signal Descriptions: PRST Push Button Reset. DEG Power Supply Status DEG Power Supply Status FAL SYSEN System Slot Identification Contributor: Joakim Ögren. February 1994 v 19 p.compactpci.gl.com/cspec.com/> Sources: Mark Sokos PCI page <http://www. Pavlat <jpavlat@prolog.eetoolbox. 177-180 Sources: "The Indispensible PC Hardware Book" by Hans-Peter Messmer. It may not be modified and re-distributed without the authors permission.edu> Sources: CompactPCI specifications v1.txt> Sources: "Inside the PCI Local Bus" by Guy W.0 <http://www.

Chapter 1: Connector Menu IndustrialPCI Connector PCI=Peripheral Component Interconnect.3 VDC Stop BETA RELEASE RE Note 1 1 1 1 1 58 (At the device (card)) DI ST RI BU The IPCI connector has three parts: . (At the backplane) UNKNOWN CONNECTOR at the backplane.3 VDC Address 2 Address 6 Ground Address 10 Address 13 Ground Snoop Done Ground Indicate Address or Data phase Address 18 Ground +5 VDC Address 24 Address 27 Ground Request 2 Ground 33 or 66 MHz Clock FO System Slot (Middle) R .Optional 60 pin PCI 64 bit extension (Top) .Mandatory 120 pin PCI 32 bit (Middle) . Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 B1 B2 B3 B4 B5 B6 B7 B8 B9 Name +3. IndustrialPCI is a version of PCI adapted for industrial and/or embedded applications.3 VDC Request 64 ??? Address 3 +5 VDC Address 8 +3.3V AD14 PAR +3. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. UNKNOWN CONNECTOR at the device (card).Optional 60 pin Custom I/O (Bottom) TIO N.3V REQ64# AD3 +5V AD8 +3.3V STOP# PR EL IM IN AR Description +3.N OT ET A YB Ground +3. IndustrialPCI (IPCI) .3V AD2 AD6 GND AD10 AD13 GND SDONE GND FRAME# AD18 GND +5V AD24 AD27 GND REQ2 GND CLK1 CLK2 GND CLK3 CLK4 +3. It may not be modified and re-distributed without the authors permission.3 VDC Address 14 Parity +3.

3 or +5 VDC Resource Lock Test Logic Ready Address 16 Address 20 +5 VDC +5 VDC Address 26 Address 29 Request 1 Request 3 +3.3 VDC IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.3V AD12 AD15 V(I/O) LOCK# TRDY# AD16 AD20 +5V +5V AD26 AD29 REQ1 REQ3 V(I/O) X2 X5 +3.3 VDC Address 12 Address 15 +3.3V Command.Chapter 1: Connector Menu B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 C/BE2# V(I/O) AD21 +3.3 VDC Grant 3 Reset Non Maskable Interrupt Reserved (6) +5 VDC Universal Serial Bus (USB)(+) Acknowledge 64 ??? Ground Address 7 Address 9 Address 11 Ground System Error Parity Error Device Select Ground Address 19 Address 22 Ground Address 25 Ground Reserved (1) Grant 2 Request 4 Sleep/Serial Data (I2C) Reserved (4) Interrupt D Interrupt B +5 VDC Universal Serial Bus (USB)(-) Address 0 Address 4 Command.N OT FO R ET A AR YB PR EL IM IN BETA RELEASE RE DI 1 1 1 1 3 1 1 1 1 1 1 ST : 2 RI BU TIO N.3 or +5 VDC Address 21 +3.3 or +5 VDC Reserved (2) Reserved (5) +3.3 or +5 VDC Address 28 Address 31 +3. It may not be modified and re-distributed without the authors permission.3V V(I/O) AD28 AD31 +3. Byte Enable 2 +3. Byte Enable 0 +3.3 VDC +3. 59 .3V GNT3 RST# NMI# X6 +5V RSTIN# USB+ ACK64# GND AD7 AD9 AD11 GND SERR# PERR# DEVSEL# GND AD19 AD22 GND AD25 GND X1 GNT2 REQ4 SLEEP#/SDAT X4 INTD# INTB# +5V USBAD0 AD4 C/BE0# +3. 1 .

Byte Enable 1 Snoop Backoff +5 VDC Initiator Ready Address 17 Ground Address 23 Command.3V AD2 AD6 GND AD10 AD13 GND SDONE GND FRAME# AD18 GND +5V AD24 AD27 GND REQ2 CLKM CLK1 CLK2 GND CLK3 CLK4 +3. Byte Enable 3 Ground Address 30 Grant 1 +5 VDC Grant 4 Reserved (3) Ground Interrupt C -12 VDC +12 VDC 1 3 IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.7 KB ohm. 1 1 R Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 B1 Name +3.3V REQ64# PR EL IM IN Description +3. .3 VDC Request 64 ??? BETA RELEASE RE 1 Note 1 1 1 1 60 DI ST RI BU TIO N. if not supported by the System Slot (CPU). 2 = Pullup resistor of 330 ohm on the System Slot (CPU). It may not be modified and re-distributed without the authors permission. FO YB ET A AR 33 or 66 MHz Clock Ground +3.N Module Bus Slot (Middle) OT 1 = Pullup resistor of 2. 3 = Pullup resistor of 4.Chapter 1: Connector Menu D22 D23 D24 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 INTA# ICPEN#/SCLK OSC (PWDN) AD1 AD5 GND M66EN GND C/BE1# SBO# +5V IRDY# AD17 GND AD23 C/BE3# GND AD30 GNT1 +5V GNT4 X3 GND INTC# -12V +12V VBATT Interrupt A ICPEN/Serial Clock (I2C) Address 1 Address 5 Ground Enable 66Mhz PCI-bus Ground Command.7 kOhm on the System Slot (CPU).3 VDC Address 2 Address 6 Ground Address 10 Address 13 Ground Snoop Done Ground Indicate Address or Data phase Address 18 Ground +5 VDC Address 24 Address 27 Ground Request 2 .

3 VDC Grant 3 Reset Non Maskable Interrupt Reserved (6) +5 VDC IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Byte Enable 2 +3.3 VDC +3.3 VDC Address 12 Address 15 +3.3V STOP# C/BE2# V(I/O) AD21 +3.N PR EL IM IN AR BETA RELEASE RE : 1 1 1 1 1 1 1 1 1 DI ST RI BU TIO N.3 or +5 VDC Resource Lock Test Logic Ready Address 16 Address 20 +5 VDC +5 VDC R OT FO YB ET A . Byte Enable 0 +3.3 VDC Address 14 Parity +3.3V V(I/O) AD28 AD31 +3.3 VDC Stop Command.3V GNT3 RST# NMI# X6 +5V RSTIN# USB+ ACK64# GND AD7 AD9 AD11 GND SERR# PERR# DEVSEL# GND AD19 AD22 GND AD25 GND X1 GNT2 REQ4 SLEEP#/SDAT X4 INTD# INTB# +5V USBAD0 AD4 C/BE0# +3.3 or +5 VDC Address 28 Address 31 +3. 61 .Chapter 1: Connector Menu B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 AD3 +5V AD8 +3.3 or +5 VDC Address 21 +3.3V AD14 PAR +3.3V AD12 AD15 V(I/O) LOCK# TRDY# AD16 AD20 +5V +5V Address 3 +5 VDC Address 8 +3. It may not be modified and re-distributed without the authors permission. 1 Universal Serial Bus (USB)(+) Acknowledge 64 ??? Ground Address 7 Address 9 Address 11 Ground System Error Parity Error Device Select Ground Address 19 Address 22 Ground Address 25 Ground Reserved (1) Grant 2 Request 4 Sleep/Serial Data (I2C) Reserved (4) Interrupt D Interrupt B +5 VDC Universal Serial Bus (USB)(-) Address 0 Address 4 Command.

3 or +5 VDC Reserved (2) Reserved (5) +3. OT FO R 1 = Pullup resistor of 2. 62 .3 VDC Interrupt A ICPEN/Serial Clock (I2C) Address 1 Address 5 Ground Enable 66Mhz PCI-bus Ground Command.7 kOhm on the System Slot (CPU). Byte Enable 1 Snoop Backoff +5 VDC Initiator Ready Address 17 Ground Address 23 Command.3 VDC Address 2 Address 6 Ground Address 10 Address 13 Ground Snoop Done Ground Indicate Address or Data phase Address 18 Ground +5 VDC Address 24 Address 27 Ground IDSEL0 Ground 33 or 66 MHz Clock ET A .3V AD2 AD6 GND AD10 AD13 GND SDONE GND FRAME# AD18 GND +5V AD24 AD27 GND IDSEL0 GND CLK1 YB Description +3. Card Slot (Middle) Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 Name +3.3V INTA# ICPEN#/SCLK OSC (PWDN) AD1 AD5 GND M66EN GND C/BE1# SBO# +5V IRDY# AD17 GND AD23 C/BE3# GND AD30 GNT1 +5V GNT4 X3 GND INTC# -12V +12V VBATT Address 26 Address 29 Request 1 Request 3 +3.N PR EL IM IN AR BETA RELEASE RE DI 1 1 1 Note 1 1 1 ST RI BU 1 3 TIO N. It may not be modified and re-distributed without the authors permission. Byte Enable 3 Ground Address 30 Grant 1 +5 VDC Grant 4 Reserved (3) Ground Interrupt C -12 VDC +12 VDC 1 1 IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Chapter 1: Connector Menu D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 AD26 AD29 REQ1 REQ3 V(I/O) X2 X5 +3.

3 VDC Address 12 Address 15 +3.3 VDC Request 64 ??? Address 3 +5 VDC Address 8 +3.3 VDC Stop Command.3 VDC +3.3 or +5 VDC Address 21 +3.3V V(I/O) AD28 AD31 +3.3 or +5 VDC Address 28 Address 31 +3.3V AD12 AD15 V(I/O) Ground Ground Ground Ground +3.3V AD14 PAR +3.3 VDC Ground Reset Non Maskable Interrupt Reserved (6) +5 VDC IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N PR EL IM IN AR YB BETA RELEASE RE : 1 1 1 1 1 1 DI ST 1 RI BU TIO N. Byte Enable 2 +3. It may not be modified and re-distributed without the authors permission.3V REQ64# AD3 +5V AD8 +3. Byte Enable 0 +3.3V STOP# C/BE2# V(I/O) AD21 +3.3 VDC Address 14 Parity +3. 63 . 1 FO R Universal Serial Bus (USB)(+) Acknowledge 64 ??? Ground Address 7 Address 9 Address 11 Ground System Error Parity Error Device Select Ground Address 19 Address 22 Ground Address 25 Ground Reserved (1) Initialization Device Select 1 Ground Sleep/Serial Data (I2C) Reserved (4) Interrupt D Interrupt B +5 VDC Universal Serial Bus (USB)(-) Address 0 Address 4 Command.3V GND RST# NMI# X6 +5V RSTIN# USB+ ACK64# GND AD7 AD9 AD11 GND SERR# PERR# DEVSEL# GND AD19 AD22 GND AD25 GND X1 IDSEL1 GND SLEEP#/SDAT X4 INTD# INTB# +5V USBAD0 AD4 C/BE0# +3.3 or +5 VDC OT ET A .Chapter 1: Connector Menu A20 A21 A22 A23 A24 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 D1 D2 D3 D4 D5 D6 D7 GND GND GND GND +3.

3 or +5 VDC Reserved (2) Reserved (5) +3.3 VDC Interrupt A ICPEN/Serial Clock (I2C) Address 1 Address 5 Ground Enable 66Mhz PCI-bus Ground Command. It may not be modified and re-distributed without the authors permission. 64 .Chapter 1: Connector Menu D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 LOCK# TRDY# AD16 AD20 +5V +5V AD26 AD29 REQ1 IDSEL2 V(I/O) X2 X5 +3.3 or +5 VDC +3. 64-bit PCI (Top) Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 Name GND X10 AD35 AD38 AD42 V(I/O) V(I/O) AD52 AD56 AD60 AD63 GND X7 Description Ground Reserved (10) Address 35 Address 38 Address 42 +3.3 or +5 VDC Address 52 Address 56 Address 60 Address 63 Ground Reserved (7) AR YB PR EL IM IN Note 2 2 2 2 2 2 2 BETA RELEASE RE 1 1 1 DI ST RI BU 1 TIO N.7 kOhm on the System Slot (CPU).3V INTA# ICPEN#/SCLK OSC (PWDN) AD1 AD5 GND M66EN GND C/BE1# SBO# +5V IRDY# AD17 GND AD23 C/BE3# GND AD30 GNT1 +5V GNT4 X3 GND INTC# -12V +12V VBATT Resource Lock Test Logic Ready Address 16 Address 20 +5 VDC +5 VDC Address 26 Address 29 Request 1 Initialization Device Select 2 +3. Byte Enable 1 Snoop Backoff +5 VDC Initiator Ready Address 17 Ground Address 23 Command. 1 3 R FO ET A .N OT 1 = Pullup resistor of 2. Byte Enable 3 Ground Address 30 Grant 1 +5 VDC Grant 4 Reserved (3) Ground Interrupt C -12 VDC +12 VDC 1 1 IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

N ET A YB AR 2 = Pullup resistor of 2. . .3V bus system) on the backplane.3 or +5 VDC Command. Byte Enable 7 Reserved (9) Address 33 Address 37 Ground Address 45 Address 47 Address 50 Address 55 Ground Address 62 Command. Byte Enable 5 Reserved (12) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.2 kOhm (3.3 or +5 VDC Address 41 Ground Address 48 Address 51 Ground Address 59 +3.7 kOhm (5V bus system) or 8. It may not be modified and re-distributed without the authors permission. Byte Enable 4 Reserved (11) Ground Address 34 +3.Chapter 1: Connector Menu B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 GND AD36 AD39 AD43 AD46 AD49 AD53 AD57 AD61 GND C/BE6# X8 AD32 GND AD40 AD44 GND GND AD54 AD58 GND PAR64 C/BE7# X9 AD33 AD37 GND AD45 AD47 AD50 AD55 GND AD62 C/BE4# X11 GND AD34 V(I/O) AD41 GND AD48 AD51 GND AD59 V(I/O) C/BE5# X12 Ground Address 36 Address 39 Address 43 Address 46 Address 49 Address 53 Address 57 Address 61 Ground Command. Byte Enable 6 Reserved (8) Address 32 Ground Address 40 Address 44 Ground Ground Address 54 Address 58 Ground Parity 64 ??? Command. ISA96/AT96 (Bottom) Pin A1 A2 A3 A4 A5 A6 Name RSTDRV IRQ9 SD11 SD9 IOCHRDY IOW# Description Interrupt 9 Data 11 Data 9 1 I/O Write 65 Note PR EL IM IN BETA RELEASE OT FO 2 2 2 2 2 2 2 2 2 2 2 2 R RE DI ST RI BU TIO N.

66 .N AR YB 1 = Pullup resistor must be integrated into the System Slot (CPU). ET A . It may not be modified and re-distributed without the authors permission. VMEbus (Bottom) Pin Name Description PR EL IM IN Address 19 Address 16 Address 12 DMA Request 6 Interrupt 4 Address 5 Address 3 Interrupt 10 BETA RELEASE OT 1 1 FO R RE DI ST RI BU TIO N.Chapter 1: Connector Menu A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 SA15 CLK SA10 SA7 T/C SA2 SD15 SD13 SD3 SD1 SMEMW# SA18 SA14 DACK6# SA9 IRQ3 IOCS16# SA1 SD7 SD5 SD10 SD8 AEN IOR# SA13 SA11 IRQ5 SA6 SA4 IRQ11 SD14 SD12 SD2 SD0 SMEMR# SA17 REF# IRQ7 SA8 MCS16# BALE SA0 SD6 SD4 0WS SBHE# SA19 SA16 SA12 DRQ6 IRQ4 SA5 SA3 IRQ10 Address 15 Clock Address 10 Address 7 Address 2 Data 15 Data 13 Data 3 Data 1 System Memory Write Address 18 Address 14 DMA Acknowledge 6 Address 9 Interrupt 3 I/O 16-bit chip select 1 Address 1 Data 7 Data 5 Data 10 Data 8 Address Enable I/O Read Address 13 Address 11 Interrupt 5 Address 6 Address 4 Interrupt 11 Data 14 Data 12 Data 2 Data 0 System Memory Read Address 17 Interrupt 7 Address 8 Address 0 Data 6 Data 4 IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

. It may not be modified and re-distributed without the authors permission. Write PR EL IM IN Address 18 Address 15 Address 5 Address 3 Address 1 Data 9 Data 4 Data 14 Bus Error Address 22 Address 20 Address 17 Address 7 Interrupt 5 Interrupt 3 Address 8 67 BETA RELEASE AR YB ET A Address 13 Address 11 Address 9 Data 1 Data 11 Data 6 .N OT FO Address 23 Address 21 Address 19 Address 16 Address 6 Address 4 Address 2 Data 8 Data 3 Data 13 R RE DI ST Data 10 Data 5 Data 15 RI Address 14 Address 12 Address 10 BU TIO N.Chapter 1: Connector Menu A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 D0 D2 D12 D7 DS1# BR3# AM1 AM3 IACKOUT# A14 A12 A10 BBSY# D10 D5 D15 SYSRES# A23 A21 A19 A16 A6 A4 A2 D8 D3 D13 SYSCLK DS0# DTACK# AS# IACK# AM4 A13 A11 A9 D1 D11 D6 BG3OUT# WR# AM0 AM2 A18 A15 A5 A3 A1 D9 D4 D14 BERR# AM5 A22 A20 A17 A7 IRQ5# IRQ3# A8 Data 0 Data 2 Data 12 Data 7 IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

.N OT FO R RE DI Address 13 Reset Data 0 Data 4 Address 1 ST RI BU TIO N. Address 17 Not connected Read Not connected Data 6 Address 0 Address 5 Address 16 Address 18 PR EL IM IN BETA RELEASE AR Address 19 Address 11 Non Maskable Interrupt Not connected Data 3 Address 3 Address 6 Data 1 Address 14 Not connected Not connected 68 YB Address 12 Address 9 Not connected Data 7 Address 2 Address 8 ET A . It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu ECB (Bottom) Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 Name D5 D2 A4 A7 BAI 2F A10 INT# VCMOS PWRCLR# A13 RESET# D0 D4 A1 WAIT# A17 IEO n/c DMARDY RD# IORQ# ? n/c D6 A0 A5 A16 A18 BAO M1# WR# n A12 A9 n/c D7 A2 A8 BUSRQ# A19 A11 NMI# PF HALT# RFSH# MRQ# n/c D3 A3 A6 IEI D1 A14 n/c n/c Description Data 5 Data 2 Data 4 Address 7 Address 10 IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

69 DESLCT# A15 Address 15 BUSAK# n/c Not connected .Chapter 1: Connector Menu E9 E10 E11 E12 The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. IndustrialPCI Connector SMP16 (Bottom) Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 Name NMI# IRQ0# D11 D9 RDYIN IOW# A15 CLK A10 A7 TC/EOP# A2 D15 D13 D3 D1 MEMW# A18 A14 DACKx# A9 IRQ3# IOCS16# A1 D7 D5 D10 D8 BUSEN IOR# A13 A11 IRQ1# A6 A4 IRQ4# D14 D12 D2 D0 MEMR# A17 INTA# INT# A8 MECS16# ALE A0 D6 D4 MMIO# BHEN Description Non Maskable Interrupt Interrupt 0 Data 11 Data 9 Address 15 Address 10 Address 7 Address 2 Data 15 Data 13 Data 3 Data 1 Address 18 Address 14 Address 9 Interrupt 3 Address 1 Data 7 Data 5 Data 10 Data 8 PR EL IM IN Address 13 Address 11 Interrupt 1 Address 6 Address 4 Interrupt 4 Data 14 Data 12 Data 2 Data 0 BETA RELEASE AR Address 17 Address 8 Address 0 Data 6 Data 4 YB ET A .N OT FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission.

It may not be modified and re-distributed without the authors permission. 70 . Floppy/EIDE (Bottom) Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 Name FDSEL1 FDSEL0 FDME1 DIR STEP WRDATA WE TRK0 WP RDDATA HDSEL DSKCHG DRVDEN1 DRVDEN0 IDECS3P# IDEA2 IDEIRQS IDEPUS IDEDRQP IDED14 IDED8 IDED6 IDED11 IDED3 FDME0 INDX IDECS3S# IDEA0 IDEDAKS# IDEIOR# IDEDRQS IDED1 #IDERST IDED10 IDED4 IDED2 IDELEDS# IDELEDP# IDECS1S# IDEIRQP IDEPUP IDEIOW# IDED15 IDED13 IDED7 GND GND GND Description Floppy Select 1 Floppy Select 0 Floppy ? Floppy Direction Floppy Step Floppy Write Data Floppy Write? Floppy Track 0 Floppy Write? Floppy ? Floppy HD Select Floppy DiskChange ? ? IDE ? IDE ? IDE ? IDE ? IDE ? IDE Data 14 IDE Data 8 IDE Data 6 IDE Data 11 IDE Data 3 Floppy Me? Floppy Index IDE ? IDE ? IDE ? IDE ? IDE ? IDE Data 1 IDE ? IDE Data 10 IDE Data 4 IDE Data 2 IDE LED ? IDE LED ? IDE ? IDE ? IDE Pull Up ? IDE ? IDE Data 15 IDE Data 13 IDE Data 7 Ground Ground Ground PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI ST RI BU TIO N.Chapter 1: Connector Menu E5 E6 E7 E8 E9 E10 E11 E12 A19 A16 A12 DRQx# IRQ2# A5 A3 IRQ5# Address 19 Address 16 Address 12 Interrupt 2 Address 5 Address 3 Interrupt 5 IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

N OT FO Data 8 Data 9 Data 10 Data 2 Data 4 R RE DI ST SCSI (Bottom) RI BU TIO N. 71 .Chapter 1: Connector Menu E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 GND GND IDECS1P# IDEA1 IDEDAKP# IDEIORDY IDED0 IDED12 IDED9 IDED5 GND GND Ground Ground IDE ? IDE ? IDE ? IDE ? IDE Data 0 IDE Data 12 IDE Data 9 IDE Data 5 Ground Ground IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 D5 D6 D7 D8 Name TERM GND I/O# REQ# ATN# D8 D9 D10 D2 D4 DP0 GND TERM GND GND GND GND GND GND GND GND GND GND GND TERM GND C/D# MSG# ACK# D12 DP1 D13 D1 D5 D7 GND TERM GND GND GND GND GND GND GND Description Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground PR EL IM IN Data 12 Data P1 Data 13 Data 1 Data 5 Data 7 Ground Ground Ground Ground Ground Ground Ground Ground BETA RELEASE AR YB ET A .

Please send any comments to Joakim Ögren.com/ipci.sips. Rob Gill <gillr@mailcity.com> ST Data 14 Data 15 Data 11 Data 0 Data 3 Data 6 Ground RI BU TIO N.N OT FO R RE Sources: IndustrialPCI page <http://www.Chapter 1: Connector Menu D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 GND GND GND GND TERM GND SEL# RST# BSY# D14 D15 D11 D0 D3 D6 GND Ground Ground Ground Ground Ground IndustrialPCI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .htm> at Standard Industrial PC Systems's (SIPS) homepage <http://www.sips. It may not be modified and re-distributed without the authors permission. 72 .com> DI Contributor: Joakim Ögren .

SmallPCI is a version of PCI adapted for small computers and PDAs.pcisig. 73 SmallPCI (SPCI) . If you have any information of value please send it to me. (At the motherboard) The specifications can be obtained from: PCI Special Interest Group 2575 NE Kathryn St.N Info: SmallPCI overview <http://www. PR EL IM IN BETA RELEASE AR YB ET A . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.com> OT FO R RE I don't have any technical information about SmallPCI at the moment. UNKNOWN CONNECTOR at the device.html> at PCI Special Interest Group's homepage <http://www. DI UNKNOWN CONNECTOR at the motherboard. It may not be modified and re-distributed without the authors permission.com/current/smallpci. OR 97124 Phone: 1-800-433-5177 Fax: 1-503-693-8344 Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.pcisig. #17 Hillsboro.Chapter 1: Connector Menu SmallPCI Connector PCI=Peripheral Component Interconnect. ST (At the device) RI BU TIO N.

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (At the device) Pin Name 1 A18 2 A16 3 A14 4 Vccr 5 CEH# 6 A11 7 A9 8 A8 9 A6 10 A5 11 A3 12 A2 13 A0 14 RAS# 15 A24 16 A23 17 A22 18 OE# 19 D15 20 D13 21 D12 22 D10 23 D9 24 D0 25 D2 26 D4 27 RFU 28 D7 29 SDA 30 SCL 31 A19 32 A17 33 A15 34 A13 35 A12 36 RESET# 37 A10 38 VS1# 39 A7 40 BS8# 41 A4 Description Address Bus Address Bus Address Bus Voltage Refresh Card Enable High Byte Address Bus Address Bus Address Bus Address Bus Address Bus Address Bus Address Bus Address Bus Row Address Strobe Address Bus Address Bus Address Bus Output Enable Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Reserved for future use Data Bus Serial Data and Address Serial Clock Address Bus Address Bus Address Bus Address Bus Address Bus Reset Address Bus Voltage Sense 1 Address Bus Bus Size 8 Address Bus Dir PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI UNKNOWN CONNECTOR at the device. ST (At the card) RI BU TIO N. 74 Miniature Card .Chapter 1: Connector Menu Miniature Card Connector Developed by Intel. Miniature Card is a memory-only expansion card. UNKNOWN CONNECTOR at the card. It may not be modified and re-distributed without the authors permission.

75 .mcif.html> at Miniature Card Implementers Forum's homepage <http://www. The following three is separate: Name GND VCC CINS# Description Dir Ground Power Card Insertion Note: Direction is card relative device.org/spec. It may not be modified and re-distributed without the authors permission.N Please send any comments to Joakim Ögren.html> PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 CEL# A1 CASL# CASH# CD# A21 BUSY# WE# D14 RFU D11 VS2# D8 D1 D3 D5 D6 RFU A20 Card Enable Low Byte Address Bus Column Address Strobe Low Byte Column Address Strobe High Byte Card Detect Address Bus Ready/Busy Write Enable Data Bus Reserved for future use Data Bus Voltage Sense 2 Data Bus Data Bus Data Bus Data Bus Data Bus Reserved for future use Address Bus Miniature Card Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Contributor: Joakim Ögren Source: Minicature Card v1.mcif.1 spec <http://www. OT FO R RE DI ST RI BU TIO N.org/spec.

3 Volts. CASH# CASH# strobes in the high byte column address for DRAM cards.x Volts (the value to be determined at a later date). CASL# CASL# strobes in the low byte column address for DRAM cards. It may not be modified and re-distributed without the authors permission. A 2 Mbyte Miniature Card that does not decode the upper address lines would repeat its address space every 2 Mbytes. etc. This signal must either be connected to card GND or left open. This signal is not used in DRAM cards. This signal must either be connected to card GND or left open. The Miniature Card specification does not require the Miniature Card to decode the upper address lines.1. the Miniature Card must reset to a predetermined state. 76 Miniature Card (Technical) . This signal is not used in DRAM cards. BU TIO N. YB CEL# enables the low byte of the data bus (D[7:0]) on the card. . When RESET# transitions from a low state to a high state.Chapter 1: Connector Menu Miniature Card (Tech) Connector This section is currently based solely on the Miniature Card specification v1. VS1# CEL# CEH# RAS# strobes in the row address for DRAM cards. Signal Descriptions: A0-A24 D0-D15 OE# indicates that the current bus cycle is a read cycle.N VS2# OT Voltage Sense 1 signal. ET A Voltage Sense 2 signal. The data bus is composed of two bytes. 400000h. PR EL IM IN RAS# BETA RELEASE AR CEH# enables the high byte of the data bus (D[15:8]) on the card. The card grounds this signal to indicate it can operate at x. FO WE# indicates that the current bus cycle is a write cycle. ST RI Address A0 to A24 are the address bus lines that can address up to 32 Mwords (64 MBytes). The card grounds this signal to indicate it can operate at 3. the low byte D[7:0] and the high byte D[15:8]. Address 0h would access the same physical location as 200000h. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 600000h. RESET# RESET# controls card initialization. R WE# RE OE# DI Data lines D0 through D15 constitute the data bus.

before the interface signals connect. FO R CD# RE SCL DI ST RI BU BUSY# is a signal generated by the card to indicate the status of operations within the Miniature Card.mcif. Contributor: Joakim Ögren Source: Minicature Card v1.org/spec. BETA RELEASE AR YB ET A BS8# is a signal driven by the host to indicate if the data bus is x8 or x16.Chapter 1: Connector Menu BUSY# Miniature Card (Tech) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. I2C: Serial Clock are used to read the attribute information structure (AIS) from the serial EEPROM in a DRAM card. in Flash Miniature Cards the BUSY# signal is tied to the components RY/BY# signal.html> Please send any comments to Joakim Ögren. CD# will be forced low. Do not confuse CD# with CINS#. BS8# GND Ground Vcc CINS# Vcc is used to supply power to the card.html> at Miniature Card Implementers Forum's homepage <http://www. TIO N. However. After a Miniature Card has been inserted. Vccr Vccr provides a low current (refresh) voltage supply. SDA I2C: Serial Data/Address. ROM Miniature Cards would always drive BUSY# high since the host will always be able to read from a ROM Miniature Card. A 16-bit host must drive this signal high. The card detect signal is located in the center of the second row of interface signals. Vccr is a feature used by DRAM Miniature Cards to "self-refresh" during "sleep" mode. When BUSY# is low.N OT CD# is a grounded interface signal. 77 .org/spec. An 8-bit host must drive BS8# low and tie the high byte data bus D[15:8] to the low byte data bus D[7:0]. the Miniature Card is busy and unable to accept some data operations from the host. When BUSY# is high.1 spec <http://www. the Miniature Card is ready to accept the next command from the host. CINS# is an early card detect that is one of the first signals to connect to the host.mcif. For example. PR EL IM IN CINS# is a grounded signal on the front of the Miniature Card that can be used for early detection of a card insertion. CINS# makes contact on the host when the front of the card is inserted into the socket. and should be one of the last interface signals to connect to the host. It may not be modified and re-distributed without the authors permission. .

Texas Instruments owns the standard today. UNKNOWN CONNECTOR at the computer. Standard: IEEE 1196. "Nubus-A simple 32-bit backplane bus". Row B Pin Name Description 1 -12 V -12 VDC PR EL IM IN Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name -12 V /SPV /SP /TM1 /AD1 /AD3 /AD5 /AD7 /AD9 /AD11 /AD13 /AD15 /AD17 /AD19 /AD21 /AD23 /AD25 /AD27 /AD29 /AD31 GND GND /ARB1 /ARB3 /ID1 /ID3 /ACK +5 V /RQST /NMRQ +12 V +5 VDC +12 VDC BETA RELEASE AR Address/Data 1 Address/Data 3 Address/Data 5 Address/Data 7 Address/Data 9 Address/Data 11 Address/Data 13 Address/Data 15 Address/Data 17 Address/Data 19 Address/Data 21 Address/Data 23 Address/Data 25 Address/Data 27 Address/Data 29 Address/Data 31 Ground Ground YB ET A . 78 NuBus . It may not be modified and re-distributed without the authors permission. (At the card) (At the computer) UNKNOWN CONNECTOR at the card.Chapter 1: Connector Menu NuBus Connector Available on old Apple Macintosh computers and on NeXT computers. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R Description -12 VDC RE Row A DI ST RI BU TIO N.

It may not be modified and re-distributed without the authors permission. 79 .N OT FO R RE DI ST RI BU TIO N. Row C Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name /RESET +5 V +5 V /TM0 /AD0 /AD2 /AD4 /AD6 /AD8 /AD10 /AD12 /AD14 /AD16 /AD18 /AD20 /AD22 /AD24 /AD26 /AD28 /AD30 GND /PFW /ARB0 /ARB2 Description Reset +5 VDC +5 VDC PR EL IM IN Address/Data 0 Address/Data 2 Address/Data 4 Address/Data 6 Address/Data 8 Address/Data 10 Address/Data 12 Address/Data 14 Address/Data 16 Address/Data 18 Address/Data 20 Address/Data 22 Address/Data 24 Address/Data 26 Address/Data 28 Address/Data 30 Ground BETA RELEASE AR YB ET A .Chapter 1: Connector Menu 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND GND +5 V +5 V +5 V +5 V * * * * GND GND GND GND GND GND GND GND GND GND GND GND ** ** ** ** +5 V +5 V GND GND +12 V Ground Ground +5 VDC +5 VDC +5 VDC +5 VDC Reserved ? Reserved ? Reserved ? Reserved ? Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Reserved ? Reserved ? Reserved ? Reserved ? +5 VDC +5 VDC Ground Ground NuBus Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu 26 27 28 29 30 31 32 /ID0 /ID2 /START +5 V +5 V GND /CLK NuBus Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Michael Van den Acker <rdsmv@huntsman.rmit. It may not be modified and re-distributed without the authors permission.CA> TIO N.McGill. Karsten Wenke <Karsten. Godel? <godel@CS.edu. 80 .de>.au>.cse.Wenke@t-online.N OT FO R RE DI ST RI BU Contributor: Joakim Ögren. +5 VDC +5 VDC Ground Clock Source: ? Please send any comments to Joakim Ögren.

It may not be modified and re-distributed without the authors permission. (At the computer) UNKNOWN CONNECTOR at the card. NuBus 90 . Row A Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name -12 V SB0 /SPV /SP /TM1 /AD1 /AD3 /AD5 /AD7 /AD9 /AD11 /AD13 /AD15 /AD17 /AD19 /AD21 /AD23 /AD25 /AD27 /AD29 /AD31 GND GND /ARB1 /ARB3 /ID1 /ID3 /ACK +5 V /RQST /NMRQ +12 V Description -12 VDC Row B Pin 1 2 3 PR EL IM IN +5 VDC +12 VDC Name -12 V GND GND BETA RELEASE AR Address/Data 1 Address/Data 3 Address/Data 5 Address/Data 7 Address/Data 9 Address/Data 11 Address/Data 13 Address/Data 15 Address/Data 17 Address/Data 19 Address/Data 21 Address/Data 23 Address/Data 25 Address/Data 27 Address/Data 29 Address/Data 31 Ground Ground Description -12 VDC Ground Ground 81 YB ET A . UNKNOWN CONNECTOR at the computer.Chapter 1: Connector Menu NuBus 90 Connector Available on old Apple Macintosh computers. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST RI BU (At the card) TIO N.

Row C Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Name /RESET SB1 +5 V +5 V /TM0 /AD0 /AD2 /AD4 /AD6 /AD8 /AD10 /AD12 /AD14 /AD16 /AD18 /AD20 /AD22 /AD24 /AD26 /AD28 /AD30 GND /PFW /ARB0 /ARB2 /ID0 /ID2 Description Reset +5 VDC +5 VDC PR EL IM IN Address/Data 0 Address/Data 2 Address/Data 4 Address/Data 6 Address/Data 8 Address/Data 10 Address/Data 12 Address/Data 14 Address/Data 16 Address/Data 18 Address/Data 20 Address/Data 22 Address/Data 24 Address/Data 26 Address/Data 28 Address/Data 30 Ground BETA RELEASE AR YB ET A .N OT +5 VDC +5 VDC Ground Ground +12 VDC FO R RE Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 +5 V +5 V +5 V +5 V /TM2 /CM0 /CM1 /CM2 GND GND GND GND GND GND GND GND GND GND GND GND /CLK2X STDBYPWR /CLK2XEN /CBUSY +5 V +5 V GND GND +12 V +5 VDC +5 VDC +5 VDC +5 VDC NuBus 90 Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 82 .

Karsten Wenke <Karsten.de> Source: ? Please send any comments to Joakim Ögren.Wenke@t-online. PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu 28 29 30 31 32 The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 83 /START +5 V +5 V GND /CLK +5 VDC +5 VDC Ground Clock . It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N. NuBus 90 Connector Contributor: Joakim Ögren.

84 Zorro II . Grounded GND /C3 CDAC /C1 /OVR RDY /INT2 /PALOPE n/c /BOSS A5 /INT6 A6 A4 GND A3 A2 A7 A1 A8 FC0 A9 FC1 A10 FC2 A11 GND A12 A13 /IPL0 A14 /IPL1 DI ST FO R . I hope the table is correct. I have now put them back again. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 A500 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A1000 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X RE A2000 X X X X X X X X X X X X X X X X X X X X A2000B X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Name GND GND GND GND +5V +5V n/c -5V n/c 28CLOCK +12V n/c /COPCFG CONFIG IN.Chapter 1: Connector Menu Zorro II Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Please contact me if not. Description Ground Ground Ground Ground +5 Volts DC +5 Volts DC -5 Volts DC 28MHz Clock +12 Volts DC Configuration Out Ground C3 Clock Clock C1 Clock Ready Interrupt 2 BU Address 5 Interrupt 6 Address 6 Address 4 Ground Address 3 Address 2 Address 7 Address 1 Address 8 Processor status 0 Address 9 Processor status 1 Address 10 Processor status 2 Address 11 Ground Address 12 Address 13 Address 14 TIO N.N OT ET A PR EL IM IN AR YB BETA RELEASE RI None: All of my X's suddenly disappeared. It may not be modified and re-distributed without the authors permission. (At the A2000) 86 PIN EDGE CONNECTOR at the A2000. I don't remember where I found this information.

PR EL IM IN BETA RELEASE AR YB ET A RI BU Address 18 Reset Address 19 Halt Address 20 Address 22 Address 21 Address 23 Ground Data 15 Data 14 Data 13 Read/Write Data 12 Data 11 Ground Data 0 Data 10 Data 1 Data 9 Data 2 Data 8 Data 3 Data 7 Data 4 Data 6 Ground Data 5 TIO N. 85 . It may not be modified and re-distributed without the authors permission.N Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. DI ST RE R FO OT .Chapter 1: Connector Menu 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A15 /IPL2 A16 /BEER A17 /VPA GND ECLK /VMA A18 RST A19 /HLT A20 A22 A21 A23 /BR /CBR GND /BGACK D15 /BG /CBG D14 /DTACK D13 R/W D12 /LDS D11 /UDS GND /AS D0 D10 D1 D9 D2 D8 D3 D7 D4 D6 GND D5 Zorro II Connector Address 15 Address 16 Bus Error Address Ground E Clock The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

N OT FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu Zorro II/III Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 86 Zorro II/III . (At the computer) 100 PIN EDGE CONNECTOR at the computer. Pin Physical Name Zorro II Name Zorro III Address Phase Zorro III Data Phase 1 Ground Ground Ground Ground 2 Ground Ground Ground Ground 3 Ground Ground Ground Ground 4 Ground Ground Ground Ground 5 +5VDC +5VDC +5VDC +5VDC 6 +5VDC +5VDC +5VDC +5VDC 7 /OWN /OWN /OWN /OWN 8 -5VDC -5VDC -5VDC -5VDC 9 /SLAVEn /SLAVEn /SLAVEn /SLAVEn 10 +12VDC +12VDC +12VDC +12VDC 11 /CFGOUTn /CFGOUTn /CFGOUTn /CFGOUTn 12 /CFGINn /CFGINn /CFGINn /CFGINn 13 Ground Ground Ground Ground 14 /C3 /C3 Clock /C3 Clock /C3 Clock 15 CDAC CDAC Clock CDAC Clock CDAC Clock 16 /C1 /C1 Clock /C1 Clock /C1 Clock 17 /CINH /OVR /CINH /CINH 18 /MTCR XRDY /MTCR /MTCR 19 /INT2 /INT2 /INT2 /INT2 20 -12VDC -12VDC -12VDC -12VDC 21 A5 A5 A5 A5 22 /INT6 /INT6 /INT6 /INT6 23 A6 A6 A6 A6 24 A4 A4 A4 A4 25 Ground Ground Ground Ground 26 A3 A3 A3 A3 27 A2 A2 A2 A2 28 A7 A7 A7 A7 29 /LOCK A1 /LOCK /LOCK 30 AD8 A8 A8 D0 31 FC0 FC0 FC0 FC0 32 AD9 A9 A9 D1 33 FC1 FC1 FC1 FC1 34 AD10 A10 A10 D2 35 FC2 FC2 FC2 FC2 36 AD11 A11 A11 D3 37 Ground Ground Ground Ground 38 AD12 A12 A12 D4 39 AD13 A13 A13 D5 40 Reserved (/EINT7) Reserved Reserved 41 AD14 A14 A14 D6 42 Reserved (/EINT5) Reserved Reserved 43 AD15 A15 A15 D7 44 Reserved (/EINT4) Reserved Reserved 45 AD16 A16 A16 D8 PR EL IM IN BETA RELEASE AR YB ET A .

87 .N OT FO R RE DI ST RI BU TIO N. Contributor: Joakim Ögren Source: Amiga 4000 User's Guide from Commodore Please send any comments to Joakim Ögren.Chapter 1: Connector Menu 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 /BERR AD17 /MTACK Ground E Clock /DS0 AD18 /RESET AD19 /HLT AD20 AD22 AD21 AD23 /BRn Ground /BGACK AD31 /BGn AD30 /DTACK AD29 READ AD28 /DS2 AD27 /DS3 Ground /CCS SD0 AD26 SD1 AD25 SD2 AD24 SD3 SD7 SD4 SD6 Ground SD5 Ground Ground Ground Ground SenseZ3 7M DOE /IORST /BCLR Reserved /FCS /DS1 Ground Ground /BERR A17 (/VPA) Ground E Clock (/VMA) A18 /RST A19 /HLT A20 A22 A21 A23 /BRn Ground /BGACK D15 /BGn D14 /DTACK D13 READ D12 /LDS D11 /UDS Ground /AS D0 D10 D1 D9 D2 D8 D3 D7 D4 D6 Ground D5 Ground Ground Ground Ground Ground E7M DOE /BUSRST /GBG (/EINT1) No Connect No Connect Ground Ground /BERR A17 /MTACK Ground E Clock /DS0 A18 /RESET A19 /HLT A20 A22 A21 A23 /BRn Ground /BGACK A31 /BGn A30 /DTACK A29 READ A28 /DS2 A27 /DS3 Ground /CCS Reserved A26 Reserved A25 Reserved A24 Reserved Reserved Reserved Reserved Ground Reserved Ground Ground Ground Ground SenseZ3 7M DOE /IORST /BCLR Reserved /FCS /DS1 Ground Ground Zorro II/III Connector /BERR D9 /MTACK Ground E Clock /DS0 D10 /RESET D11 /HLT D12 D14 D13 D15 /BRn Ground /BGACK D31 /BGn D30 /DTACK D29 READ D28 /DS2 D27 /DS3 Ground /CCS D16 D26 D17 D25 D18 D24 D19 D23 D20 D22 Ground D21 Ground Ground Ground Ground SenseZ3 7M DOE /IORST /BCLR Reserved /FCS /DS1 Ground Ground The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Name n/c n/c n/c n/c n/c n/c n/c n/c GND +5V A23 A22 A21 A20 A19 A18 A17 A16 GND +5V A15 A14 A13 A12 A11 A10 A9 A8 GND +5V A7 A6 A5 A4 A3 A2 A1 A0 GND +5V D31 D30 D29 D28 D27 D26 D25 D24 GND Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Ground +5 Volts DC Address 23 Address 22 Address 21 Address 20 Address 19 Address 18 Address 17 Address 16 Ground +5 Volts DC Address 15 Address 14 Address 13 Address 12 Address 11 Address 10 Address 9 Address 8 Ground +5 Volts DC Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Ground +5 Volts DC Data 31 Data 30 Data 29 Data 28 Data 27 Data 26 Data 25 Data 24 Ground PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission. 88 Amiga 1200 CPU-port . (At the computer) UNKNOWN CONNECTOR at the computer.Chapter 1: Connector Menu Amiga 1200 CPU-port Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST RI BU TIO N.

PR EL IM IN BETA RELEASE AR YB Address Strobe Data Strobe Read/Write Bus Error Reserved EClock pulse Ground +5 Volts DC Processor Status 2 Processor Status 1 Processor Status 0 Reserved Reserved Reserved 89 ET A Reserved Reset Halt Reserved Reserved .Chapter 1: Connector Menu 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 +5V D23 D22 D21 D20 D19 D18 D17 D16 GND +5V D15 D14 D13 D12 D11 D10 D9 D8 GND +5V D7 D6 D5 D4 D3 D2 D1 D0 GND +5V /IPL2 /IPL1 /IPL0 n/c /RST /HLT n/c n/c SIZE1 SIZE0 /AS /DS R/W /BERR n/c /AVEC /DSACK1 /DSACK2 CPUCKLA ECLOCK GND +5V FC2 FC1 FC0 /RMC n/c n/c n/c +5 Volts DC Data 23 Data 22 Data 21 Data 20 Data 19 Data 18 Data 17 Data 16 Ground +5 Volts DC Data 15 Data 14 Data 13 Data 12 Data 11 Data 10 Data 9 Data 8 Ground +5 Volts DC Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 Ground +5 Volts DC Amiga 1200 CPU-port Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. . It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N.

Chapter 1: Connector Menu 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 n/c /BR /BG n/c /BOSS /FPUCS /FPUSENSE CCKA /RESET GND +5V /NETCS /SPARECS /RTCCS /FLASH /REG /CCENA /WAIT /KBRESET /IORD /IOWR /OE /WE /OVR XRDY /ZORRO /WIDE /INT2 /INT6 GND +5V SYSTEM1 SYSTEM0 /xRxD /xTxD /CONFIG OUT AGND ALEFT ARIGHT +12V -12V Reserved Slot specific Bus Arbitration Slot specific Bus Arbitration Reserved FPU Chip select FPU Sense Reset Ground +5 Volts DC Realtime Clock Chip select Amiga 1200 CPU-port Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB Audio Ground Audio Left Audio Right +12 Volts DC -12 Volts DC ET A . 90 . Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.N Interrupt level 2 Interrupt level 6 Ground +5 Volts DC System1 Ground System0 Ground OT FO /DTACK Override External Ready R RE Keyboard reset IO Read IO Write Output enable DI ST RI BU TIO N.

(At the computer) 60 PIN EDGE CONNECTOR (. 91 Amiga 1000 Ramex .Chapter 1: Connector Menu Amiga 1000 Ramex Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission.156") at the computer. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A B C D E F H J K L M N P R S T U V Name GND D15 +5V D12 GND D11 +5V D8 GND D7 +5V D4 GND D3 +5V D0 GND DRA4 DRA5 DRA6 DRA7 GND /RAS GND GND /CASU0 GND /CASL0 +5V +5V GND D14 +5V D13 GND D10 +5V D9 GND D6 +5V D5 GND D2 +5V D1 GND DRA3 Description Ground Data 15 +5 Volts DC Data 12 Ground Data 11 +5 Volts DC Data 8 Ground Data 7 +5 Volts DC Data 4 Ground Data 3 +5 Volts DC Data 0 Ground Ground Ground Ground Ground Ground Data 14 +5 Volts DC Data 13 Ground Data 10 +5 Volts DC Data 9 Ground Data 6 +5 Volts DC Data 5 Ground Data 2 +5 Volts DC Data 1 Ground PR EL IM IN BETA RELEASE AR YB +5 Volts DC +5 Volts DC ET A .

PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu W X Y Z AA BB CC DD EE FF HH JJ DRA2 DRA1 DRA0 GND /RRW GND GND /CASU1 GND /CASL1 +5V +5V Amiga 1000 Ramex Connector Ground Ground Ground Ground +5 Volts DC +5 Volts DC The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N. 92 .

55/3. It may not be modified and re-distributed without the authors permission. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name RGB16 RGB17 LINELF LINERT C28D +5V ARED +5V GND +12V AGREEN GND GND /CSYNC ABLUE /XCLKEN GND BURST /C4 GND GND /HSYNC RGB4 GND RGB7 /VSYNC RGB15 BLANK RGB23 /PIXELSW -5V GND /XCLK /C1 +5V PSTROBE Dir Description Red Bit 0 Red Bit 1 Audio Line Out Left Audio Line Out Right Pixel-Synchronous Clock +5 Volts DC (1 A) Analog Red +5 Volts DC (1 A) Digital Ground +12 Volts DC (40 mA) Analog Green Digital Ground Digital Ground Composite Sync Analog Blue Genlock Clock Enable Digital Ground Burst Gate 3. Video Expansion (Amiga) .Chapter 1: Connector Menu Amiga Video Expansion Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.58 MHz Clock Digital Ground Digital Ground Horizontal Sync (47 Ohm) Blue Bit 4 Digital Ground Blue Bit 7 Vertical Sync (47 Ohm) Green Bit 7 Video Blank Red 7 Genlock Overlay (47 Ohm) -5 Volts DC Digital Ground Genlock Clock C1 Clock +5 Volts DC (1 A) Printer Port Handshake - - 1 2 3 4 5 6 7 8 9 10 11 12 PR EL IM IN GND RGB20 RGB21 RGB22 GND RGB12 RGB13 RGB14 GND RGB5 RGB6 GND AR - - - - - BETA RELEASE YB ET A - Digital Ground Red Bit 4 Red Bit 5 Red Bit 6 Digital Ground Green Bit 4 Green Bit 5 Green Bit 6 Digital Ground Blue Bit 5 Blue Bit 6 Ground 93 . (At the computer) 36+54 PIN EDGE CONNECTOR at the computer.N - OT FO R - RE - DI - ST RI BU TIO N.

55/3. YB ET A .Chapter 1: Connector Menu 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 SOG TBASE CDAC PPOUT /C3 PBUSY /LPEN /PACK PSEL GND PPD0 PPD1 PPD2 PPD3 PPD4 PPD5 PPD6 PPD7 /LED GND RAWLF AGND RAWRT AGND n/c n/c GND GND n/c n/c GND GND RGB18 RGB19 RGB8 RGB9 RGB10 RGB11 RGB0 RGB1 RGB2 RGB3 Amiga Video Expansion Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.09/7. Note: Do not mix analog & digital grounds. - - Contributor: Joakim Ögren Source: Amiga 4000 User's Guide from Commodore Please send any comments to Joakim Ögren.N - OT FO R RE - Sync-On-Green Indicator 50/60 Hz Software Clock Timebase 7. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR Note: Direction is Motherboard relative Card.16 MHz Clock Printer Port Paper Out 3. 94 .58 MHz Clock Printer Port Busy Light Pen Input Printer Port Acknowledge Handshake Printer Port Select Digital Ground Printer Port Data Bit 0 Printer Port Data Bit 1 Printer Port Data Bit 2 Printer Port Data Bit 3 Printer Port Data Bit 4 Printer Port Data Bit 5 Printer Port Data Bit 6 Printer Port Data Bit 7 LED (Audio filter bypass) Setting Digital Ground Raw (Unfiltered) Audio Left Audio Ground Raw (Unfiltered) Audio Right Audio Ground Reserved for future expansion Reserved for future expansion Digital Ground Digital Ground Reserved for future expansion Reserved for future expansion Digital Ground Digital Ground Red Bit 2 Red Bit 3 Green Bit 0 Green Bit 1 Green Bit 2 Green Bit 3 Blue Bit 0 Blue Bit 1 Blue Bit 2 Blue Bit 3 DI ST RI BU TIO N.

(At the computer) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Name A31 A30 A29 A28 A27 A26 A25 A24 DGND VCC A23 A22 A21 A20 A19 A18 A17 A16 DGND VCC A15 A14 A13 A12 A11 A10 A9 A8 DGND VCC A7 A6 A5 A4 A3 A2 A1 A0 DGND VCC D31 D30 D29 D28 D27 D26 D25 D24 DGND Description Address 31 Address 30 Address 29 Address 28 Address 27 Address 26 Address 25 Address 24 Data Ground +5 VDC Address 23 Address 22 Address 21 Address 20 Address 19 Address 18 Address 17 Address 16 Data Ground +5 VDC Address 15 Address 14 Address 13 Address 12 Address 11 Address 10 Address 9 Address 8 Data Ground +5 VDC Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Data Ground +5 VDC Data 31 Data 30 Data 29 Data 28 Data 27 Data 26 Data 25 Data 24 Data Ground PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI Comment Probably not connected since 68EC020 Probably not connected since 68EC020 Probably not connected since 68EC020 Probably not connected since 68EC020 Probably not connected since 68EC020 Probably not connected since 68EC020 Probably not connected since 68EC020 ST RI BU UNKNOWN 182 PIN CONNECTOR (SAME AS MCA) at the computer.Chapter 1: Connector Menu CD32 Expansion-port Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. TIO N. 95 CD32 Expansion-port .

Chapter 1: Connector Menu 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 VCC D23 D22 D21 D20 D19 D18 D17 D16 DGND VCC D15 D14 D13 D12 D11 D10 D9 D8 DGND VCC D7 D6 D5 D4 D3 D2 D1 D0 DGND VCC /IPL2 /IPL1 /IPL0 /RST /HALT /ECS /OCS SIZE1 +5 VDC Data 23 Data 22 Data 21 Data 20 Data 19 Data 18 Data 17 Data 16 Data Ground +5 VDC Data 15 Data 14 Data 13 Data 12 Data 11 Data 10 Data 9 Data 8 Data Ground +5 VDC Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 Data Ground +5 VDC Interrupt Priority Level 2 Interrupt Priority Level 1 Interrupt Priority Level 0 Reset Halt ECS?? OCS?? Size 1 Size 0 CD32 Expansion-port Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R 90 SIZE0 91 92 93 94 95 96 /AS /DS /R/W /BERR /AVEC PR EL IM IN AR YB Address Strobe Data Strobe Read/Write Bus Error Autovector Req Data Ack 1 Data Ack 0 Data Ground +5 VDC Function Codes 2 Function Codes 1 Function Codes 0 96 Autovector request during interrupt acknowledge Data trasnfer and size acknowledge Data transfer and size acknowledge 97 98 99 100 101 102 103 104 105 106 /DSACK1 /DSACK0 CPUCLK_A DGND VCC FC2 FC1 FC0 BETA RELEASE RE Indicates number of bytes remaining to transfer Indicates number of bytes remaining to transfer DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission. ET A . .

/CPU_BR /EXP_BG /CPU_BG /EXP_BR /PUNT /RESET /INT2 /INT6 /KB_CLOCK /KB_DATA /FIRE0 /FIRE1 /LED /ACTIVE /RXD /TXD /DKRD /DKWD SYSTEM /DKWE CONFIG_OUT DGND +12V DGND +12V 17MHZ EXT_AUDIO DA_DATA /MUTE DA_LRCLK DA_BCLK DGND VCC DR DG DB DI /PIXELSW_EXT /PIXELSW /BLANK PIXELCLK DGND VCC /CSYNC CCK_B /HSYNC /VSYNC VGND VGND AR_EXT AR AG_EXT AG CPU bus request?? Expansion bus granted?? CPU bus granted?? Expansion bus request?? FO R .N Data Ground +12V DC Data Ground +12V DC OT PR EL IM IN AR Data Ground +5 VDC Digital Red Digital Green Digital Blue Digital Intensity YB Pixelclock Data Ground +5 VDC Composite sync Color clock ?? Horizontal sync Vertical sync Video ground Video ground Analog Red External Analog Red Analog Green External Analog Green ET A BETA RELEASE RE 68020 RESET Interrupt 2 Interrupt 2 Keyboard clock Keyboard data Fire Button 0?? Fire Button 1?? Power On LED ?? Disk active LED Serial Receive Serial Transmit Serial data in Serial data out Floppy interface (Paula?) Floppy interface (Paula?) Floppy interface (Paula?) For FMV interface ?? For FMV interface ?? For FMV interface ?? For FMV interface ?? For FMV interface ?? For FMV interface ?? For manipulating RBG data Not buffered. It may not be modified and re-distributed without the authors permission. DI ST Generate a level 2 interrupt Generate a level 6 interrupt RI BU TIO N. 97 .Chapter 1: Connector Menu 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 CD32 Expansion-port Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

DI Contributor: Joakim Ögren ST Enable External video clock (Genlock) External video clock (Genlock) External Video Disable internal video interfaces Data Ground +5 VDC Audio Ground +12V DC Left sound External Left sound Right sound External Right sound RI BU TIO N.txt>. Please send any comments to Joakim Ögren.demon. PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission.e.N OT FO R RE Source: CD32 expansion port info <ftp://ftp.Chapter 1: Connector Menu 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 AB_EXT AB VGND VGND /NTSC /XCLKEN XCLK /EXT_VIDEO DGND VCC AGND +12V LEFT_EXT LEFT RIGHT_EXT RIGHT Analog Blue External Analog Blue Video ground Video ground CD32 Expansion-port Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.se>.kth. usenet posting by Anders Stenkvist <ask_me@elixir..uk/pub/amiga/docs/cd32-pinouts. 98 .co.

99 CardBus .Chapter 1: Connector Menu CardBus Connector 32-bit bus defined by PCMCIA. 68 PIN ??? FEMALE at the peripherals. It may not be modified and re-distributed without the authors permission. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Name GND CAD0 CAD1 CAD3 CAD5 CAD7 CCBE0# CAD9 CAD11 CAD12 CAD14 CCBE1# CPAR CPERR# CGNT# CINT# Vcc Vpp1 CCLK CIRDY# CCBE2# CAD18 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD29 RSRVD CCLKRUN# GND GND CCD1# CAD2 CAD4 CAD6 RSRVD CAD8 CAD10 Description Ground Address/Data 0 Address/Data 1 Address/Data 3 Address/Data 5 Address/Data 7 Command/Byte Enable 0 Address/Data 9 Address/Data 11 Address/Data 12 Address/Data 14 Command/Byte Enable 1 Parity Parity error Grant Interrupt Vcc Vpp1 CCLK Initiator Ready Command/Byte Enable 2 Address/Data 18 Address/Data 20 Address/Data 21 Address/Data 22 Address/Data 23 Address/Data 24 Address/Data 25 Address/Data 26 Address/Data 27 Address/Data 29 Reserved CCLKRUN# Ground Ground Card Detect 1 Address/Data 2 Address/Data 4 Address/Data 6 Reserved Address/Data 8 Address/Data 10 PR EL IM IN BETA RELEASE AR YB ET A . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST RI BU (At the controller) TIO N. (At the peripherals) 68 PIN ??? MALE at the controller.

100 . Contributor: Joakim Ögren. It may not be modified and re-distributed without the authors permission.html> at PC Card's homepage <http://www.com> FO R RE DI ST RI BU TIO N.pc-card.com/stand_overview.net> Please send any comments to Joakim Ögren.N OT Source: PC Card Standard <http://www. PR EL IM IN BETA RELEASE AR YB ET A . Marek Hostasa <maro@adcomsys.pc-card.Chapter 1: Connector Menu 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 CVS1 CAD13 CAD15 CAD16 RSRVD CBLOCK# CSTOP# CDEVSEL# Vcc Vpp2 CTRDY# CFRAME# CAD17 CAD19 CVS2 CRST# CSERR# CREQ# CCBE3# CAUDIO CSTSCHG CAD28 CAD30 CAD31 CCD2# GND Address/Data 13 Address/Data 15 Address/Data 16 Reserved Block ??? Stop transfer cycle Device Select Vcc Vpp2 Target Ready Address or Data phase Address/Data 17 CAD19 Reset System Error Request ??? Command/Byte Enable 3 Audio ??? Address/Data 28 Address/Data 30 Address/Data 31 Card Detect 2 Ground CardBus Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Memory I/O+Mem GND GND D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 CE1# CE1# A10 A10 OE# OE# A11 A11 A9 A9 A8 A8 A13 A13 A14 A14 WE# WE# READY IREQ# Vcc Vcc Vpp1 Vpp1 A16 A16 A15 A15 A12 A12 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 A0 D0 D0 D1 D1 D2 D2 WP IOIS16# GND GND GND GND CD1# CD1# D11 D11 D12 D12 D13 D13 D14 D14 D15 D15 CE2# CE2# Description Ground Data 3 Data 4 Data 5 Data 6 Data 7 Address 10 Output Enable Address 11 Address 9 Address 8 Address 13 Address 14 Write Enable ??? Vcc Vpp1 Address 16 Address 15 Address 12 Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Data 0 Data 1 Data 2 PR EL IM IN AR BETA RELEASE YB Ground Ground Card Detect 1 Data 11 Data 12 Data 13 Data 14 Data 15 101 ET A . PC Card . 68 PIN ??? FEMALE at the peripherals. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU (At the controller) TIO N. (At the peripherals) 68 PIN ??? MALE at the controller.Chapter 1: Connector Menu PC Card Connector 16-bit bus defined by PCMCIA. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

102 .com> FO R Battery Voltage 2 / Speaker ??? Battery Voltage 1 / ??? Data 8 Data 9 Data 10 RE DI ST RI BU TIO N.com/stand_overview.pc-card.Chapter 1: Connector Menu 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 VS1# RSRVD RSRVD A17 A18 A19 A20 A21 Vcc Vpp2 A22 A23 A24 A25 VS2# RESET WAIT# RSRVD REG# BVD2 BVD1 D8 D9 D10 CD2# GND VS1# IORD# IOWR# A17 A18 A19 A20 A21 Vcc Vpp2 A22 A23 A24 A25 VS2# RESET WAIT# INPACK# REG# SPKR# STSCHG# D8 D9 D10 CD2# GND Reserved / IORD# Reserved / IOWR# Address 17 Address 18 Address 19 Address 20 Address 21 Vcc Vpp2 Address 22 Address 23 Address 24 Address 25 Reset Reserved / ??? PC Card Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.html> at PC Card's homepage <http://www. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .pc-card.N OT Source: PC Card Standard <http://www. Ground Contributor: Joakim Ögren Please send any comments to Joakim Ögren.

Chapter 1: Connector Menu PC Card ATA Connector This specification makes it possible to share ATA & PC Card with the same connectors. It may not be modified and re-distributed without the authors permission. PC Card ATA . 68 PIN ??? FEMALE at the peripherals. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Namel Ground DD3 DD4 DD5 DD6 DD7 /CS0 Host x x x x x x x Dir Dev x x x x x x x i x PC-Card equiv Ground D3 D4 D5 D6 D7 /CE1 A10 /OE /SELATA x ET A INTRQ VCC x x i x x . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N DA2 DA1 DA0 DD0 DD1 DD2 /IOCS16 Ground Ground /CD1 DD11 DD12 DD13 DD14 DD15 /CS1 x x x x x x x x x x x x x x x x i i i i i x x x x x x x x x x x x x x x x 1) PR EL IM IN BETA RELEASE AR YB OT /CS1 x x 1) i A9 A8 /WE /READY:IREQ VCC A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 /WP:IOIS16 Ground Ground /CD1 D11 D12 D13 D14 D15 /CE2 103 FO R RE DI ST RI BU (At the controller) TIO N. (At the peripherals) 68 PIN ??? MALE at the controller.

o = Optional. 104 /DIOR /DIOW x x i x x /VS1 /IORD /IOWR . 1) Device shall support only one /CS1 signal pin. 2) Device shall support either /M/S or CSEL but not both. It may not be modified and re-distributed without the authors permission.N x = Required.Chapter 1: Connector Menu 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 PC Card ATA Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. nothing = Not connected. PR EL IM IN BETA RELEASE AR YB ET A Contributor: Joakim Ögren . 3) Device shall hold this signal negated if it does not support this function. Source: ATA-2 specifications Please send any comments to Joakim Ögren. i = Ignored by host in ATA mode. OT FO /RESET IORDY DMARQ /DMACK /DASP /PDIAG DD8 DD9 DD10 /CD2 Ground x o o o x x x x x x x /VS2 RESET /WAIT /INPACK /REG /BVD2:SPKR /BVD1:STSCHG D8 D9 D10 /CD2 Ground R RE DI ST M/SCSEL x x x 2) x 2) i x x 3) x 3) o x x x x x x x RI BU VCC x x VCC TIO N.

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (At the peripherals) 68 PIN ??? MALE at the controller.N OT FO R RE DI ST RI BU (At the controller) TIO N. 105 PCMCIA . Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Name GND D3 D4 D5 D6 D7 /CE1 A10 /OE A11 A9 A8 A13 A14 /WE:/P /READY:/IREQ VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 /WP:/IOIS16 GND GND /CD1 D11 D12 D13 D14 D15 /CE2 Dir Description Ground Data 3 Data 4 Data 5 Data 6 Data 7 Card Enable 1 Address 10 Output Enable Address 11 Address 9 Address 8 Address 13 Address 14 Write Enable : Program Ready : Busy (IREQ) +5V Programming Voltage (EPROM) Address 16 Address 15 Address 12 Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Data 0 Data 1 Data 2 Write Protect : IOIS16 Ground Ground Card Detect 1 Data 11 Data 12 Data 13 Data 14 Data 15 Card Enable 2 PR EL IM IN BETA RELEASE AR YB ET A . 68 PIN ??? FEMALE at the peripherals. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu PCMCIA Connector PCMCIA=Personal Computer Memory Card International Association.

Karsten Wenke <Karsten. Note: Direction is Controller (computer) relative PCMCIA-card.de> FO Register Select Battery Voltage Detect 2 : SPKR Battery Voltage Detect 1 : STSCHG Data 8 Data 9 Data 10 Card Detect 2 Ground R RE DI ? ? ? ? ST RI BU TIO N.Chapter 1: Connector Menu 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 /VS1 /IORD /IOWR A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 /VS2 RESET /WAIT /INPACK /REG /BVD2:SPKR /BVD1:STSCHG D8 D9 D10 /CD2 GND PCMCIA Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .N OT Contributor: Joakim Ögren.Wenke@t-online. Source: ? Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission. 106 ? ? Refresh I/O Read I/O Write Address 17 Address 18 Address 19 Address 20 Address 21 +5V Programmeing Voltage 2 (EPROM) Address 22 Address 23 Address 24 Address 25 RFU RESET WAIT .

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Name GND D3 D4 D5 D6 D7 /CE1 A10 /OE A9 A8 A7 VCC A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 /WP:/IOIS16 /CD2 /CD1 D0 D0 D0 D0 D0 /CE2 /VS1 /IORD /IOWR /WE /READY:/RDY:/IREQ VCC CSEL Description Ground Data 3 Data 4 Data 5 Data 6 Data 7 Card Enable 1 Address 10 Output Enable Address 9 Address 8 Address 7 +5V Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Data 0 Data 1 Data 2 Write Protect : IOIS16 Card Detect 2 Card Detect 1 Data 0 Data 0 Data 0 Data 0 Data 0 Card Enable 2 Refresh I/O Read I/O Write Write Enable Ready : Busy : IREQ +5V PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu CompactFlash Connector Developed by SanDisk. 107 CompactFlash . It may not be modified and re-distributed without the authors permission. (At the peripherals) 50 PIN ??? MALE at the controller. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. See PC-Card ATA for more information. Is compatible with PC-Card ATA with a simple passive adapter.N OT FO R RE DI ST RI (At the controller) BU TIO N. 50 PIN ??? FEMALE at the peripherals.

Contributor: Joakim Ögren Please send any comments to Joakim Ögren.N OT FO R RE DI ST Source: SanDisk's CompactFlash ABC <http://www.sandisk.htm> at SanDisk's homepage <http://www.com/sd/support/teched/cfpc_5.sandisk.Chapter 1: Connector Menu 40 41 42 43 44 45 46 47 48 49 50 /VS2 RESET /WAIT /INPACK /REG /BVD2:SPKR /BVD1:STSCHG D8 D9 D10 GND RFU Reset Wait CompactFlash Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.com> RI BU Register Select Battery Voltage Detect 2 : SPKR Battery Voltage Detect 1 : STSCHG Data 8 Data 9 Data 10 Ground TIO N. PR EL IM IN BETA RELEASE AR YB ET A . 108 . It may not be modified and re-distributed without the authors permission.

N OT FO R RE PA=Component side PB=Solder side DI UNKNOWN CONNECTOR at the backplane. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 109 C-bus II .Chapter 1: Connector Menu C-bus II Connector Developed by Corolla C-bus II is the successor to C-bus & Extended C-bus. UNKNOWN CONNECTOR at the device (card). (At the backplane) Pin PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PA32 PA33 PA34 PA35 PA36 PA37 PA38 Name GND AUX18 AUX16 GND AUX14 AUX12 GND AUX10 AUX8 GND AUX6 AUX4 GND AUX2 AUX0 GND RESERVED8 RESERVED6 RESERVED4 RESERVED2 RESERVED0 GND GND AGND CID1 CBCLK GND CRST# LED# GND CARB2 CARB0 GND TM2# TM0# GND STRT# CD31 PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission. ST (At the device (card)) RI BU TIO N.

Chapter 1: Connector Menu PA39 PA40 PA41 PA42 PA43 PA44 PA45 PA46 PA47 PA48 PA49 PA50 PA51 PA52 PA53 PA54 PA55 PA56 PA57 PA58 PA59 PA60 PA61 PA62 PA63 PA64 PA65 PA66 PA67 PA68 PA69 PA70 PA71 PA72 PA73 PA74 PA75 PA76 PA77 PA78 PA79 PA80 PA81 PA82 PA83 PA84 PA85 PA86 PA87 PA88 PA89 PA90 PA91 PB1 PB2 PB3 PB4 PB5 PB6 GND CD30 CD29 GND CD28 CD27 GND CD26 CD25 GND CD24 CD23 GND CD22 CD21 GND CD20 CD19 GND CD18 CD17 GND CD16 E3 GND E2 CD15 GND CD14 CD13 GND CD12 CD11 GND CD10 CD9 GND CD8 CD7 GND CD6 CD5 GND CD4 CD3 GND CD2 CD1 GND CD0 E1 GND E0 C-bus II Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission. PR EL IM IN +5V AUX19 AUX17 +5V AUX15 AUX13 BETA RELEASE AR YB ET A . 110 .

3V C-bus II Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.3V CD52 CD51 +3.Chapter 1: Connector Menu PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PB32 PB33 PB34 PB35 PB36 PB37 PB38 PB39 PB40 PB41 PB42 PB43 PB44 PB45 PB46 PB47 PB48 PB49 PB50 PB51 PB52 PB53 PB54 PB55 PB56 PB57 PB58 PB59 PB60 PB61 PB62 PB63 PB64 PB65 PB66 +5V AUX11 AUX9 +5V AUX7 AUX5 +5V AUX3 AUX1 +5V RESERVED9 RESERVED7 RESERVED5 RESERVED3 RESERVED1 VTERM +5V CID3 CID2 CID0 +5V FAULT# LOCKCB# +5V CARB3 CARB1 +5V TM3# TM1# +5V ACK# CD63 +5V CD62 CD61 +5V CD60 CD59 +5V CD58 CD57 +5V CD56 CD55 +3. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N. 111 .3V CD50 CD49 +3.3V E6 CD47 +3.3V CD48 E7 +3.3V CD54 CD53 +3. PR EL IM IN BETA RELEASE AR YB ET A .

3V CD34 CD33 +3.html> at Collary's homepage <http://www.3V CD38 CD37 +3.3V E4 C-bus II Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.corollary.collary.N OT Sources: C-bus II Technology architecture <http://www.3V CD32 E5 +3. 112 . PR EL IM IN BETA RELEASE AR YB ET A . Contributor: Joakim Ögren Please send any comments to Joakim Ögren.Chapter 1: Connector Menu PB67 PB68 PB69 PB70 PB71 PB72 PB73 PB74 PB75 PB76 PB77 PB78 PB79 PB80 PB81 PB82 PB83 PB84 PB85 PB86 PB87 PB88 PB89 PB90 PB91 CD46 CD45 +3.com> FO R RE DI ST RI BU TIO N.3V CD44 CD43 +3.3V CD42 CD41 +3.3V CD40 CD39 +3.com/cbusii.3V CD36 CD35 +3. It may not be modified and re-distributed without the authors permission.

Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. (At the device) UNKNOWN CONNECTOR at the motherboard. ST RI BU (At the motherboard) TIO N.N OT FO R Info: Solid State Floppy Disk Card Forum <http://www.com> RE DI I don't have any technical information about SSFDC at the moment.ssfdc. It may not be modified and re-distributed without the authors permission. UNKNOWN CONNECTOR at the device.Chapter 1: Connector Menu SSFDC Connector SSFDC=Solid State Floppy Disk Card. PR EL IM IN BETA RELEASE AR YB ET A . If you have any information of value please send it to me. 113 SSFDC . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

pc104. (At the backplane) Contributor: Joakim Ögren Sources: <http://www. It may not be modified and re-distributed without the authors permission.3 spec Sources: PC/104 pinout <http://www.org/pc104/consp1. 114 PC/104 .N OT FO R RE DI ST UNKNOWN CONNECTOR at the backplane.html> PC/104 v2.pc104.org/pc104/pinouts.org/pc104/consp5. UNKNOWN CONNECTOR at the device (card).html> Info: PC/104 Consortium <http://www. RI (At the device (card)) BU TIO N.pc104.Chapter 1: Connector Menu PC/104 Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.html> Please send any comments to Joakim Ögren. PR EL IM IN Pin J1/P1 Number Row A 0 -1 IOCHCHK* 2 SD7 3 SD6 4 SD5 5 SD4 6 SD3 7 SD2 8 SD1 9 SD0 10 IOCHRDY 11 AEN 12 SA19 13 SA18 14 SA17 15 SA16 16 SA15 17 SA14 18 SA13 19 SA12 20 SA11 21 SA10 22 SA9 23 SA8 24 SA7 25 SA6 26 SA5 27 SA4 28 SA3 29 SA2 30 SA1 31 SA0 32 0V J1/P1 Row B -0V RESETDRV +5V IRQ9 -5V DRQ2 -12V ENDXFR* +12V (KEY)2 SMEMW* SMEMR* IOW* IOR* DACK3* DRQ3 DACK1* DRQ1 REFRESH* SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2* TC BALE +5V OSC 0V 0V BETA RELEASE AR YB ET A J2/P2 Row C1 0V SBHE* LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR* MEMW* SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 -------------- J2/P2 Row D1 0V MEMCS16* IOCS16* IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0* DRQ0 DACK5* DRQ5 DACK6* DRQ6 DACK7* DRQ7 +5V MASTER* 0V (KEY)2 0V -------------- .

N OT FO R RE DI ST RI BU TIO N.Chapter 1: Connector Menu Unibus Connector Available on the old Digital PDP-11. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 2 x 36 EDGE MALE at the cards/modules. +------------//--------+ |AA1 AB1 AC1 // AU1 AV1| |AA2 AB2 AC2 // AU2 AV2| +------------//--------+ +------------//--------+ |BA1 BB1 BC1 // BU1 BV1| |BA2 BB2 BC2 // BU2 BV2| +------------//--------+ (At the computer) 2 x 36 EDGE FEMALE at the backplane. PIN AA1 AA2 AB1 AB2 AC1 AC2 AD1 AD2 AE1 AE2 AF1 AF2 AH1 AH2 AJ1 AJ2 AK1 AK2 AL1 AL2 AM1 AM2 AN1 AN2 AP1 AP2 AR1 AR2 AS1 AS2 AT1 AT2 AU1 AU2 AV1 AV2 BA1 BA2 BB1 BB2 BC1 BC2 SIGNAL /INIT POWER(+5v) /INTR GROUND /D00 GROUND /D02 /D01 /D04 /D03 /D06 /D05 /D08 /D07 /D10 /D09 /D12 /D11 /D14 /D13 /PA /D15 GROUND /PB GROUND /BBSY GROUND /SACK GROUND /NPR GROUND /BR7 NPG /BR6 BG7 GROUND BG6 POWER(+5v) BG5 GROUND /BR5 GROUND PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission. 115 Unibus .

com> Source: Digital PDP-11 peripherals handbook Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu BD1 BD2 BE1 BE2 BF1 BF2 BH1 BH2 BJ1 BJ2 BK1 BK2 BL1 BL2 BM1 BM2 BN1 BN2 BP1 BP2 BR1 BR2 BS1 BS2 BT1 BT2 BU1 BU2 BV1 BV2 GROUND /BR4 GROUND BG4 /ACLO /DCLO /A01 /A00 /A03 /A02 /A05 /A04 /A07 /A06 /A09 /A08 /A11 /A10 /A13 /A12 /A15 /A14 /A17 /A16 GROUND /C1 /SSYN /CO /MSYN GROUND Unibus Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 116 . Contributor: Rob Gill <gillr@mailcity.

N OT FO R RE DI ST 25 PIN D-SUB MALE at the DTE (Computer). 25 PIN D-SUB FEMALE at the DCE (Modem). It may not be modified and re-distributed without the authors permission. (At the DTE) Contributor: Joakim Ögren. 117 RS232 .Chapter 1: Connector Menu RS232 Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. RI (At the DCE) BU TIO N. Note: Do not connect SHIELD(1) to GND(7).CTS S. YB Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name GND TXD RXD RTS CTS DSR GND CD STF S. Petr Krc <magneton@mail.cz> Please send any comments to Joakim Ögren.RXD RCK LL S.TXD TCK S. PR EL IM IN Source: ? BETA RELEASE AR Note: Direction is DTE (Computer) relative DCE (Modem).RTS DTR RL RI DSR XCK TI ITU-T Dir 101 103 104 105 106 107 102 109 126 ? ? ? 114 ? 115 141 ? 108 140 125 111 113 142 Description Shield Ground Transmit Data Receive Data Request to Send Clear to Send Data Set Ready System Ground Carrier Detect RESERVED RESERVED Select Transmit Channel Secondary Carrier Detect Secondary Clear to Send Secondary Transmit Data Transmission Signal Element Timing Secondary Receive Data Receiver Signal Element Timing Local Loop Control Secondary Request to Send Data Terminal Ready Remote Loop Control Ring Indicator Data Signal Rate Selector Transmit Signal Element Timing Test Indicator ET A .firstnet.CD S.

Chapter 1: Connector Menu Serial (PC 9) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N. 118 Serial (PC 9) . Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. (At the Computer) 9 PIN D-SUB MALE at the Computer. PR EL IM IN BETA RELEASE AR YB ET A . Pin 1 2 3 4 5 6 7 8 9 Name Dir CD RXD TXD DTR GND DSR RTS CTS RI Description Carrier Detect Receive Data Transmit Data Data Terminal Ready System Ground Data Set Ready Request to Send Clear to Send Ring Indicator Note: Direction is DTE (Computer) relative DCE (Modem).

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name SHIELD TXD RXD RTS CTS DSR GND CD n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c DTR n/c RI n/c n/c n/c Dir Description Shield Ground Transmit Data Receive Data Request to Send Clear to Send Data Set Ready System Ground Carrier Detect - Data Terminal Ready Ring Indicator - Note: Direction is DTE (Computer) relative DCE (Modem).Chapter 1: Connector Menu Serial (PC 25) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (At the computer) 25 PIN D-SUB MALE at the computer. PR EL IM IN BETA RELEASE AR YB Contributor: Joakim Ögren ET A . It may not be modified and re-distributed without the authors permission. 119 Serial (PC 25) . Note: Do not connect SHIELD(1) to GND(7). Source: Amiga 4000 User's Guide from Commodore Please send any comments to Joakim Ögren.N - OT - FO R RE DI ST RI BU TIO N.

Source: Amiga 4000 User's Guide from Commodore Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB Contributor: Joakim Ögren ET A +12 Volts DC (20 mA max) C2=Clock 3.Chapter 1: Connector Menu Serial (Amiga 1000) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N Data Terminal Ready +5 Volts DC OT ? - -5 Volts DC (50mA max) Amiga Audio Out (Left) Amiga Audio In (Right) EB=Buffered Port Clock 716 kHz Interrupt 2 FO R - RE DI ST RI BU TIO N. 120 Serial (Amiga 1000) .58MHz Reset . It may not be modified and re-distributed without the authors permission. Note: Do not connect SHIELD(1) to GND(7). Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name SHIELD TXD RXD RTS CTS DSR GND CD n/c n/c n/c n/c n/c -5V AUDO AUDI EB /INT2 n/c DTR +5V n/c +12V /C2 /RESET Dir Description Shield Ground Transmit Data Receive Data Request to Send Clear to Send Data Set Ready System Ground Carrier Detect - Note: Direction is DTE (Computer) relative DCE (Modem). (At the Amiga 1000) 25 PIN D-SUB MALE at the Amiga 1000.

25 PIN D-SUB FEMALE at the cable. Note: Do not connect SHIELD(1) to GND(7).N - Description Shield Ground Transmit Data Receive Data Request to Send Clear to Send Data Set Ready System Ground Carrier Detect +12 Volts DC (20 mA max) -12 Volts DC (20 mA max) Amiga Audio Out (Left) Speed Indicate OT FO R RE DI ST 25 PIN D-SUB MALE at the computer. It may not be modified and re-distributed without the authors permission. YB Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name SHIELD TXD RXD RTS CTS DSR GND CD +12V -12V AUDO n/c n/c n/c n/c n/c n/c AUDI n/c DTR n/c RI n/c n/c n/c Dir Amiga Audio In (Right) Data Terminal Ready - Ring Indicator - ET A - . RI (At the cable) BU TIO N. (At the computer) Contributor: Joakim Ögren Please send any comments to Joakim Ögren.Chapter 1: Connector Menu Serial (Amiga) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 121 Serial (Amiga) . PR EL IM IN Source: Amiga 4000 User's Guide from Commodore BETA RELEASE AR Note: Direction is DTE (Computer) relative DCE (Modem).

Pin 1 2 3 4 5 6 7 8 9 Name Dir PG TXD RXD RTS CTS DSR GND DCD DTR Description Protective Ground Transmit Data Receive Data Request to Send Clear to Send Data Set Ready Signal Ground Carrier Detect Data Terminal Ready Note: Direction is DTE (Computer) relative DCE (Modem).N OT FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .com/fms/MSX/Portar.Chapter 1: Connector Menu Serial (MSX) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 122 Serial (MSX) . (At the Computer) 9 PIN D-SUB FEMALE at the Computer.freeflight. Contributor: Joakim Ögren Source: Mayer's SV738 X'press I/O map <http://www.txt> Please send any comments to Joakim Ögren.

Petr Krc <magneton@mail.cz> Source: ? Please send any comments to Joakim Ögren. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name SHIELD TXD RXD n/c n/c DSR GND DCD n/c n/c ? n/c n/c n/c n/c n/c TTY-TXD n/c n/c DTR n/c n/c ? ? TTY-RXD Dir Description Shield Ground Transmit Data Receive Data Not connected Not connected Data Set Ready System Ground Data Carrier Detect Not connected Not connected Reverse Channel Not connected Not connected Not connected Not connected Not connected TTY Receive Data Not connected Not connected Data Terminal Ready Not connected Not connected TTY Receive Data Return TTY Transmit Data Return TTY Receive Data - Contributor: Joakim Ögren. (At the printer) 25 PIN D-SUB MALE at the printer.firstnet. 123 Serial (Printer) . PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu Serial (Printer) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N - OT - FO - R RE - DI ST RI BU TIO N.

Gilles Ries <gries@glo. +5 VDC Clock Not connected Note: Direction is Computer relative Mouse.Chapter 1: Connector Menu Mouse (PS/2) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.be> Source: ? Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission. Contributor: Joakim Ögren.N OT FO R RE DI ST RI BU TIO N. Pin 1 2 3 4 5 6 Name Dir DATA n/c GND VCC CLK n/c Description Key Data Not connected Gnd Power . (At the computer) 6 PIN MINI-DIN FEMALE (PS/2 STYLE) at the computer. PR EL IM IN BETA RELEASE AR YB ET A . 124 Mouse (PS/2) .

Chapter 1: Connector Menu Serial (15) Connector Seems to be available at a 14. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name GROUND SUSP# COMBDSR# COMBRTS# COMBCTS# COMBRI# n/c GROUND +5VIN COMBDTR# COMBDCD# COMBTXD COMBRXD SPKDATA GROUND RS232 Dir GND ? DSR RTS CTS RI ? GND Description Ground DTR CD TXD RXD Ground +5V DC In Data Terminal Ready Carrier Detect Transmit Data Receive Data GND Ground Source: ? Please send any comments to Joakim Ögren.N Contributor: Joakim Ögren. Joerg Brinkel <jb@itm.de> OT ? FO R RE Data Set Ready Request to Send Clear to Send Ring Indicator DI ST RI (At the modem) BU TIO N. PR EL IM IN BETA RELEASE AR YB ET A . 125 Serial (15) . It may not be modified and re-distributed without the authors permission. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.rwth-aachen. 2 4 6 10 12 14 .[][][][][][][][][][][][][][][] 1 3 5 7 8 9 11 13 15 15 PIN FEMALE ??? at the modem.4kbps modem called Speedster.

brouhaha. DEC Dual RS-232 126 .cs.vt.vt. It may not be modified and re-distributed without the authors permission. Contributor: Joakim Ögren. (At the computer) 25 PIN D-SUB MALE at the computer.cs.edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. The 1st Port is located on the normal pins.N OT FO R RE DI ST RI BU TIO N.Chapter 1: Connector Menu DEC Dual RS-232 Connector Found on the DEC Multia and DEC UDB (Universal Desktop Box). Woods <woods@weird. and the 2nd port is located on some "spare" pins. PR EL IM IN BETA RELEASE AR YB 2 ET A .com> Please send any comments to Joakim Ögren.com> Sources: Tommy's pinout Collection <http://csgrad. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Port 1 1 1 1 1 1+2 1 Name Dir n/c TXD RXD RTS CTS DSR GND DCD n/c n/c DTR DCD CTS TXD n/c RXD n/c n/c RTS DTR n/c RI DSR n/c RI Description Not connected Transmit Data Receive Data Ready To Send Clear To Send Data Set Ready Ground Data Carrier Detect Not connected Not connected Data Terminal Ready Data Carrier Detect Clear To Send Transmit Data Not connected Receive Data Not connected Not connected Ready To Send Data Terminal Ready Not connected Ring Indicator Data Set Ready Not connected Ring Indicator 2 2 2 2 2 2 1 1 2 Note: Direction is DTE (Computer) relative DCE (Modem). It contains two Serial ports on one connector.edu> Sources: Digital UDB Information <http://www. Greg A.com/~eric/computers/udb.html> by Eric Smith <eric@brouhaha.

Article ID: TECHINFO-0001699 OT Contributor: Joakim Ögren. It may not be modified and re-distributed without the authors permission. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.ca>. Ben Harris <bjh@mail.sys.edu> FO Note: GPi is connected to SCC Data Carrier Detect (or to Receive/Transmit Clock if the VIA1 SYNC signal is high). Use RXD.dotcom. Nathan Schmidt <nathans@stanford.html> Sources: Apple Tech Info Library. Classic II. LC II or IIsi. Pierre Olivier <olipie@aei. Ground RXD+. Macintosh RS-422 127 .mac. RE DI ST RI BU TIO N. LC. Pin 1 2 3 4 5 6 7 8 Name Dir HSKo HSKi/CLK TXDGND RXDTXD+ GPi RXD+ Description Output Handshake Input Handshake or External Clock Transmit Data (-) Ground Receive Data (-) Transmit Data (+) General Purpose Input Receive Data (+) Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . GPi as CD.cis. Not connected on the Macintosh Plus. Classic. R Note: Direction is DTE (Computer) relative DCE (Modem).N Sources: comp.as RXD.Chapter 1: Connector Menu Macintosh RS-422 Connector It's possible to connect RS-232 peripheral to the RS-422 port available on Macintosh computers.comm FAQ Part 1 <http://www.edu/hypertext/faq/usenet/macintosh/comm-faq/part1/faq. (At the computer) 8 PIN MINI-DIN FEMALE at the computer.ohio-state.as TXD. TXD.fr>. Leave TXD+ unconnected.

It may not be modified and re-distributed without the authors permission. 128 RS422 .Chapter 1: Connector Menu RS422 Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Petr Krc <magneton@mail. 37 PIN D-SUB FEMALE at the DCE (Modem).N OT FO R RE DI ST 37 PIN D-SUB MALE at the DTE (Computer). RI (At the DCE) BU TIO N. (At the DTE) Note: Direction is DTE (Computer) relative DCE (Modem).firstnet.cz> Source: ? Please send any comments to Joakim Ögren. Contributor: Joakim Ögren. PR EL IM IN Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Name Dir GND SRI n/c SD ST RD RTS RR CTS LL DM TR RR RL IC SF/SR TT TM GND RC GND /SD GND GND /RS /RT /CS IS /DM /TR /RR SS SQ NS /TT SB SC Description Shield Ground Signal Rate Indicator Spare Send Data Send Timing Receive Data Request To Send Receiver Ready Clear To Send Local Loopback Data Modem Terminal Ready Receiver Ready Remote Loopback Incoming Call Select Frequency/Select Rate Terminal Timing Test Mode Ground Receive Twister-Pair Common Spare Twister-Pair Return Send Data TPR Send Timing TPR Receive Timing TPR Request To Send TPR Receive Timing TPR Clear To Send TPR Terminal In Service Data Mode TPR Terminal Ready TPR Receiver TPR Select Standby Signal Quality New Signal Terminal Timing TPR Standby Indicator Send Twister Pair Common BETA RELEASE AR YB ET A .

9 PIN D-SUB MALE at the mouse cable. It may not be modified and re-distributed without the authors permission. it may be converted into output handshake in later equipment.N Contributor: Ben Harris <bjh@mail. Source: Apple Tech Info Library. negative going component +12 VDC Handshake input. positive going component Receive Data. negative going component R RE DI ST RI BU (At the Computer) TIO N. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Article ID: TECHINFO-0001424 PR EL IM IN BETA RELEASE AR YB ET A Please send any comments to Joakim Ögren.fr> OT 8 9 Rx+ Rx- FO 3 4 5 6 7 GND Tx+ Tx+12V DSR/HSK Description Ground +5 VDC. Pin Name 1 GND 2 +5V Dir Note: Direction is Computer relative Equipment. (At the Equipment) 9 PIN D-SUB FEMALE at the computer. Receive Data. . Signal name depends on mode: Used for Flow Control or Clock In.Chapter 1: Connector Menu Macintosh Serial Connector Available on Macintosh Mac 512KE and earlier. Ground Transmit Data.dotcom. 129 Macintosh Serial . Don't use this one. positive going component Transmit Data.

It's just the normal User Port.Chapter 1: Connector Menu C64 RS232 User Port Connector Available on the Commodore C64/C128. Software emulated.sys. Pin A B+C D E F H K L M N Name GND FLAG2+PB0 PB1 PB2 PB3 PB4 PB6 PB7 PA2 GND RS232 GND RxD RTS DTR RI DCD CTS DSR TxD GND Contributor: Joakim Ögren.edu/~thompsbb/cbm_conn. C64 RS232 User Port 130 .N OT Source: Usenet posting in comp. Help on modem -> c64 <http://www. Arwin Vosselman <0vosselman01@flnet.edu> Sources: Commodore 64 Programmer's Reference Guide FO R Description Protective Ground Receive Data (Must be applied to both pins!) Ready To Send Data Terminal Ready Ring Indicator Data Carrier Detect Clear To Send Data Set Ready Transmit Data Signal Ground RE DI ST RI BU TIO N.nl>. used as a RS232 port. (At the computer) UNKNOWN CONNECTOR at the computer. Mark Sokos <msokos1@gl.edu> Please send any comments to Joakim Ögren. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .cbm. It's TTL level. and RXD/TXD is inverted. The signals does not have true RS232 levels.txt> by Lasher Glenn <gl8574@lima.umbc.albany.vuse.vanderbilt.

It may not be modified and re-distributed without the authors permission.fr> Source: DEC DLV11-J Printset.dotcom.(0V for RS-232. 10 PIN IDC MALE at the Serial card.N OT FO R RE DI ST RI BU (at the serial card) TIO N. Reader enable for 20mA) Ground Not connected (no pin) Receive data Receive data + Ground +12 VDC Note: Direction is Serial card relative other Devices. M8043-0-1.Chapter 1: Connector Menu DEC DLV11-J Serial Connector Available on the DEC DLV11-J Serial card The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. sheet 7 Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . 131 DEC DLV11-J Serial . Contributor: Ben Harris <bjh@mail. Pin 1 2 3 4 5 6 7 8 9 10 Name Dir CLK ? GND TXD+ TXDGND n/c RXDRXD+ GND +12V Description Clock Ground Transmit data + Transmit data .

Pin 1 2 3 4 5 6 7 8 Name RTS DTR TXD n/c n/c RXD DSR CTS Description Dir Request To Send Data Terminal Ready Tranceive Data Not connected Not connected Receive Data Data Set Ready Clear To Send Source: ? Please send any comments to Joakim Ögren. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. RJ45 MALE CONNECTOR at the cables.Chapter 1: Connector Menu Cisco Console Port Connector Used to configure a Cisco router.N Contributor: Joakim Ögren.sg> OT FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission.com. 132 Cisco Console Port . PR EL IM IN BETA RELEASE AR YB ET A . (At the Cisco hub) (At the cables) RJ45 FEMALE CONNECTOR at the Cisco routers. Damien Miller <dmiller@vitnet.

133 RocketPort Serialport . RJ45 MALE CONNECTOR at the cables. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Karl Asha <karl@blackdown. DI ST RI BU TIO N.N Contributor: Joakim Ögren.com> OT Pin 1 2 3 3 6 6 7 8 Name RTS DTR GND TXD RXD DCD DSR CTS Description Dir Request To Send Data Terminal Ready Ground Tranceive Data Receive Data Data Carrier Detect Data Set Ready Clear To Send FO R RE RJ45 FEMALE CONNECTOR at the RocketPort card. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu RocketPort Serialport Connector Available at RocketPort serialport expansion cards. PR EL IM IN BETA RELEASE AR YB ET A . (At the RocketPort card) (At the cables) Source: ? Please send any comments to Joakim Ögren.

Chapter 1: Connector Menu CoCo Serial Printer Connector Available on the Tandy Color Computer. 134 CoCo Serial Printer .com> Source: Tandy TRP 100 printer manual Please send any comments to Joakim Ögren.N OT FO R RE DI ST RI BU (At the computer) TIO N. 4 PIN DIN 270° FEMALE at the computer. Pin 1 2 3 4 Name Description NC /BUSY Enabled when the printer is busy GND DATA RS-232 level data Contributor: Rob Gill <gillr@mailcity. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. also known as CoCo. PR EL IM IN BETA RELEASE AR YB ET A .

5 PIN UNKNOWN CONNECTOR at the multimeter Conrad Name 1 RTS 2 RXD 3 TXD 4 DTR 5 GND Description Dir Request To Send Receive Data Transmit Data Data Terminal Ready Ground Note: Since the multimeter is a DCE the pin naming can seem strange. Anselm Belz <a. It may not be modified and re-distributed without the authors permission.de> Source: ? Please send any comments to Joakim Ögren. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Conrad Electronics MM3610D 135 .Chapter 1: Connector Menu Conrad Electronics MM3610D Connector This connector is available on the Conrad Electronics Multimeter 3610D and is used to connect it to a computer.belz@samson. (At the multimeter).N OT FO R RE DI ST RI BU TIO N. Contributors: Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .mbis.

(At the PC) 25 PIN D-SUB FEMALE at the PC. Petr Krc <magneton@mail.Chapter 1: Connector Menu Parallel (PC) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name Dir /STROBE D0 D1 D2 D3 D4 D5 D6 D7 /ACK BUSY PE SEL /AUTOFD /ERROR /INIT /SELIN GND GND GND GND GND GND GND GND Description Strobe Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Acknowledge Busy Paper End Select Autofeed Error Initialize Select In Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Note: Direction is Computer relative Device. It may not be modified and re-distributed without the authors permission.firstnet.cz> Source: ? Please send any comments to Joakim Ögren.N OT FO R RE DI ST RI BU TIO N. PR EL IM IN BETA RELEASE AR YB ET A . Contributor: Joakim Ögren. 136 Parallel (PC) .

N OT FO R RE DI ST RI BU TIO N. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name Dir /STROBE D0 D1 D2 D3 D4 D5 D6 D7 /ACK BUSY POUT SEL +5V PULLUP n/c /RESET GND GND GND GND GND GND GND GND GND Note: Direction is Computer relative Peripheral. 137 Parallel (Amiga) . Contributor: Joakim Ögren Source: Amiga 4000 User's Guide from Commodore Please send any comments to Joakim Ögren. Reset Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground . It may not be modified and re-distributed without the authors permission. (At the Amiga) 25 PIN D-SUB FEMALE at the Amiga. PR EL IM IN BETA RELEASE AR YB ET A Description Strobe Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Acknowledge Busy Paper Out Select (Shared with RS232 RING-indicator) +5 Volts DC (10 mA max) Not connected.Chapter 1: Connector Menu Parallel (Amiga) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

PR EL IM IN BETA RELEASE AR YB ET A Description Strobe Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Acknowledge Busy Paper Out Select (Shared with RS232 RING-indicator) Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground +5 Volts DC (10 mA max) Not connected. 138 Parallel (Amiga 1000) .N OT FO R RE DI ST RI BU TIO N. Reset . It may not be modified and re-distributed without the authors permission. Contributor: Joakim Ögren Source: Amiga 4000 User's Guide from Commodore Please send any comments to Joakim Ögren. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name Dir /STROBE D0 D1 D2 D3 D4 D5 D6 D7 /ACK BUSY POUT SEL GND GND GND GND GND GND GND GND GND +5V n/c /RESET Note: Direction is Computer relative Peripheral.Chapter 1: Connector Menu Parallel (Amiga 1000) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (At the Amiga 1000) 25 PIN D-SUB MALE at the Amiga 1000.

Data or RLE Data Bit 6 Address. Marco Furter <maf@pop. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name Dir nStrobe data0 data1 data2 data3 data4 data5 data6 data7 /nAck Busy PError Select /nAutoFd /nFault /nInit /nSelectIn GND GND GND GND GND GND GND GND Description Strobe Address.com/msdn> YB ET A . Data or RLE Data Bit 0 Address.ch> Source: Microsoft MSDN Library: Extended Capabilities Port Specs Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR Info: Microsoft MSDN Library <http://www. It may not be modified and re-distributed without the authors permission.microsoft. Data or RLE Data Bit 4 Address. Data or RLE Data Bit 3 Address. 139 ECP Parallel .agri. Contributor: Joakim Ögren.Chapter 1: Connector Menu ECP Parallel Connector ECP = Extended Capabilities Port The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Data or RLE Data Bit 7 Acknowledge Busy Paper End Select Autofeed Error Initialize Select In Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Note: Direction is Computer relative Device. Data or RLE Data Bit 5 Address. Data or RLE Data Bit 2 Address. Data or RLE Data Bit 1 Address.N OT FO R RE DI ST RI BU (At the PC) TIO N. 25 PIN D-SUB FEMALE at the PC.

In the reverse direction this signal indicates that the data is RLE compressed by being low. handshaking with nAck in the reverse direction.microsoft. Sets the transfer direction. Signal Descriptions: nStrobe data 0-7 nAck Contains address. data or RLE data. Can be used in both directions. ET A .Chapter 1: Connector Menu ECP Parallel (Tech) Connector This file is designed to give a basic overview of the port found in most newer PC computers called ECP Parallel port. It may not be modified and re-distributed without the authors permission. Rob Gill <gillr@mailcity. TIO N. In the forward direction this signal indicates whether the data lines contain ECP address or data. PError Select Printer is online. Low=Forward. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Busy This signal deasserts to indicate that the peripheral can accept data.com> Source: Microsoft MSDN Library: Extended Capabilities Port Specs Info: Microsoft MSDN Library <http://www. It is for informational purposes only.com/msdn> Please send any comments to Joakim Ögren. and is intended to give designers and hobbyists sufficient information to design their own ECP compatible devices. Contributor: Joakim Ögren . Valid data driven by the peripheral when asserted. PR EL IM IN BETA RELEASE AR YB Requests a byte of data from the peripheral when asserted. RI BU This file is not intended to be a thorough coverage of the standard. ECP Parallel (Technical) 140 . In forward direction this handshakes with nStrobe.N OT FO R RE DI ST This signal is registers data or address into the slave on the assering edge during . Used to acknowledge a change in the direction of transfer. High=Forward. nAutoFd nFault nInit nSelectIn Generates an error interrupt when asserted. Low in ECP mode. This signal handshakes with nAutoFd in reverse. High=Reverse.

Peter Korsgaard <jacmet@post5.Chapter 1: Connector Menu Centronics Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.firstnet.N OT FO R RE DI ST RI BU TIO N. Petr Krc <magneton@mail. (At the Printer) 36 PIN CENTRONICS FEMALE at the Printer. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name Dir /STROBE D0 D1 D2 D3 D4 D5 D6 D7 /ACK BUSY POUT SEL /AUTOFEED n/c 0V CHASSIS GND +5 V PULLUP GND GND GND GND GND GND GND GND GND GND GND /GNDRESET /RESET /FAULT 0V n/c +5 V /SLCT IN Note: Direction is Printer relative Computer. 141 Centronics .tele. Contributor: Joakim Ögren. It may not be modified and re-distributed without the authors permission. PR EL IM IN Description Strobe Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Acknowledge Busy Paper Out Select Autofeed Not used Logic Ground Shield Ground +5 V DC (50 mA max) Signal Ground (Strobe Ground) Signal Ground (Data 0 Ground) Signal Ground (Data 1 Ground) Signal Ground (Data 2 Ground) Signal Ground (Data 3 Ground) Signal Ground (Data 4 Ground) Signal Ground (Data 5 Ground) Signal Ground (Data 6 Ground) Signal Ground (Data 7 Ground) Signal Ground (Acknowledge Ground) Signal Ground (Busy Ground) Reset Ground Reset Fault (Low when offline) Signal Ground Not used +5 V DC Select In (Taking low or high sets printer on line or off line respectively) BETA RELEASE AR YB ET A .dk>.cz> Source: ? Please send any comments to Joakim Ögren.

com/fms/MSX/Portar.freeflight. PR EL IM IN BETA RELEASE AR YB ET A . Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name /STB PDB0 PDB1 PDB2 PDB3 PDB4 PDB5 PDB6 PDB7 n/c BUSY n/c n/c GND Dir Description Strobe Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 - Printer is busy Signal Ground Note: Direction is Computer relative Printer.Chapter 1: Connector Menu MSX Parallel Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.txt> Please send any comments to Joakim Ögren.N OT FO R RE DI ST RI BU TIO N. Contributor: Joakim Ögren Source: Mayer's SV738 X'press I/O map <http://www. 142 MSX Parallel . (At the Computer) 14 PIN CENTRONICS FEMALE at the Computer.

Filippo Fiani <nathannever@rocketmail. 26 PIN IDC MALE at the Computer. ET A .Chapter 1: Connector Menu Parallel (Olivetti M10) Connector Available on an old portable computer called Olivetti M10.com> Source: ? Please send any comments to Joakim Ögren. 143 Parallel (Olivetti M10) .N OT FO R RE DI ST RI BU (At the Computer) TIO N. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB Note: Direction is Computer relative Device. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Name Dir /STROBE D0 D1 D2 D3 D4 D5 D6 D7 /ACK BUSY PE SELIN GND GND GND GND GND GND GND GND GND GND GND RESETGND /RESET Description Strobe Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Acknowledge Busy Paper End Select In Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Reset Ground Reset Contributor: Joakim Ögren.

uk> Source: Amstrad CPC6128 User Instructions Manual Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission. 144 Amstrad CPC6128 Printer Port .N OT FO R RE DI ST RI BU TIO N.diron.co. PR EL IM IN Note: Pin 18 does not exist BETA RELEASE AR YB ET A . (At the computer) 34 PIN FEMALE EDGE at the computer. Agnello Guarracino <aggy@ooh.Chapter 1: Connector Menu Amstrad CPC6128 Printer Port Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 16 17 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Name /STROBE D0 D1 D2 D3 D4 D5 D6 GND n/c BUSY n/c n/c GND n/c n/c n/c GND n/c GND GND GND GND GND GND GND GND n/c GND n/c n/c n/c n/c GND n/c n/c Description Strobe Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Ground Not connected Busy Not connected Not connected Ground Not connected Not connected Not connected Ground Not connected Ground Ground Ground Ground Ground Ground Ground Ground Not connected Ground Not connected Not connected Not connected Not connected Ground Not connected Not connected Contributor: Joakim Ögren.

0 at USB Implementers Forum <http://www. Microsoft.Chapter 1: Connector Menu Universal Serial Bus (USB) Connector Developed by Compaq. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 4 PIN ??? FEMALE at the peripherals. ST (At the peripherals) RI BU TIO N. NEC and Northern Telecom.org> Sources: USB Specification v1.usb. IBM PC Co.htm> at USB Implementers Forum <http://www.. Universal Serial Bus (USB) 145 . It may not be modified and re-distributed without the authors permission.org> PR EL IM IN BETA RELEASE AR YB ET A . Intel. Digital Equipment Corp.com/~usb/usbfaq.N OT Please send any comments to Joakim Ögren. FO R RE DI 4 PIN ??? MALE at the controller.teleport. (At the controller) Pin 1 2 3 4 Name VCC DD+ GND Description +5 VDC Data Data + Ground Contributor: Joakim Ögren Sources: USB FAQ <http://www.usb.

RE DI ST RI BU TIO N. Intel.5 Mbps speed (non-shielded cable) Definitions: Power usage: Voltage: Shielding: Cable: Shield should only be connected to Ground at the host.35 V from it's host or hub to the hubs output port.Easy of use . Self-powered hubs: Draw Max 100 mA. USB Device = A hub or a Function.Full speed: 12 Mbps speed (requires shielded cable) .25 V. .Hot plug and unplug . must supply 500 mA to each port.127 physical devices . but only low-power functions need to be working at this voltage. Features: . YB ET A . Self-powered functions: Draw Max 100 mA. .20 AWG non-twisted Non-shielded: Data: 28 AWG non-twisted Power: 28 AWG . Universal Serial Bus (USB) (Technical) 146 .N Bus-powered hubs: Draw Max 100 mA at power up and 500 mA normally. bus-powered functions: Draw Max 100 mA.Chapter 1: Connector Menu Universal Serial Bus (USB) (Tech) Connector USB was developed by Compaq.Supplied voltage by a host or a powered hub ports is between 4.True Plug'n'Play.20 AWG non-twisted Power Gauge Max length PR EL IM IN BETA RELEASE AR . must supply 500 mA to each port.Low cost . NEC and Northern Telecom. IBM PC Co.4 V. It may not be modified and re-distributed without the authors permission.Maximum voltage drop for bus-powered hubs is 0. High power. only one host per USB system.75 V and 5.Normal operational voltage for functions is minimum 4.Low cost cables and connectors Bandwidth: . Shielded: Data: 28 AWG twisted Power: 28 AWG . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. . Low power. bus-powered functions: Self-powered hubs: Draw Max 100 mA..Low speed: 1. No device should connect Shield to Ground. Microsoft. Suspended device: Max 0. .75 V.5 mA OT FO R USB Host = The computer.All hubs and functions must be able to send configuration data at 4. Digital Equipment Corp.

usb. Universal Serial Bus (USB) (Tech) Connector Cable colors: Pin 1 2 3 4 Name VCC DD+ GND Cable colorDescription Red +5 VDC White Data Green Data + Black Ground Please send any comments to Joakim Ögren.00 m .com/~usb/usbfaq.org> ST Contributor: Joakim Ögren RI BU TIO N. PR EL IM IN BETA RELEASE AR YB ET A .33 m 5.teleport. It may not be modified and re-distributed without the authors permission.htm> at USB Implementers Forum <http://www.org> Sources: USB Specification v1.08 m 3.81 m 1.0 at USB Implementers Forum <http://www.31 m 2.usb.Chapter 1: Connector Menu 28 26 24 22 20 The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI Sources: USB FAQ <http://www. 147 0.

GeekPort 148 .N OT FO R RE DI 37 PIN D-SUB MALE CONNECTOR at the device. ST RI BU TIO N. It may not be modified and re-distributed without the authors permission. This is a dream for all hobby engineers who like to connect the computer to the coffee machine. (At the device) (At the computer) Note: Direction is Computer relative Device.Chapter 1: Connector Menu GeekPort Connector The GeekPort is a connector available at Be's BeBox computers. 37 PIN D-SUB FEMALE CONNECTOR at the computer. Contributor: Joakim Ögren PR EL IM IN Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Name GND A1 A3 A5 A7 GND +5V GND +12V GND -12V GND +5V GND B0 B2 B4 B6 GND A0 A2 A4 A6 AIref A2D1 A2D2 A2D3 A2D4 D2A1 D2A2 D2A3 D2A4 AOref B1 B3 B5 B7 Description Dir Ground Digital A 1 Digital A 3 Digital A 5 Digital A 7 Ground +5 VDC Ground +12 VDC Ground -12 VDC Ground +5 VDC Ground Digital B 0 Digital B 2 Digital B 4 Digital B 6 Ground Digital A 0 Digital A 2 Digital A 4 Digital A 6 Analog In Reference Analog In 1 Analog In 2 Analog In 3 Analog In 4 Analog Out 1 Analog Out 2 Analog Out 3 Analog Out 4 Analog Out Reference Digital B 1 Digital B 3 Digital B 5 Digital B 7 BETA RELEASE AR YB ET A . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

be.html> at Be's homepage <http://www.Chapter 1: Connector Menu GeekPort Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.com/documentation/be_book/DeviceKit/DPort. Sources: BeBox GeekPort DeviceKit <http://www. It may not be modified and re-distributed without the authors permission.html> Sources: BeBox GeekPort DeviceKit: Digital port <http://www.com/documentation/be_book/DeviceKit/A2D2A.be.be.com/documentation/be_book/DeviceKit/geek.html> 149 . Please send any comments to Joakim Ögren.com> Sources: BeBox GeekPort DeviceKit: Analog port <http://www.be.N OT FO R RE DI ST RI BU TIO N. PR EL IM IN BETA RELEASE AR YB ET A .

Chapter 1: Connector Menu

C64 Serial I/O Connector

Available on the Commodore C64, C16, C116 and +4 computers.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the cable) 6 PIN DIN (DIN45322) FEMALE at the Computer. 6 PIN DIN (DIN45322) MALE at the Cable. Pin 1 2 3 4 5 6 Name /SRQIN GND ATN CLK DATA /RESET Description Serial SRQIN Ground Serial ATN In/Out Serial CLK In/Out Serial DATA In/Out Reset

Source: SAMS Computerfacts CC8 Commodore 16.
Please send any comments to Joakim Ögren.

PR EL IM IN

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AR

YB

ET A

.N

OT

FO

Contributor: Joakim Ögren, Arwin Vosselman <0vosselman01@flnet.nl>

R

RE

DI

ST

RI

BU

(At the computer)

TIO N.
150

C64/C16/C116/+4 Serial I/O

Chapter 1: Connector Menu

Atari ACSI DMA Connector

Used to connect Laser printers or Harddrives.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the Devices) 19 PIN D-SUB ?? at the Computer. 19 PIN D-SUB ?? at the Devices. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name D0 D1 D2 D3 D4 D5 D6 D7 /CS IRQ GND /RST GND ACK GND A1 GND R/W REQ Description Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Chip Select Interrupt Request Ground Reset Ground Acknowledge Ground ? Ground Read/Write Data Request

Source: ?

Please send any comments to Joakim Ögren.

PR EL IM IN

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Contributor: Joakim Ögren, Lawrence Wright <lwright@silk.net>, Steve & Sally Blair <blair@mailbox.uq.edu.au>

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Atari ACSI DMA

Chapter 1: Connector Menu

VGA (VESA DDC) Connector

VGA=Video Graphics Adapter or Video Graphics Array. VESA=Video Electronics Standards Association. DDC=Display Data Channel.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

Videotype: Analogue.

(At the videocard)

Note: Direction is Computer relative Monitor.
Source: ?

Please send any comments to Joakim Ögren.

PR EL IM IN

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Contributor: Joakim Ögren

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Name Dir RED GREEN BLUE RES GND RGND GGND BGND +5V SGND ID0 SDA HSYNC or CSYNC VSYNC SCL

Description Red Video (75 ohm, 0.7 V p-p) Green Video (75 ohm, 0.7 V p-p) Blue Video (75 ohm, 0.7 V p-p) Reserved Ground Red Ground Green Ground Blue Ground +5 VDC Sync Ground Monitor ID Bit 0 (optional) DDC Serial Data Line Horizontal Sync (or Composite Sync) Vertical Sync DDC Data Clock Line

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VGA (VESA DDC)

Chapter 1: Connector Menu

VGA (15) Connector

VGA=Video Graphics Adapter or Video Graphics Array. Videotype: Analogue.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the videocard)

Contributor: Joakim Ögren Source: ?

PR EL IM IN

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Note: Direction is Computer relative Monitor.

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Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Name Dir RED GREEN BLUE ID2 GND RGND GGND BGND KEY SGND ID0 ID1 or SDA HSYNC or CSYNC VSYNC ID3 or SCL

Description Red Video (75 ohm, 0.7 V p-p) Green Video (75 ohm, 0.7 V p-p) Blue Video (75 ohm, 0.7 V p-p) Monitor ID Bit 2 Ground Red Ground Green Ground Blue Ground Key (No pin) Sync Ground Monitor ID Bit 0 Monitor ID Bit 1 Horizontal Sync (or Composite Sync) Vertical Sync Monitor ID Bit 3

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VGA (15)

Chapter 1: Connector Menu

VGA (9) Connector

VGA=Video Graphics Adapter or Video Graphics Array. Videotype: Analogue.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the videocard)

Pin 1 2 3 4 5 6 7 8 9

Name Dir RED GREEN BLUE HSYNC VSYNC RGND GGND BGND SGND

Description Red Video Green Video Blue Video Horizontal Sync Vertical Sync Red Ground Green Ground Blue Ground Sync Ground

Note: Direction is Computer relative Monitor.
Contributor: Joakim Ögren Source: ?
Please send any comments to Joakim Ögren.

PR EL IM IN

BETA RELEASE

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VGA (9)

Chapter 1: Connector Menu

CGA Connector

CGA=Color Graphics Adapter. Videotype: TTL, 16 colors. Also known as IBM RGBI.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the videocard)

(At the monitor cable) 9 PIN D-SUB FEMALE at the videocard. 9 PIN D-SUB MALE at the monitor cable. Pin 1 2 3 4 5 6 7 8 9 Name GND GND R G B I RES HSYNC VSYNC Description Ground Ground Red Green Blue Intensity Reserved Horizontal Sync Vertical Sync

Contributor: Joakim Ögren Source: ?
Please send any comments to Joakim Ögren.

PR EL IM IN

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CGA

Chapter 1: Connector Menu

EGA Connector

EGA=Enhanced Graphics Adapter. Videotype: TTL, 16/64 colors.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the videocard)

Pin 1 2 3 4 5 6 7 8 9

Name GND SR PR PG PB SG/I SB H V

Description Ground Secondary Red Primary Red Primary Green Primary Blue Secondary Green / Intensity Secondary Blue Horizontal Sync Vertical Sync

Contributor: Joakim Ögren Source: ?
Please send any comments to Joakim Ögren.

PR EL IM IN

BETA RELEASE

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EGA

Chapter 1: Connector Menu

PGA Connector

Videotype: Analogue.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the monitor cable) 9 PIN D-SUB FEMALE at the videocard. 9 PIN D-SUB MALE at the monitor cable. Pin 1 2 3 4 5 6 7 8 9 Name R G B CSYNC MODE RGND GGND BGND GND Description Red Green Blue Composite Sync Mode Control Red Ground Green Ground Blue Ground Ground

Contributor: Joakim Ögren Source: ?
Please send any comments to Joakim Ögren.

PR EL IM IN

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PGA

158 MDA (Hercules) .N OT FO Pin 1 2 3 4 5 6 7 8 9 Name GND GND n/c n/c n/c I M H V Intensity Mono Video Horizontal Sync Vertical Sync R RE DI Description Ground Ground ST 9 PIN D-SUB FEMALE at the videocard. 9 PIN D-SUB MALE at the monitor cable. RI (At the monitor cable) BU TIO N. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu MDA (Hercules) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . (At the videocard) Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.

PR EL IM IN BETA RELEASE AR YB ET A n/c GND GND GND GND n/c n/c . Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Name PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 CLK BLK HSYNC VSYNC GND GND GND GND Description DAC Pixel Data Bit 0 (PB) DAC Pixel Data Bit 1 (PG) DAC Pixel Data Bit 2 (PR) DAC Pixel Data Bit 3 (PI) DAC Pixel Data Bit 4 (SB) DAC Pixel Data Bit 5 (SG) DAC Pixel Data Bit 6 (SR) DAC Pixel Data Bit 7 (SI) DAC Clock DAC Blanking Horizontal Sync Vertical Sync Ground Ground Ground Ground Select Internal Video Select Internal Sync Select Internal Dot Clock Not used Ground Ground Ground Ground Not used Not used Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.Chapter 1: Connector Menu VESA Feature Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 159 VESA Feature . It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N. (At the videocard) 26 PIN IDC at the Video card.

Chapter 1: Connector Menu Macintosh Video Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name Dir RGND R CSYNC SENSE0 G GGND SENSE1 n/c B SENSE2 SGND VSYNC BGND HSYNCGND HSYNC Description Red Ground Red Composite sync Monitor Sense 0 Green Green Ground Monitor Sense 1 No connection Blue Monitor sense 2 Sync Ground Vertical Sync Blue Ground Horizontal Sync Ground Horizontal Sync Note: Direction is Computer relative Monitor.cs. It may not be modified and re-distributed without the authors permission.N OT Contributor: Joakim Ögren FO R RE DI ST RI BU TIO N.vt. Source: Tommy's pinout Collection <http://csgrad.edu> Please send any comments to Joakim Ögren.cs.vt.edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad. PR EL IM IN BETA RELEASE AR YB ET A . (At the Computer) 15 PIN D-SUB FEMALE at the Computer. 160 Macintosh Video .

N OT FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Name Dir /XCLK /XCLKEN RED GREEN BLUE DI DR DG DB /CSYNC /HSYNC /VSYNC GNDRTN /PIXELSW /C1 GND GND GND GND GND -12V -5V +12V +5V Note: Direction is Computer relative Monitor. PR EL IM IN BETA RELEASE AR YB ET A 22 23 Description Extern Clock Extern Clock Enable (47 Ohm) Analog Red (75 Ohm) Analog Green (75 Ohm) Analog Blue (75 Ohm) Digital Intensity (47 Ohm) Digital Red (47 Ohm) Digital Green (47 Ohm) Digital Blue (47 Ohm) Composite Sync (47 Ohm) Horizontal Sync (47 Ohm) Vertical Sync (47 Ohm) Digital Ground (for /XCLKEN) Don't connect with pin 16-20. Contributor: Joakim Ögren Source: Amiga 4000 User's Guide from Commodore Please send any comments to Joakim Ögren.Chapter 1: Connector Menu Amiga Video Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (At the Amiga) 23 PIN D-SUB MALE at the Amiga. Genlock overlay (47 Ohm) Clock out (47 Ohm) Video Ground Video Ground Video Ground Video Ground Video Ground -12 Volts DC (10 mA max) (A500/A600/A1200) -5 Volts DC (10 mA max) (A1000/A2000/A3000/A4000) +12 Volts DC (100 mA max) +5 Volts DC (100 mA max) . 161 Amiga Video .

N OT FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A . 162 Amiga 1000 RF Monitor . Pin 1 2 3 4 5 6 7 8 Name Dir n/c GND AUDL CVIDEO GND n/c +12V AUDR Description Not connected Ground Audio Left Composite Video Ground Not connected +12 VDC Audio Right Note: Direction is Computer relative Monitor. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. (At the computer) 8 PIN DIN "C" FEMALE at the computer.Chapter 1: Connector Menu Amiga 1000 RF Monitor Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

ca/~ewaniu/cdtv/cdtv-technical. Buffered Red (out from video card) Video Ground Green (in to video card) Genlock mode 0 (from computer.-.-. genlock button) Blue (in to video card) Genlock signal Buffered Blue (out from video card) Vertical Sync (in to video card) Horizontal Sync (in to video card) Composite Sync (in to video card) Buffered Composite Sync (out from video card) Video Ground Audio Right Output (from computer to RF modulator) Digital Ground Audio Left Output (from computer to RF modulator) -12 VDC (can be -5 VDC instead) Digital Ground +12 VDC CD/TV button. 163 CDTV Video Slot .html> Please send any comments to Joakim Ögren.-. (Low=CDTV video on RF. Contributor: Joakim Ögren Source: Darren Ewaniuk's CDTV Technical Information <http://nyquist.-.-. It may not be modified and re-distributed without the authors permission.ee. PR EL IM IN BETA RELEASE AR Description Video Ground Video Ground External Genlock Clock (in) Red (in to video card) Enables External Clock on XCLK.-.Chapter 1: Connector Menu CDTV Video Slot Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 2 4 6 8 10 12 -.--.-. genlock button) Buffered Green (out from video card) Genlock mode 1 (from computer.58 MHz color clock (C1 clock) Video Ground +5 VDC YB ET A .-1 3 5 7 9 11 14 --13 16 --15 18 --17 20 --19 22 --21 24 --24 26 --25 28 --27 30 --29 (At the computer) 30 PIN ??? CONNECTOR at the computer. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Name GND GND XCLK R /XCLKEN BR GND G GMS0 BG GMS1 B /PIXELSW BB VSYNC CSYNC HSYNC BCSYNC GND AUDR DGND AUDL -12V DGND +12V /CD/TV VCC /CCK GND VCC Note: Used for RF-modulator usually. High=Antenna) +5 VDC 3.-.N OT FO R RE DI ST RI BU TIO N.ualberta.

Chapter 1: Connector Menu PlayStation A/V Connector Availble on the Sony PlayStation Videogame. +--------------+ | oooooooooooo | +--------------+ 1 12 (At the PlayStation) 12 PIN ?? at the PlayStation. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.gamesx. PR EL IM IN BETA RELEASE AR YB ET A .com/psxav.htm> Please send any comments to Joakim Ögren.net> Source: Sony PlayStation A/V Pinout <http://www. 164 PlayStation A/V . It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N. Pin 1 2 3 4 5 6 7 8 9 10 11 12 Name GND RT GND LT Y SYNC C VGND B +5V R G Description Ground Right Audio Ground Left Audio S-Video Y Composite Sync S-Video C Video Ground Blue +5 VDC Red Green Contributor: Lawrence Wright <lwright@silk.

(At the Monitor) 6 PIN DIN FEMALE at the Monitor.com/~gscott/t-1084.interlog.N OT FO R RE Source: National Amiga's C1084 page <http://www. PR EL IM IN BETA RELEASE AR YB ET A .html> DI ST RI BU TIO N.Chapter 1: Connector Menu Commodore 1084 & 1084S (Analog) Connect The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. Pin 1 2 3 4 5 6 Name G HSYNC GND R B VSYNC Description Green Horizontal Sync Ground Red Blue Vertical Sync Contributor: Joakim Ögren Please send any comments to Joakim Ögren. 165 Commodore 1084 & 1084S (Analog) .

Pin 1 2 3 4 5 6 7 8 Name n/c R G B I GND HSYNC VSYNC Description Not connected Red Green Blue Intensity Ground Horizontal Sync Vertical Sync Contributor: Joakim Ögren Source: National Amiga's C1084 page <http://www.interlog.com/~gscott/t-1084.Chapter 1: Connector Menu Commodore 1084 & 1084S (Digital) Connect The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI ST RI BU TIO N. 166 Commodore 1084 & 1084S (Digital) . It may not be modified and re-distributed without the authors permission.html> Please send any comments to Joakim Ögren. (At the Monitor) 8 PIN DIN 'C' FEMALE at the Monitor.

(At the Monitor) 9 PIN D-SUB FEMALE at the Monitor.com/~gscott/t-1084d.N OT FO R RE DI ST RI BU TIO N.interlog.Chapter 1: Connector Menu Commodore 1084d & 1084dS Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .html> Please send any comments to Joakim Ögren. Pin 1 2 3 4 5 6 7 8 9 Name GND GND R G B I CSYNS HSYNC VSYNC Analog Mode Ground Ground Red Green Blue n/c Composite Sync n/c n/c Digital Mode Ground Ground Red Green Blue Intensity n/c Horizontal Sync Vertical Sync Contributor: Joakim Ögren Source: National Amiga's C1084d page <http://www. 167 Commodore 1084d & 1084dS .

Pin 1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A 1B 2B 3B 4B 5B 6B 7B 8B 9B 10B 11B 12B Name AL AGND GND GND (chroma) B HSYNC G CHROMA GND ??? +5V ??? +5V ??? ? AR AGND GND R CSYNC ? LGND LUM GND CVBSGND CVBS ? Description Audio Left Audio Ground Ground Ground (Chroma) RGB Blue Horizontal sync RGB Green Chroma Ground ??? +5 VDC ??? +5 VDC ??? ? Contributor: Joakim Ögren Please send any comments to Joakim Ögren.N OT FO R RE DI ST RI (At the Atari) BU TIO N.redsun.net/jaguar/aeo/aeo_0306.Chapter 1: Connector Menu Atari Jaguar A/V Connector TOP (duh) 1A The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR Source: Scooping out Jaguar RGB by Duncan Brown <BROWN_DU@Eisner.txt> YB Right audio Audio GND Ground RGB Red Composite (Vertical) Sync ? Luminance Ground Luminance Ground Composite Video Ground Composite Video ? ET A .3 Issue 6 <http://www. It may not be modified and re-distributed without the authors permission.Org> in Atari Explorer Online Vol.DECUS. 168 Atari Jaguar A/V . 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B 7A 7B 8A 8B 9A 9B 10A 10B 11A 11B 12A 12B 1B 12 PIN ?? at the Atari.

ac.faq.N Source: Video Games FAQ (Part 3) <http://www. +-------------------+ | 11 9 7 5 3 1 | | 12 10 8 6 4 2 | +-------------------+ (At the SNES) UNKNOWN CONNECTOR at the SNES.video-games. Pin 1 2 3 4 5 6 7 8 9 10 11 12 Name R G CSYNC B GND GND Y C CVBS +5V L+R L-R Description Red (Requires 200 uF in series) Green (Requires 200 uF in series) Composite Sync Blue (Requires 200 uF in series) Ground Ground S-Video Y S-Video C Composite Video (NTSC) +5 VDC Left+Right Audio (Mono) Left-Right Audio (Used to calculate Stereo) Contributor: Joakim Ögren Please send any comments to Joakim Ögren. 169 SNES Video . Pinout from Radio Electronics April 1992 OT FO R RE DI ST RI BU TIO N. PR EL IM IN BETA RELEASE AR YB ET A .ox. It may not be modified and re-distributed without the authors permission.uk/internet/news/faq/archive/games.lib. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Chapter 1: Connector Menu SNES Video Connector Available on the Nintendo SNES.html>.part3.

net>. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Chapter 1: Connector Menu NeoGeo Audio/Video Connector Available on the NeoGeo videogame.N OT FO R Contributor: Joakim Ögren. Enzo <enzo@gaianet. Pin 1 2 3 4 5 6 7 8 Name Dir AOUT GND VIDEO +5V GREEN RED NSYNC BLUE Description Audio out Ground Composite Video Out +5 VDC Green Video Red Video Negative Sync Blue Video Note: Direction is Computer relative Monitor. Steffen Kupfer <Steffen_Kupfer@compuserve. It may not be modified and re-distributed without the authors permission. 8 PIN DIN (DIN45326) FEMALE at the Computer. Source: ? Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . 170 NeoGeo Audio/Video .com> RE DI ST RI BU (At the Computer) TIO N.

171 Amstrad CPC6128 Monitor .Chapter 1: Connector Menu Amstrad CPC6128 Monitor Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (At the computer) 6 PIN DIN (DIN45322) FEMALE at the computer.diron. Agnello Guarracino <aggy@ooh. It may not be modified and re-distributed without the authors permission.uk> Please send any comments to Joakim Ögren. Pin 1 2 3 4 5 6 Name RED GREEN BLUE SYNC GND LUM Contributor: Joakim Ögren.co.N OT FO R RE Source: Amstrad CPC6128 User Instructions Manual DI ST RI BU TIO N. PR EL IM IN BETA RELEASE AR YB ET A .

uk> PR EL IM IN BETA RELEASE AR YB ET A .co. Source: Amstrad 6128 Plus Home Computer Manual Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu Amstrad CPC6128 Plus Monitor Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Contributor: Joakim Ögren.N OT FO R RE DI ST RI BU TIO N. 172 Amstrad CPC6128 Plus Monitor . Colin Gaunt <c. (At the computer) 8 PIN MINI-DIN FEMALE at the computer.gaunt@c-gaunt.prestel. Pin 1 2 3 4 5 6 7 8 Name Dir NSYNC GREEN LUM RED BLUE AOL AOR GND Description Sync? Green Lumninace Red Blue Audio Output Left Audio Output Right Ground Note: Direction is Computer relative Monitor.

au> Source: ? Please send any comments to Joakim Ögren. 173 Atari ST Monitor . 13 PIN DIN MALE at the Devices.Chapter 1: Connector Menu Atari ST Monitor Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Name AO CVIDEO CS MD AI G R +12V HSYNC B MVIDEO VSYNC GND Description Audio Out Composite Video Clock Select Monochrome Detect / Clock In Audio In Green Red +12 VDC (520ST has GND) Horizontal Sync Blue Monochrome Video Vertical Sync Ground FO R RE DI ST 13 PIN DIN FEMALE at the Computer. (At the Computer) Contributor: Joakim Ögren. It may not be modified and re-distributed without the authors permission.edu.net>.uq. Lawrence Wright <lwright@silk. RI (At the Devices) BU TIO N. Steve & Sally Blair <blair@mailbox. PR EL IM IN BETA RELEASE AR YB ET A .

(At the Computer) 13 PIN 13W3 FEMALE at the Computer.cs.html> for info on attaching old workstation monitors to VGA boards.vt.edu> BETA RELEASE AR YB See http://cvs.Chapter 1: Connector Menu Sun Video Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 174 Sun Video .anu.edu.nl/~everdij/hitachi.html <http://rugmd0. may not be connected.anu.rug.chem. R RE DI ST RI BU TIO N.chem.N OT FO *) Considered obsolete. ET A Bit 2 Bit 1 Bit 0 Resolution 0 0 0 ? 0 0 1 Reserved 0 1 0 1280 x 1024 76Hz 0 1 1 1152 x 900 66Hz 1 0 0 1152 x 900 76Hz 19" 1 0 1 Reserved 1 1 0 1152 x 900 76Hz 16-17" 1 1 1 No monitor connected .cs.nl/~everdij/hitachi.vt.au:80/monitorconversion/ <http://cvs. It may not be modified and re-distributed without the authors permission. PR EL IM IN Source: Tommy's pinout Collection <http://csgrad. Pin 1 2 3 4 5 6 7 8 9 10 R G B Name GND VSYNC SENSE2 SENSEGND CSYNC HSYNC GND SENSE1 SENSE0 CGND RED GREEN/GRAY BLUE Description Ground* Vertical Sync* Sense #2 Sense Ground Composite Sync Horizontal Sync* Ground* Sense #1 Sense #0 Composite Ground Red Green/Gray Blue Monitor-sense bits defined as: Value 0 1 2 3 4 5 6 7 Contributor: Joakim Ögren Please send any comments to Joakim Ögren.edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad.rug.au:80/monitorconversion/> and http://rugmd0.edu.

75 ohms.2V p-p) Ground Bright Output Composite Sync Vertical Sync Green Red Blue R RE DI ST RI BU (At the computer) TIO N. It may not be modified and re-distributed without the authors permission. Contributor: Joakim Ögren Source: Online ZX Spectrum 128 Manual Page 3 <http://users.ac. (At the monitor cable) 8 PIN DIN (DIN45326) FEMALE at the computer.uk/~uzdm0006/Damien/speccy/128manua/sp128p03. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Pin 1 2 3 4 5 6 7 8 Name Dir CVBS GND BOUT CSYNC VSYNC G R B Note: Direction is Computer relative Monitor.Chapter 1: Connector Menu ZX Spectrum 128 RGB Connector Can be found at the Sinclair ZX Spectrum 128. 1.N Please send any comments to Joakim Ögren. OT FO Description Composite Video (PAL.ox. 8 PIN DIN (DIN45326) MALE at the monitor cable. 175 ZX Spectrun 128 RGB .html> PR EL IM IN BETA RELEASE AR YB ET A .

Pin 1 2 3 4 5 6 7 8 9 10 11 12 Name VSYNC GND HSYNC GND VIDEO GND +12V GND +12V SPK SPK ? Description Vertical Sync Ground Horizontal Sync Ground Video Ground +12 VDC Ground +12 VDC Speaker Speaker ? Contributor: Joakim Ögren Source: Tommy's pinout Collection <http://csgrad.edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad. PR EL IM IN BETA RELEASE AR YB ET A .edu> Please send any comments to Joakim Ögren.vt.N OT FO R RE DI ST RI BU TIO N.cs. (At the computer) 12 PIN IDC MALE at the computer.cs.vt. 176 3b1/7300 Video . It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu 3b1/7300 Video Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

io.Chapter 1: Connector Menu CM-8/CoCo RGB Connector Available on the Tandy/Radio Shack Color Computer (CoCo).io. +-----------+ | 1 3 5 7 9 | | 2 4 8 10| +-----------+ (At the CoCo) UNKNOWN CONNECTOR at the CoCo. 177 CM-8/CoCo RGB .N OT Source: Tandy Color Computer FAQ <http://www.com/~vga2000/faqs/coco. Pin 1 2 3 4 5 6 7 8 9 10 Name GND GND R G B KEY AUDIO HSYNC VSYNC n/c Description Ground Ground Red Green Blue No Pin Audio Horizontal Sync Vertical Sync No Connection Contributor: Joakim Ögren Please send any comments to Joakim Ögren.faq> at Video Game Advantage's homepage <http://www. PR EL IM IN BETA RELEASE AR YB ET A .com/~vga2000/> FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

PR EL IM IN BETA RELEASE AR YB Source: Tommy's pinout Collection <http://csgrad.cs.edu> ET A .cs.edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad.N OT FO R RE DI ST RI BU TIO N.vt. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name ? VSYNC HSYNC ? VIDEO ? ? ? ? ? ? ? GND GND GND ? ? ? ? ? ? ? ? ? ? Description ? Vertical Sync Horizontal Sync ? Video ? ? ? ? ? ? ? Ground Ground Ground ? ? ? ? ? ? ? ? ? ? Contributor: Joakim Ögren Please send any comments to Joakim Ögren. 178 AT&T 53D410 . It may not be modified and re-distributed without the authors permission. (At the computer) 25 PIN D-SUB ??? at the computer.vt.Chapter 1: Connector Menu AT&T 53D410 Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

vt.vt.N OT FO R RE DI ST RI BU TIO N. Pin 1 2 3 4 5 6 7 8 Name TEXT R G B I GND HSYNC/CSYNC VSYNC Description Special TEXT signal (??) Red Green Blue Intensity Signal Ground Horizontal or Composite Sync Vertical Sync Contributor: Joakim Ögren Source: Tommy's pinout Collection <http://csgrad.cs.cs.Chapter 1: Connector Menu AT&T 6300 Taxan Monitor Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . (At the Monitor) 8 PIN DIN (DIN45326) FEMALE at the Monitor.edu> Please send any comments to Joakim Ögren. 179 AT&T 6300 Taxan Monitor . It may not be modified and re-distributed without the authors permission.edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad.

cs.edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad. and ID1 is 1.Chapter 1: Connector Menu AT&T PC6300 Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.edu> Please send any comments to Joakim Ögren. 180 AT&T PC6300 .cs. PR EL IM IN BETA RELEASE AR YB ET A .vt.N OT FO R RE DI ST RI BU TIO N. Pin 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name HSYNC ID0 VSYNC R G B n/c n/c ID1 MODE0 n/c /DEGAUSS GND GND GND GND GND GND GND GND n/c n/c +15V +15V Description Horizontal Sync Monitor ID 0 Vertical Sync Red Green Blue Not connected Not connected Monitor ID 1 Mode 0 Not connected Degauss Ground Ground Ground Ground Ground Ground Ground Ground Not connected Not connected +15 VDC +15 VDC Monochrome monitor: ID0 and ID1 are open Color monitor: ID0 is 0. probably 5V. It may not be modified and re-distributed without the authors permission.vt. not 15V Contributor: Joakim Ögren Source: Tommy's pinout Collection <http://csgrad. (At the computer) 25 PIN D-SUB ??? at the computer.

(At the computer) (At the cable) 5 PIN DIN 180° (DIN41524) FEMALE at the Computer.edu/~thompsbb/cbm_conn.Chapter 1: Connector Menu Vic 20 Video Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.vuse. 181 Vic 20 Video .N OT FO Source: CBM Memorial Page Pinouts <http://www.vanderbilt. It may not be modified and re-distributed without the authors permission. Contributor: Joakim Ögren Please send any comments to Joakim Ögren. Pin 1 2 3 4 5 Name Dir +6V GND AUDIO VLOW VHIGH Description +6 VDC (10 mA max) Ground Audio Video Low (Unconnected ?) Video High Note: Direction is Computer relative Monitor. 5 PIN DIN 180° (DIN41524) MALE at the Cable. PR EL IM IN BETA RELEASE AR YB ET A .txt> R RE DI ST RI BU TIO N.

It may not be modified and re-distributed without the authors permission. (At the computer) (At the cable) 5 PIN DIN 180° (DIN41524) FEMALE at the Computer. 5 PIN DIN 180° (DIN41524) MALE at the Cable. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . 182 C64 Audio/Video .N OT FO R RE DI ST RI BU TIO N.Chapter 1: Connector Menu C64 Audio/Video Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Pin 1 2 3 4 5 Name Dir LUM GND AOUT VOUT AIN Description Luminance Ground Audio Out Video Out Audio In Note: Direction is Computer relative Monitor.

PR EL IM IN BETA RELEASE AR YB ET A .txt> Please send any comments to Joakim Ögren.vanderbilt. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.edu/~thompsbb/cbm_conn.Chapter 1: Connector Menu C65 Video Connector Available on the Commodore C65 computer. Pin 1 2 3 4 5 6 7 8 9 Name Dir GND ? R G B ? CSYNC HSYNC VSYNC Description Ground ? Red Green Blue ? Composite Sync Horizontal Sync Vertical Sync Contributor: Joakim Ögren Source: CBM Memorial Page Pinouts <http://www.vuse. RE DI ST RI BU (At the Computer) TIO N. It may not be modified and re-distributed without the authors permission. 183 C65 Video .N OT FO R Note: Direction is Computer relative Monitor. 9 PIN D-SUB MALE at the Computer.

edu/~thompsbb/cbm_conn. 184 C128 RGBI . It may not be modified and re-distributed without the authors permission. (At the Computer) 9 PIN D-SUB FEMALE at the Computer. Contributor: Joakim Ögren Please send any comments to Joakim Ögren.sys.txt> by Marko Makela <msmakela@cc. C128 screen cables <http://www.vuse.cbm.helsinki.vanderbilt. Pin 1 2 3 4 5 6 7 8 9 Name Dir GND GND R G B I VIDEO HSYNC VSYNC Description Ground Ground Red Green Blue Intensity Composite Video Horizontal Sync Vertical Sync Note: Direction is Computer relative Monitor.N OT FO Source: Usenet posting in comp.fi> R RE DI ST RI BU TIO N.Chapter 1: Connector Menu C128 RGBI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .

Contributor: Joakim Ögren Source: CBM Memorial Page Pinouts <http://www.N OT FO R RE DI ST RI BU TIO N.vanderbilt.edu/~thompsbb/cbm_conn. It may not be modified and re-distributed without the authors permission. C128/C64C Video 185 . (At the Computer) 8 PIN DIN (DIN45326) FEMALE at the Computer. Pin 1 2 3 4 5 6 7 8 Name Dir LUM GND AOUT VOUT AIN n/c n/c C Description Luminance (monochrome video) Ground Audio out Composite Video out Audio in (into the SID chip) Not connected Not connected Chroma Note: Direction is Computer relative Monitor. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Compatible with cables for the 5 pin D-SUB on C64's.vuse. PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu C128/C64C Video Connector Seems to be available on the C128 and the C64C (white colour).txt> Please send any comments to Joakim Ögren.

8 PIN DIN (DIN45326) FEMALE at the Computer.txt> Sources: SAMS Computerfacts CC8 Commodore 16.nl> RE DI ST RI BU (At the Computer) TIO N.vanderbilt. Pin 1 2 3 4 5 6 7 8 Name Dir LUM GND AOUT VOUT AIN COLOR n/c +5VDC Description Luminance (monochrome video) Ground Audio out Composite Video out Audio in (into the SID chip) Color ? Not connected +5 VDC Note: Direction is Computer relative Monitor. PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission.edu/~thompsbb/cbm_conn. Arwin Vosselman <0vosselman01@flnet. R Contributor: Joakim Ögren.N OT FO Sources: CBM Memorial Page Pinouts <http://www. 186 C16/C116/+4 Audio/Video .Chapter 1: Connector Menu C16/C116/+4 Audio/Video Connector Available on Commodore C16/C116/+4 computers. Please send any comments to Joakim Ögren. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.vuse.

sys. DI ST RI BU (At the Monitor) TIO N.uk/internet/news/faq/archive/cbm-main-faq.ac. 187 CBM 1902A . Pin 1 2 3 4 5 6 Name Dir n/c AUDIO GND C n/c L Description Not connected Audio Ground Chroma Not connected Luminance Contributor: Joakim Ögren PR EL IM IN BETA RELEASE AR YB ET A . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Chapter 1: Connector Menu CBM 1902A Connector Available on the Commodore CBM 1902A monitor.3.lib.cbm General FAQ v3.1. It may not be modified and re-distributed without the authors permission.p7.N OT FO Please send any comments to Joakim Ögren. R Source: comp.html> RE Note: Direction is Monitor relative Computer.ox.1 Part 7 <http://www. 6 PIN DIN FEMALE at the Monitor.

Pin 1 2 3 4 5 Name +5v GND AUDIO VIDEO RF VID Description Power System ground Audio out Composite Video out RF Video out Source: Spectravideo SVI 328 mk II User Manual Please send any comments to Joakim Ögren.Chapter 1: Connector Menu Spectravideo SVI318/328 Audio/Video Conne The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission.com> ST RI BU TIO N.N OT FO R RE DI Contributor: Rob Gill <gillr@mailcity. (At the computer) 5 PIN DIN 180° (DIN41524) FEMALE at the computer. 188 Spectravideo SVI318/328 Audio/Video .

15 PIN D-SUB MALE at the joystick cable. 189 PC Gameport .Y Button 2 +5 VDC +5 VDC Button 4 Joystick 2 .Y Button 3 +5 VDC FO R RE DI ST 15 PIN D-SUB FEMALE at the computer.Chapter 1: Connector Menu PC Gameport Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.X Ground Joystick 2 . It may not be modified and re-distributed without the authors permission. RI (At the joystick cable) BU TIO N. (At the computer) Note: Direction is Computer relative Joystick.N OT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name Dir +5V /B1 X1 GND GND Y1 /B2 +5V +5V /B4 X2 GND Y2 /B3 +5V Description +5 VDC Button 1 Joystick 1 . Source: ? Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A Contributor: Joakim Ögren .X Ground Ground Joystick 1 . Note: Use 100kohm resistor.

Ground and VCC has been used for this. (At the computer) Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.N Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name Dir +5V /B1 X1 GND GND Y1 /B2 +5V +5V /B4 X2 MIDITXD Y2 /B3 MIDIRXD Description +5 VDC Button 1 Joystick 1 . .Y Button 3 MIDI Receive OT FO R RE DI 15 PIN D-SUB FEMALE at the computer. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A Note: Direction is Computer relative Joystick. Note: Use 100 kohm resistor.X MIDI Transmit Joystick 2 .Chapter 1: Connector Menu PC Gameport+MIDI Connector Some soundcards have some MIDI signals included in their Gameport. PC Gameport+MIDI 190 .Y Button 2 +5 VDC +5 VDC Button 4 Joystick 2 .X Ground Ground Joystick 1 . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 15 PIN D-SUB MALE at the joystick cable. ST (At the joystick cable) RI BU TIO N.

N Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu Amiga Mouse/Joy Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 191 Amiga Mouse/Joy . (At the computer) Note: Direction is Computer relative Device. Note: Pot is a linear 470 kOhm (±10 %) Contributor: Joakim Ögren Source: Amiga 4000 User's Guide from Commodore PR EL IM IN BETA RELEASE AR YB ET A . OT FO Pin 1 2 3 4 5 6 7 8 9 Mouse/TrackballLightpen V-pulse n/c H-pulse n/c VQ-pulse n/c HQ-pulse n/c BUTTON 3(M) Penpress BUTTON 1(L) /Beamtrigger +5V +5V GND GND BUTTON 2(R) BUTTON 2 Digital Joystick Paddle Dir /FORWARD BUTTON 3 /BACK n/c /LEFT BUTTON 1 /RIGHT BUTTON 2 n/c PotX /BUTTON 1 n/c +5V +5V GND GND BUTTON 2 PotY ST 9 PIN D-SUB MALE at the computer. RI Comment (At the mouse/joy cable) RE DI BU R 50 mA max TIO N. 9 PIN D-SUB FEMALE at the mouse/joy cable.

Arwin Vosselman <0vosselman01@flnet. Note: Pot is a linear 470 kOhm (±10 %) YB Pin 1 2 3 4 5 6 7 8 9 Name Dir JOYB0 JOYB1 JOYB2 JOYB4 POT BY BUTTON B +5V GND POT BX Comment 50 mA max ET A .N OT Control Port 2 FO 50 mA max R RE DI ST 9 PIN D-SUB MALE at the computer.Chapter 1: Connector Menu C64 Control Port Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 9 PIN D-SUB FEMALE at the joystick cable. 192 C64 Control Port . PR EL IM IN Sources: Amiga 4000 User's Guide from Commodore Sources: Commodore 64 Programmer's Reference Guide BETA RELEASE AR Note: Direction is Computer relative Device. It may not be modified and re-distributed without the authors permission. RI (At the joystick cable) BU TIO N. (At the computer) Control Port 1 Pin 1 2 3 4 5 6 7 8 9 Name Dir JOYA0 JOYA1 JOYA2 JOYA4 POT AY BUTTON A/LP +5V GND POT AX Comment Contributor: Joakim Ögren.nl> Please send any comments to Joakim Ögren.

C116 and +4 computers. Pin 1 2 3 4 5 6 7 8 Name Dir JOYA0 JOYA1 JOYA2 JOYA3 +5VDC BUTTON A ? GND COMMON A ? ? Is connected to DATA2 thru a buffer. Arwin Vosselman <0vosselman01@flnet.nl> Source: SAMS Computerfacts CC8 Commodore 16. Is connected to DATA1 thru a buffer. It may not be modified and re-distributed without the authors permission. 193 C16/C116/+4 Joystick . Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu C16/C116/+4 Joystick Connector Available on the Commodore C16. Note: Direction is Computer relative Device. Contributor: Joakim Ögren. 8 PIN MINI-DIN FEMALE at the computer.N Pin 1 2 3 4 5 6 7 8 Name Dir JOYB0 JOYB1 JOYB2 JOYB3 +5VDC BUTTON B ? GND COMMON B ? ? Comment OT FO Joystick 2 R RE DI ST Comment RI Joystick 1 BU (At the computer) TIO N. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

RI (At the joystick cable) BU TIO N. . 9 PIN D-SUB FEMALE at the joystick cable.N Contributor: Joakim Ögren OT Warning: Pin 5 is +5V on MSX and Mouse Button 2 on Amiga. 194 MSX Joystick .com/fms/MSX/Portar. Source: Mayer's SV738 X'press I/O map <http://www. connecting an Amiga mouse to a MSX and pressing mousebutton 2 will shortcut the supply voltage.txt> PR EL IM IN BETA RELEASE AR YB ET A Please send any comments to Joakim Ögren. Since Amiga mousebutton is active low. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu MSX Joystick Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.freeflight. FO Pin 1 2 3 4 5 6 7 8 9 Name Dir /FORWARD /BACK /LEFT /RIGHT +5V /TRG1 /TRG2 OUTPUT GND Description Forward Backward Left Right +5 VDC (50mA max) Trigger A / Output 1 Trigger A / Output 1 Output 3 Signal Ground R RE DI ST 9 PIN D-SUB MALE at the computer. (At the computer) Note: Direction is Computer relative Joystick.

(At the Computer) 9 PIN D-SUB ??? at the Computer.vt.vt.cs. PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission. Contributor: Joakim Ögren Please send any comments to Joakim Ögren.N OT FO Source: Tommy's pinout Collection <http://csgrad.cs. 195 SGI Mouse (Model 021-0004-002) .edu> R RE DI - ST - RI BU TIO N. Pin 1 2 3 4 5 6 7 8 9 Name +5V -5V n/c n/c MTXD n/c n/c n/c GND Dir Description +5 VDC -5 VDC Not connected Not connected Data Not connected Not connected Not connected Ground Note: Direction is Computer relative Mouse.Chapter 1: Connector Menu SGI Mouse (Model 021-0004-002) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad.

Chapter 1: Connector Menu Macintosh Mouse Connector Available on Macintosh Mac Plus and earlier.dotcom. (At the mouse cable) 9 PIN D-SUB FEMALE at the computer.fr> Source: Apple Tech Info Library.N OT Note: Direction is Computer relative Mouse. It may not be modified and re-distributed without the authors permission. 9 PIN D-SUB MALE at the mouse cable. FO Description Chassis ground +5 VDC Chassis ground Horizontal movement line (connected to VIA PB4 line) Horizontal movement line (connected to SCC DCDA-line) Not connected Mouse button line (connected to VIA PB3) Vertical movement line (connected to VIA PB5 line) Vertical movement line (connected to SCC DCDB-line) R RE DI ST RI BU (At the computer) TIO N. Pin 1 2 3 4 5 6 7 8 9 Name Dir CGND +5V CGND X2 X1 n/c SWY2 Y1 Contributor: Ben Harris <bjh@mail. 196 Macintosh Mouse . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . Article ID: TECHINFO-0001424 Please send any comments to Joakim Ögren.

It may not be modified and re-distributed without the authors permission. RI (At the mouse/joy cable) BU TIO N.edu. Steve & Sally Blair <blair@mailbox.uq. (At the computer) Note: Direction is Computer relative Device.N OT FO Pin 1 2 3 4 5 6 7 8 9 Mouse XB XA YA YB n/c LEFTBUTTON +5V GND RIGHTBUTTON JoystickDir UP DOWN LEFT RIGHT n/c FIRE +5V GND res Comment R RE DI ST 9 PIN D-SUB MALE at the computer. 9 PIN D-SUB FEMALE at the mouse/joy cable. Contributor: Joakim Ögren. 197 Atari Mouse/Joy .au> PR EL IM IN BETA RELEASE AR YB ET A . Source: ? Please send any comments to Joakim Ögren.Chapter 1: Connector Menu Atari Mouse/Joy Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .N OT Contributor: Joakim Ögren FO R RE DI ST RI BU (At the computer) TIO N.txt> by Andrew Hague <andrew@minster. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name UP0 DOWN0 LEFT0 RIGHT0 PAD0Y FIRE0/LIGHT GUN VCC n/c GND FIRE2 UP2 DOWN2 LEFT2 RIGHT2 PAD0X Description Up 0 Down 0 Left 0 Right 0 Paddle 0 Y Fire 0/Lightgun +5 VDC Not connected Ground Fire 2 Up 2 Down 2 Left 2 Right 2 Paddle 0 X Source: Do-It-Yourself Atari Jaguar Controller <http://dcpu1. 198 Atari Enhanced Joystick . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.ac. UNKNOWN CONNECTOR at the computer.uk:6666/~andrew/atari/DIYjoypad.uk> Please send any comments to Joakim Ögren. Jaguar & STe.cs.Chapter 1: Connector Menu Atari Enhanced Joystick Connector Can be found at Atari Falcon.ac.york.york.

9 PIN D-SUB FEMALE at the joystick cable. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .dhp. RI (At the joystick cable) BU TIO N. Note: Connect Direction/Button to Ground for action. 199 Atari 2600 Joystick .utah.faq>.com/~sloppy/files/classic/atari/atari. Contributor: Joakim Ögren Source: Classic Atari 2600/5200/7800 Game Systems FAQ <http://www.edu> Please send any comments to Joakim Ögren.Chapter 1: Connector Menu Atari 2600 Joystick Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO Pin 1 2 3 4 5 6 7 8 9 Color Dir WHT BLU GRN BRN n/c ORG n/c BLK n/c - Description Up Down Left Right Not connected Button Not connected Ground(-) Not connected R RE DI ST 9 PIN D-SUB MALE at the Atari. (At the Atari) Note: Direction is Computer relative Joystick. Pinout by Greg Alt <galt@cs.

right column Keypad -. 2. 3) Top side buttons 0 volts -.com/~sloppy/files/classic/atari/atari.second row and Pause Keypad -. and Reset common Keypad -.bottom row Pot common Horizontal pot (POT0. 1. 5.third row and Reset Keypad -. 200 Atari 5200 Joystick . 2.ground Contributor: Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .dhp.com> Please send any comments to Joakim Ögren.faq> FO R RE DI ST RI BU TIO N. 7) 5 volts DC Bottom side buttons (TRIG0.N OT Source: Classic Atari 2600/5200/7800 Game Systems FAQ <http://www. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description Keypad -. It may not be modified and re-distributed without the authors permission. Eric Parent <eparent@equinox.shaysnet. 4. Pause.middle column Keypad -. 3.top row and Start Keypad -. 6) Vertical pot (POT1. (At the Atari) UNKNOWN CONNECTOR at the Atari.left column Start.Chapter 1: Connector Menu Atari 5200 Joystick Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

It may not be modified and re-distributed without the authors permission.faq> OT Note: Direction is Computer relative Joystick.dhp. RI (At the joystick cable) BU TIO N. FO Pin 1 2 3 4 5 6 7 8 9 Color Dir WHT BLU GRN BRN RED ORG ? n/c BLK YLW Description Up Down Left Right Button (R)ight (-) Both buttons (+) Not connected Ground(-) Button (L)eft (-) R RE DI ST 9 PIN D-SUB MALE at the Atari.Chapter 1: Connector Menu Atari 7800 Joystick Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N Source: Classic Atari 2600/5200/7800 Game Systems FAQ <http://www. And Both Button to Button L and Button R for action. 9 PIN D-SUB FEMALE at the joystick cable.com/~sloppy/files/classic/atari/atari. 201 Atari 7800 Joystick . (At the Atari) Contributor: Joakim Ögren Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . Note: Connect Direction and Button(L/R) to Ground for action.

202 Amstrad Digital Joystick .Chapter 1: Connector Menu Amstrad Digital Joystick Connector Available at the Amstrad CPC6128 and CPC6128 Plus. (At the Joystick cable) 9 PIN D-SUB MALE at the Computer.uk>.prestel. Digital Joystick 1 Pin 1 2 3 4 5 6 7 8 9 Name Dir UP DOWN LEFT RIGHT n/c FIRE2 FIRE1 GND GND Description Up Down Left Right Not connected Fire button 2 Fire button 1 Ground Ground Digital Joystick 2 Pin 1 2 3 4 5 6 7 8 9 Name Dir UP DOWN LEFT RIGHT n/c FIRE2 FIRE1 GND n/c Description Up Down Left Right Not connected Fire button 2 Fire button 1 Ground Not connected Contributor: Joakim Ögren. Colin Gaunt <c.uk> Source: Amstrad 6128 Plus Home Computer Manual Source: Amstrad CPC6128 User Instructions Manual Please send any comments to Joakim Ögren. YB ET A . 9 PIN D-SUB FEMALE at the Joystick cable.N OT FO R RE DI ST RI BU (At the Computer) TIO N. It may not be modified and re-distributed without the authors permission. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.co. Agnello Guarracino <aggy@ooh.gaunt@c-gaunt.co.diron. PR EL IM IN BETA RELEASE AR Note: Direction is Computer relative Joystick.

N Contributor: Joakim Ögren.Chapter 1: Connector Menu NeoGeo Joystick Connector Available on the NeoGeo videogame. 14 PIN CANNON (2 ROWS) ?? at the Computer. Source: ? Please send any comments to Joakim Ögren. BU (At the Computer) TIO N. Enzo <enzo@gaianet. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. again? Not connected Start Button "C" Button "A" Button Left Up RI Could anyone please tell me what kind of connector it has. 203 NeoGeo Joystick . PR EL IM IN BETA RELEASE AR YB ET A .net> OT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name GND n/c SELECT BUTTOND BUTTONB RIGHT DOWN n/c BUTTOND n/c START BUTTONC BUTTONA LEFT UP - - - FO R RE DI ST Dir Description Ground Not connected Select Button "D" Button "B" Button Right Down Not connected "D" Button. It may not be modified and re-distributed without the authors permission. Note: Direction is Computer relative Joystick.

Chapter 1: Connector Menu Keyboard (5 PC) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI Contributor: Joakim Ögren ST RI Technical CLK/CTS. Open-collector Reset on some very old keyboards. Pin 1 2 3 4 5 Name CLOCK DATA n/c GND VCC Description Clock Data Not connected Ground +5 VDC Source: ? Please send any comments to Joakim Ögren. Open-collector RxD/TxD/RTS. (At the computer) 5 PIN DIN 180° (DIN41524) FEMALE at the computer. 204 Keyboard (5 PC) . BU TIO N. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .

It may not be modified and re-distributed without the authors permission. Contributor: Joakim Ögren. +5 VDC Clock Not connected Note: Direction is Computer relative Keyboard. Gilles Ries <gries@glo. PR EL IM IN BETA RELEASE AR YB ET A .be> Source: ? Please send any comments to Joakim Ögren. (At the computer) 6 PIN MINI-DIN FEMALE (PS/2 STYLE) at the computer.Chapter 1: Connector Menu Keyboard (6 PC) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 205 Keyboard (6 PC) . Pin 1 2 3 4 5 6 Name Dir DATA n/c GND VCC CLK n/c Description Key Data Not connected Gnd Power .N OT FO R RE DI ST RI BU TIO N.

PR EL IM IN BETA RELEASE AR YB ET A . (At the computer) 5 PIN DIN 180° (DIN41524) FEMALE at the computer. 206 Keyboard (XT) . Open-collector Reset Ground +5 VDC Source: ? Please send any comments to Joakim Ögren.N OT FO R RE DI Contributor: Joakim Ögren ST RI BU TIO N. Open-collector Data RxD. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu Keyboard (XT) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Pin 1 2 3 4 5 Name CLK DATA /RESET GND VCC DescriptionTechnical Clock CLK/CTS.

Rob Gill <gillr@mailcity. PR EL IM IN BETA RELEASE AR YB ET A . TIO N. (At the computer) Source: ? Please send any comments to Joakim Ögren.com> ST Pin 1 2 3 4 5 A1000 +5 Volts CLOCK DATA GND n/c A2000/A3000 KCLK KDAT n/c GND +5 Volts RI BU 5 PIN DIN 180° (DIN41524) FEMALE (A1000/A2000/A3000) at the computer.Chapter 1: Connector Menu Keyboard (5 Amiga) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI Contributor: Joakim Ögren . 207 Keyboard (5 Amiga) . It may not be modified and re-distributed without the authors permission.

de> DI ST Pin 1 2 3 4 5 6 Name Dir /DATA n/c GND +5V CLOCK n/c - Description Data Not connected Ground +5 Volts DC (100 mA max) Clock Not connected RI BU 6 PIN MINI-DIN FEMALE (PS/2 STYLE) (A4000/CD32/CDTV) at the computer.fh-hannover.rz. It may not be modified and re-distributed without the authors permission.N OT FO R RE Contributor: Joakim Ögren. Keyboard (6 Amiga) 208 . TIO N. PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu Keyboard (6 Amiga) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (At the computer) Note: Direction is Computer relative Keyboard. Dirk Duesterberg <duesterb@unixserv. Source: Amiga 4000 User's Guide from Commodore Please send any comments to Joakim Ögren.

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Pin 1 2 3 4 5 6 Name Dir /DATA /TxD GND +5V CLOCK /RxD Description Data Transmit Data (0-5V and reversed) Ground +5 Volts DC (100 mA max) Clock Receive Data (0-5V and reversed) Contributor: Joakim Ögren.txt>.uk/pub/amiga/docs/cd32-pinouts. It may not be modified and re-distributed without the authors permission. R Source: CD32 keyboard port info <ftp://ftp.fido.demon.N OT FO Please send any comments to Joakim Ögren.co. DI ST RI BU (At the computer) TIO N. usenet posting by Klaus Hegemann <Klaus_Hegemann@punk.rz.de>.Chapter 1: Connector Menu Keyboard (Amiga CD32) Connector The Amiga CD32 keyboard connector also includes a serialport. Dirk Duesterberg <duesterb@unixserv. RE Note: Direction is Computer relative Keyboard.de> PR EL IM IN BETA RELEASE AR YB ET A . 6 PIN MINI-DIN FEMALE (PS/2 STYLE) at the computer. 209 Keyboard (Amiga CD32) .fh-hannover.

Chapter 1: Connector Menu Macintosh Keyboard Connector Available on Macintosh Mac Plus and earlier. (At the Keyboard) RJ11 FEMALE CONNECTOR at the Computer. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. RE DI ST RI BU (At the Computer) TIO N. Pin 1 2 3 4 Name Dir CGND KBD1 ? KBD2 ? +5V Description Chassis ground Keyboard clock Keyboard data +5 VDC Source: Apple Tech Info Library. 210 Macintosh Keyboard .N OT FO Contributor: Ben Harris <bjh@mail.fr> R Note: Direction is Computer relative Keyboard. Article ID: TECHINFO-0001424 Please send any comments to Joakim Ögren.dotcom. PR EL IM IN BETA RELEASE AR YB ET A . RJ11 MALE CONNECTOR at the Keyboard. It may not be modified and re-distributed without the authors permission.

cs.vt. It may not be modified and re-distributed without the authors permission.N OT FO Please send any comments to Joakim Ögren.cs. Pin 1 2 3 4 5 6 7 8 9 Name DATA CLOCK GND GND +12V n/c n/c n/c n/c Description Data Clock Ground Ground +12 VDC Not connected Not connected Not connected Not connected Contributor: Joakim Ögren PR EL IM IN BETA RELEASE AR YB ET A .vt. (At the Computer) 9 PIN D-SUB ??? at the Computer.edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad. 211 AT&T 6300 Keyboard . R Source: Tommy's pinout Collection <http://csgrad.edu> RE DI ST RI BU TIO N.Chapter 1: Connector Menu AT&T 6300 Keyboard Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

212 Internal Diskdrive .N Note: Can be an Edge-connector on old PC's. (At the computer & diskdrives) 34 PIN IDC MALE at the computer & diskdrives. OT Note: Direction is Computer relative Diskdrive. It may not be modified and re-distributed without the authors permission. Ground.Chapter 1: Connector Menu Internal Diskdrive Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 Name Dir /REDWC n/c n/c /INDEX /MOTEA /DRVSB /DRVSA /MOTEB /DIR /STEP /WDATE /WGATE /TRK00 /WPT /RDATA /SIDE1 /DSKCHG Description Density Select Reserved Reserved Index Motor Enable A Drive Sel B Drive Sel A Motor Enable B Direction Step Write Data Floppy Write Enable Track 0 Write Protect Read Data Head Select Disk Change Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . FO R RE DI ST RI BU TIO N. Note: All odd pins are GND.

Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Name /REDWC n/c n/c n/c /FD2S /DCG /SIDE /DLOCK /HLD /INDEX /READY n/c /SEL1 /SEL2 /SEL3 /SEL4 /DIR /STEP /WDAT /WGAT /TR00 /WPROT /RDATA n/c n/c Dir Description Reduced Write Current Reserved Reserved Reserved Disk is two sided Disk has been changed/door open Side select Door lock Head load Index Pulse Ready Not connected Select Drive 1 Select Drive 2 Select Drive 3 Select Drive 4 Direction Step Write data Write gate Track 00 (Zero) Write protect Read data Not connected Not connected - Note: Direction is Computer relative Diskdrive.N OT FO R RE DI ST - RI BU TIO N. Dennis Painter <dwp@rocketmail. It may not be modified and re-distributed without the authors permission. 213 8" Floppy Diskdrive . (At the computer) 50 PIN EDGE or IDC at the computer??. Note: All odd pins are GND.Chapter 1: Connector Menu 8" Floppy Diskdrive Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.com> ET A - . Ground. PR EL IM IN BETA RELEASE AR YB Contributor: Joakim Ögren. Source: ? Please send any comments to Joakim Ögren.

1=Lower) Disk is Write Protected Drive Head position over Track 0 Disk Write Enable Disk Write Data Step the Head-Pulse. First low. 540 mA surge DI ST RI BU TIO N.Chapter 1: Connector Menu Amiga External Diskdrive Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. then high Select Head Direction (0=Inner. It may not be modified and re-distributed without the authors permission. 214 Amiga External Diskdrive . (At the Amiga) 23 PIN D-SUB FEMALE at the Amiga. . ET A Note: Direction is Computer relative Diskdrive.N OC OC OC OC OC OC OC OT FO R RE OC OC OC Description Disk Ready Disk Read Data Ground Ground Ground Ground Ground Disk Motor Control Select Drive 2 Disk Reset Disk Removed From Drive-Latched Low +5 Volts DC (250 mA max) Select Disk Side (0=Upper. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Name /RDY /DKRD GND GND GND GND GND /MTRXD /SEL2 /DRES /CHNG +5V /SIDE /WPRO /TKO /DKWE /DKWD /STEP DIR /SEL3 /SEL1 /INDEX +12V Dir Contributor: Joakim Ögren Source: Amiga 4000 User's Guide from Commodore PR EL IM IN BETA RELEASE AR YB Please send any comments to Joakim Ögren. 1=Outer) Select Drive 3 Select Drive 1 Disk Index Pulse +12 Volts DC (160 mA max.

Drive Select 1 Direction (0=In. Contributor: Joakim Ögren Source: Mayer's SV738 X'press I/O map <http://www.freeflight. It may not be modified and re-distributed without the authors permission. 1=Side 0) +12 VDC +12 VDC +5 VDC Select Drive 0 Motor On Ready Ground Ground Ground Ground Ground Ground . (At the Computer) 25 PIN D-SUB FEMALE at the Computer.N OT FO R RE DI ST RI BU TIO N. 215 MSX External Diskdrive . Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name Dir +12V +5V +5V /INDEX /DSEL1 DIR /STEP WRITEDATA /WRITEGATE /TRACK00 /WRITEPROTECT READDATA /SIDESELECT +12V +12V +5V /DSEL1 /MOTOR READY GND GND GND GND GND GND Note: Direction is Computer relative Diskdrive. PR EL IM IN BETA RELEASE AR YB ET A Description +12 VDC +5 VDC +5 VDC Sector hole passed sensor.txt> Please send any comments to Joakim Ögren. Write Data Write Gate Head is over Track 00 (outermost track) Write protected disk (0=Write protected) Data read from diskette. 1=Dir) Moves head 1 step in DIR direction. Side Select (0=Side 1.com/fms/MSX/Portar.Chapter 1: Connector Menu MSX External Diskdrive Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

Agnello Guarracino <aggy@ooh. (At the computer) 34 PIN MALE EDGE at the computer.diron. It may not be modified and re-distributed without the authors permission.uk> Please send any comments to Joakim Ögren. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name READY GND SIDE 1 SELECT GND READ DATA GND WRITE PROTECT GND TRACK 0 GND WRITE GATE GND WRITE DATA GND STEP GND DIRECTION SELECT GND MOTOR ON GND n/c GND DRIVE SELECT 1 GND n/c GND INDEX GND n/c GND n/c GND n/c GND Contributor: Joakim Ögren.Chapter 1: Connector Menu Amstrad CPC6128 Diskdrive 2 Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST RI BU TIO N. PR EL IM IN Source: Amstrad CPC6128 User Instructions Manual BETA RELEASE AR YB ET A .co. 216 Amstrad CPC6128 Diskdrive 2 .

co. PR EL IM IN BETA RELEASE AR YB ET A . Contributor: Joakim Ögren. Colin Gaunt <c. Note: All even pins are GND.uk> Source: Amstrad 6128 Plus Home Computer Manual Please send any comments to Joakim Ögren.gaunt@c-gaunt. Ground.N OT FO Step head Write Data Write Gate Track 00 Write Protect Read Data R RE DI ST RI BU TIO N.Chapter 1: Connector Menu Amstrad CPC6128 Plus External Diskdrive C The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.prestel. 217 Amstrad CPC6128 Plus External Diskdrive . It may not be modified and re-distributed without the authors permission. Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 Name n/c n/c n/c NINDEX n/c NDSEL1 n/c NMOTOR NDSEL NSTEP NWDATA NWGATE NTK00 NWRPT NRDDTA NSIDE1 NREADY n/c Dir ? ? ? ? Description Not connected Not connected Not connected Not connected Not connected ? ? Not connected Note: Direction is Computer relative Diskdrive. (At the Computer) 36 PIN D-SUB MALE at the Computer.

dotcom. Article ID: TECHINFO-0001424 ET A Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name CGND CGND CGND CGND -12V +5V +12V +12V n/c PWM CA0 CA1 CA2 LSTRB WrReqHdSel Enbl2Rd Wr Dir . PR EL IM IN BETA RELEASE AR YB Source: Apple Tech Info Library. 218 Macintosh External Drive . 19 PIN D-SUB MALE at the Diskdrive.N ? ? ? ? ? ? ? ? Description Chassis ground Chassis ground Chassis ground Chassis ground -12 VDC +5 VDC +12 VDC +12 VDC Not connected Regulates speed of the drive Control line to send commands to the drive Control line to send commands to the drive Control line to send commands to the drive Control line to send commands to the drive Turns on the ability to write data to the drive Control line to send commands to the drive Enables the Rd line (else Rd is tristated) Data actually read from the drive Data actually written to the drive OT FO R RE DI ST 19 PIN D-SUB FEMALE at the Computer. Contributor: Ben Harris <bjh@mail.fr> Please send any comments to Joakim Ögren. RI (At the Diskdrive) BU TIO N.Chapter 1: Connector Menu Macintosh External Drive Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (At the Computer) Note: Direction is Computer relative Diskdrive. It may not be modified and re-distributed without the authors permission.

RI (At the Diskdrive) BU TIO N.au> OT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name RD SIDE0 GND INDEX SEL0 SEL1 GND MOTOR DIR STEP WD WG TRK00 WP Description Read Data Side 0 Select Ground Index Drive 0 Select Drive 1 Select Ground Motor On Direction In Step Write Data Write Gate Track 00 Write Protect FO R RE DI ST 14 PIN DIN FEMALE at the Computer.Chapter 1: Connector Menu Atari Floppy Port Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (At the Computer) Source: ? Please send any comments to Joakim Ögren. Steve & Sally Blair <blair@mailbox. It may not be modified and re-distributed without the authors permission. 14 PIN DIN MALE at the Diskdrive. Lawrence Wright <lwright@silk.uq.net>.edu.N Contributor: Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . 219 Atari Floppy Port .

Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Name Dir DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 PARITY GND GND GND TMPWR GND GND /ATN GND /BSY /ACK /RST /MSG /SEL /C/D /REQ /I/O Description Data Bus 0 Data Bus 1 Data Bus 2 Data Bus 3 Data Bus 4 Data Bus 5 Data Bus 6 Data Bus 7 Data Parity (odd Parity) Ground Ground Ground Termination Power Ground Ground Attention Ground Busy Acknowledge Reset Message Select Control/Data Request Input/Output Note: Direction is Device relative Bus (other Devices). 220 SCSI Internal (Single-ended) . SCSI was ratified in 1986. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.) 50 PIN IDC MALE at the controller & harddisk.Chapter 1: Connector Menu SCSI Internal (Single-ended) Connector SCSI=Small Computer System Interface. are connected to ground. Based on an original design by Shugart Associates. BETA RELEASE AR YB ET A . Pin 25 is left open. (At the controller & harddisk) (At the cable. 50 PIN IDC FEMALE at the cable. except pin 25. PR EL IM IN All odd-numbered pins. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N.

Chapter 1: Connector Menu SCSI Internal (Differential) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.) (At the cable.N OT FO R RE DI ST RI BU TIO N. (at the controller & harddisk. It may not be modified and re-distributed without the authors permission.) 50 PIN IDC MALE at the controller & harddisk. 221 SCSI Internal (Differential) . Pin 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name GND GND +DB0 -DB0 +DB1 -DB1 +DB2 -DB2 +DB3 -DB3 +DB4 -DB4 +DB5 -DB5 +DB6 -DB6 +DB7 -DB7 +DBP -DBP DIFFSENS GND res res TERMPWR TERMPWR res res +ATN -ATN GND GND +BSY -BSY +ACK -ACK +RST -RST +MSG -MSG +SEL -SEL +C/D -C/D Dir Description Ground Ground +Data Bus 0 -Data Bus 0 +Data Bus 1 -Data Bus 1 +Data Bus 2 -Data Bus 2 +Data Bus 3 -Data Bus 3 +Data Bus 4 -Data Bus 4 +Data Bus 5 -Data Bus 5 +Data Bus 6 -Data Bus 6 +Data Bus 7 -Data Bus Parity7 +Data Bus Parity (odd Parity) -Data Bus Parity (odd Parity) ??? Ground Reserved Reserved Termination Power Termination Power Reserved Reserved +Attention -Attention Ground Ground +Bus is busy -Bus is busy +Acknowledge -Acknowledge +Reset -Reset +Message -Message +Select -Select +Control or Data -Control or Data ? PR EL IM IN BETA RELEASE AR - YB - ET A . 50 PIN IDC FEMALE at the cable.

de> Source: ? Please send any comments to Joakim Ögren. Contributor: Joakim Ögren.Chapter 1: Connector Menu 45 46 47 48 49 50 +REQ -REQ +I/O -I/O GND GND SCSI Internal (Differential) Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Wenke@t-online. Note: Direction is Device relative Bus (other Devices). 222 +Request -Request +In/Out -In/Out Ground Ground . PR EL IM IN BETA RELEASE AR YB ET A . Karsten Wenke <Karsten. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N.

N OT FO R RE DI ST 50 PIN CENTRONICS FEMALE at the controller & devices. It may not be modified and re-distributed without the authors permission. RI BU TIO N. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. (At the controller & devices) (At the cable) Note: Direction is Device relative Bus (other Devices).Chapter 1: Connector Menu SCSI External Centronics 50 (Single-ended) C The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR Pin 1-25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name Dir GND DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 PARITY GND GND GND TMPWR GND GND /ATN n/c /BSY /ACK /RST /MSG /SEL /C/D /REQ /I/O Description Ground Data Bus 0 Data Bus 1 Data Bus 2 Data Bus 3 Data Bus 4 Data Bus 5 Data Bus 6 Data Bus 7 Data Parity (odd Parity) Ground Ground Ground Termination Power Ground Ground Attention Not connected Busy Acknowledge Reset Message Select Control/Data Request Input/Output YB ET A . 50 PIN CENTRONICS MALE at the cable. 223 SCSI External Centronics 50 (Single-ended) .

RI BU TIO N.N OT ? - FO R RE DI Dir Description Ground +Data Bus 0 +Data Bus 1 +Data Bus 2 +Data Bus 3 +Data Bus 4 +Data Bus 5 +Data Bus 6 +Data Bus 7 +Data Bus Parity (odd Parity) ??? Reserved Termination Power Reserved +Attention Ground +Bus is busy +Acknowledge +Reset +Message +Select +Control or Data +Request +In/Out Ground Ground -Data Bus 0 -Data Bus 1 -Data Bus 2 -Data Bus 3 -Data Bus 4 -Data Bus 5 -Data Bus 6 -Data Bus Parity7 -Data Bus Parity (odd Parity) Ground Reserved Termination Power Reserved -Attention Ground -Bus is busy ST 50 PIN CENTRONICS FEMALE at the controller & devices. 224 SCSI External Centronics 50 (Differential) .Chapter 1: Connector Menu SCSI External Centronics 50 (Differential) Co The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 50 PIN CENTRONICS MALE at the cable. (At the controller & devices) (At the cable) Pin 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Name GND +DB0 +DB1 +DB2 +DB3 +DB4 +DB5 +DB6 +DB7 +DBP DIFFSENS res TERMPWR res +ATN GND +BSY +ACK +RST +MSG +SEL +C/D +REQ +I/O GND GND -DB0 -DB1 -DB2 -DB3 -DB4 -DB5 -DB6 -DB7 -DBP GND res TERMPWR res -ATN GND -BSY - PR EL IM IN BETA RELEASE AR - - YB ET A . It may not be modified and re-distributed without the authors permission.

Contributor: Joakim Ögren.Chapter 1: Connector Menu 43 44 45 46 47 48 49 50 -ACK -RST -MSG -SEL -C/D -REQ -I/O GND SCSI External Centronics 50 (Differential) Co The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.de> PR EL IM IN BETA RELEASE AR YB ET A .Wenke@t-online.N OT FO R RE DI ST RI BU TIO N. Note: Direction is Device relative Bus (other Devices). Karsten Wenke <Karsten. 225 -Acknowledge -Reset -Message -Select -Control or Data -Request -In/Out Ground . Source: ? Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

YB Pin 1-25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name Dir GND DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 PARITY GND GND GND TMPWR GND GND /ATN n/c /BSY /ACK /RST /MSG /SEL /C/D /REQ /I/O Description Ground Data Bus 0 Data Bus 1 Data Bus 2 Data Bus 3 Data Bus 4 Data Bus 5 Data Bus 6 Data Bus 7 Data Parity (odd Parity) Ground Ground Ground Termination Power Ground Ground Attention Not connected Busy Acknowledge Reset Message Select Control/Data Request Input/Output ET A . PR EL IM IN Source: ? BETA RELEASE AR Note: Direction is Device relative Bus (other Devices). 226 SCSI-II External Hi D-Sub (Single-ended) . Contributor: Joakim Ögren Please send any comments to Joakim Ögren. 50 PIN HI-DENSITY D-SUB MALE at the cable. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu SCSI-II External Hi D-Sub (Single-ended) Co The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST 50 PIN HI-DENSITY D-SUB FEMALE at the controller & devices. RI (To the cable). (At the controller & devices). BU TIO N.

BU TIO N.Chapter 1: Connector Menu SCSI-II External Hi D-Sub (Differential) Con The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 227 SCSI-II External Hi D-Sub (Differential) .N OT FO R RE DI ST 50 PIN HI-DENSITY D-SUB FEMALE at the controller & devices. RI (To the cable). (At the controller & devices). It may not be modified and re-distributed without the authors permission. 50 PIN HI-DENSITY D-SUB MALE at the cable. Pin 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Name GND +DB0 +DB1 +DB2 +DB3 +DB4 +DB5 +DB6 +DB7 +DBP DIFFSENS res TERMPWR res +ATN GND +BSY +ACK +RST +MSG +SEL +C/D +REQ +I/O GND GND -DB0 -DB1 -DB2 -DB3 -DB4 -DB5 -DB6 -DB7 -DBP GND res TERMPWR res -ATN GND -BSY -ACK Dir ? - - - - Description Ground +Data Bus 0 +Data Bus 1 +Data Bus 2 +Data Bus 3 +Data Bus 4 +Data Bus 5 +Data Bus 6 +Data Bus 7 +Data Bus Parity (odd Parity) ??? Reserved Termination Power Reserved +Attention Ground +Bus is busy +Acknowledge +Reset +Message +Select +Control or Data +Request +In/Out Ground Ground -Data Bus 0 -Data Bus 1 -Data Bus 2 -Data Bus 3 -Data Bus 4 -Data Bus 5 -Data Bus 6 -Data Bus Parity7 -Data Bus Parity (odd Parity) Ground Reserved Termination Power Reserved -Attention Ground -Bus is busy -Acknowledge PR EL IM IN BETA RELEASE AR YB ET A .

PR EL IM IN BETA RELEASE AR YB ET A .Wenke@t-online. It may not be modified and re-distributed without the authors permission. 228 -Reset -Message -Select -Control or Data -Request -In/Out Ground . Contributor: Joakim Ögren.N OT FO R RE DI ST RI BU Note: Direction is Device relative Bus (other Devices).de> Source: ? Please send any comments to Joakim Ögren. Karsten Wenke <Karsten.Chapter 1: Connector Menu 44 45 46 47 48 49 50 -RST -MSG -SEL -C/D -REQ -I/O GND SCSI-II External Hi D-Sub (Differential) Con The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. TIO N.

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name Dir GND DB1 DB3 DB5 DB7 GND /SEL GND TMPWR /RST C/D I/O GND DB0 DB2 DB4 DB6 PARITY GND /ATN /MSG /ACK BSY /REQ GND Description Ground Data Bus 1 Data Bus 3 Data Bus 5 Data Bus 7 Ground Select Ground Termination Power Reset Control/Data Input/Output Ground Data Bus 0 Data Bus 2 Data Bus 4 Data Bus 6 Data Parity Ground Attention Message Acknowledge Busy Request Ground Note: Direction is Device relative Bus (other Devices).rl. (At the cable) 25 PIN D-SUB FEMALE at the controller.c3d.Chapter 1: Connector Menu SCSI External D-Sub (Future Domain) Conne Seems to be available on some Future Domain SCSI-controllers only. 229 SCSI External D-Sub (Future Domain) .af. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. 25 PIN D-SUB MALE at the cable.mil> BETA RELEASE AR YB ET A . Contributor: Joakim Ögren Source: TheRef Please send any comments to Joakim Ögren.N OT FO R RE DI ST RI BU (At the controller) TIO N. PR EL IM IN TechTalk <http://theref.

230 SCSI External D-Sub (PC/Amiga/Mac) . RI (At the cable) BU TIO N.N OT FO R RE DI ST 25 PIN D-SUB FEMALE at the controller. (At the controller) Note: Direction is Device relative Bus (other Devices). PR EL IM IN BETA RELEASE AR YB Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name Dir /REQ /MSG I/O /RST /ACK BSY GND DB0 GND DB3 DB5 DB6 DB7 GND C/D GND /ATN GND /SEL PARITY DB1 DB2 DB4 GND TMPWR Description Request Message Input/Output Reset Acknowledge Busy Ground Data Bus 0 Ground Data Bus 3 Data Bus 5 Data Bus 6 Data Bus 7 Ground Control/Data Ground Attention Ground Select Data Parity Data Bus 1 Data Bus 2 Data Bus 4 Ground Termination Power ET A . It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu SCSI External D-Sub (PC/Amiga/Mac) Conne The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 25 PIN D-SUB MALE at the cable. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.

231 Novell and Procomp External SCSI . It may not be modified and re-distributed without the authors permission.com> Source: Black Box Corporation. FaxBack document for SCSI Please send any comments to Joakim Ögren. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.pulsenet. Contributor: Joakim Ögren.N OT FO R RE DI ST RI BU (At the controller) TIO N. PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu Novell and Procomp External SCSI Connecto This interface is nowadays considered obsolete. Randy Hoffman <runtime@borg. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Name Dir GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND TERMPWR /DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7 /DBP /ATN /BSY /ACK /RST /MSG /SEL /C/D /REQ /I/O Description Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Termination Power Data Bus 0 Data Bus 1 Data Bus 2 Data Bus 3 Data Bus 4 Data Bus 5 Data Bus 6 Data Bus 7 Data Bus Parity Attention Busy Acknowledge Reset Message Select Control/Data Request Input/Output Note: Direction is Device relative Bus (other Devices). 37 PIN D-SUB FEMALE at the controller.

IDE Internal . 40 PIN IDC FEMALE at the cable. (At the controller & peripherals) (At the cable) 40 PIN IDC MALE at the controller & peripherals. Newer version of IDE goes under the name ATA=AT bus Attachment. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu IDE Internal Connector IDE=Integrated Drive Electronics. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name /RESET GND DD7 DD8 DD6 DD9 DD5 DD10 DD4 DD11 DD3 DD12 DD2 DD13 DD1 DD14 DD0 DD15 GND KEY n/c GND /IOW GND /IOR GND IO_CH_RDY ALE n/c GND IRQR /IOCS16 DA1 n/c DA0 DA2 /IDE_CS0 /IDE_CS1 /ACTIVE GND Dir Description Reset Ground Data 7 Data 8 Data 6 Data 9 Data 5 Data 10 Data 4 Data 11 Data 3 Data 12 Data 2 Data 13 Data 1 Data 14 Data 0 Data 15 Ground Key Not connected Ground Write Strobe Ground Read Strobe Ground PR EL IM IN AR - ? - BETA RELEASE YB - Address Latch Enable Not connected Ground Interrupt Request IO ChipSelect 16 Address 1 Not connected Address 0 Address 2 (1F0-1F7) (3F6-3F7) Led driver Ground 232 ET A . Developed by Compaq and Western Digital. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST RI BU TIO N.

Dan Williams <dan_williams@sunshine. It may not be modified and re-distributed without the authors permission. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Chapter 1: Connector Menu IDE Internal Connector Source: ? Please send any comments to Joakim Ögren. 233 Note: Direction is Controller relative Devices (Harddisks).net> .N OT FO R RE DI ST RI BU TIO N. PR EL IM IN BETA RELEASE AR YB ET A . Contributors: Joakim Ögren.

BETA RELEASE AR YB ? ? ? ? ? Description Reset Ground Data 7 Data 8 Data 6 Data 9 Data 5 Data 10 Data 4 Data 11 Data 3 Data 12 Data 2 Data 13 Data 1 Data 14 Data 0 Data 15 Ground Key (Pin missing) DMA Request Ground Write Strobe Ground Read Strobe Ground I/O Ready Spindle Sync or Cable Select DMA Acknowledge Ground Interrupt Request IO ChipSelect 16 Address 1 Passed Diagnostics Address 0 Address 2 (1F0-1F7) (3F6-3F7) Led driver Ground ET A . Developed by Western Digital.Chapter 1: Connector Menu ATA Internal Connector ATA=AT bus Attachment. (At the controller & peripherals) (At the cable) 40 PIN IDC MALE at the controller & peripherals. It may not be modified and re-distributed without the authors permission.. 40 PIN IDC FEMALE at the cable. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name /RESET GND DD7 DD8 DD6 DD9 DD5 DD10 DD4 DD11 DD3 DD12 DD2 DD13 DD1 DD14 DD0 DD15 GND KEY DMARQ GND /DIOW GND /DIOR GND IORDY SPSYNC:CSEL /DMACK GND INTRQ /IOCS16 DA1 PDIAG DA0 DA2 /IDE_CS0 /IDE_CS1 /ACTIVE GND Dir PR EL IM IN Note: Direction is Controller relative Devices (Harddisks).N OT FO R RE DI ST RI BU TIO N. Conner & Seagate ?. 234 ATA Internal .

PR EL IM IN YB ET A . It may not be modified and re-distributed without the authors permission. 235 .The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Source: ? Please send any comments to Joakim Ögren. Rob Gill <gillr@mailcity.com> AR BETA RELEASE ST RI BU ATA Internal Connector TIO N.N OT FO R RE DI Chapter 1: Connector Menu Contributor: Joakim Ögren .

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO Note: Direction is Controller relative Devices (harddisks).75") MALE at the controller & peripherals. PR EL IM IN BETA RELEASE AR YB ET A . R Pin 41 42 43 44 Name Dir +5VL +5VM GND /TYPE Description +5 VDC (Logic) +5 VDC (Motor) Ground Type (0=ATA) RE DI 44 PIN IDC (0. See ATA for pin 1-40. 236 ATA (44) Internal . Nick Schirmer <nes@oz. 44 PIN IDC (0. ST RI BU TIO N.Chapter 1: Connector Menu ATA (44) Internal Connector ATA=AT bus Attachment.net> Source: ? Please send any comments to Joakim Ögren.75") FEMALE at the cable. This connector is mostly used for 2. (At the controller & peripherals) (At the cable) Contributor: Joakim Ögren. It may not be modified and re-distributed without the authors permission.5" internal harddisks.

Chapter 1: Connector Menu ESDI Connector ESDI=Enhanced Small Device Interface. R (At the harddisk) RE (At the harddisk) DI ST RI BU TIO N.N OT 34 PIN IDC FEMALE at the Harddisk. 20 PIN IDC FEMALE at the Harddisk. (At the controller) (At the controller) Control connector Pin Name Description 2 Head Sel 3 4 Head Sel 2 6 Write Gate 8 Config/Stat Data 10 Transfer Acknowledge 12 Attention 14 Head Sel 0 16 Sect/Add MK Found 18 Head Sel 1 20 Index 22 Ready 24 Transfer Request 26 Drive Sel 1 28 Drive Sel 2 30 Drive Sel 3 32 Read Gate 34 Command Data Note: All odd are GND. FO 34 PIN IDC MALE at the Controller. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 20 PIN IDC MALE at the Controller. Developed by Maxtor in the early 1980's as an upgrade and improvement to the ST506 design. ESDI 237 . It may not be modified and re-distributed without the authors permission. Data connector Pin Name Description 1 Drive Selected 2 Sect/Add MK Found 3 Seek Complete 4 Address Mark Enable PR EL IM IN BETA RELEASE AR YB ET A . Ground.

Chapter 1: Connector Menu 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (reserved. 238 .N OT FO R RE DI Contributor: Joakim Ögren ST RI BU TIO N. for step mode) GND Ground Write Clock+ Write ClockCartridge Changed Read Ref Clock+ Read Ref ClockGND Ground NRZ Write Data+ NRZ Write DataGND Ground GND Ground NRZ Read Data+ NRZ Read DataGND Ground GND Ground ESDI Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission. Source: ? Please send any comments to Joakim Ögren.

Ground. (At the controller) 34 PIN IDC MALE at the Controller. Seagate originally developed it to support their ST506 (5 MB) and ST412 (10 MB) drives. Later a new encoding method was developed. Data connector PR EL IM IN Pin Name Description 2 Head Sel 8 4 Head Sel 4 6 Write Gate 8 Seek Complete 10 Track 0 12 Write Fault 14 Head Sel 1 16 RES (reserved) 18 Head Sel 2 20 Index 22 Ready 24 Step 26 Drive Sel 1 28 Drive Sel 2 30 Drive Sel 3 32 Drive Sel 4 34 Direction In BETA RELEASE AR YB ET A . RLL had the advantage that it was possible to store 50% more with it.Chapter 1: Connector Menu ST506/412 Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Often called 2. But it required better drives. RLL (Run Length Limited).7 RLL because the recording scheme involves patterns with no more than 7 successive zeros and no less than two. Control connector Note: All odd pins are GND. 20 PIN IDC MALE at the Controller. 20 PIN IDC FEMALE at the Harddisk. This is almost never an problem. It may not be modified and re-distributed without the authors permission. The first drives used an encoding method called MFM (Modified Frequency Modulation). TIO N. ST506/412 239 .N OT (At the harddisk) FO (At the harddisk) R RE (At the controller) DI ST RI BU Developed by Seagate. Also known as MFM or RLL since these are the encoding methods used to store data. 34 PIN IDC FEMALE at the Harddisk.

N OT FO R RE DI ST RI BU TIO N. PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name Description Drive Selected GND Ground RES (reserved) GND Ground RES (reserved) GND Ground RES (reserved) GND Ground RES (reserved) RES (reserved) GND Ground GND Ground Write Data+ Write DataGND Ground GND Ground Read Data+ Read DataGND Ground GND Ground ST506/412 Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission. 240 .

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Name /IDE-RESET D0 D2 D4 D6 GND D8 D10 D12 D14 GND GND GND GND GND GND GND +5V +5V GND D1 D3 D5 D7 GND D9 D11 D13 D15 /IOW /IOR IDE-IRQ IDE-A2 IDE-A1 IDE-A0 /BICS1 /BICS0 Description Drive Reset Data bit 0 Data bit 2 Data bit 4 Data bit 6 Ground Data bit 8 Data bit 10 Data bit 12 Data bit 14 Ground Ground Ground Ground Ground Ground Ground 5V Power 5V Power Ground Data bit 1 Data bit 3 Data bit 5 Data bit 7 Ground Data bit 9 Data bit 11 Data bit 13 Data bit 15 I/O Write I/O Read Interrupt Request Address bit 2 Address bit 1 Address bit 0 Chip Select 1 Chip Select 0 Contributor: Joakim Ögren Source: SX-1 External IDE connector <ftp://ftp.Chapter 1: Connector Menu Paravision SX-1 External IDE Connector Paravision was formerly Microbotics.txt>. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Please send any comments to Joakim Ögren. usenet posting by Mike Pinso <microbotics1@bix.com> at Paravision.co. 37 PIN D-SUB FEMALE at the controller. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU (At the controller) TIO N. 241 Paravision SX-1 External IDE .uk/pub/amiga/docs/cd32-pinouts. PR EL IM IN BETA RELEASE AR YB ET A .demon.

bluedream.Chapter 1: Connector Menu Mitsumi CD-ROM Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N. (at the controller & CD-ROM) (at the cable. 40 PIN IDC FEMALE at the cable.com> Source: SoundFX 16-bit Multimedia Kit Hardware Manual from Reveal Please send any comments to Joakim Ögren. 242 Mitsumi CD-ROM .) 40 PIN IDC MALE at the controller & CD-ROM. PR EL IM IN BETA RELEASE AR YB ET A . Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name A0 GND A1 GND n/c GND n/c GND n/c GND n/c GND INT GND REQ GND ACK GND RE GND WE GND EN GND DB0 GND DB1 GND DB2 GND DB3 GND DB4 GND DB5 GND DB6 GND DB7 GND Description Address Bit 0 Ground Address Bit 1 Ground Not connected Ground Not connected Ground Not connected Ground Not connected Ground Interrupt Ground Data request For DMA Ground Data Acknowledge For DMA Ground Read Enable Ground Write Enable Ground Bus Enable Ground Data Bit 0 Ground Data Bit 1 Ground Data Bit 2 Ground Data Bit 3 Ground Data Bit 4 Ground Data Bit 5 Ground Data Bit 6 Ground Data Bit 7 Ground Contributor: Keith Solomon <zarathos@thorn.

PR EL IM IN YB ET A . It may not be modified and re-distributed without the authors permission.The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 243 .N OT FO R RE DI Chapter 1: Connector Menu AR BETA RELEASE ST RI BU Mitsumi CD-ROM Connector TIO N.

) 40 PIN IDC MALE at the controller & CD-ROM. PR EL IM IN BETA RELEASE AR YB ET A . Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name GND RESET GND GND GND MODE0 GND MODE1 GND WRITE GND READ GND ST0 GND n/c GND n/c GND ST1 GND EN GND ST2 GND S/DE GND ST3 GND GND D7 D6 GND D5 D4 D3 GND D2 D1 D0 Description Ground CD-Reset Ground Ground Ground Operation Mode Bit 0 Ground Operation Mode Bit 1 Ground CD-Write Ground CD-Read Ground CD-Status Bit 0 Ground No Connection Ground No Connection Ground CD-Status Bit 1 Ground CD-Data Enable Ground CD-Status Bit 2 Ground CD-Status/Data Enable Ground CD-Status Bit 3 ground ground CD-Data 7 CD-Data 6 ground CD-Data 5 CD-Data 4 CD-Data 3 ground CD-Data 2 CD-Data 1 CD-Data 0 Contributor: Keith Solomon <zarathos@thorn.N OT FO R RE DI ST RI BU TIO N. 40 PIN IDC FEMALE at the cable. It may not be modified and re-distributed without the authors permission. 244 Panasonic CD-ROM . (at the controller & CD-ROM) (at the cable.Chapter 1: Connector Menu Panasonic CD-ROM Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.bluedream.com> Source: SoundFX 16-bit Multimedia Kit Hardware Manual from Reveal Please send any comments to Joakim Ögren.

PR EL IM IN YB ET A .The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 245 . It may not be modified and re-distributed without the authors permission.N OT FO R RE DI Chapter 1: Connector Menu AR BETA RELEASE ST RI BU Panasonic CD-ROM Connector TIO N.

) 34 PIN IDC MALE at the controller & CD-ROM.bluedream. It may not be modified and re-distributed without the authors permission. (at the controller & CD-ROM) (at the cable.com> Source: SoundFX 16-bit Multimedia Kit Hardware Manual from Reveal Please send any comments to Joakim Ögren. 246 Sony CD-ROM . Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name RESET GND DB7 GND DB6 GND DB5 GND DB4 GND DB3 GND DB2 GND DB1 GND DB0 GND WE GND RE GND ACK GND REQ GND INT GND A1 GND A0 GND EN GND Description Reset Ground Data Bit 7 Ground Data Bit 6 Ground Data Bit 5 Ground Data Bit 4 Ground Data Bit 3 Ground Data Bit 2 Ground Data Bit 1 Ground Data Bit 0 Ground Write Enable Ground Read Enable Ground Data Acknowledge For DMA Ground Data Request For DMA Ground Interrupt Ground Address Bit 1 Ground Address Bit 0 Ground Bus Enable Ground Contributor: Keith Solomon <zarathos@thorn. 34 PIN IDC FEMALE at the cable. PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI ST RI BU TIO N.Chapter 1: Connector Menu Sony CD-ROM Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

247 C64 Cassette .Chapter 1: Connector Menu C64 Cassette Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . Source: Commodore 64 Programmer's Reference Guide Please send any comments to Joakim Ögren. Arwin Vosselman <0vosselman01@flnet. (At the computer) 6 PIN MALE EDGE at the computer.N OT FO R RE Contributor: Joakim Ögren.nl> DI ST RI BU TIO N. Pin A-1 B-2 C-3 D-4 E-5 F-6 Name Dir GND +5V MOTOR READ WRITE SENSE Description Ground +5 Volts DC Cassette Motor Cassette Read Cassette Write Cassette Sense Note: Direction is Computer relative Cassette. It may not be modified and re-distributed without the authors permission.

Source: SAMS Computerfacts CC8 Commodore 16. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Contributor: Joakim Ögren. It may not be modified and re-distributed without the authors permission. 7 PIN MINI-DIN FEMALE at the computer.Chapter 1: Connector Menu C16/C116/+4 Cassette Connector Available on the Commodore C16. Arwin Vosselman <0vosselman01@flnet. C116 and +4 computers. Pin 1 2 3 4 5 6 7 Name Dir GND +5V MOTOR READ WRITE SENSE GND Description Ground +5 Volts DC Cassette Motor Cassette Read Cassette Write Cassette Sense Ground Note: Direction is Computer relative Cassette.N OT FO R RE DI ST RI BU (At the computer) TIO N.nl> PR EL IM IN BETA RELEASE AR YB ET A . Please send any comments to Joakim Ögren. 248 C16/C116/+4 Cassette .

N OT FO R RE DI ST RI BU (At the CoCo) TIO N. UNKNOWN CONNECTOR at the CoCo. Pin 1 2 3 4 5 Description Motor Relay Ground Motor Relay Signal Input Signal Output Contributor: Joakim Ögren Source: Tandy Color Computer FAQ <http://www.com/~vga2000/faqs/coco.io. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.faq> at Video Game Advantage's homepage <http://www.com/~vga2000/> Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission.io. PR EL IM IN BETA RELEASE AR YB ET A . 249 CoCo Cassette .Chapter 1: Connector Menu CoCo Cassette Connector Available on the Tandy/Radio Shack Color Computer (CoCo).

N OT FO Note: Direction is Computer relative Cassette. R RE DI ST RI BU TIO N. Pin 1 2 3 4 5 6 7 8 Name Dir GND GND GND CMTOUT CMTIN REM+ REMGND Description Ground Ground Ground Sound Output Sound Input Remote control (from relay) Remote control (from relay) Ground Contributor: Joakim Ögren Source: Mayer's SV738 X'press I/O map <http://www. 250 MSX Cassette .com/fms/MSX/Portar.Chapter 1: Connector Menu MSX Cassette Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .txt> Please send any comments to Joakim Ögren.freeflight. 8 PIN DIN (DIN45326) MALE at the cassette cable. (At the computer) (At the cassette cable) 8 PIN DIN (DIN45326) FEMALE at the computer.

PR EL IM IN BETA RELEASE AR YB ET A . Pin 1 2 3 4 5 6 7 Name 12v CASR CASW AUDIO GND ME READY Description Power 100mA Cassette data read Cassette data write Cassette audio System ground System Ready Contributor: Rob Gill <gillr@mailcity.N OT FO R RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu Spectravideo SVI318/328 Cassette Connector +-------------+ |1 2 3 4 5 6 7| +-------------+ The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (At the computer) 7 PIN FEMALE EDGE CONNECTOR at the computer.com> Source: SVI mk II user manual Please send any comments to Joakim Ögren. 251 Spectravideo SVI318/328 Cassette .

diron.uk> ST RI BU TIO N. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A . Agnello Guarracino <aggy@ooh. Pin 1 2 3 4 5 Name REMOTE SWITCH GND REMOTE SWITCH DATA IN DATA OUT Source: Amstrad CPC6128 User Instructions Manual Please send any comments to Joakim Ögren. (At the computer) 5 PIN DIN 180° (DIN41524) FEMALE at the computer.N OT FO R RE DI Contributor: Joakim Ögren. 252 Amstrad CPC6128 Tape .Chapter 1: Connector Menu Amstrad CPC6128 Tape Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.co.

ibm.answers/pc-hardware-faq/part1>. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Name VCC /CAS DQ0 A0 A1 DQ1 A2 A3 GND DQ2 A4 A5 DQ3 A6 A7 DQ4 A8 A9 A10 DQ5 /WE GND DQ6 A11 DQ7 QP /RAS /CASP DP VCC Description +5 VDC Column Address Strobe Data 0 Address 0 Address 1 Data 1 Address 2 Address 3 Ground Data 2 Address 4 Address 5 Data 3 Address 6 Address 7 Data 4 Address 8 Address 9 Address 10 Data 5 Write Enable Ground Data 6 Address 11 Data 7 Data Parity Out Row Address Strobe Something Parity ???? Data Parity In +5 VDC Contributor: Joakim Ögren. BETA RELEASE AR YB ET A .sys.siemens.net> Source: comp.wpi.N OT FO R RE DI ST RI BU TIO N. 1MB & 4MB.behrendt@ffm-r1.edu/pub/usenet/news. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.edu> Please send any comments to Joakim Ögren. Helfried Behrendt <helfried.hardware. (At the computer) 30 PIN SIMM at the computer. PR EL IM IN Note: SIMM above is a 4MBx9. 253 30 pin SIMM .Chapter 1: Connector Menu 30 pin SIMM Connector SIMM=Single Inline Memory Module.pc.* FAQ Part 4 <ftp://rtfm. maintained by Ralph Valentino <ralf@alum. A11 is N/C on 256kB. A9 is N/C on 256kB.mit. A10 is N/C on 256kB & 1MB. QP & DP is N/C on SIMMs without parity.ffm1.

N OT FO R RE DI ST RI BU (At the computer) TIO N. bits 0-7) Parity bit 2 (for the 2nd byte. It may not be modified and re-distributed without the authors permission. bits 16-23) Parity bit 1 (for the 1st byte. 72 PIN SIMM at the computer. bits 8-15) Parity bit 4 (for the 4th byte. bits 24-31) Ground Column Address Strobe 0 Column Address Strobe 2 Column Address Strobe 3 Column Address Strobe 1 Row Address Strobe 0 PR EL IM IN BETA RELEASE AR YB ET A . 254 72 pin SIMM . Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Non-ParityParity VSS VSS DQ0 DQ0 DQ16 DQ16 DQ1 DQ1 DQ17 DQ17 DQ2 DQ2 DQ18 DQ18 DQ3 DQ3 DQ19 DQ19 VCC VCC n/c n/c A0 A0 A1 A1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 A10 A10 DQ4 DQ4 DQ20 DQ20 DQ5 DQ5 DQ21 DQ21 DQ6 DQ6 DQ22 DQ22 DQ7 DQ7 DQ23 DQ23 A7 A7 A11 A11 VCC VCC A8 A8 A9 A9 /RAS3 /RAS3 /RAS2 /RAS2 n/c PQ3 n/c PQ1 n/c PQ2 n/c PQ4 VSS VSS /CAS0 /CAS0 /CAS2 /CAS2 /CAS3 /CAS3 /CAS1 /CAS1 /RAS0 /RAS0 Description Ground Data 0 Data 16 Data 1 Data 17 Data 2 Data 18 Data 3 Data 19 +5 VDC Not connected Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 10 Data 4 Data 20 Data 5 Data 21 Data 6 Data 22 Data 7 Data 23 Address 7 Address 11 +5 VDC Address 8 Address 9 Row Address Strobe 3 Row Address Strobe 2 Parity bit 3 (for the 3rd byte.Chapter 1: Connector Menu 72 pin SIMM Connector SIMM=Single Inline Memory Module The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

100 ns 80 ns 70 ns 60 ns Contributors: Joakim Ögren.com/products/memory/> Please send any comments to Joakim Ögren.chips.com. BETA RELEASE AR YB ET A . 512k. Mark Brown <bugman@total. 1M and 4M modules. 255 .tw> Source: Various productsheets at IBM Memory Products <http://www.Chapter 1: Connector Menu 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 /RAS1 n/c /WE n/c DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ16 n/c PD1 PD2 PD3 PD4 n/c VSS /RAS1 n/c /WE n/c DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ16 n/c PD1 PD2 PD3 PD4 n/c VSS Row Address Strobe 1 Not connected Read/Write Not connected Data 8 Data 24 Data 9 Data 25 Data 10 Data 26 Data 11 Data 27 Data 12 Data 28 +5 VDC Data 29 Data 13 Data 30 Data 14 Data 31 Data 16 Not connected Presence Detect 1 Presence Detect 2 Presence Detect 3 Presence Detect 4 Not connected Ground 72 pin SIMM Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.ibm. PR EL IM IN Notes: A9 is a N/C on 256k and 512k modules. Size: PD2 GND GND NC NC PD1 GND NC GND NC Size 4 or 64 MB 2 or 32 MB 1 or 16 MB 8 MB Accesstime: PD4 GND GND NC NC PD3 GND NC GND NC Accesstime 50. Karsten Wenke <Karsten. 1M and 4M modules. SOYO Computer Inc <http://www. It may not be modified and re-distributed without the authors permission. RAS1/RAS3 are N/C on 256k.Wenke@t-online.soyo.net>.de>. A10 is a N/C on 256k.N OT FO R RE DI ST RI BU TIO N.

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 ECC VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC PD5 A0 A1 A2 A3 A4 A5 A6 n/c DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A7 DQ16 VCC A8 A9 n/c /RAS1 DQ17 DQ18 DQ19 DQ20 VSS /CAS0 A10 A11 /CAS1 OptimizedDescription VSS Ground DQ0 Data 0 DQ1 Data 1 DQ2 Data 2 DQ3 Data 3 DQ4 Data 4 DQ5 Data 5 DQ6 Data 6 DQ7 Data 7 VCC +5 VDC PD5 Presence Detect 5 A0 Address 0 A1 Address 1 A2 Address 2 A3 Address 3 A4 Address 4 A5 Address 5 A6 Address 6 n/c Not connected DQ8 Data 8 DQ9 Data 9 DQ10 Data 10 DQ11 Data 11 DQ12 Data 12 DQ13 Data 13 DQ14 Data 14 DQ15 Data 15 A7 Address 7 DQ16 Data 16 VCC +5 VDC A8 Address 8 A9 Address 9 n/c Not connected /RAS1 Row Address Strobe 1 DQ17 Data 17 DQ18 Data 18 DQ19 Data 19 DQ20 Data 20 VSS Ground /CAS0 Column Address Strobe 0 A10 Address 10 A11 Address 11 /CAS1 Column Address Strobe 1 PR EL IM IN BETA RELEASE AR YB ET A . 256 72 pin ECC SIMM .N OT FO R RE DI ST 72 PIN SIMM at the computer. It may not be modified and re-distributed without the authors permission. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Chapter 1: Connector Menu 72 pin ECC SIMM Connector SIMM=Single Inline Memory Module ECC=Error Correcting Code. RI BU (At the computer) TIO N.

257 .com/products/memory/> OT FO R RE DI ST RI BU TIO N. Contributor: Joakim Ögren Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 /RAS0 /RAS1 DQ21 /WE /ECC DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 n/c n/c n/c PD1 PD2 PD3 PD4 n/c VSS /RAS0 /RAS1 DQ21 /WE /ECC DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 PD1 PD2 PD3 PD4 DQ39 VSS Row Address Strobe 0 Row Address Strobe 1 Data 21 Read/Write Data 22 Data 23 Data 24 Data 25 Data 26 Data 27 Data 28 Data 29 Data 30 Data 31 +5 VDC Data 32 Data 33 Data 34 Data 35 Data 36 Data 37 Data 38 Presence Detect 1 Presence Detect 2 Presence Detect 3 Presence Detect 4 Data 39 Ground 72 pin ECC SIMM Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.chips. It may not be modified and re-distributed without the authors permission.N Source: Various productsheets at IBM Memory Products <http://www.ibm.

258 72 pin SO DIMM . Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Non-ParityParity Description VSS VSS Ground DQ0 DQ0 Data 0 DQ1 DQ1 Data 1 DQ2 DQ2 Data 2 DQ3 DQ3 Data 3 DQ4 DQ4 Data 4 DQ5 DQ5 Data 5 DQ6 DQ6 Data 6 DQ7 DQ7 Data 7 VCC VCC +5 VDC PD1 PD1 Presence Detect 1 A0 A0 Address 0 A1 A1 Address 1 A2 A2 Address 2 A3 A3 Address 3 A4 A4 Address 4 A5 A5 Address 5 A6 A6 Address 6 A10 A10 Address 10 n/c PQ8 Data 8 (Parity 1) DQ9 DQ9 Data 9 DQ10 DQ10 Data 10 DQ11 DQ11 Data 11 DQ12 DQ12 Data 12 DQ13 DQ13 Data 13 DQ14 DQ14 Data 14 DQ15 DQ15 Data 15 A7 A7 Address 7 A11 A11 Address 11 VCC VCC +5 VDC A8 A8 Address 8 A9 A9 Address 9 /RAS3 RAS3 Row Address Strobe 3 /RAS2 RAS2 Row Address Strobe 2 DQ16 DQ16 Data 16 n/c PQ17 Data 17 (Parity 2) DQ18 DQ18 Data 18 DQ19 DQ19 Data 19 VSS VSS Ground /CAS0 CAS0 Column Address Strobe 0 /CAS2 CAS2 Column Address Strobe 2 /CAS3 CAS3 Column Address Strobe 3 /CAS1 CAS1 Column Address Strobe 1 /RAS0 RAS0 Row Address Strobe 0 /RAS1 RAS1 Row Address Strobe 1 A12 A12 Address 12 /WE WE Read/Write PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu 72 pin SO DIMM Connector SO DIMM=Small Outline Dual Inline Memory Module The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 72 PIN SO DIMM at the computer.N OT FO R RE DI ST RI BU (At the computer) TIO N. It may not be modified and re-distributed without the authors permission.

Mark Brown <bugman@total. Jim Burd <JimBurd@aol. It may not be modified and re-distributed without the authors permission.com> Source: Various productsheets at IBM Memory Products <http://www.net>.N OT FO R RE DI ST RI BU TIO N. Contributor: Joakim Ögren.chips.Chapter 1: Connector Menu 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A13 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 n/c DQ27 DQ28 DQ29 DQ31 DQ30 VCC DQ32 DQ33 DQ34 n/c PD2 PD3 PD4 PD5 PD6 PD7 VSS A13 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 PQ26 DQ27 DQ28 DQ29 DQ31 DQ30 VCC DQ32 DQ33 DQ34 PQ35 PD2 PD3 PD4 PD5 PD6 PD7 VSS Address 13 Data 20 Data 21 Data 22 Data 23 Data 24 Data 25 Data 26 (Parity 3) Data 27 Data 28 Data 29 Data 31 Data 30 +5 VDC Data 32 Data 33 Data 34 Data 35 (Parity 4) Presence Detect 2 Presence Detect 3 Presence Detect 4 Presence Detect 1 Presence Detect 6 Presence Detect 7 Ground 72 pin SO DIMM Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.com/products/memory/> Please send any comments to Joakim Ögren.ibm. 259 . PR EL IM IN BETA RELEASE AR YB ET A .

Chapter 1: Connector Menu 144 pin SO DIMM Connector SO SIMM=Small Outline Single Inline Memory Module The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 144 PIN SO SIMM at the computer. It may not be modified and re-distributed without the authors permission. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Normal ECC VSS VSS VSS VSS DQ0 DQ0 DQ32 DQ32 DQ1 DQ1 DQ33 DQ33 DQ2 DQ2 DQ34 DQ34 DQ3 DQ3 DQ35 DQ35 VCC VCC VCC VCC DQ4 DQ4 DQ36 DQ36 DQ5 DQ5 DQ37 DQ37 DQ6 DQ6 DQ38 DQ38 DQ7 DQ7 DQ39 DQ39 VSS VSS VSS VSS /CAS0 /CAS0 /CAS4 /CAS4 /CAS1 /CAS1 /CAS5 /CAS5 VCC VCC VCC VCC A0 A0 A3 A3 A1 A1 A4 A4 A2 A2 A5 A5 VSS VSS VSS VSS DQ8 DQ8 DQ40 DQ40 DQ9 DQ9 DQ41 DQ41 DQ10 DQ10 DQ42 DQ42 DQ11 DQ11 DQ43 DQ43 VCC VCC VCC VCC DQ12 DQ12 Description Ground Ground Data 0 Data 32 Data 1 Data 33 Data 2 Data 34 Data 3 Data 35 +5 VDC +5 VDC Data 4 Data 36 Data 5 Data 37 Data 6 Data 38 Data 7 Data 39 Ground Ground Column Address Strobe 0 Column Address Strobe 4 Column Address Strobe 1 Column Address Strobe 5 +5 VDC +5 VDC Address 0 Address 3 Address 1 Address 4 Address 2 Address 5 Ground Ground Data 8 Data 40 Data 9 Data 41 Data 10 Data 42 Data 11 Data 43 +5 VDC +5 VDC Data 12 PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI ST RI BU (At the computer) TIO N. 260 144 pin SO DIMM .

Chapter 1: Connector Menu 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 DQ44 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 VSS VSS n/c n/c n/c n/c DU DU VCC VCC DU DU /WE n/c /RAS0 n/c /RAS1 n/c /OE n/c VSS VSS n/c n/c n/c n/c VCC VCC DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 VSS VSS DQ20 DQ52 DQ21 DQ53 DQ22 DQ54 DQ23 DQ55 VCC VCC A6 A7 A8 A11 VSS DQ44 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 VSS VSS CB0 CB4 CB1 CB5 DU DU VCC VCC DU DU /WE n/c /RAS0 n/c /RAS1 n/c /OE n/c VSS VSS CB2 CB6 CB3 CB7 VCC VCC DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 VSS VSS DQ20 DQ52 DQ21 DQ53 DQ22 DQ54 DQ23 DQ55 VCC VCC A6 A7 A8 A11 VSS Data 44 Data 13 Data 45 Data 14 Data 46 Data 15 Data 47 Ground Ground 144 pin SO DIMM Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT Not connected Ground Ground FO Don't use Don't use +5 VDC +5 VDC Don't use Don't use Read/Write Not connected Row Address Strobe 0 Not connected Row Address Strobe 1 Not connected R RE DI ST RI BU TIO N. +5 VDC +5 VDC Data 16 Data 48 Data 17 Data 49 Data 18 Data 50 Data 19 Data 51 Ground Ground Data 20 Data 52 Data 21 Data 53 Data 22 Data 54 Data 23 Data 55 +5 VDC +5 VDC Address 6 Address 7 Address 8 Address 11 Ground PR EL IM IN BETA RELEASE AR YB ET A . 261 . It may not be modified and re-distributed without the authors permission.

PR EL IM IN BETA RELEASE AR YB Source: Various productsheets at IBM Memory Products <http://www.net> Please send any comments to Joakim Ögren.chips. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS A9 A12 A10 A13 VCC VCC /CAS2 /CAS6 /CAS3 /CAS7 VSS /VSS DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 VCC VCC DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 VSS VSS SDA SCL VCC VCC VSS A9 A12 A10 A13 VCC VCC /CAS2 /CAS6 /CAS3 /CAS7 VSS /VSS DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 VCC VCC DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 VSS VSS SDA SCL VCC VCC Ground Address 9 Address 12 Address 10 Address 13 +5 VDC +5 VDC Column Address Strobe 2 Column Address Strobe 6 Column Address Strobe 3 Column Address Strobe 7 Ground Ground Data 24 Data 56 Data 25 Data 57 Data 26 Data 58 Data 27 Data 59 +5 VDC +5 VDC Data 28 Data 60 Data 29 Data 61 Data 30 Data 62 Data 31 Data 63 Ground Ground +5 VDC +5 VDC 144 pin SO DIMM Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 262 .N OT FO R RE DI ST RI BU TIO N. Contributor: Joakim Ögren. Mark Brown <bugman@total.com/products/memory/> ET A .ibm.

263 168 pin DRAM DIMM (Unbuffered) .N OT FO R RE DI ST Front.3 VDC Read/Write Input Column Address Strobe 0 Column Address Strobe 1 Row Address Strobe 0 Output Enable Ground Address 0 Address 2 Address 4 Address 6 Address 8 Address 10 Address 12 +5 VDC or +3. 168 PIN DIMM at the computer.3 VDC Data 14 Data 15 Parity/Check Bit Input/Output 0 Parity/Check Bit Input/Output 1 Ground Parity/Check Bit Input/Output 8 Parity/Check Bit Input/Output 9 +5 VDC or +3. It may not be modified and re-distributed without the authors permission. Front Side (left side 1-42.3 VDC +5 VDC or +3.3 VDC Data 4 Data 5 Data 6 Data 7 Data 8 Ground Data 9 Data 10 Data 11 Data 12 Data 13 +5 VDC or +3. right side 43-84) Back Side (left side 85-126. right side 127-168) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Non-Parity?Parity? 72 ECC? VSS VSS VSS DQ0 DQ0 DQ0 DQ1 DQ1 DQ1 DQ2 DQ2 DQ2 DQ3 DQ3 DQ3 VCC VCC VCC DQ4 DQ4 DQ4 DQ5 DQ5 DQ5 DQ6 DQ6 DQ6 DQ7 DQ7 DQ7 DQ8 DQ8 DQ8 VSS VSS VSS DQ9 DQ9 DQ9 DQ10 DQ10 DQ10 DQ11 DQ11 DQ11 DQ12 DQ12 DQ12 DQ13 DQ13 DQ13 VCC VCC VCC DQ14 DQ14 DQ14 DQ15 DQ15 DQ15 n/c CB0 CB0 n/c CB1 CB1 VSS VSS VSS n/c n/c n/c n/c n/c n/c VCC VCC VCC /WE0 /WE0 /WE0 /CAS0 /CAS0 /CAS0 /CAS1 /CAS1 /CAS1 /RAS0 /RAS0 /RAS0 /OE0 /OE0 /OE0 VSS VSS VSS A0 A0 A0 A2 A2 A2 A4 A4 A4 A6 A6 A6 A8 A8 A8 A10 A10 A10 A12 A12 A12 VCC VCC VCC VCC VCC VCC DU DU DU 80 ECC? VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS CB8 CB9 VCC /WE0 /CAS0 /CAS1 /RAS0 /OE0 VSS A0 A2 A4 A6 A8 A10 A12 VCC VCC DU Description Ground Data 0 Data 1 Data 2 Data 3 +5 VDC or +3. Left RI BU (At the computer) TIO N.3 VDC Don't Use PR EL IM IN BETA RELEASE AR YB ET A .Chapter 1: Connector Menu 168 pin DRAM DIMM (Unbuffered) Connecto DIMM=Dual Inline Memory Module The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

Pin 85 86 87 88 89 90 91 92 93 94 PR EL IM IN Back. It may not be modified and re-distributed without the authors permission. .3 VDC YB ET A . Left Non-Parity?Parity? 72 ECC? VSS VSS VSS DQ32 DQ32 DQ32 DQ33 DQ33 DQ33 DQ34 DQ34 DQ34 DQ35 DQ35 DQ35 VCC VCC VCC DQ36 DQ36 DQ36 DQ37 DQ37 DQ37 DQ38 DQ38 DQ38 DQ39 DQ39 DQ39 AR Row Address Strobe 2 Column Address Strobe 2 Column Address Strobe 3 Read/Write Input +5 VDC or +3.Chapter 1: Connector Menu Front.3 VDC Parity/Check Bit Input/Output 10 Parity/Check Bit Input/Output 11 Parity/Check Bit Input/Output 2 Parity/Check Bit Input/Output 3 Ground Data 16 Data 17 Data 18 Data 19 +5 VDC or +3. Right Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Non-Parity?Parity? 72 ECC? VSS VSS VSS /OE2 /OE2 /OE2 /RAS2 /RAS2 /RAS2 /CAS2 /CAS2 /CAS2 /CAS3 /CAS3 /CAS3 /WE2 /WE2 /WE2 VCC VCC VCC n/c n/c n/c n/c n/c n/c n/c CB2 CB2 n/c CB3 CB3 VSS VSS VSS DQ16 DQ16 DQ16 DQ17 DQ17 DQ17 DQ18 DQ18 DQ18 DQ19 DQ19 DQ19 VCC VCC VCC DQ20 DQ20 DQ20 n/c n/c n/c DU DU DU n/c n/c n/c VSS VSS VSS DQ21 DQ21 DQ21 DQ22 DQ22 DQ22 DQ23 DQ23 DQ23 VSS VSS VSS DQ24 DQ24 DQ24 DQ25 DQ25 DQ25 DQ26 DQ26 DQ26 DQ27 DQ27 DQ27 VCC VCC VCC DQ28 DQ28 DQ28 DQ29 DQ29 DQ29 DQ30 DQ30 DQ30 DQ31 DQ31 DQ31 VSS VSS VSS n/c n/c n/c n/c n/c n/c n/c n/c n/c SDA SDA SDA SCL SCL SCL VCC VCC VCC 80 ECC? VSS /OE2 /RAS2 /CAS2 /CAS3 /WE2 VCC CB10 CB11 CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 n/c DU n/c VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS n/c n/c n/c SDA SCL VCC 168 pin DRAM DIMM (Unbuffered) Connecto Description Ground The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.3 VDC Data 36 Data 37 Data 38 Data 39 264 RE DI ST RI BU TIO N.3 VDC Data 20 Not connected Don't Use Not connected Ground Data 21 Data 22 Data 23 Ground Data 24 Data 25 Data 26 Data 27 +5 VDC or +3.N OT 80 ECC? VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 BETA RELEASE FO R Description Ground Data 32 Data 33 Data 34 Data 35 +5 VDC or +3.3 VDC Data 28 Data 29 Data 30 Data 31 Ground Not connected Not connected Not connected Serial Data Serial Clock +5 VDC or +3.

3 VDC Don't Use Don't Use OT 80 ECC? VSS DU /RAS3 /CAS6 /CAS7 DU VCC CB14 CB15 CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 n/c DU n/c VSS DQ53 DQ54 PR EL IM IN BETA RELEASE AR YB FO R Description Ground Don't Use Column Address Strobe 3 Column Address Strobe 6 Column Address Strobe 7 Don't Use +5 VDC or +3.N Data 40 Ground Data 41 Data 42 Data 43 Data 44 Data 45 +5 VDC or +3. Back. It may not be modified and re-distributed without the authors permission.3 VDC Don't Use Column Address Strobe 4 Column Address Strobe 5 Row Address Strobe 1 Don't Use Ground Address 1 Address 3 Address 5 Address 7 Address 9 Address 11 Address 13 +5 VDC or +3. .3 VDC Parity/Check Bit Input/Output 14 Parity/Check Bit Input/Output 15 Parity/Check Bit Input/Output 6 Parity/Check Bit Input/Output 7 Ground Data 48 Data 49 Data 50 Data 51 +5 VDC or +3. Right Pin 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Non-Parity?Parity? 72 ECC? VSS VSS VSS DU DU DU /RAS3 /RAS3 /RAS3 /CAS6 /CAS6 /CAS6 /CAS7 /CAS7 /CAS7 DU DU DU VCC VCC VCC n/c n/c n/c n/c n/c n/c n/c CB6 CB6 n/c CB7 CB7 VSS VSS VSS DQ48 DQ48 DQ48 DQ49 DQ49 DQ49 DQ50 DQ50 DQ50 DQ51 DQ51 DQ51 VCC VCC VCC DQ52 DQ52 DQ52 n/c n/c n/c DU DU DU n/c n/c n/c VSS VSS VSS DQ53 DQ53 DQ53 DQ54 DQ54 DQ54 ET A .3 VDC Data 52 Not connected Don't Use Not connected Ground Data 53 Data 54 265 RE DI ST RI BU TIO N.3 VDC Data 46 Data 47 Parity/Check Bit Input/Output 4 Parity/Check Bit Input/Output 5 Ground Parity/Check Bit Input/Output 12 Parity/Check Bit Input/Output 13 +5 VDC or +3.Chapter 1: Connector Menu 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 n/c n/c VSS n/c n/c VCC DU /CAS4 /CAS5 /RAS1 DU VSS A1 A3 A5 A7 A9 A11 A13 VCC DU DU DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS n/c n/c VCC DU /CAS4 /CAS5 /RAS1 DU VSS A1 A3 A5 A7 A9 A11 A13 VCC DU DU DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS n/c n/c VCC DU /CAS4 /CAS5 /RAS1 DU VSS A1 A3 A5 A7 A9 A11 A13 VCC DU DU DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS CB12 CB13 VCC DU /CAS4 /CAS5 /RAS1 DU VSS A1 A3 A5 A7 A9 A11 A13 VCC DU DU 168 pin DRAM DIMM (Unbuffered) Connecto The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

ibm.N OT FO R RE Contributor: Joakim Ögren.Chapter 1: Connector Menu 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VCC DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VCC DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VCC DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VCC 168 pin DRAM DIMM (Unbuffered) Connecto The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.3 VDC ST RI Data 55 Ground Data 56 Data 57 Data 58 Data 59 +5 VDC or +3. Source: Various productsheets at IBM Memory Products <http://www. PR EL IM IN BETA RELEASE AR YB ET A . Mark Brown <bugman@total.com/products/memory/> Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission.chips.net> DI Not connected Serial Address 0 Serial Address 1 Serial Address 2 +5 VDC or +3.3 VDC Data 60 Data 61 Data 62 Data 63 Ground BU TIO N. 266 .

267 168 pin SDRAM DIMM (Unbuffered) . Left RI BU (At the computer) TIO N. It may not be modified and re-distributed without the authors permission.3 VDC Data 14 Data 15 Parity/Check Bit Input/Output 0 Parity/Check Bit Input/Output 01 Ground Parity/Check Bit Input/Output 8 Parity/Check Bit Input/Output 9 +5 VDC or +3. right side 43-84) Back Side (left side 85-126. Front Side (left side 1-42.3 VDC +5 VDC or +3.3 VDC Data 4 Data 5 Data 6 Data 7 Data 8 Ground Data 9 Data 10 Data 11 Data 12 Data 13 +5 VDC or +3. 168 PIN DIMM at the computer. right side 127-168) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Non-Parity72 ECC? VSS VSS DQ0 DQ0 DQ1 DQ1 DQ2 DQ2 DQ3 DQ3 VDD VDD DQ4 DQ4 DQ5 DQ5 DQ6 DQ6 DQ7 DQ7 DQ8 DQ8 VSS VSS DQ9 DQ9 DQ10 DQ10 DQ11 DQ11 DQ12 DQ12 DQ13 DQ13 VDD VDD DQ14 DQ14 DQ15 DQ15 n/c CB0 n/c CB1 VSS VSS n/c n/c n/c n/c VDD VDD /WE /WE DQMB0 DQMB0 DQMB1 DQMB1 /S0 /S0 DU DU VSS VSS A0 A0 A2 A2 A4 A4 A6 A6 A8 A8 A10/AP A10/AP BA1 BA1 VDD VDD VDD VDD CK0 CK0 80 ECC? VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS CB8 CB9 VDD /WE DQMB0 DQMB1 /S0 DU VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD CK0 Description Ground Data 0 Data 1 Data 2 Data 3 +5 VDC or +3.N OT FO R RE DI ST Front.Chapter 1: Connector Menu 168 pin SDRAM DIMM (Unbuffered) Connec DIMM=Dual Inline Memory Module The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.3 VDC Clock signal 0 PR EL IM IN BETA RELEASE AR YB ET A .3 VDC Read/Write Byte Mask signal 0 Byte Mask signal 1 Chip Select 0 Don't Use Ground Address 0 Address 2 Address 4 Address 6 Address 8 Address 10 Bank Address 1 +5 VDC or +3.

It may not be modified and re-distributed without the authors permission.3 VDC Parity/Check Bit Input/Output 10 Parity/Check Bit Input/Output 11 Parity/Check Bit Input/Output 2 Parity/Check Bit Input/Output 3 Ground Data 16 Data 17 Data 18 Data 19 +5 VDC or +3. Right Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Non-Parity72 ECC? VSS VSS DU DU /S2 /S2 DQMB2 DQMB2 DQMB3 DQMB3 DU DU VDD VDD n/c n/c n/c n/c n/c CB2 n/c CB3 VSS VSS DQ16 DQ16 DQ17 DQ17 DQ18 DQ18 DQ19 DQ19 VDD VDD DQ20 DQ20 n/c n/c Vref.3 VDC Data 36 Data 37 Data 38 Data 39 268 FO R RE DI ST RI BU TIO N.3 VDC Data 20 Not connected Clock Enable Signal 1 Ground Data 21 Data 22 Data 23 Ground Data 24 Data 25 Data 26 Data 27 +5 VDC or +3.3 VDC Data 28 Data 29 Data 30 Data 31 Ground Clock signal 2 Not connected Not connected Serial Data Serial Clock +5 VDC or +3.NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 n/c n/c SDA SCL VDD 168 pin SDRAM DIMM (Unbuffered) Connec The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.NC Vref.3 VDC Pin 85 86 87 88 89 90 91 92 93 94 PR EL IM IN Back.NC CKE1 CKE1 VSS VSS DQ21 DQ21 DQ22 DQ22 DQ23 DQ23 VSS VSS DQ24 DQ24 DQ25 DQ25 DQ26 DQ26 DQ27 DQ27 VDD VDD DQ28 DQ28 DQ29 DQ29 DQ30 DQ30 DQ31 DQ31 VSS VSS CK2 CK2 n/c n/c n/c n/c SDA SDA SCL SCL VDD VDD 80 ECC? VSS DU /S2 DQMB2 DQMB3 DU VDD CB10 CB11 CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 n/c Vref.Chapter 1: Connector Menu Front. . Description Ground Don't Use Chip Select 2 Byte Mask signal 2 Byte Mask signal 3 Don't Use +5 VDC or +3.N OT Description Ground Data 32 Data 33 Data 34 Data 35 +5 VDC or +3. Left Non-Parity72 ECC? VSS VSS DQ32 DQ32 DQ33 DQ33 DQ34 DQ34 DQ35 DQ35 VDD VDD DQ36 DQ36 DQ37 DQ37 DQ38 DQ38 DQ39 DQ39 AR YB ET A 80 ECC? VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 BETA RELEASE .

NC n/c VSS DQ53 DQ54 PR EL IM IN AR YB BETA RELEASE .Chapter 1: Connector Menu 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 n/c n/c VSS n/c n/c VDD /CAS DQMB4 DQMB5 /S1 /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CK1 A12 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS n/c n/c VDD /CAS DQMB4 DQMB5 /S1 /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CK1 A12 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS CB12 CB13 VDD /CAS DQMB4 DQMB5 /S1 /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CK1 A12 168 pin SDRAM DIMM (Unbuffered) Connec The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Back.3 VDC Column Address Strobe Byte Mask signal 4 Byte Mask signal 5 Chip Select 1 Row Address Strobe Ground Address 1 Address 3 Address 5 Address 7 Address 9 Bank Address 0 Address 11 +5 VDC or +3.NC Vref.3 VDC Data 52 Not connected Not connected Ground Data 53 Data 54 269 FO R RE DI ST RI BU TIO N.3 VDC Clock signal 1 Address 12 OT Description Ground Clock Enable Signal 0 Chip Select 3 Byte Mask signal 6 Byte Mask signal 7 Address 13 +5 VDC or +3.3 VDC Data 46 Data 47 Parity/Check Bit Input/Output 4 Parity/Check Bit Input/Output 5 Ground Parity/Check Bit Input/Output 12 Parity/Check Bit Input/Output 13 +5 VDC or +3.3 VDC Parity/Check Bit Input/Output 14 Parity/Check Bit Input/Output 15 Parity/Check Bit Input/Output 6 Parity/Check Bit Input/Output 7 Ground Data 48 Data 49 Data 50 Data 51 +5 VDC or +3.N Data 40 Ground Data 41 Data 42 Data 43 Data 44 Data 45 +5 VDC or +3. Right Pin 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Non-Parity72 ECC? VSS VSS CKE0 CKE0 /S3 /S3 DQMB6 DQMB6 DQMB7 DQMB7 A13 A13 VDD VDD n/c n/c n/c n/c n/c CB6 n/c CB7 VSS VSS DQ48 DQ48 DQ49 DQ49 DQ50 DQ50 DQ51 DQ51 VDD VDD DQ52 DQ52 n/c n/c Vref. . It may not be modified and re-distributed without the authors permission.NC n/c n/c VSS VSS DQ53 DQ53 DQ54 DQ54 ET A 80 ECC? VSS CKE0 /S3 DQMB6 DQMB7 A13 VDD CB14 CB15 CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 n/c Vref.

3 VDC Data 60 Data 61 Data 62 Data 63 Ground Clock signal 3 Not connected Serial address 0 Serial address 1 Serial address 2 +5 VDC or +3. PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission.N OT FO R RE Contributor: Joakim Ögren DI Data 55 Ground Data 56 Data 57 Data 58 Data 59 +5 VDC or +3. 270 .com/products/memory/> Please send any comments to Joakim Ögren.3 VDC ST RI BU TIO N. Source: Various productsheets at IBM Memory Products <http://www.ibm.Chapter 1: Connector Menu 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VDD DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VDD DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 n/c SA0 SA1 SA2 VDD 168 pin SDRAM DIMM (Unbuffered) Connec The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.chips.

ualberta.html> PR EL IM IN Description Data Bus 0 Data Bus 1 Data Bus 2 Data Bus 3 Data Bus 4 Data Bus 5 Data Bus 6 Data Bus 7 Data Bus 8 Data Bus 9 Data Bus 10 Data Bus 11 Data Bus 12 Data Bus 13 Data Bus 14 Data Bus 15 Address Bus 1 Address Bus 2 Address Bus 3 Address Bus 4 Address Bus 5 Address Bus 6 Address Bus 7 Address Bus 8 Address Bus 9 Address Bus 10 Address Bus 11 Address Bus 12 Address Bus 13 Address Bus 14 Address Bus 15 Address Bus 16 Address Bus 17 Read/Write (High=Read) Chip Select Odd Bytes Chip Select Even Bytes +5 Volts DC Ground Address Bus 18 (Short J16 to connect A18 to processor bus) Address Bus 19 (Short J17 to connect A19 to processor bus) BETA RELEASE AR YB ET A .N OT FO R RE DI ST RI (At the computer) BU TIO N. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 R/W /CSMCOD /CSMCEN VCC GND A18 A19 Note: Address space=$E00000-$E7FFFF Contributor: Joakim Ögren Source: Darren Ewaniuk's CDTV Technical Information <http://nyquist. 1111111111222222222233333333334 1234567890123456789012345678901234567890 +----------------------------------------+ |OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO| +----------------------------------------+ 40 PIN ??? CONNECTOR at the computer.ca/~ewaniu/cdtv/cdtv-technical.Chapter 1: Connector Menu CDTV Memory Card Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 271 CDTV Memory Card Port . It may not be modified and re-distributed without the authors permission.ee.

N OT FO R RE DI Chapter 1: Connector Menu AR BETA RELEASE ST RI BU CDTV Memory Card Connector TIO N. 272 .The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN YB ET A . It may not be modified and re-distributed without the authors permission. Please send any comments to Joakim Ögren.

Pin 1 2 3 4 5 6 7 8 Name VCC R/W CLOCK RESET GND VPP I/O FUSE Description +5 VDC Read/Write Clock Reset Ground +21 VDC In/Out Fuse Contributor: Joakim Ögren Source: Telecard/Smartcard Technical Spec & Info <http://www. (At the card) UNKNOWN CONNECTOR at the card.ut. 273 SmartCard AFNOR . It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI -------------+------------| 8 | 4 | | | | +-------\ | /-------+ | 7 +----+----+ 3 | | | | | +--------| |--------+ | 6 | | 2 | | + +----+ | +-------/ | \-------+ | 5 | 1 | | | | -------------+------------- BU TIO N.txt> by Stephane Bausson <sbausson@ensem.u-nancy. .ee/~kalev/smartcar.physic.fr> PR EL IM IN BETA RELEASE AR YB ET A Please send any comments to Joakim Ögren.Chapter 1: Connector Menu SmartCard AFNOR Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

txt> by Stephane Bausson <sbausson@ensem. Pin 1 2 3 4 5 6 7 8 Name VCC RESET CLOCK n/c GND n/c I/O n/c Description +5 VDC Reset Clock Not connected Ground Not connected In/Out Not connected Contributor: Joakim Ögren Source: Telecard/Smartcard Technical Spec & Info <http://www.N OT FO R RE DI ST RI -------------+------------| 1 | 5 | | | | +-------\ | /-------+ | 2 +----+ + 6 | | | | | +--------| |--------+ | 3 | | 7 | | +----+----+ | +-------/ | \-------+ | 4 | 8 | | | | -------------+------------- BU TIO N.ut.physic.fr> PR EL IM IN BETA RELEASE AR YB ET A Please send any comments to Joakim Ögren. . 274 SmartCard ISO 7816-2 .u-nancy.Chapter 1: Connector Menu SmartCard ISO 7816-2 Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.ee/~kalev/smartcar. (At the card) UNKNOWN CONNECTOR at the card. It may not be modified and re-distributed without the authors permission.

Pin 1 2 3 4 5 6 7 8 Name VCC R/W CLOCK RESET GND VPP I/O FUSE Description +5 VDC Read/Write Clock Reset Ground +21 VDC In/Out Fuse Contributor: Joakim Ögren Source: Telecard/Smartcard Technical Spec & Info <http://www. 275 SmartCard ISO .u-nancy.fr> Please send any comments to Joakim Ögren.ut.N SmartCard ISO 7816-2 OT FO R RE DI ST RI -------------+------------| 1 | 5 | | | | +-------\ | /-------+ | 2 +----+ + 6 | | | | | +--------| |--------+ | 3 | | 7 | | +----+----+ | +-------/ | \-------+ | 4 | 8 | | | | -------------+------------- BU TIO N. (At the card) UNKNOWN CONNECTOR at the card. It may not be modified and re-distributed without the authors permission.physic.ee/~kalev/smartcar.Chapter 1: Connector Menu SmartCard ISO Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN Pin 1 2 3 4 5 6 7 8 Name VCC RESET CLOCK n/c GND n/c I/O n/c Description +5 VDC Reset Clock Not connected Ground Not connected In/Out Not connected BETA RELEASE AR -------------+------------| 1 | 5 | | | | +-------\ | /-------+ | 2 +----+ + 6 | | | | | +--------| |--------+ | 3 | | 7 | | +----+----+ | +-------/ | \-------+ | 4 | 8 | | | | -------------+------------- YB ET A .txt> by Stephane Bausson <sbausson@ensem.

0-0. 21 PIN SCART MALE at the Cable.: 0.7 V Data 1: Data Out (Unavailable ??) RGB Red Ground Data Ground RGB Red In / Chrominance . It may not be modified and re-distributed without the authors permission. Signal Level <1k ohm >10k ohm RI (At the cable) BU TIO N.7 V 75 ohm SCART Imped ET A Audio/RGB switch / 16:9 RGB Green Ground Data 2: Clockpulse Out (Unavailable ??) RGB Green In 0.5 V rms 0.Chapter 1: Connector Menu SCART Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.5 V rms 0.3 V burst) 75 ohm 1-3 V=RGB.N OT FO AR YB 75 ohm 0.7 V (Chrom.5 V rms <1k ohm 0.4 V=Composite 75 ohm 1V 75 ohm 1V 75 ohm 17 VGND Composite Video Ground 18 BLNKGND Blanking Signal Ground 19 VOUT Composite Video Out 20 VIN Composite Video In / Luminance 21 SHIELD Contributor: Joakim Ögren PR EL IM IN 16 BLNK Blanking Signal Ground/Shield (Chassis) BETA RELEASE 276 . RE R DI 0.5 V rms >10k ohm 0. (At the video/TV) Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 AOR AIR AOL AGND B GND AIL B SWTCH G GND CLKOUT G DATA R GND DATAGND R Description Audio Out Right Audio In Right Audio Out Left + Mono Audio Ground RGB Blue Ground Audio In Left + Mono RGB Blue In ST 21 PIN SCART FEMALE at the Video/TV.

277 .N OT FO R RE DI ST RI BU TIO N. Video Demystified at Keith Jack's pages <http://www.mindspring. It may not be modified and re-distributed without the authors permission.com/~kjack1/scart. SCART Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Chapter 1: Connector Menu Source: Various sources.html> Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .

html> ST RI BU TIO N. PR EL IM IN BETA RELEASE AR YB ET A . 278 S-Video .Chapter 1: Connector Menu S-Video Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Pin 1 2 3 4 Name GND GND Y C Description Ground (Y) Ground (C) Intensity (Luminance) Color (Chrominance) Contributor: Joakim Ögren Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission.mindspring.N OT FO R RE DI Source: Video Demystified at Keith Jack's pages <http://www.com/~kjack1/svideo. (At the peripheral) 4 PIN MINI-DIN FEMALE at the peripheral.

elfa.N OT FO Contributor: Joakim Ögren R 1 1 1 4 4 4 Out L Out R Ground 2 1 4 2 3 5 2 1 4 2 3 5 2 3 5 2 3 5 2 2 RE DI ST RI BU TIO N. tuner Taperecorder Amplifier Taperecorder Amplifier Amplifier Receiver Microphone In L 3 3 In R 5 5 Source: ELFA <http://www. 279 DIN Audio . 5 PIN DIN 180° (DIN41524) MALE at the cable. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A . Peripheral Amplifier Amplifier Tuner Tuner Recordplayer Taperecorder Taperecorder Taperecorder Connected Pickup.se>'s catalog Nr 44 Please send any comments to Joakim Ögren. (At the peripheral) (At the cable) 5 PIN DIN 180° (DIN41524) FEMALE at the peripheral.Chapter 1: Connector Menu DIN Audio Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

5 mm MONO TELEPHONE MALE at the cable. PR EL IM IN BETA RELEASE AR YB ET A . 280 3.5 mm Mono Telephone plug .Chapter 1: Connector Menu 3.N OT FO R RE DI ST RI BU TIO N. (At the cable) 3. It may not be modified and re-distributed without the authors permission.5 mm Mono Telephone plug The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Name Description SIGNAL Signal GROUND Ground Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.

Contributor: Joakim Ögren. 281 3. (At the cable) 3.de> PR EL IM IN BETA RELEASE AR YB ET A . Name L R GROUND Source: ? Please send any comments to Joakim Ögren.N OT FO R RE DI ST Description Left Signal Right Signal Ground RI BU TIO N.htw-zittau.5 mm Stereo Telephone plug The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.5 mm STEREO TELEPHONE MALE at the cable.Chapter 1: Connector Menu 3. It may not be modified and re-distributed without the authors permission. Uwe Hartmann <uhartmann@i-stud.5 mm Stereo Telephone plug .

PR EL IM IN BETA RELEASE AR YB ET A .25 mm MONO TELEPHONE MALE at the cable. Name Description SIGNAL Signal GROUND Ground Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.25 mm Mono Telephone plug The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.25 mm Mono Telephone plug . It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu 6.N OT FO R RE DI ST RI BU TIO N. (At the cable) 6. 282 6.

(At the cable) 6.Chapter 1: Connector Menu 6. 283 6. Name L R GROUND Source: ? Please send any comments to Joakim Ögren.25 mm Stereo Telephone plug The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST Description Left Signal Right Signal Ground RI BU TIO N. Contributor: Joakim Ögren PR EL IM IN BETA RELEASE AR YB ET A .25 mm Stereo Telephone plug . It may not be modified and re-distributed without the authors permission.25 mm STEREO TELEPHONE MALE at the cable.

Scott Lindenthaler <scott@teraflop.25" peripherals.com>.edu>.Chapter 1: Connector Menu 5. (At the peripheral) UNKNOWN CONNECTOR at the powersupply cable.25" Power . 284 5. Pin 1 2 3 4 Name +12V GND GND +5V Color Yellow Black Black Red Source: ? Please send any comments to Joakim Ögren.N OT FO R Contributors: Joakim Ögren. Eric Sprigg <Eric_Sprigg@compuserve. UNKNOWN CONNECTOR at the peripheral. PR EL IM IN BETA RELEASE AR YB ET A .com> RE Description +12 VDC +12 V Ground (Same as +5 V Ground) +5 V Ground +5 VDC DI ST RI BU (At the powersupply cable) TIO N. Sven Gunnar Bilen <sbilen@umich. It may not be modified and re-distributed without the authors permission. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.25" Power Connector Used for harddisks & 5.

285 3. UNKNOWN CONNECTOR at the peripheral.N OT FO Source: ? R Contributor: Joakim Ögren RE Description +5 VDC +5 V Ground +12 V Ground (Same as +5 V Ground) +12 VDC DI ST RI BU (At the powersupply cable) TIO N. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu 3. (At the peripheral) UNKNOWN CONNECTOR at the powersupply cable. PR EL IM IN BETA RELEASE AR YB ET A .5" Power .5" Power Connector Used for floppies. Pin 1 2 3 4 Name +5V GND GND +12V Color Red Black Black Yellow Please send any comments to Joakim Ögren. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

Contributor: Joakim Ögren.N Description Ground Ground -5 VDC +5 VDC +5 VDC +5 VDC OT FO R Description Power Good. 286 Motherboard Power . RI BU TIO N. Product specification is PS-90331.net> Source: ? Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission. 2x MOLEX 90331-0001 CONNECTOR at the Powersupply cables. PR EL IM IN BETA RELEASE AR YB ET A . Bill Shepherd <contrav@usaor. +5 VDC (or n/c) +12 VDC -12 VDC Ground Ground RE DI ST 2x MOLEX 15-48-0106 CONNECTOR at the Computer. (At the Computer) (At the Powersupply cables) P8 Pin 1 2 3 4 5 6 Name PG +5V +12V -12V GND GND Color Orange Red Yellow Blue Black Black P9 Pin 1 2 3 4 5 6 Name GND GND -5V +5V +5V +5V Color Black Black White or Yellow Red Red Red Note: Pins part number is 08-50-0276.Chapter 1: Connector Menu Motherboard Power Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. +5 VDC when all voltages has stabilized.

N OT FO R RE DI ST RI BU TIO N. (At the computer) UNKNOWN CONNECTOR at the computer. PR EL IM IN BETA RELEASE AR YB ET A . Pin 1 2 3 Name +5V /HS +5V Description +5 VDC HighSpeed +5 VDC Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. 287 Turbo LED .Chapter 1: Connector Menu Turbo LED Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

Chapter 1: Connector Menu

AT Backup Battery Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the computer) UNKNOWN CONNECTOR at the computer. Pin 1 2 3 4 Name BATT+ key GND GND Description Battery+ Key Ground Ground

Contributor: Joakim Ögren Source: ?
Please send any comments to Joakim Ögren.

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288

AT Backup Battery

Chapter 1: Connector Menu

AT LED/Keylock Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the computer) UNKNOWN CONNECTOR at the computer. Pin 1 2 3 4 5 Name LED GND GND KS GND Description LED Power Ground Ground Key Switch Ground

Source: ?
Please send any comments to Joakim Ögren.

PR EL IM IN

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AT LED/Keylock

Chapter 1: Connector Menu

PC Speaker Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the computer) UNKNOWN CONNECTOR at the computer. Pin 1 2 3 4 Name -SP key GND +SP5V Description -Speaker Key Ground +Speaker +5 VDC

Contributor: Joakim Ögren Source: ?
Please send any comments to Joakim Ögren.

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PC Speaker

Chapter 1: Connector Menu

Motherboard IrDA Connector

For motherboards with a IrDA compliant Infrared Module connector.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

1 2 3 4 5 . . . . .

5 PIN IDC MALE at the motherboard. Pin 1 2 3 4 5 Name +5v n/c IRRX GND IRTX Description Power Not connected IR Module data received System GND IR Module data transmit

Contributor: Rob Gill <gillr@mailcity.com> Source: ASUS motherboard manual
Please send any comments to Joakim Ögren.

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Motherboard IrDA

Chapter 1: Connector Menu

Motherboard CPU Cooling fan Connector

1 2 3 . . .

3 PIN IDC MALE at the motherboard
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

Source: ASUS Motherboard Manual
Please send any comments to Joakim Ögren.

PR EL IM IN

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Motherboard CPU Cooling fan

Chapter 1: Connector Menu

Ethernet 10/100Base-T Connector

Same connector and pinout for both 10Base-T and 100Base-TX.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the network interface cards/hubs)

(At the cables)

Contributor: Joakim Ögren, Jeffrey R. Broido <broidoj@gti.net>

Please send any comments to Joakim Ögren.

PR EL IM IN

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Name TX+ TXRX+ n/c n/c RXn/c n/c

Description Tranceive Data+ Tranceive DataReceive Data+ Not connected Not connected Receive DataNot connected Not connected

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Ethernet 10/100Base-T

Chapter 1: Connector Menu

Ethernet 100Base-T4 Connector

100Base-T4 uses all four pairs. 100Base-TX only uses two pairs.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the network interface cards/hubs)

(At the cables)

Contributor: Joakim Ögren, Kim Scholte <KScholte@BigFoot.Com>

Please send any comments to Joakim Ögren.

PR EL IM IN

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Name TX_D1+ TX_D1RX_D2+ BI_D3+ BI_D3RX_D2BI_D4+ BI_D4-

Description Tranceive Data+ Tranceive DataReceive Data+ Bi-directional Data+ Bi-directional DataReceive DataBi-directional Data+ Bi-directional Data-

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Ethernet 100Base-T4

Chapter 1: Connector Menu

AUI Connector

Is the directions right???
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

15 PIN D-SUB FEMALE at the Ethernet card. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description control in circuit shield control in circuit A data out circuit A data in circuit shield data in circuit A voltage common ? control out circuit shield control in circuit B data out circuit B data out circuit shield data in circuit B voltage plus voltage shield ?

Source: Tommy's pinout Collection <http://csgrad.cs.vt.edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad.cs.vt.edu>
Please send any comments to Joakim Ögren.

PR EL IM IN

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AUI

Chapter 1: Connector Menu

Atari 2600 Cartridge Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

Top D3 D4 D5 D6 D7 A12 A10 A11 A9 A8 +5V SGND --1- --2- --3- --4- --5- --6- --7- --8- --9- -10- -11- -12GND D2 D1 D0 A0 A1 A2 A3 A4 A5 A6 A7 Bottom

UNKNOWN CONNECTOR at the Atari. Connect a 2716 or 2732/2532 EPROM.

* to inverter and back to 18 for chip select

Contributor: Joakim Ögren Source: Classic Atari 2600/5200/7800 Game Systems FAQ <http://www.dhp.com/~sloppy/files/classic/atari/atari.faq>
Please send any comments to Joakim Ögren.

PR EL IM IN

Pin 1 2 3 4 5 6 7 8 9 10 11 12

2716 Pin 1 2 3 4 5 6 7 8 9 10 11 n/c

CPU Name A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND

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Description Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Data 0 Data 1 Data 2 Ground

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2716 Pin 13 14 15 16 17 * 19 n/c 22 23 24 12

CPU Name D3 D4 D5 D6 D7 A12 A10 A11 A9 A8 +5V SGND

Description Data 3 Data 4 Data 5 Data 6 Data 7 Address 12 Address 10 Address 11 Address 9 Address 8 +5 VDC Shield Ground

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Atari 2600 Cartridge

Chapter 1: Connector Menu

Atari 5200 Cartridge Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the Atari) UNKNOWN CONNECTOR at the Atari. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name D0 D1 D2 D3 D4 D5 D6 D7 Enable 80-8F Enable 40-7F Not Connected Ground Ground Ground (System Clock 02 on 2 port) A6 A5 A2 Interlock A0 A1 A3 A4 Ground Ground (Video In on 2 port) Ground +5 VDC A7 Not Connected A8 Audio In (2 port) A9 A13 A10 A12 A11 Interlock

Contributor: Joakim Ögren Source: Classic Atari 2600/5200/7800 Game Systems FAQ <http://www.dhp.com/~sloppy/files/classic/atari/atari.faq>
Please send any comments to Joakim Ögren.

PR EL IM IN

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Atari 5200 Cartridge

Chapter 1: Connector Menu

Atari 5200 Expansion Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the Atari) UNKNOWN CONNECTOR at the Atari. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name +5 VDC Audio Out (2 port) Ground R/W Early Enable E0-EF D6 D4 D2 D0 IRQ Ground Serial Data In Serial In Clock Serial Out Clock Serial Data Out Audio In A14 System Clock 01 A11 A7 A6 A5 A4 A3 A2 A1 A0 Ground D1 D3 D5 D7 Not connected Ground Not connected +5 VDC

Contributor: Joakim Ögren Source: Classic Atari 2600/5200/7800 Game Systems FAQ <http://www.dhp.com/~sloppy/files/classic/atari/atari.faq>
Please send any comments to Joakim Ögren.

PR EL IM IN

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Atari 5200 Expansion

Chapter 1: Connector Menu

Atari 7800 Cartridge Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the Atari) UNKNOWN CONNECTOR at the Atari. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name R/W HALT D3 D4 D5 D6 D7 A12 A10 A11 A9 A8 +5V GND A13 A14 A15 EAUDIO A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 Gnd IRQ CLK2 Description Read/Write Halt Data 3 Data 4 Data 5 Data 6 Data 7 Address 12 Address 10 Address 11 Address 9 Address 8 +5 VDC Ground Address 13 Address 14 Address 15 EAudio ??? Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Data 0 Data 1 Data 2 Gnd Interrupt Clock 2 ???

Contributor: Joakim Ögren

Please send any comments to Joakim Ögren.

PR EL IM IN

Source: Classic Atari 2600/5200/7800 Game Systems FAQ <http://www.dhp.com/~sloppy/files/classic/atari/atari.faq>

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Atari 7800 Cartridge

Chapter 1: Connector Menu

Atari 7800 Expansion Connector

Gnd +5v CVideo MLum0 Mlum3 Blank OscDis ExtMen Gnd --1-- --2-- --3-- --4-- --5-- --6-- --7-- ---8-- --9-The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

-18-- -17-Gnd Audio

-16-- -15-- -14-- -13-- -12-- --11-- -10-Rdy MCol MLum2 MLum1 Msync Clk2 ExtOsc

UNKNOWN CONNECTOR at the Atari. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Name GND +5V CVIDEO MLUM0 MLUM3 BLANK OSCDIS EXTMEN GND EXTOSC CLK2 MSYNC MLUM1 MLUM2 MCOL RDY AUDIO GND Description Ground +5 VDC Input to RF modulator (Video+Audio) Maria Luminance Bit 0 Maria Luminance Bit 3 Blanking output Disable 14.31818 MHz Master Clock External Maria Enable Input Ground External clock to replace Master Clock Phase 2 Clock from the 6502 Maria Composite Sync Maria Luminance Bit 1 Maria Luminance Bit 2 Maria Color Phase Angle Input to the 6502 Audio Ground

Source: Classic Atari 2600/5200/7800 Game Systems FAQ <http://www.dhp.com/~sloppy/files/classic/atari/atari.faq>, Pinout by Harry Dodgson
Please send any comments to Joakim Ögren.

PR EL IM IN

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Atari 7800 Expansion

Chapter 1: Connector Menu

Atari Cartridge Port Connector

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

(At the Computer)

Contributor: Joakim Ögren, Lawrence Wright <lwright@silk.net>, Steve & Sally Blair <blair@mailbox.uq.edu.au>

PR EL IM IN

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Name +5V +5V D14 D15 D12 D13 D10 D11 D8 D9 D6 D7 D4 D5 D2 D3 D0 D1 A13 A15 A8 A14 A7 A9 A6 A10 A5 A12 A11 A4 RS3 A3 RS4 A2 UDS A1 LDS GND GND GND

Description +5 VDC +5 VDC Data 14 Data 15 Data 12 Data 13 Data 10 Data 11 Data 8 Data 9 Data 6 Data 7 Data 4 Data 5 Data 2 Data 3 Data 0 Data 1 Address 13 Address 15 Address 8 Address 14 Address 7 Address 9 Address 6 Address 10 Address 5 Address 12 Address 11 Address 4 ROM Select 3 Address 3 ROM Select 4 Address 2 Upper Data Strobe Address 1 Lower Data Strobe Ground Ground Ground

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Atari Cartridge Port

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

Source: ?

Please send any comments to Joakim Ögren.

PR EL IM IN YB ET A .N OT FO R RE DI

Chapter 1: Connector Menu

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Chapter 1: Connector Menu

GameBoy Cartridge Connector

Available on the Nintendo GameBoy.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.

UNKNOWN CONNECTOR at the GameBoy. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name VCC ? /RESET /WR ? A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 /CS D0 D1 D2 D3 D4 D5 D6 D7 /RD ? GND

Contributor: Joakim Ögren

Source: Nintendo GameBoy FAQ <http://www.freeflight.com/fms/stuff/gameboy.faq>, Pinout by Peter Knight & Josef Mollers
Please send any comments to Joakim Ögren.

PR EL IM IN

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Description +5 VDC ? Connected on Gameboy, but not used on GamePaks. Reset Write ? Used by paging PAL on high capacity GamePaks. Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Address 8 Address 9 Address 10 Address 11 Address 12 Address 13 Address 14 Chip Select Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Read ? Connected on Gameboy, but not used on Game-Paks. Ground

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GameBoy Cartridge

N OT FO R RE DI ST RI BU 49 47 45 5 3 1 +---------//-----+ | H H H //H H H | | ======//====== | | H H H// H H H | +-----//---------+ 50 48 46 6 4 2 TIO N. 304 MSX Expansion . NC. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Name Dir /CS1 /CS2 /CS12 /SLTSL n/c /RFSH /WAIT /INT /M1 /BUSDIR /IORQ /MREQ /WR /RD /RESET n/c A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 GND CLOCK GND Description Memory Read in addresses 4000-7FFF Memory Read in addresses 8000-BFFF Memory Read in addresses 4000-BFFF Low when Slot 2 (cartridge slot) is selected Not connected. Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Address 8 Address 9 Address 10 Address 11 Address 12 Address 13 Address 14 Address 15 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Ground CPU clock. Tells CPU to wait.579 MHz Ground PR EL IM IN BETA RELEASE AR YB ET A . Refresh signal is not maintained OC. Refresh signal from CPU OC. (At the Computer) 50 PIN ?? at the Computer. (Address=Address) Write signal (strobe) Read signal (strobe) Reset Not connected. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu MSX Expansion Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (Address=Port) Memory request signal. 3. I/O request signal. was used to control the data direction. Requests a interrupt to CPU (call to addr 38h) CPU fetches first part of instruction from memory.

305 NC.Chapter 1: Connector Menu 44 45 46 47 48 49 50 SW1 +5V SW2 +5V +12V SOUNDIN -12V MSX Expansion Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Insert/remove detection for protection +5 VDC (300mA max /slot) +12 VDC (50mA max /slot) Sound input (-5dBm) -12 VDC (50mA max /slot) .txt> BU Note: Direction is Computer relative Peripheral. PR EL IM IN BETA RELEASE AR YB ET A .com/fms/MSX/Portar.freeflight. Contributor: Joakim Ögren Please send any comments to Joakim Ögren. Insert/remove detection for protection +5 VDC (300mA max /slot) NC. TIO N.N OT FO R RE DI ST RI Source: Mayer's SV738 X'press I/O map <http://www. It may not be modified and re-distributed without the authors permission.

$07ff) RAM 2 (Memory location $0800 .$7fff) BLK 5 (Memory location $a000 .Chapter 1: Connector Menu Vic 20 Memory Expansion Connector Available on Commodore Vic 20 computers. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 306 Vic 20 Memory Expansion .$bfff) RAM 1 (Memory location $0400 .$0bff) RAM 3 (Memory location $0c00 . starting at $9130 Decoded I/O block 3. 0=W) 6502 Interrupt Request Not connected +5 VDC PR EL IM IN BETA RELEASE AR YB ET A .$3fff) BLK 2 (Memory location $4000 .$5fff) BLK 3 (Memory location $6000 . 0=W) Read/Write from CPU (1=R. (At the Computer) UNKNOWN CONNECTOR at the Computer. It may not be modified and re-distributed without the authors permission.$0fff) Read/Write from Vic chip (1=R. On the left side. starting at $9140 Phase 2 System Clock Non maskable Interrupt 6502 Reset Not connected Ground Ground Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 BLK 1 (Memory location $2000 . Pin A B C D E F H J K L M N P R S T U V W X Y Z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Name GND CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 CA10 CA11 CA12 CA13 I/O 2 I/O 3 S02 /NMI /RESET n/c GND GND CD0 CD1 CD2 CD3 CD4 CD5 CD6 CD7 /BLK 1 /BLK 2 /BLK 3 /BLK 5 RAM 1 RAM 2 RAM 3 V R/W C R/W /IRQ n/c +5V Description Ground Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Address 8 Address 9 Address 10 Address 11 Address 12 Address 13 Decoded I/O block 2.N OT FO R RE DI ST RI BU 1 TOP 22 +-------------------//----------------+ | =================//================ | +-----------------//------------------+ A BOTTOM Z TIO N.

and Howard W.uwaterloo. PR EL IM IN BETA RELEASE AR YB ET A . 1992. Machines.com> Sources: "The Vic Revealed" by Nick Hampshire. Commodore Business. Inc. Sources: "Vic20 Programmer's Reference Guide". 307 . Sources: Inside your Vic 20 <http://ccnga.Chapter 1: Connector Menu 22 GND Ground Contributor: Joakim Ögren Vic 20 Memory Expansion Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Inc. Sams & Company.txt> by Ward Shrake <wardshrake@aol.ca/pub/cbm/vic-20/cartgrab. Hayden Book Co. Inc. It may not be modified and re-distributed without the authors permission. TIO N.N OT FO R RE DI ST RI BU Please send any comments to Joakim Ögren. 1982.

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A B C D E F H J K L M N P R S T U V W X Y Z Name GND +5V +5V /IRQ /CR/W DOTCLK I/O 1 /GAME /EXROM I/O 2 /ROML BA /DMA CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 GND GND /ROMH /RESET /NMI S02 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 GND Description Ground +5 Volts DC +5 Volts DC Interrupt Request Dot Clock Game ROM Low Cartridge Data 7 Cartridge Data 7 Cartridge Data 7 Cartridge Data 7 Cartridge Data 7 Cartridge Data 7 Cartridge Data 7 Cartridge Data 7 Ground Contributor: Joakim Ögren. (At the computer) 44 PIN FEMALE EDGE at the computer.N OT FO R RE DI ST RI BU TIO N.nl> Source: Commodore 64 Programmer's Reference Guide Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu C64 Cartridge Expansion Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 308 C64 Cartridge Expansion . PR EL IM IN Cartridge Address 15 Cartridge Address 14 Cartridge Address 13 Cartridge Address 12 Cartridge Address 11 Cartridge Address 10 Cartridge Address 9 Cartridge Address 8 Cartridge Address 7 Cartridge Address 6 Cartridge Address 5 Cartridge Address 4 Cartridge Address 3 Cartridge Address 2 Cartridge Address 1 Cartridge Address 0 Ground BETA RELEASE AR YB ET A Ground ROM High Reset Non Maskable Interrupt . Arwin Vosselman <0vosselman01@flnet.

It may not be modified and re-distributed without the authors permission. 309 .The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN YB ET A .N OT FO R RE DI Chapter 1: Connector Menu AR BETA RELEASE ST RI BU C64 Cartridge Expansion Connector TIO N.

Jestin Nesselroad Please send any comments to Joakim Ögren. (At the computer) 24 PIN MALE EDGE (DZM 12 DREH) at the computer. PR EL IM IN BETA RELEASE AR YB Source: Commodore 64 Programmer's Reference Guide ET A .phase) (100 mA max) Ground Ground Flag 2 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 PA2 Ground Contributor: Joakim Ögren.N OT FO R RE DI ST RI BU TIO N. 310 C64 User Port . Also a reset output for devices. Pin 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F H J K L M N Name GND +5V /RESET CNT1 SP1 CNT2 SP2 /PC2 ATN +9V AC +9V AC GND GND /FLAG2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA2 GND Description Ground +5 VDC (100 mA max) Reset. from CIA #2 Serial Port 2.se>. Nikolas Engström <nikolas. from CIA #2 Serial Attention In +9 VAC (+ phase) (100 mA max) +9 VAC (.landskrona. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu C64 User Port Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.engstrom@pop. from CIA #1 Serial Port 1. from CIA #1 Counter 2. Arwin Vosselman <0vosselman01@flnet. will force a Cold Start.nl>. Counter 1. from CIA #2 Handshaking line.

Chapter 1: Connector Menu C128 Expansion Bus Connector Available at the Commodore 128. 44 PIN FEMALE EDGE at the computer. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.18MHz Video Dot Clock I/O Chip select $de00-deff Sensed for memory map configuration Sensed for memory map configuration I/O Chip select $df00-dfff External ROM select $8000-Bfff Bus available output Direct memory access input Data bit 7 Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 System Ground System Ground External ROM Select $c000-ffff System Reset Signal Non-Maskable Interrupt System 1MHz clock Translated address bit 15 Translated address bit 14 Translated address bit 13 Translated address bit 12 Translated address bit 11 Translated address bit 10 Translated address bit 9 Translated address bit 8 Shared address bit 7 Shared address bit 6 Shared address bit 5 Shared address bit 4 Shared address bit 3 Shared address bit 2 Shared address bit 1 Shared address bit 0 System Ground Contributor: Rob Gill <gillr@mailcity. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A B C D E F H J K L M N P R S T U V W X Y Z Name GND +5V +5V /IRQ R/W DClock I/O1 /GAME /EXROM I/O2 /ROML BA /DMA D7 D6 D5 D4 D3 D2 D1 D0 GND GND /ROMH /RESET /NMI 1MHz TA15 TA14 TA13 TA12 TA11 TA10 TA9 TA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 GND Description System Ground System Vcc System Vcc Interrupt request System Read/Write Signal 8.N OT FO R RE DI ST RI BU (At the computer) TIO N. 311 C128 Expansion Bus .com> PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission.

PR EL IM IN YB ET A . AR BETA RELEASE ST RI BU C128 Expansion Bus Connector TIO N. It may not be modified and re-distributed without the authors permission.The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 312 .N OT FO R RE DI Chapter 1: Connector Menu Source: Commodore 128 Programmers reference guide. Please send any comments to Joakim Ögren.

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A B C D E F H J K L M N P R S T U V W X Y Z Name GND +5V +5V /IRQ R/W C1HIGH C2LOW C2HIGH /CS1 /CS0 /CAS MUX BA D7 D6 D5 D4 D3 D2 D1 D0 AEC EAI PHI 2 GND GND C1LOW /RESET /RAS PHI 0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 n/c Description Ground +5 VDC +5 VDC Interrupt Read/Write (1=Read. 313 C16/C116/+4 Expansion Bus .Chapter 1: Connector Menu C16/+4 Expansion Bus Connector Available on Commodore C16. 50 PIN FEMALE EDGE (2 mm pitch) at the Computer. C116 and +4 computers. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 0=Write) External Cartridge Chip Selects C1 High External Cartridge Chip Selects C2 Low (reserved) External Cartridge Chip Selects C2 High (reserved) Chip Select Line 1 Chip Select Line 0 Column Address Strobe DRAM address multiplex control signal Bus Available (Low=DMA) Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 Address Enable Code External Audio In Artificial Phi 2 signal Ground Ground External Cartridge Chip Selects C1 Low Reset Row Address Strobe Artificial Phi 0 Signal Address 15 Address 14 Address 13 Address 12 Address 11 Address 10 Address 9 Address 8 Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Not connected PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU (At the Computer) TIO N.

Pinout specs for cbm machines needed <http://www.vuse.sys. Arwin Vosselman <0vosselman01@flnet.cbm.Chapter 1: Connector Menu AA n/c BB n/c CC GND Not connected Not connected Ground C16/+4 Expansion Bus Connector PHI 2: Address valid on the rising edge. Sources: Article in C'T September 1986.txt> by Lonnie McClure <lmcclure@delphi.com> Sources: SAMS Computerfacts CC8 Commodore 16. Contributor: Joakim Ögren.N OT FO R RE DI ST RI BU Sources: Usenet posting in comp. TIO N. data valid on the falling edge The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.nl> Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission. 314 .edu/~thompsbb/cbm_conn.vanderbilt.

Pinout specs for cbm machines needed <http://www. UNKNOWN CONNECTOR at the Computer. ET A . Arwin Vosselman <0vosselman01@flnet. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu +4 User Port Connector Available on Commodore +4 computer. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 315 +4 User Port .sys.edu/~thompsbb/cbm_conn.vuse.nl> Please send any comments to Joakim Ögren.vanderbilt. Pin 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H I J K L Name GND +5V /BRESET P2/CSE P3 P4 P5 RxC ATN +9V +9V GND GND P0 RxD RTS DTR P7 DCD P6 CTS DSR TxD GND Description Ground +5 VDC ? Data 2/Cassette Sense Data 3 Data 4 Data 5 Receive Clock Attention? +9 VAC +9 VAC Ground Ground Data 0 Receive Data Request to Send Data Terminal Ready Data 7 Data Carrier Detect Data 6 Clear to Send Data Set Ready Transmit Data Ground Contributor: Joakim Ögren.cbm. PR EL IM IN BETA RELEASE AR YB Sources: Usenet posting in comp.txt> by Lonnie McClure <lmcclure@delphi.com> Sources: SAMS Computerfacts CC8 Commodore 16.N OT FO R RE DI ST RI BU (At the Computer) TIO N.

16 MHz CDAC clock (90° before system clock) 3. 316 CDTV Diagnostic Slot .Chapter 1: Connector Menu CDTV Diagnostic Slot Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.58 MHz CCKQ clock (C3) 7. (At the computer) 80 PIN ??? CONNECTOR at the computer. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Name GND GND VCC VCC /CFGOUT /CFGIN GND CCKQ CDAC CCK /OVR XRDY /INT2 n/c A5 /INT6 A6 A4 GND A3 A2 A7 A1 A8 /FC0 A9 /FC1 A10 /FC2 A11 GND A12 A13 /IPL0 A14 /IPL1 A15 /IPL2 A16 /BERR A17 /VPA GND E /VMA A18 /RST A19 /HLT Description Ground Ground +5 VDC +5 VDC Configout AutoConfig signal (not connected) Configin AutoConfig signal (grounded) Ground 3. It may not be modified and re-distributed without the authors permission.58 MHz CCK clock (C1) Override (Disables /DTACK generation of Gary) External Ready (Generates wait states while low). Level 2 Interrupt not connected Address Bus 5 Level 6 Interrupt Address Bus 6 Address Bus 4 Ground Address Bus 3 Address Bus 2 Address Bus 7 Address Bus 1 Address Bus 8 Processor Function Code Status (bit 0) Address Bus 9 Processor Function Code Status (bit 1) Address Bus 10 Processor Function Code Status (bit 2) Address Bus 11 Ground Address Bus 12 Address Bus 13 Interrupt Priority Level (bit 0) Address Bus 14 Interrupt Priority Level (bit 1) Address Bus 15 Interrupt Priority Level (bit 2) Address Bus 16 Bus Error Address Bus 17 Valid Peripheral Address (asserted by Gary) Ground E Clock Valid Memory Address (asserted by Gary) Address Bus 18 Reset Address Bus 19 Halt PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI ST RI BU TIO N.

ca/~ewaniu/cdtv/cdtv-technical. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A Contributor: Joakim Ögren . OT Address Bus 20 Address Bus 22 Address Bus 21 Address Bus 23 Bus Request Ground Bus Grant Acknowledge Data Bus 15 Bus Grant Data Bus 14 Data Transfer Acknowledge (normally asserted by Gary) Data Bus 13 Read/Write (high=read. 317 .ualberta.N Note: Pin 7-80 is equivalent with the Amiga 500's pin 13-86 at the 86 pin Amiga 500 connector.Chapter 1: Connector Menu 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 A20 A22 A21 A23 /BR GND /BGACK D15 /BG D14 /DTACK D13 R/W D12 /LDS D11 /UDS GND /AS D0 D10 D1 D9 D2 D8 D3 D7 D4 D6 GND D5 CDTV Diagnostic Slot Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.ee. low=write) Data Bus 12 Lower Data Strobe Data Bus 11 Upper Data Strobe Ground Address Strobe Data Bus 0 Data Bus 10 Data Bus 1 Data Bus 9 Data Bus 2 Data Bus 8 Data Bus 3 Data Bus 7 Data Bus 4 Data Bus 6 Ground Data Bus 5 FO R RE DI ST RI BU TIO N. Source: Darren Ewaniuk's CDTV Technical Information <http://nyquist.html> Please send any comments to Joakim Ögren.

318 CDTV Expansion Slot .html> Please send any comments to Joakim Ögren.N OT FO R RE DI ST RI BU TIO N. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Name GND GND VCC VCC SD1 SD0 SD3 SD2 SD5 SD4 SD7 SD6 /SDREQ /INTX /CSS /SDACK /IOR /IOW A8 7M A6 A7 A4 A5 A2 A3 /IFRST A1 GND GND Description Ground Ground +5 VDC +5 VDC Data Bus 1 Data Bus 0 Data Bus 3 Data Bus 2 Data Bus 5 Data Bus 4 Data Bus 7 Data Bus 6 DMA Request Interrupt Request Chip Select DMA Acknowledge I/O Read I/O Write Address Bus 8 7.ca/~ewaniu/cdtv/cdtv-technical. 2 4 6 8 10 12 -.--.ualberta.Chapter 1: Connector Menu CDTV Expansion Slot Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.-.-.-1 3 5 7 9 11 14 --13 16 --15 18 --17 20 --19 22 --21 24 --24 26 --25 28 --27 30 --29 (At the computer) 30 PIN ??? CONNECTOR at the computer.ee. It may not be modified and re-distributed without the authors permission.-.-.-.-.16 MHz System Clock Address Bus 6 Address Bus 7 Address Bus 4 Address Bus 5 Address Bus 2 Address Bus 3 +5 VDC Address Bus 1 Ground Ground Contributor: Joakim Ögren Source: Darren Ewaniuk's CDTV Technical Information <http://nyquist. PR EL IM IN BETA RELEASE AR YB ET A .-.-.

Contributor: Joakim Ögren Source: Video Games FAQ (Part 3) <http://www.uk/internet/news/faq/archive/games.video-games.faq. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. UNKNOWN CONNECTOR at the PC Engine. PR EL IM IN +5 VDC BETA RELEASE AR YB ET A .Chapter 1: Connector Menu PC-Engine Cartridge Connector Available on the PC Engine. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Name ? ? A18? A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND D3 D4 D5 D6 D7 /CE A10 /OE A11 A9 A8 A13 A14 A17 A19? R/W ? ? ? +5V Description Address 18 Address 16 Address 15 Address 12 Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Data 0 Data 1 Data 2 Ground Data 3 Data 4 Data 5 Data 6 Data 7 Chip Select Address 10 Output Enable Address 11 Address 9 Address 8 Address 13 Address 14 Address 17 Address 19 Read/Write Pin 1 is the short pin on the left (if the card is to inserted forwards) Pin 38 is the long pin on the right.com> Please send any comments to Joakim Ögren.ox. 319 PC-Engine Cartridge . It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU (At the PC Engine) TIO N.part3.lib. Pinout by David Shadoff <daves@interlog.html>.ac.

Chapter 1: Connector Menu SNES Cartridge Connector Available on the Nintendo SNES. +-------------------------------//----------------------------+ | 32 33 34 35 | 36 37 38 39 40 //53 55 56 57 58 | 59 60 61 62 | | 01 02 03 04 | 05 06 07 08 09// 22 24 25 26 27 | 28 29 30 31 | +----------------------------//-------------------------------+ (At the SNES) UNKNOWN CONNECTOR at the SNES. SNES Cartridge . It may not be modified and re-distributed without the authors permission. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name Description PR EL IM IN GND A12 A13 A14 A15 A16 A17 A18 A19 BETA RELEASE AR GND A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 /IRQ D0 D1 D2 D3 /READ CIC CIC /RAM ENABLE VCC Ground Address 11 Address 10 Address 9 Address 8 Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Interrupt Data 0 Data 1 Data 2 Data 3 Read ? ? RAM Enable +5 VDC YB Ground Address 12 Address 13 Address 14 Address 15 Address 16 Address 17 Address 18 Address 19 320 ET A . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST RI BU TIO N.

N OT FO R RE Contributor: Joakim Ögren DI ST RI BU TIO N. 321 .uk/internet/news/faq/archive/games.Chapter 1: Connector Menu 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 A20 A21 A22 A23 /ROM ENABLE D4 D5 D6 D7 /WRITE CIC CIC n/c VCC Address 20 Address 21 Address 22 Address 23 ROM Enable Data 4 Data 5 Data 6 Data 7 Write ? ? Not connected +5 VDC SNES Cartridge Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.ox.ac.faq.html>. PR EL IM IN BETA RELEASE AR YB ET A .de> Please send any comments to Joakim Ögren.part3.lib. Source: Video Games FAQ (Part 3) <http://www.video-games. Pinout by Thomas Rolfes <rolfes@uni-muenster.

It may not be modified and re-distributed without the authors permission.ac.Chapter 1: Connector Menu TG-16 Cartridge Connector Available on the TG-16. Contributor: Joakim Ögren Source: Video Games FAQ (Part 3) <http://www.com> Please send any comments to Joakim Ögren.N OT FO R RE DI ST RI BU (At the TG-16) TIO N. 322 TG-16 Cartridge . UNKNOWN CONNECTOR at the TG-16.faq.video-games.html>.part3.lib. Pinout by David Shadoff <daves@interlog.ox. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Name ? ? A18? A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 GND D4 D3 D2 D1 D0 /CE A10 /OE A11 A9 A8 A13 A14 A17 A19? R/W ? ? ? +5V Description Address 18 Address 16 Address 15 Address 12 Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Data 7 Data 6 Data 5 Ground Data 4 Data 3 Data 2 Data 1 Data 0 Chip Select Address 10 Output Enable Address 11 Address 9 Address 8 Address 13 Address 14 Address 17 Address 19 Read/Write Pin 1 is the short pin on the left (if the card is to inserted forwards) Pin 38 is the long pin on the right. PR EL IM IN +5 VDC BETA RELEASE AR YB ET A .uk/internet/news/faq/archive/games.

Chapter 1: Connector Menu ZX Spectrum AY-3-8912 Connector Can be found at Sinclair ZX Spectrum's.ox.uk/~uzdm0006/Damien/speccy/pinouts. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name SOUND C PORT VCC SOUND B SOUND A GND PORT PORT PORT PORT PORT PORT PORT CLOCK CLOCK RESET A8 BDIR BC2 BC1 D7 D6 D5 D4 D3 D2 D1 D0 Description Sound C (Can be tied together with A & B) ? +5 VDC Sound B (Can be tied together with A & C) Sound A (Can be tied together with B & C) Ground ? ? ? ? ? ? ? ? ? Reset Address 8? ? ? ? Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 Contributor: Joakim Ögren Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR Source: ZX Spectrum FAQ <http://users. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU (At the computer) TIO N. 323 ZX Spectrum AY-3-8912 . I think The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.ac. UNKNOWN CONNECTOR at the computer.html> YB ET A .

PR EL IM IN Write Read Write Enable Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Interrupt +5 VDC (One of the +5V is decoupled through a RC-low-pass. UNKNOWN CONNECTOR at the computer. save and load.ox. Data 0 Keyboard Data 0 Keyboard Data 1 Data 1 Data 2 Keyboard Data 2 Keyboard Data 3 Data 3 Keyboard Data 4 Data 4 Analog-I/O-line for beep.html> Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu ZX Spectrum ULA Connector Can be found at Sinclair ZX Spectrum's. (A0(CPU) OR /IORQ) for the I/O-port FEh ROM ChipSelect Row Address Strobe Address 14 Address 15 ??? The 14 MHz crystal. Color-difference signals. Other side grounded through capacitor.) +5 VDC (One of the +5V is decoupled through a RC-low-pass.ac. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name /WR /RD /WE A0 A1 A2 A3 A4 A5 A6 /INT +5V +5V U V /Y D0 T0 T1 D1 D2 T2 T3 D3 T4 D4 SOUND D5 D6 D7 CLOCK /IO-ULA /ROM CS /RAS A14 A15 /MREQ Q Description Contributor: Joakim Ögren Source: ZX Spectrum FAQ <http://users.N OT FO R RE DI ST RI BU (At the computer) TIO N.uk/~uzdm0006/Damien/speccy/pinouts. BETA RELEASE AR YB ET A . Inverted Video+Sync. Data 5 Data 6 Data 7 The clock-source to the CPU including the inhibited T-states.) Color-difference signals. I think The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 324 ZX Spectrum ULA .

N OT FO R RE DI ST RI BU TIO N. 325 Spectravideo SVI318/328 Expansion Bus . 300mA Game adapter control signal Power. 100mA Power.58MHz system clock Buffered Address bus " " " " " " " " " " " " " " " RAM expansion refresh Video-CPU write select Z80 M1 CPU-Video write select Z80 WR Z80 MREQ Z80 IORQ Z80 RD Buffered Data Bus " " " " " " " Audio input signal Z80 INT Disable user RAM Disable basic ROM Enable bank 32 Memory (8000-ffff) Enable bank 31 Memory (0000-7FFF) Enable bank 22 Memory (8000-FFFF) Enable bank 21 Memory (0000-7FFF) System Ground PR EL IM IN I/O I/O I/O I/O I/O I/O I/O I/O - BETA RELEASE AR YB ET A . Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Name +5v /CNTRL2 +12v -12v /CNTRL1 /WAIT /RST CPU CLK A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 /RFSH /EXCSR /M1 /EXCSW /WR /MREQ /IORQ /RD D0 D1 D2 D3 D4 D5 D6 D7 CSOUND /INT /RAMDIS /ROMDIS /BK32 /BK31 /BK22 /BK21 GND Dir Description Power. It may not be modified and re-distributed without the authors permission. 50mA Game adapter control signal Z80 WAIT Z80 RST Buffered 3.Chapter 1: Connector Menu Spectravideo SVI318/328 Expansion Bus Con The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (At the computer) 50 PIN MALE EDGE the computer.

326 . PR EL IM IN BETA RELEASE AR YB ET A .com> Source: SVI 328 Mk II User Manual Please send any comments to Joakim Ögren.N OT FO R RE DI ST RI BU TIO N.Chapter 1: Connector Menu 50 GND System Ground Contributor: Rob Gill <gillr@mailcity. It may not be modified and re-distributed without the authors permission. Spectravideo SVI318/328 Expansion Bus Con The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

Chapter 1: Connector Menu Spectravideo SVI318/328 Game Cartridge Co The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR Source: SVI 328 mk II user manual YB ET A . (At the computer) 30 PIN FEMALE EDGE at the computer.N OT FO R RE DI ST RI BU TIO N.com> Please send any comments to Joakim Ögren. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Name +5v +5v A7 A12 A6 A13 A5 A8 A4 A9 A3 A11 A10 A2 A0 A1 D0 D7 D1 D6 D2 D5 D3 D4 CCS3 CCS4 CCS1 CCS2 GND GND Contributor: Rob Gill <gillr@mailcity. It may not be modified and re-distributed without the authors permission. 327 Spectravideo SVI318/328 Game Cartridge .

328 MIDI Out .N OT FO R RE DI ST RI BU (At the peripheral) TIO N. (At the cable) 5 PIN DIN 180° (DIN41524) FEMALE at the peripheral. 5 PIN DIN 180° (DIN41524) MALE at the cable.Chapter 1: Connector Menu MIDI Out Connector MIDI=Musical Instrument Digital Interface. PR EL IM IN BETA RELEASE AR YB ET A . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. Pin 1 2 3 4 5 Name n/c GND n/c CSINK CSRC Description Not connected Ground Not connected Current Sink Current Source Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.

Pin 1 2 3 4 5 Name n/c n/c n/c CSRC CSINK Description Not connected Not connected Not connected Current Source Current Sink Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.Chapter 1: Connector Menu MIDI In Connector MIDI=Musical Instrument Digital Interface. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI ST RI BU (At the peripheral) TIO N. 329 MIDI In . (At the cable) 5 PIN DIN 180° (DIN41524) FEMALE at the peripheral. It may not be modified and re-distributed without the authors permission. 5 PIN DIN 180° (DIN41524) MALE at the cable.

edu> FO Pins 2 and 5 are connected to Common when they are true. Pin 1 2 3 4 5 6 7 8 9 Contributor: Joakim Ögren Please send any comments to Joakim Ögren.cs. On pin 8. 330 Minuteman UPS . shorting to ground will shutdown.Chapter 1: Connector Menu Minuteman UPS Connector Is the directions right??? The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. when running off the battery.vt. 9 PIN D-SUB ??? at the UPS.edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad.N OT Source: Tommy's pinout Collection <http://csgrad. PR EL IM IN BETA RELEASE AR YB ET A . R RE Description Unused Battery power Unused Common (same as 7) Low battery RS-232 level shutdown Common (same as 4) Ground level shutdown (A500 and above. reserved on <A500) Reserved DI ST RI BU (At the UPS) TIO N. On pin 6. an rs-232 high level (>9V) will shutdown.cs. It may not be modified and re-distributed without the authors permission.vt.

PR EL IM IN BETA RELEASE AR YB ET A . 7 PIN DIN 'O' FEMALE at the computer. It may not be modified and re-distributed without the authors permission.Chapter 1: Connector Menu C64 Power Supply Connector Available at the Commodore 64. 331 C64 Power Supply . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST RI BU (At the computer) TIO N.com> Source: Commodore 64 Programmers Reference Guide Please send any comments to Joakim Ögren. Pin 1 2 3 4 5 6 7 Name Shield Ground Shield Ground Shield Ground nc +5v In 9Vac in 9Vac in Contributor: Rob Gill <gillr@mailcity.

RI (At the cable) BU TIO N. (At the computer) Contributor: Joakim Ögren.N OT FO R RE Pin L R GND Description Left Channel Right Channel Ground DI ST 3.5 mm STEREO TELEPHONE MALE at the cable.diron. 3. PR EL IM IN BETA RELEASE AR YB ET A .co.Chapter 1: Connector Menu Amstrad CPC6128 Stereo Connector The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Agnello Guarracino <aggy@ooh.uk> Source: Amstrad CPC6128 User Instructions Manual Please send any comments to Joakim Ögren.5 mm STEREO TELEPHONE FEMALE at the computer. 332 Amstrad CPC6128 Stereo . It may not be modified and re-distributed without the authors permission.

Serial (PC 25) .(Technical) . but the most common connectors.Parallel (PC) .(Technical) .Keyboard (6 PC) Data storage interfaces: .SCSI Internal PR EL IM IN .(Technical) FO R Buses: RE This is not exactly 10 entries.Amiga Video Joystick/Mouse: Diskdrive: Keyboard: .PCI .Gameport (PC) .VGA (9) .Serial (PC 9) .The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. If you don't find what you are searching for here.Internal Diskdrive . It may not be modified and re-distributed without the authors permission. In/Out: Video: . 333 .VGA (15) . Chapter 2 ST Connector Top 10 Menu What does the information that is listed for each connector mean? See the tutorial.Mouse/Joy (Amiga) BETA RELEASE AR YB ET A .ISA . DI RI BU TIO N.(Technical) . look at the full list.Keyboard (5 PC) .N OT .VESA LocalBus (VLB) .EISA .Centronics Printer .

334 .SCSI External (Amiga/Mac) .SCART Networking: .SCSI External Centronics 50 .SIMM 30-pin . Memories: .Ethernet 10Base-T Last updated 1997-11-17. (C) Joakim Ögren 1996.1997 PR EL IM IN BETA RELEASE AR YB ET A .SIMM 72-pin .Chapter 2: Connector Top 10 Menu The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.IDE Internal . It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI Home audio/video: BU TIO N.ATA Internal .

C64 Centronics Printer YB Printer: ET A .N OT FO R RE DI ST RI BU TIO N.Centronics Printercable .64NET .GEOCable Misc Serial: .Modem (9p to 25p) .Two-Wire Modem (9p to 25p) .Two-Wire Modem (25p to 25p) .Macintosh Modem (Without DTR) .Conrad Electronics MM3610D (25p) PR EL IM IN Parallel: BETA RELEASE AR . Nullmodem: .The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Macintosh Modem (With DTR) . Chapter 3 Cable Menu What does the information that is listed for each connector mean? See the tutorial.Serial Printer (25p to 25p) .Mac to C64 Nullmodem Modem: . It may not be modified and re-distributed without the authors permission.Nullmodem (9p to 25p) .Modem (9p to 15p) .Nullmodem (9p to 9p) .Cisco Console (25p) .Modem (25p to 25p) . 335 .Nullmodem (25p to 25p) .Serial Printer (9p to 25p) .ParNet Parallel .Cisco Console (9p) .RocketPort Serial (25) Cable .LapLink/InterLink Parallel .Conrad Electronics MM3610D (9p) .

C128/C64C to CBM 1902A Monitor cable .C128/C64C to SCART (S-Video) cable .Paravision SX1 to IDE .ESDI cable .IDE cable .Serial Port Loopback (25p Norton) .Misc unsupported cables YB ET A Networking: .Video to TV SCART cable .Serial Port Loopback (9p CheckIt) . (C) Joakim Ögren 1996.Ethernet 10/100Base-T Straight Thru cable .Amiga to C1084 Monitor cable .ST506/412 cable .Chapter 3: Cable Menu .9 to 15 pin VGA cable .Ethernet 100Base-T4 Crossover cable Misc: Last updated 1997-11-17.SCSI Cable (D-Sub to Hi D-Sub) .Serial Port Loopback (9p Norton) .Mac to HP48 Loopback plugs: The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.X1541 cable .Floppy cable .1997 PR EL IM IN BETA RELEASE AR .Parallel Port Loopback (Norton) . 336 .NeoGeo to SCART cable OT FO R TV/Video/Monitor: RE DI ST RI BU .MIDI cable .N .Parallel Port Loopback (CheckIt) .ParaLoad cable .Amiga to SCART cable .Ethernet 10/100Base-T Crossover cable .Serial Port Loopback (25p CheckIt) TIO N. It may not be modified and re-distributed without the authors permission. Data storage: .SCSI cable (Amiga/Mac) .

Pin 1. Should be simple to read. Strobe Data Bit 0 Data Bit 1 Data Bit 2 25-DSub 1 2 3 4 36-Cen 1 2 3 4 337 PR EL IM IN BETA RELEASE AR Below the pictures there is texts that describes the connectors. (To the Printer) FO (To the computer) R RE There may be some pictures I haven't drawn yet. It may not be modified and re-distributed without the authors permission. Pin 2. BU Pictures of the connectors TIO N.N OT Normally are one or more pictures. Short tutorial . and NOT the soldside.Chapter 3: Cable Menu Cable Tutorial Heading The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. This means that I don't know what kind of connector it is or how it looks. The first is a female connector and the send a male. The texts insde parentheses will tell you at which kind of the device it will look like that. Pin table The pin table is perhaps the information you are looking for. Sometimes when not the same pin is connected to each side there is another column describing the name at connector 2. First at each page there a short heading describing the cable. Look at the example below. I illustrate this with the following advanced picture: DI (To the computer) ST RI After that there is at each page there is one or more pictures of the connectors. YB . Name. These are seen from the front. Holes (female connectors usually) are darkened. Including the name of the physical connector. Sometimes there is some question marks only. ET A (To the Computer) Texts describing the connectors 25 PIN D-SUB MALE to the Computer 36 PIN CENTRONICS MALE to the Printer. Contains mostly the following three columns.

Contributor: Joakim Ögren Source: Amiga 4000 User's Guide from Commodore PR EL IM IN BETA RELEASE AR YB ET A . 5 6 7 8 9 .. Cable Tutorial The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 338 ...Chapter 3: Cable Menu Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 ...N OT FO R RE DI ST RI All persons that helped me or sent me information about the connector will be listed here. I must admit that I am bad at writing the source. BU Contributor & Source TIO N. 5 6 7 8 9 . It may not be modified and re-distributed without the authors permission. The source of the information is perhaps a book or another site.. but I will try to fill in these in the future.

Contributor: Joakim Ögren .umu. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N Source: ? OT FO R RE DI Transmit Data Receive Data Data Set Ready + Carrier Detect System Ground Data Terminal Ready Clear to Send Request to Send ST RI BU (To Computer 1). 9 PIN D-SUB FEMALE to Computer 2.com> Please send any comments to Joakim Ögren. (To Computer 2). It may not be modified and re-distributed without the authors permission. 9 PIN D-SUB FEMALE to Computer 1.Chapter 3: Cable Menu Nullmodem (9-9) Cable Use this cable between two DTE devices (for instance two computers). Don Rifkin <Don. Drew Sullivan <drew@ss. Receive Data Transmit Data Data Terminal Ready System Ground Data Set Ready + Carrier Detect Request to Send Clear to Send D-Sub 1 2 3 4 5 6+1 7 8 D-Sub 2 3 2 6+1 5 4 8 7 Note: DSR & CD are jumpered to fool the programs to think that they are online. Niklas Edmundsson <nikke@ing.Rifkin@mci. 339 Nullmodem (9-9) Cable .se>.org>. PR EL IM IN BETA RELEASE AR YB ET A . TIO N.

(To Computer 2).Chapter 3: Cable Menu Nullmodem (9-25) Cable Use this cable between two DTE devices (for instance two computers). Receive Data Transmit Data Data Terminal Ready System Ground Data Set Ready + Carrier Detect Request to Send Clear to Send D-Sub 9 2 3 4 5 6+1 7 8 D-Sub 25 2 3 6+8 7 20 5 4 Note: DSR & CD are jumpered to fool the programs to think that they are online. TIO N. 25 PIN D-SUB FEMALE to Computer 2. 340 Nullmodem (9-25) Cable .com> FO R RE DI Transmit Data Receive Data Data Set Ready + Carrier Detect System Ground Data Terminal Ready Clear to Send Request to Send ST RI BU (To Computer 1). Drew Sullivan <drew@ss. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Don Rifkin <Don. Source: ? Please send any comments to Joakim Ögren.org>.umu.Rifkin@mci. Niklas Edmundsson <nikke@ing.N OT Contributor: Joakim Ögren. It may not be modified and re-distributed without the authors permission.se>. 9 PIN D-SUB FEMALE to Computer 1. PR EL IM IN BETA RELEASE AR YB ET A .

341 Nullmodem (25-25) Cable . Receive Data Transmit Data Data Terminal Ready System Ground Data Set Ready + Carrier Detect Request to Send Clear to Send D-Sub 1 3 2 20 7 6+8 4 5 D-Sub 2 2 3 6+8 7 20 5 4 Note: DSR & CD are jumpered to fool the programs to think that they are online.se>.Rifkin@mci. (To Computer 2). Niklas Edmundsson <nikke@ing.org>.com> FO R RE DI Transmit Data Receive Data Data Set Ready + Carrier Detect System Ground Data Terminal Ready Clear to Send Request to Send ST RI BU (To Computer 1). Don Rifkin <Don. PR EL IM IN BETA RELEASE AR YB ET A . 25 PIN D-SUB FEMALE to Computer 2.Chapter 3: Cable Menu Nullmodem (25-25) Cable Use this cable between two DTE devices (for instance two computers). It may not be modified and re-distributed without the authors permission. TIO N. 25 PIN D-SUB FEMALE to Computer 1.com>. Richard Marker <richmarker@aol.umu. Source: ? Please send any comments to Joakim Ögren. Drew Sullivan <drew@ss.N OT Contributor: Joakim Ögren. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

au> PR EL IM IN BETA RELEASE AR YB ET A . Mac to C64 Nullmodem Cable 342 .4+5 RXD+ 8 TXD+ 6 C64 1+12+A+N M B+C D+E Source: Usenet posting in comp. DZM 12 DREH to the C64 UserPort.edu. It uses inverted TTL level for the signals. (At the Computer) (To the C64). The RS-422 ports on the Macintosh has both an inverted and non-inverted input. Pierre Olivier <olipie@aei.oulu.cbm. FO Contributor: Joakim Ögren. It may not be modified and re-distributed without the authors permission. A very simple C64 to Macintosh serial cable <http://stekt. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.ca> R GND TXD (PA2) RXD (FLAG2+PB0) RTS+DTR (PB1+PB2) RE DI ST RI BU TIO N. 8 PIN MINI-DIN MALE to the Macintosh.sys. Mac GND+RXD.N OT Please send any comments to Joakim Ögren.newcastle. By using the inverted instead of non-inverted the inverted C64 level is back to normal.fi/~jopi/electronics/cbm/C64_to_mac> by Chris Baird <c8923075@cs.Chapter 3: Cable Menu Mac to C64 Nullmodem Cable The RS-232 standard on the C64 is a little bit strange.

(To Computer). RI BU TIO N. Modem (9-25) Cable 343 . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .dk> Please send any comments to Joakim Ögren.N Source: ? OT Shield Transmit Data Receive Data Request to Send Clear to Send Data Set Ready System Ground Carrier Detect Data Terminal Ready Ring Indicator Female Male Dir 1 3 2 2 3 7 4 8 5 6 6 5 7 1 8 4 20 9 22 FO R RE DI 9 PIN D-SUB FEMALE to the Computer 25 PIN D-SUB MALE to the Modem ST (To Modem). It may not be modified and re-distributed without the authors permission. Søren Graversen <graver@post1.tele.Chapter 3: Cable Menu Modem (9-25) Cable This cable should be used for DTE to DCE (for instance computer to modem) connections with hardware handshaking. Contributor: Joakim Ögren.

Contributor: Joakim Ögren.tele. Modem (25-25) Cable 344 . RI BU TIO N. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Chapter 3: Cable Menu Modem (25-25) Cable This cable should be used for DTE to DCE (for instance computer to modem) connections with hardware handshaking. Søren Graversen <graver@post1. It may not be modified and re-distributed without the authors permission.N Source: ? OT Shield Ground Transmit Data Receive Data Request to Send Clear to Send Data Set Ready System Ground Carrier Detect Data Terminal Ready Ring Indicator Female 1 2 3 4 5 6 7 8 20 22 Male Dir 1 2 3 4 5 6 7 8 20 22 FO R RE DI 25 PIN D-SUB FEMALE to the Computer 25 PIN D-SUB MALE to the Modem ST (To Modem). PR EL IM IN BETA RELEASE AR YB ET A . (To Computer).dk> Please send any comments to Joakim Ögren.

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. RI BU TIO N. Two-Wire Modem (9-25) Cable 345 . (To Computer). Shield Ground Transmit Data Receive Data System Ground Female Male Dir 1 3 2 2 3 5 7 7 8 Request to Send Clear to Send 4 5 Data Set Ready Carrier Detect Data Terminal Ready Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission.Chapter 3: Cable Menu Two-Wire Modem (9-25) Cable This cable should be used for DTE to DCE (for instance computer to modem) connections without hardware handshaking. PR EL IM IN BETA RELEASE AR YB ET A 6 8 20 .N OT Data Set Ready 6 Carrier Detect 1 Data Terminal Ready 4 FO Jumper these: Request to Send Clear to Send R RE DI 9 PIN D-SUB FEMALE to the Computer 25 PIN D-SUB MALE to the Modem ST (To Modem).

It may not be modified and re-distributed without the authors permission. (To Computer).N OT Data Set Ready 6 Carrier Detect 8 Data Terminal Ready 20 FO Jumper these: Request to Send Clear to Send R RE DI 25 PIN D-SUB FEMALE to the Computer 25 PIN D-SUB MALE to the Modem ST (To Modem).Chapter 3: Cable Menu Two-Wire Modem (25-25) Cable This cable should be used for DTE to DCE (for instance computer to modem) connections without hardware handshaking. PR EL IM IN BETA RELEASE AR YB ET A 6 8 20 . RI BU TIO N. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Two-Wire Modem (25-25) Cable 346 . Shield Ground Transmit Data Receive Data System Ground Female 1 2 3 7 Male Dir 1 2 3 7 4 5 Request to Send Clear to Send 4 5 Data Set Ready Carrier Detect Data Terminal Ready Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.

comm FAQ Part 1 <http://www. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.edu/hypertext/faq/usenet/macintosh/comm-faq/part1/faq.Chapter 3: Cable Menu Macintosh Modem (With DTR) Cable This cable should be used for DTE to DCE (for instance computer to modem) connections with DTR. PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI ST (To the Modem). 25 PIN D-SUB MALE to the Modem HSKo HSKi TxDRxDGND+RxD+ GPi Mac Dir 1 2 3 5 4+8 5 Modem 4+20 RTS+DTR 5 CTS 2 TxD 3 RxD 7 GND 8 DCD Contributor: Joakim Ögren.html> Please send any comments to Joakim Ögren.mac.sys. RI BU TIO N.ca> Source: comp. (At the Computer) 8 PIN MINI-DIN MALE to the Computer. It may not be modified and re-distributed without the authors permission. Pierre Olivier <olipie@aei.cis.ohio-state. Macintosh Modem (With DTR) Cable 347 .

edu/hypertext/faq/usenet/macintosh/comm-faq/part1/faq.ohio-state. It may not be modified and re-distributed without the authors permission. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.comm FAQ Part 1 <http://www. RI BU TIO N.N OT FO R - RE DI ST (To the Modem). 25 PIN D-SUB MALE to the Modem HSKo HSKi TxDRxDGND+RxD+ Mac 1 2 3 5 4+8 Dir Modem 4 RTS 5 CTS 2 TxD 3 RxD 7 GND 6+20 DSR+DTR Contributor: Joakim Ögren. Macintosh Modem (Without DTR) Cable 348 .mac. Pierre Olivier <olipie@aei.ca> Source: comp. PR EL IM IN BETA RELEASE AR YB ET A .sys.Chapter 3: Cable Menu Macintosh Modem (Without DTR) Cable This cable should be used for DTE to DCE (for instance computer to modem) connections without DTR. (At the Computer) 8 PIN MINI-DIN MALE to the Computer.cis.html> Please send any comments to Joakim Ögren.

ST RI BU TIO N. It may not be modified and re-distributed without the authors permission. Karl Asha <karl@blackdown.Chapter 3: Cable Menu RocketPort Serial (25) Cable Use this cable to connect a RocketPort serialport card to a modem. 349 RocketPort Serial (25) Cable . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 25 PIN D-SUB MALE to the modem DI (To the modem).com> Source: ? Please send any comments to Joakim Ögren. (To the RocketPort card) Contributor: Joakim Ögren.N OT Description Request To Send Data Terminal Ready Ground Tranceive Data Receive Data Data Carrier Detect Data Set Ready Clear To Send RJ45 1 2 3 3 6 6 7 8 D-Sub Dir 4 20 7 2 3 8 6 5 FO R RE RJ45 MALE CONNECTOR to the RocketPort card. PR EL IM IN BETA RELEASE AR YB ET A .

It may not be modified and re-distributed without the authors permission.4kbps Speedster modem to a computer. Modem (9-15) Cable 350 . Carrier Detect Receive Data Transmit Data Data Terminal Ready System Ground Data Set Ready Request to Send Clear to Send Ring Indicator Source: ? Please send any comments to Joakim Ögren. Contributor: Joakim Ögren.Chapter 3: Cable Menu Modem (9-15) Cable This cable should be used to connect an internal 14. TIO N.de> PR EL IM IN BETA RELEASE AR YB ET A . (At the modem) 9 PIN D-SUB FEMALE to the Computer 15 PIN FEMALE ??? to the modem. Joerg Brinkel <jb@itm. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO 9 pin 15 pin Dir 1 11 2 13 3 12 4 10 5 1+8+15 6 3 7 4 8 5 9 6 R RE DI ST RI BU (To Computer).rwth-aachen.

26 27 28. 351 Printer Cable .20 21. Petr Krc <magneton@mail.Chapter 3: Cable Menu Printer Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST 25 PIN D-SUB MALE to the Computer 36 PIN CENTRONICS MALE to the Printer. It may not be modified and re-distributed without the authors permission.29 30.16 Shield+17 ET A .cz> Source: ? PR EL IM IN Please send any comments to Joakim Ögren. BETA RELEASE AR YB Strobe Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Acknowledge Busy Paper Out Select Autofeed Error Reset Select Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Signal Ground Shield 25-DSub 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Shield 36-Cen 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 31 36 33 19.24 25. RI (To the Printer) BU TIO N.22 23.firstnet. (To the Computer) Contributor: Joakim Ögren.

9 PIN D-SUB FEMALE to Computer. 25 PIN D-SUB FEMALE to Printer.N OT FO R DI ST RI BU (To Computer). Receive Data Transmit Data Clear To Send + Data Set Ready Carrier Detect + Data Terminal Ready Ground Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission. D-Sub 1 3 2 8+6 1+4 5 RE 7 D-Sub 2 3 Transmit Data 2 Receive Data 20 Data Terminal Ready Ground PR EL IM IN BETA RELEASE AR YB ET A . TIO N.Chapter 3: Cable Menu Serial Printer (9-25) Cable Use this cable between two a computer (DTE) and a printer (DTE) devices. (To Printer). 352 Serial Printer (9-25) Cable . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

25 PIN D-SUB FEMALE to Printer. 25 PIN D-SUB FEMALE to Computer. TIO N. Receive Data Transmit Data Clear To Send + Data Set Ready Carrier Detect + Data Terminal Ready Ground Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.Chapter 3: Cable Menu Serial Printer (25-25) Cable Use this cable between two a computer (DTE) and a printer (DTE) devices.N OT FO R DI ST RI BU (To Computer). The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (To Printer). It may not be modified and re-distributed without the authors permission. 353 Serial Printer (25-25) Cable . D-Sub 1 2 3 5+6 8 + 20 7 RE 7 D-Sub 2 3 Transmit Data 2 Receive Data 20 Data Terminal Ready Ground PR EL IM IN BETA RELEASE AR YB ET A .

GND FLAG2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA2 GND C64 Dir 1. TIO N.edu/~thompsbb/cbm_conn. pinout by Roy Kannady <kannady@pogo.den.N B C D E F H J K L M 3 Printer 19-30. It may not be modified and re-distributed without the authors permission.) The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.txt>.N Contributor: Joakim Ögren OT Ground Acknowledge Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Strobe Initialize Printer FO R RE DI ST (To the Printer) RI BU (To the C64). DZM 12 DREH to the C64 UserPort.com> Please send any comments to Joakim Ögren.vanderbilt.33 10 2 3 4 5 6 7 8 9 1 31 Source: CBM Memorial Page Pinouts <http://www. PR EL IM IN BETA RELEASE AR YB ET A . 354 C64 Centronics Printer Cable .12.A.mmc.Chapter 3: Cable Menu C64 Centronics Printer Cable Requires a cartridge with Centronics support (TFCIII or ActionReplay. 36 PIN CENTRONICS MALE to the Printer.vuse.

355 LapLink/InterLink Parallel Cable .MS-DOS v6. RI BU Will work with: .N OT FO R RE DI ST (To Computer 1).0 & v5.Norton Commander v4.Chapter 3: Cable Menu LapLink/InterLink Parallel Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 25 PIN D-SUB MALE to Computer 2.LapLink from Travelling Software . It may not be modified and re-distributed without the authors permission. (To Computer 2). 25 PIN D-SUB MALE to Computer 1.Windows 95 Direct Cable connection from Microsoft . PR EL IM IN BETA RELEASE AR YB ET A Pin 2 3 4 5 6 10 11 12 13 15 16 17 25 Pin 15 13 12 10 11 5 6 4 3 2 16 17 25 Name Error Select Paper Out Acknowledge Busy Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 1 Data Bit 0 Reset Select Signal Ground . Name Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Acknowledge Busy Paper Out Select Error Reset Select Signal Ground Source: ? Contributor: Joakim Ögren Please send any comments to Joakim Ögren.0 InterLink from Microsoft .0 from Symantec TIO N.

RI (To Computer 2). 25 PIN D-SUB MALE to Computer 2. BU TIO N. 356 ParNet Parallel Cable . Name Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Acknowledge + Select Busy Paper Out Signal Ground Contributor: Joakim Ögren Source: ? Pin 2 3 4 5 6 7 8 9 10+13 11 12 17-25 Pin 2 3 4 5 6 7 8 9 10+13 11 12 17-25 Name Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Acknowledge + Select Busy Paper Out Signal Ground Please send any comments to Joakim Ögren.N OT FO R RE DI ST 25 PIN D-SUB MALE to Computer 1.Chapter 3: Cable Menu ParNet Parallel Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission. (To Computer 1).

82.58 documentation by Paul Gardner-Stephen <gardners@ist.flinders. BU TIO N.Chapter 3: Cable Menu 64NET Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 357 64NET Cable . Contributor: Joakim Ögren Source: 64NET v1.au> Please send any comments to Joakim Ögren. 25 PIN D-SUB MALE to the PC RI (To PC). It may not be modified and re-distributed without the authors permission.edu.N OT FO GND PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 C64 Dir A C D E F H J K L PC 25 10 11 12 5 6 7 8 9 GND /ACK BUSY PE D3 D4 D5 D6 D7 R RE DI ST DZM 12 DREH to the C64 UserPort. PR EL IM IN BETA RELEASE AR YB ET A . (To C64).

3.p7.html> OT Ground Flag 2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA2 Ground C64 A B C D E F H J K L M N Printer 33 Ground 11 Busy 2 Data 1 3 Data 2 4 Data 3 5 Data 4 6 Data 5 7 Data 6 8 Data 7 9 Data 8 1 Strobe 16 Ground FO R RE DI ST DZM 12 DREH to the C64 UserPort. 358 GEOCable Cable .1 Part 7 <http://www.N Source: comp.1. Contributor: Joakim Ögren Please send any comments to Joakim Ögren. RI (To the Printer) BU TIO N.uk/internet/news/faq/archive/cbm-main-faq. It may not be modified and re-distributed without the authors permission. 36 PIN CENTRONICS MALE at the Printer. PR EL IM IN BETA RELEASE AR YB ET A . (To the C64).cbm General FAQ v3.Chapter 3: Cable Menu GEOCable Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.ox.lib.sys.ac.

N Source: ? OT Receive Data Transmit Data Data Terminal Ready Ground (use as shield) Data Set Ready Request to Send Clear to Send Female 2 3 4 5 6 7 8 2 8 1 FO Male 3 6 7 Dir R RE 9 PIN D-SUB FEMALE to the Computer RJ45 MALE CONNECTOR to the Cisco router.Chapter 3: Cable Menu Cisco Console (9) Cable Use this cable to configure a Cisco router thru the Console port at the router. DI (To the Cisco router) ST RI BU (To Computer). PR EL IM IN BETA RELEASE AR YB ET A . Contributor: Joakim Ögren. TIO N. It may not be modified and re-distributed without the authors permission.com. Damien Miller <dmiller@vitnet.sg> Please send any comments to Joakim Ögren. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 359 Cisco Console (9) Cable .

PR EL IM IN BETA RELEASE AR YB ET A . 360 Cisco Console (25) Cable .com. TIO N. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N Source: ? OT Shield Ground Transmit Data Receive Data Request to Send Clear to Send Data Set Ready Data Terminal Ready Female 1 2 3 4 5 6 20 Male Dir 6 3 8 1 2 7 FO R RE 25 PIN D-SUB FEMALE to the Computer RJ45 MALE CONNECTOR to the Cisco router.Chapter 3: Cable Menu Cisco Console (25) Cable Use this cable to configure a Cisco router thru the Console port at the router. Contributor: Joakim Ögren. It may not be modified and re-distributed without the authors permission. DI (To the Cisco router) ST RI BU (To Computer).sg> Please send any comments to Joakim Ögren. Damien Miller <dmiller@vitnet.

PC 7 2 3 4 5 Conrad Dir 1 2 3 4 5 Contributor: Joakim Ögren. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Chapter 3: Cable Menu Conrad Electronics MM3610D (9) Cable Use this cable to connect a Conrad Electronics Multimeter 3610D to a PC:s serialport.belz@samson. Conrad Electronics MM3610D Cable 361 . TIO N.mbis.de> PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU (To PC). 9 PIN D-SUB FEMALE to PC. (To multimeter). 5 PIN UNKNOWN CONNECTOR to the multimeter Request To Send Receive Data Transmit Data Data Terminal Ready Ground Source: ? Please send any comments to Joakim Ögren. Anselm Belz <a.

N OT FO R RE DI ST RI BU (To PC).de> PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission. PC 4 3 2 20 7 Conrad Dir 1 2 3 4 5 Contributor: Joakim Ögren. TIO N. 25 PIN D-SUB FEMALE to PC. 5 PIN UNKNOWN CONNECTOR to the multimeter Request To Send Receive Data Transmit Data Data Terminal Ready Ground Source: ? Please send any comments to Joakim Ögren.mbis.Chapter 3: Cable Menu Conrad Electronics MM3610D (25) Cable Use this cable to connect a Conrad Electronics Multimeter 3610D to a PC:s serialport. Conrad Electronics MM3610D Cable 362 . Anselm Belz <a. (To multimeter). The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.belz@samson.

8 PIN MINI-DIN MALE to the Computer.sys.edu.fi/~jopi/electronics/cbm/C64_to_mac> by Tomas Moberg <fr94tmg@ing.cbm.fi/~jopi/electronics/cbm/C64_to_mac> by Chris Baird <c8923075@cs. Mac to C64 Interface <http://stekt.sys. Pierre Olivier <olipie@aei.umu. It may not be modified and re-distributed without the authors permission.Chapter 3: Cable Menu Mac to HP48 Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. A very simple C64 to Macintosh serial cable <http://stekt. (At the Computer) (To the HP48).newcastle.N OT FO Sources: Usenet posting in comp. 4 PIN ??? FEMALE to the HP48 TxDRxDGND+RxD+ Shield Mac HP48 3 5 4+8 SHIELD SHIELD RxD TxD GND Shield Contributor: Joakim Ögren.au> R RE DI ST RI BU TIO N.cbm. PR EL IM IN BETA RELEASE AR YB ET A .oulu.se> Sources: Usenet posting in comp.oulu. 363 Mac to HP48 Cable .ca> Please send any comments to Joakim Ögren.

N OT FO R RE Contributor: Joakim Ögren DI Pin 2 3 4 5 6 Pin 15 13 12 10 11 Name Error Select Paper Out Acknowledge Busy ST RI BU TIO N. This one works with Norton Utilities: Norton Diagnostics from Symantec. Parallel Port Loopback (Norton) 364 . 25 PIN D-SUB MALE to Computer. PR EL IM IN BETA RELEASE AR YB ET A .Chapter 3: Cable Menu Parallel Port Loopback (Norton) Used to verify that a port is working. (To Computer). It may not be modified and re-distributed without the authors permission. Name Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Source: ? Please send any comments to Joakim Ögren. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

Contributor: Joakim Ögren. 25 PIN D-SUB MALE to Computer. 365 Parallel Port Loopback (CheckIt) . TIO N. "Coolsys" <coolsys@geocities. This one works with CheckIt. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI Pin 11 10 12 13 2 Pin 17 16 14 1 15 Name Select Input Initialize Auto Feed Strobe Error ST RI BU (To Computer). The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.com> PR EL IM IN BETA RELEASE AR YB ET A . Name Busy Acknowledge Paper end Select Data Bit 0 Source: ? Please send any comments to Joakim Ögren.Chapter 3: Cable Menu Parallel Port Loopback (CheckIt) Used to verify that a port is working.

9 PIN D-SUB FEMALE to Computer. Serial Port Loopback (9 Norton) 366 .N OT FO R RE DI ST Pin 2 7 1 Pin Pin 3 8 4 6 Pin RI BU TIO N. (To Computer). The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Chapter 3: Cable Menu Serial Port Loopback (9 Norton) Used to verify that a port is working. This one works with Norton Utilities: Norton Diagnostics from Symantec. It may not be modified and re-distributed without the authors permission. Name Jumpering 1 Jumpering 2 Jumpering 3 Source: ? Please send any comments to Joakim Ögren. 9 Contributor: Joakim Ögren PR EL IM IN BETA RELEASE AR YB ET A .

Serial Port Loopback (25 Norton) 367 . Name Jumpering 1 Jumpering 2 Jumpering 3 Source: ? Please send any comments to Joakim Ögren. 25 PIN D-SUB FEMALE to Computer.N OT FO R RE DI ST Pin 2 4 6 Pin Pin 3 5 8 20 Pin RI BU TIO N. 22 Contributor: Joakim Ögren PR EL IM IN BETA RELEASE AR YB ET A . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Chapter 3: Cable Menu Serial Port Loopback (25 Norton) Used to verify that a port is working. This one works with Norton Utilities: Norton Diagnostics from Symantec. (To Computer). It may not be modified and re-distributed without the authors permission.

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . 368 Serial Port Loopback (9 CheckIt) .N OT FO R RE DI ST RI BU (To Computer). TIO N. 9 PIN D-SUB FEMALE to Computer. It may not be modified and re-distributed without the authors permission.Chapter 3: Cable Menu Serial Port Loopback (9 CheckIt) Used to verify that a port is working. "Coolsys" <coolsys@geocities. Name CD CD RXD DTR RTS Pin 1 1 2 4 7 Pin 6 9 3 6 8 Name DSR RI TXD DSR CTS Contributor: Joakim Ögren.com> Source: ? Please send any comments to Joakim Ögren. This one works with CheckIt.

This one works with CheckIt.N OT FO R RE DI Contributor: Joakim Ögren.Chapter 3: Cable Menu Serial Port Loopback (25 CheckIt) Used to verify that a port is working. Name Jumpering 1 Jumpering 2 Jumpering 3 Source: ? Please send any comments to Joakim Ögren. TIO N. It may not be modified and re-distributed without the authors permission. 22 PR EL IM IN BETA RELEASE AR YB ET A . 369 Serial Port Loopback (25 CheckIt) . "Coolsys" <coolsys@geocities.com> ST Pin 2 4 6 Pin Pin 3 5 8 20 Pin RI BU (To Computer). 25 PIN D-SUB FEMALE to Computer. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

TIO N. (To the Controller) (To the Drive 2) Source: TheRef TechTalk <http://theref. Each drive should be jumpered to act as Drive 2. It may not be modified and re-distributed without the authors permission. The IDC could also be an edge connector on some old drives. OT (To the Drive 1) FO R RE DI Controller Drive 2 Twist Drive 1 +--+ +--+ +--+ |::|===================| |============| | <-Pin 1 |::|===================| |=====\/=====| | |::|===================| |=====/\=====| | |::|===================| |============| | |::|===================| |============| | |::|===================| |============| | |::|===================| |============| | +--+ +--+ +--+ ST RI BU The original floppy cable required that each drive was jumpered to the right ID. If only one drive is used then leave the middle connector free. But IBM come up with an idea to avoid jumpering the floppies. 34 PIN IDC FEMALE to the Drive 2.Chapter 3: Cable Menu Floppy Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Floppy Cable 370 .mil> Please send any comments to Joakim Ögren.c3d. PR EL IM IN Contributor: Joakim Ögren BETA RELEASE AR Wire 1-9 Wire 10 Wire 11 Wire 12 Wire 13 Wire 14 Wire 15 Wire 16 Wire 17-34 ControllerDrive 1 Drive 2 1-9 1-9 1-9 10 16 10 11 15 11 12 14 12 13 13 13 14 12 14 15 11 15 16 10 16 17-34 17-34 17-34 YB ET A . 34 PIN IDC FEMALE to the Drive 1.rl.af.N 34 PIN IDC FEMALE to the Controller. If wire 10-16 are twisted before the last connector the jumpering is avoided.

If only one drive is used. 2 to 2 and so on. The drives can be connected in any order. Only remember that one should be jumpered as Master and the other as Slave. The IDE interface requires only one cable. IDE Cable 371 . It may not be modified and re-distributed without the authors permission. ET A ControllerDrive 1 Drive 2 Wire 1-40 1-40 1-40 1-40 . or most common Master else). jumper it as Single (if such a mode exists.Chapter 3: Cable Menu IDE Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 40 PIN IDC FEMALE to the Drive 2. OT FO (To the Drive 2) R RE DI ST RI BU TIO N. 40 PIN IDC FEMALE to the Drive 1. All pins straight from 1 to 1.N 40 PIN IDC FEMALE to the Controller. Controller Drive 1 or 2 Drive 1 or 2 +--+ +--+ +--+ |::|===================|::|============|::| <-Pin 1 |::|===================|::|============|::| |::|===================|::|============|::| |::|===================|::|============|::| |::|===================|::|============|::| |::|===================|::|============|::| |::|===================|::|============|::| +--+ +--+ +--+ (To the Controller) (To the Drive 1) Contributor: Joakim Ögren Source: ? PR EL IM IN BETA RELEASE AR YB Please send any comments to Joakim Ögren.

PR EL IM IN BETA RELEASE AR YB ET A Request Message Input/Output Reset Acknowledge Busy Data Bus 0 Data Bus 3 Data Bus 5 Data Bus 6 Data Bus 7 Control/Data Attention Select Data Parity Data Bus 1 Data Bus 2 Data Bus 4 Termination Power DSub 1 2 3 4 5 6 8 10 11 12 13 15 17 19 20 21 22 23 25 IDC 48 42 50 40 38 36 2 8 12 14 16 46 32 44 18 4 6 10 26 . (To the Amiga/Mac). Note: All the other pins (7+9+14+16+18+24) at the DSub should be connected to the all odd pins except 25 at the IDC connector. RI BU TIO N. It may not be modified and re-distributed without the authors permission. 372 SCSI Cable (Amiga/Mac) . 50 PIN IDC FEMALE to the peripheral. (To the peripheral).Chapter 3: Cable Menu SCSI Cable (Amiga/Mac) The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST 25 PIN D-SUB FEMALE to the Amiga/Mac. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.

(To the Amiga/Mac).N OT FO R RE DI ST 25 PIN D-SUB MALE to the Amiga/Mac. RI (To the peripheral). Source: ? Please send any comments to Joakim Ögren. Note: All the other pins (7+9+14+16+18+24) at the DSub should be connected to pins 1-25 at the Hi-density D-Sub connector. It may not be modified and re-distributed without the authors permission. 373 SCSI Cable (D-Sub to Hi D-Sub) . PR EL IM IN BETA RELEASE AR YB Contributor: Joakim Ögren ET A Request Message Input/Output Reset Acknowledge Busy Data Bus 0 Data Bus 3 Data Bus 5 Data Bus 6 Data Bus 7 Control/Data Attention Select Data Parity Data Bus 1 Data Bus 2 Data Bus 4 Termination Power DSub 1 2 3 4 5 6 8 10 11 12 13 15 17 19 20 21 22 23 25 Hi DSub 49 46 50 45 44 43 26 29 31 32 33 48 41 47 34 27 28 30 38 . 50 PIN HI-DENSITY D-SUB MALE to the peripheral. BU TIO N.Chapter 3: Cable Menu SCSI Cable (D-Sub to Hi D-Sub) The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

since the twist will do the job. By twisting some wires on the control cable it won't be necessary to set the ID for each drive. 34 PIN IDC FEMALE to the Drive 1. The control cable is shared between the two drives. But each drive has each own data cable. OT (To the Drive 1) FO R RE DI Control cable ST RI BU TIO N.N 34 PIN IDC FEMALE to the Controller. BETA RELEASE YB (To the Controller) (To the Drive) ET A . It may not be modified and re-distributed without the authors permission. Wires 25 to 29 should be twisted between drive 1 & drive 2. The ST506/412 interface requires two cables. Controller Drive 2 Twist Drive 1 +--+ +--+ +--+ |::|===================| |============| | <-Pin 1 |::|===================| |============| | |::|===================| |============| | |::|===================| |============| | |::|===================| |=====\/=====| | |::|===================| |=====/\=====| | |::|===================| |============| | +--+ +--+ +--+ (To the Controller) (To the Drive 2) PR EL IM IN Data cable AR Wire 1-24 Wire 25 Wire 26 Wire 27 Wire 28 Wire 29 Wire 30-34 ControllerDrive 1 Drive 2 1-9 1-9 1-9 25 29 25 26 28 26 27 27 27 28 26 28 29 25 29 30-34 30-34 30-34 20 PIN IDC FEMALE to the Controller. 34 PIN IDC FEMALE to the Drive 2. ST506/412 Cable 374 . 20 PIN IDC FEMALE to the Drive. one for control and one for data.Chapter 3: Cable Menu ST506/412 Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

N OT FO R RE DI ST RI BU TIO N.af.c3d.rl. Please send any comments to Joakim Ögren.mil> The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . 375 . It may not be modified and re-distributed without the authors permission.Chapter 3: Cable Menu Controller Wire 1-20 1-20 Drive 1-20 ST506/412 Cable Contributor: Joakim Ögren Source: TheRef TechTalk <http://theref.

By twisting some wires on the control cable it won't be necessary to set the ID for each drive. The ESDI interface requires two cables. since the twist will do the job.Chapter 3: Cable Menu ESDI Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. ControllerDrive BETA RELEASE YB (To the Controller) (To the Drive) ET A . The control cable is shared between the two drives. 34 PIN IDC FEMALE to the Drive 1. Wires 25 to 29 should be twisted between drive 1 & drive 2. 20 PIN IDC FEMALE to the Drive. one for control and one for data. ESDI Cable 376 . 34 PIN IDC FEMALE to the Drive 2. OT (To the Drive 1) FO R RE DI Control cable ST RI BU TIO N. Controller Drive 2 Twist Drive 1 +--+ +--+ +--+ |::|===================| |============| | <-Pin 1 |::|===================| |============| | |::|===================| |============| | |::|===================| |============| | |::|===================| |=====\/=====| | |::|===================| |=====/\=====| | |::|===================| |============| | +--+ +--+ +--+ (To the Controller) (To the Drive 2) Data cable PR EL IM IN AR Wire 1-24 Wire 25 Wire 26 Wire 27 Wire 28 Wire 29 Wire 30-34 ControllerDrive 1 Drive 2 1-9 1-9 1-9 25 29 25 26 28 26 27 27 27 28 26 28 29 25 29 30-34 30-34 30-34 20 PIN IDC FEMALE to the Controller.N 34 PIN IDC FEMALE to the Controller. It may not be modified and re-distributed without the authors permission. But each drive has each own data cable.

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 377 .c3d.af. Wire 1-20 1-20 Contributor: Joakim Ögren PR EL IM IN YB ET A .rl.mil> Please send any comments to Joakim Ögren.N OT FO R RE DI Source: TheRef TechTalk <http://theref. It may not be modified and re-distributed without the authors permission. Chapter 3: Cable Menu AR 1-20 ESDI Cable BETA RELEASE ST RI BU TIO N.

(To the controller) 37 PIN D-SUB FEMALE to the controller. But most harddisks require both +5V and +12V. Description Drive Reset Data bit 0 Data bit 2 Data bit 4 Data bit 6 Ground Data bit 8 Data bit 10 Data bit 12 Data bit 14 Ground Ground Ground Ground 5V Power 5V Power Ground Data bit 1 Data bit 3 Data bit 5 Data bit 7 Ground Data bit 9 Data bit 11 Data bit 13 Data bit 15 I/O Write I/O Read Interrupt Request Address bit 2 Address bit 1 Address bit 0 Chip Select 1 Chip Select 0 D-Sub 1 2 3 4 5 6 7 8 9 10 11+12 13+14 15+16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 IDC 1 17 13 9 5 2 4 8 12 16 19 22 24 26 n/c n/c 30 21 22 23 24 40 26 27 28 29 23 25 31 36 33 35 38 37 Note: Pin 18+19 (+5V) can be used to power the harddisk. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.Chapter 3: Cable Menu Paravision SX1 to IDE Cable Can be used to connect a normal IDE harddisk to the Paravision SX1. Paravision SX1 to IDE Cable 378 . 40 PIN IDC FEMALE to the harddisk. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI ST (To the Harddrive) RI BU TIO N. Paravision was earlier known as Microbotics.

21 PIN SCART MALE to the Video Recorder. (To the TV) Red Red Ground Green Green Ground Blue Blue Ground Status / 16:9 Reserved Reserved Fast Blanking Ground Fast Blanking Video Out Ground Video In Ground Video Out Video In Ground Ground Source: ? 15 13 11 9 7 5 8 10 12 14 16 17 18 19 20 21 15 13 11 9 7 5 8 10 12 14 16 18 17 20 19 21 Red Red Ground Green Green Ground Blue Blue Ground Contributor: Joakim Ögren PR EL IM IN BETA RELEASE AR Please send any comments to Joakim Ögren.Chapter 3: Cable Menu Video to TV SCART Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. YB Status / 16:9 Reserved Reserved Fast Blanking Ground Fast Blanking Video In Ground Video Out Ground Video In Video Out Ground ET A .N OT FO R RE Audio Right Out Audio Right In Audio Left Out Audio Left In Audio Ground TV 1 2 3 6 4 VCR 2 1 6 3 4 Audio Right In Audio Right Out Audio Left In Audio Left Out Audio Ground DI ST 21 PIN SCART MALE to the TV. RI (To the Video Recorder) BU TIO N. 379 Video to TV SCART cable . It may not be modified and re-distributed without the authors permission.

N OT Audio IN Left GND FO R Analog Red Analog Green Analog Blue Composite Sync Video GND GND +12V +12V Amiga 3 4 5 10 17 19 22 22 TV 15 11 7 20 17 18 16 8 RGB Red In RGB Green In RGB Blue In Video In Video GND Blanking GND Blanking (Connect via a 150 Ohm resistor) Audio/RGB switch (Connect via a 1 kOhm resistor) RE DI ST 23 PIN D-SUB FEMALE to the Amiga 21 PIN SCART MALE to the TV RI (To the TV) BU TIO N. It may not be modified and re-distributed without the authors permission. (To the Amiga) Phono Right Phono Right GND Phono Left Phono Left GND Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. 380 Amiga to SCART cable . 2 4 6 4 Audio IN Right GND PR EL IM IN BETA RELEASE AR YB ET A .Chapter 3: Cable Menu Amiga to SCART Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

N OT FO Red Video Green Video Blue Video Horizontal Sync Vertical Sync Red GND Green GND Blue GND Sync GND 9-Pin 1 2 3 4 5 6 7 8 9 15-Pin 1 2 3 13 14 6 7 8 10 + 11 R RE DI ST 9 PIN D-SUB MALE to the Computer 15 PIN HIGHDENSITY D-SUB FEMALE to the Monitor RI (To the Monitor) BU TIO N.Chapter 3: Cable Menu 9 to 15 pin VGA Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (To the Computer) Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. 381 9 to 15 pin VGA cable . It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .

Philips 1084 monarin kytkenta <http://www.elektroniikka.hautanen@compart.fi> R RE DI ST RI BU TIO N.edu/~thompsbb/cbm_conn.vanderbilt. (To the Amiga) (At the Monitor) 23 PIN D-SUB FEMALE to the Amiga.Chapter 3: Cable Menu Amiga to C1084 Monitor Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO Source: Usenet posting in sfnet.harrastus. It may not be modified and re-distributed without the authors permission. R G B SYNC GND Amiga C1084 3 4 4 1 5 5 10 2 16 3 R G B HSYNC GND Contributor: Joakim Ögren Please send any comments to Joakim Ögren.txt> by Kari Hautanen <kari. 6 PIN DIN MALE at the Monitor. 382 Amiga to C1084 Monitor Cable .vuse. PR EL IM IN BETA RELEASE AR YB ET A .

uk/internet/news/faq/archive/cbm-main-faq.1 Part 7 <http://www. R Source: cbm.1. LUM CHROMA GND AOUT ComputerC1902A 1 6 8 4 2 3 3 2 LUM CHROMA GND AUDIO Contributor: Joakim Ögren PR EL IM IN BETA RELEASE AR YB ET A .3.html> RE DI ST RI BU TIO N. It may not be modified and re-distributed without the authors permission.lib.sys General FAQ v3.ac. 383 C128/C64C to CBM 1902A Monitor Cable .p7.comp. 6 PIN DIN MALE at the Monitor.ox. (At the Computer) (At the Monitor) 8 PIN DIN (DIN45326) MALE at the Computer.N OT FO Please send any comments to Joakim Ögren.Chapter 3: Cable Menu C128/C64C to CBM 1902A Monitor Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

384 C128/C64C to SCART (S-Video) Cable .Chapter 3: Cable Menu C128/C64C to SCART (S-Video) Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE ComputerTV 1 20 8 15 2 4+17 3 2+6 LUM CHROMA GND AUDIO DI ST RI BU TIO N. (To the Computer) (To the TV) 8 PIN DIN (DIN45326) MALE at the Computer. Contributor: Joakim Ögren. It may not be modified and re-distributed without the authors permission. Claudio Brazzale <brzcld@dei. 21 PIN SCART MALE to the TV LUM CHROMA GND AOUT Source: ? Please send any comments to Joakim Ögren.unipd.it> PR EL IM IN BETA RELEASE AR YB ET A .

21 PIN SCART MALE to the TV Audio Out Ground Composite Video Out ? Green Red Blue Source: ? Please send any comments to Joakim Ögren. Steffen Kupfer <Steffen_Kupfer@compuserve. Contributor: Joakim Ögren.Chapter 3: Cable Menu NeoGeo to SCART Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R NeoGeo 1 2 3 4 5 6 8 TV 6+2 18 20 16 11 15 7 Audio In Left+Right Blanking Signal Ground Composite Video In Blanking Signal RGB Green In RGB Red In RGB Blue In RE DI ST RI BU TIO N.com> PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission. Enzo <enzo@gaianet. (To the Computer) (To the TV) 8 PIN DIN (DIN45326) MALE to the Computer.net>. 385 NeoGeo to SCART Cable .

Chapter 3: Cable Menu Ethernet 10/100Base-T Crossover Cable This cable can be used to cascade hubs.N OT Name TX+ TXRX+ RX- NIC1 1 2 3 6 NIC2 3 6 1 2 Name RX+ RXTX+ TX- FO RJ45 MALE CONNECTOR to network interface card 1. Broido <broidoj@gti.com>.rit. Ethernet 10/100Base-T Crossover Cable 386 . Jeffrey R. 8-8.etsiig.beon.isc.must together in another pair. Note 1: It's important that each pair is kept as a pair. Contributors: Joakim Ögren. or for connecting two Ethernet stations back-to-back without a hub. Pero <JDP6640@ritvax. Jason D.net>. Jim C? <jimc@megalink. R RE DI ST (To network interface card 1).edu> . 5-5. Patrick Smart <Patrick@mail. RJ45 MALE CONNECTOR to network interface card 2. Cayce Balara <CayceB@yardboy. . Oscar Fernandez Sierra <oscar@charpy.uniovi.net>. PR EL IM IN BETA RELEASE AR YB Source: ? ET A Note 2: You could also connect 4-4. 7-7. (Just as the table above shows). (To network interface card 2).must be in the pair. It may not be modified and re-distributed without the authors permission.es>. TX+ & TX.be> Please send any comments to Joakim Ögren. It works with both 10Base-T and 100Base-TX. RI BU TIO N. and RX+ & RX. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

Jeffrey R. (Just as the table above shows).net> Source: ? Please send any comments to Joakim Ögren. a reference to old telephone connectors. Contributor: Joakim Ögren .etsiig. this is how the pairs are named: ET A . BETA RELEASE AR Pair 1 2 3 4 Pins 4&5 1&2 3&6 7&8 Common color Blue Orange Green Brown YB Just for your information.uniovi. RJ45 MALE CONNECTOR to hub). RI BU TIO N. R RE DI ST (To network interface card).side is called the "ring".N RX- OT Name TX+ TXRX+ Pin 1 2 3 4 5 6 7 8 Cable Color White/Orange Orange White/Green Blue White/Blue Green White/Brown Brown Pin 1 2 3 4 5 6 7 8 Name TX+ TXRX+ FO RJ45 MALE CONNECTOR to network interface card).must be in the pair.Chapter 3: Cable Menu Ethernet 10/100Base-T Straight Thru Cable This cable will work with both 10Base-T and 100Base-TX and is used to connect a network interface card to a hub or network outlet. Broido <broidoj@gti. (To hub). TX+ & TX. It may not be modified and re-distributed without the authors permission. Ethernet 10/100Base-T Straight Thru Cable 387 . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Oscar Fernandez Sierra <oscar@charpy. These cables are sometimes called "whips". PR EL IM IN The + side of each pair is called the "tip" and the .es>. RX- Note: It's important that each pair is kept as a pair. and RX+ & RX.must together in another pair.

Ethernet 100Base-T4 Crossover Cable 388 . R RE DI ST (To network interface card 1). Contributors: Joakim Ögren. Kim Scholte <KScholte@BigFoot.must together in another pair etc.Chapter 3: Cable Menu Ethernet 100Base-T4 Crossover Cable This cable can be used to cascade hubs.must be in the pair. (To network interface card 1). PR EL IM IN BETA RELEASE AR YB ET A Name TX_D1+ TX_D1RX_D2+ RX_D2BI_D3+ BI_D3BI_D4+ BI_D4- Pin 1 2 3 6 4 5 7 8 Pin 3 6 1 2 7 8 4 5 Name RX_D2+ RX_D2TX_D1+ TX_D1BI_D4+ BI_D4BI_D3+ BI_D3- .N OT FO RJ45 MALE CONNECTOR to network interface card 1. or for connecting two Ethernet stations back-to-back without a hub. RJ45 MALE CONNECTOR to network interface card 2. (Just as the table above shows). The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Note 1: It's important that each pair is kept as a pair.Com> Source: ? Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission. and RX+ & RX. RI BU TIO N. TX+ & TX.

Source: ParaLoad documentation Please send any comments to Joakim Ögren. (To C64). PR EL IM IN BETA RELEASE AR YB ET A .N OT Contributor: Joakim Ögren FO Ground FLAG2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA2 C64 A B C D E F H J K L M Amiga 17-25 Ground 1 Strobe 2 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 11 Busy R RE DI ST DZM 12 DREH at the C64 UserPort.Chapter 3: Cable Menu ParaLoad Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. BU TIO N. It may not be modified and re-distributed without the authors permission. 25 PIN D-SUB MALE at the Amiga RI (To Amiga). 389 ParaLoad Cable .

ch>.se> R RE DI ST (To the Diskdrive) RI BU TIO N. PR EL IM IN BETA RELEASE AR YB ET A .eriksson@mbox309.swipnet.epfl. 6 PIN DIN (DIN45322) MALE to the Cable GND STROBE AUTOFEED SELECTIN INIT PC 18-25 1 14 17 16 Diskdrive 2 GND 3 ATN 4 CLOCK 5 DATA 6 RESET Source: X1541 documentation Please send any comments to Joakim Ögren.Eriksson <magnus. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.N OT FO Contributor: Joakim Ögren. Magnus. (To the PC). The X1541 software is written by Leopoldo Ghielmetti <GHIELMET@eldi.Chapter 3: Cable Menu X1541 Cable Used to transfer data from a Commodore 1541/1581 diskdrive to a PC. 25 PIN D-SUB MALE to the PC. X1541 Cable 390 .

391 MIDI Cable .N OT FO R RE DI ST RI BU TIO N. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission. (To the 1st peripheral) (To the 2nd peripheral) 5 PIN DIN 180° (DIN41524) MALE to the 1st peripheral. 5 PIN DIN 180° (DIN41524) MALE to the 1st peripheral. 1st Shield 2 Current Source 4 Current Sink 5 2nd 2 4 5 Note: Although that pin 2 only is connected at MIDI Out it's simpler to connect it to both ends.Chapter 3: Cable Menu MIDI Cable The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

PR EL IM IN BETA RELEASE AR (To the C1702). 23 PIN D-SUB FEMALE to the Amiga. Handle with care. i.e 74LS04) (Via 2 Hex Inverters.Chapter 3: Cable Menu Misc Unsupported Cables These cables may or may not be correctly constructed. i. Amiga to IBM RGBI Cable (To the Monitor). 392 Misc unsupported Cables .e 74LS04) (Via 2 Hex Inverters. Ground Ground Digital Red Digital Green Digital Blue Digital Intensity Horizontal Sync Verical Sync +5V 9 Pin 1 2 3 4 5 6 8 9 23 Pin 16 16 9 8 9 6 11 12 23 Comment C128 80 columns to 1702 monitor Cable (To the C128). It may not be modified and re-distributed without the authors permission.e 74LS04) (Power for the IC) FO R RE DI ST RI BU TIO N.e 74LS04) (Via 2 Hex Inverters.psu.N OT (Via 2 Hex Inverters.e 74LS04) (Via 1 Hex Inverters. i.e 74LS04) (Via 1 Hex Inverters. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (To the Amiga).edu> Please send any comments to Joakim Ögren. i. i. 9 PIN D-SUB ?? to the Monitor. PHONO MALE to the Monitor. YB ET A . C128 C1702 Ground 1 1 Ground Monochrome out 7 2 Signal Contributor: Joakim Ögren Source: Gordon <GAJ2@psuvm. 9 PIN D-SUB MALE to the C128. i.

1997 PR EL IM IN BETA RELEASE AR .9p to 25p Serial adapter Parallel: . (C) Joakim Ögren 1996.PS/2 to Serial Mouse Adapter .A1000 to Amiga Parallel adapter Last updated 1997-11-17. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N.Serial to PS/2 Mouse Adapter ET A . Serial: .Mini-DIN to DIN Keyboard adapter .PS/2 Keyboard (Gateway) Y Adapter .PC 2 Joysticks adapter YB . Chapter 4 Adapter Menu What does the information that is listed for each adapter mean? See the tutorial.Nullmodem adapter . 393 .Centronics to LapLink adapter Keyboard: Mouse: Joysticks: Video: Misc: .DIN to Mini-DIN Keyboard adapter .The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Macintosh Video to VGA Adapter .PS/2 Keyboard (IBM Thinkpad) Y Adapter .Amiga 4 Joysticks adapter .

The texts inside parentheses will tell you at which kind of the device it will look like that. YB ET A (To the Computer). Carrier Detect Receive Data Transmit Data Data Terminal Ready 9-Pin 1 2 3 4 25-Pin 8 3 2 20 394 PR EL IM IN BETA RELEASE AR Below the pictures there is texts that describes the connectors. I illustrate this with the following advanced picture: DI (To the computer) ST RI After that there is at each page there is one or more pictures of the connectors. Holes (female connectors usually) are darkened. These are seen from the front. usually there's two connectors. Look at the example below. This means that I don't know what kind of connector it is or how it looks. First at each page there a short heading describing the adapter. Texts describing the connectors 9 PIN D-SUB FEMALE to the Computer. It may not be modified and re-distributed without the authors permission. 25 PIN D-SUB MALE to the Serialcable. Including the name of the physical connector. and NOT the soldside. It should be quite simple to read.Chapter 4: Adapter Menu Adapter Tutorial Heading The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. FO (To the computer) R RE There may be some pictures I haven't drawn yet. Contains mostly the following three columns. (To the Serialcable). Name. Short tutorial . Pin table The pin table is perhaps the information you are looking for. Sometimes when not the same pin is connected to each side there is another column describing the name at connector 2. The first is a female connector and the send a male.N OT Normally are one or more pictures. . BU Pictures of the connectors TIO N. Pin 2. Pin 1. Sometimes there is some question marks only.

N OT FO R RE DI ST RI BU All persons that helped me or sent me information about the connector will be listed here.Chapter 4: Adapter Menu System Ground Data Set Ready Request to Send Clear to Send Ring Indicator The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 5 6 7 8 9 7 6 4 5 22 395 . but I will try to fill in these in the future. Adapter Tutorial Contributor & Source Contributor: Joakim Ögren Source: Amiga 4000 User's Guide from Commodore PR EL IM IN BETA RELEASE AR YB ET A . TIO N. I must admit that I am bad at writing the source. It may not be modified and re-distributed without the authors permission. The source of the information is perhaps a book or another site.

(To the Serialcable). The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 25 PIN D-SUB FEMALE to the Computer.Chapter 4: Adapter Menu Nullmodem Adapter This adapter will enable you to use a normal serialcable as a nullmodem. PR EL IM IN BETA RELEASE AR YB ET A . 25 PIN D-SUB MALE to the Serialcable. TIO N. Shield Ground Transmit Data Receive Data Request to Send Clear to Send Data Set Ready Data Terminal Ready Ground Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. 396 Nullmodem Adapter . It may not be modified and re-distributed without the authors permission.N OT FO Female 1 2 3 4 5 6 20 7 Male 1 3 2 5 4 20 6 7 Shield Ground Receive Data Transmit Data Clear to Send Request to Send Data Terminal Ready Data Set Ready Ground R RE DI ST RI BU (To the Computer).

Chapter 4: Adapter Menu 9 to 25 Serial Adapter This adapter will enable you to connect a 25 pin serialcable to a 9 pin connector at the computer. (To the Computer). OT FO R RE DI 9 PIN D-SUB FEMALE to the Computer. RI BU TIO N. Carrier Detect Receive Data Transmit Data Data Terminal Ready System Ground Data Set Ready Request to Send Clear to Send Ring Indicator Contributor: Joakim Ögren Source: ? 9-Pin 1 2 3 4 5 6 7 8 9 25-Pin 8 3 2 20 7 6 4 5 22 PR EL IM IN BETA RELEASE AR YB ET A . ST (To the Serialcable).N Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission. 25 PIN D-SUB MALE to the Serialcable. 9 to 25 Serial Adapter 397 . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

Centronics to LapLink Adapter 398 . It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .cz> Please send any comments to Joakim Ögren. 25 PIN D-SUB MALE to the Computer.Chapter 4: Adapter Menu Centronics to LapLink Adapter This adapter will allow you to use a normal printercable (Centronics) as a LapLink/InterLink cable.firstnet. (To the Printer cable) (To the Computer) 36 PIN CENTRONICS FEMALE to the Printer cable.N 36-Cen 2 3 4 5 6 10 11 12 13 32 16 17 19-30+33 25-DSub 15 13 12 10 11 5 6 4 3 2 16 17 18-25 Name Error Select Paper Out Acknowledge Busy Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 1 Data Bit 0 Reset Select Signal Ground OT FO R RE DI ST RI BU TIO N. Name Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Acknowledge Busy Paper Out Select Error Reset Select Signal Ground Source: ? Contributor: Joakim Ögren. Petr Krc <magneton@mail. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

Shield Data Ground +5 VDC Clock Source: ? Please send any comments to Joakim Ögren.N OT FO Contributor: Joakim Ögren. Gilles Ries <gries@glo. It may not be modified and re-distributed without the authors permission.be> R Mini-DIN DIN Shield Shield 1 2 3 4 4 5 5 1 RE DI ST RI BU TIO N. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 5 PIN DIN 180° (DIN41524) MALE to the computer. PR EL IM IN BETA RELEASE AR YB ET A . Mini-DIN to DIN Keyboard Adapter 399 .Chapter 4: Adapter Menu Mini-DIN to DIN Keyboard Adapter This adapter will enable you to use a keyboard with a 6 pin Mini-DIN connector to a computer with a 5 pin DIN connector. (To the keyboard) (To the computer) 6 PIN MINI-DIN FEMALE (PS/2 STYLE) to the keyboard.

(To the keyboard) (To the computer) 5 PIN DIN 180° (DIN41524) FEMALE to the keyboard. Shield Clock Data Ground +5 VDC Source: ? Please send any comments to Joakim Ögren.Chapter 4: Adapter Menu DIN to Mini-DIN Keyboard Adapter This adapter will enable you to use a keyboard with a 5 pin DIN connector to a computer with a 6 pin Mini-DIN connector. PR EL IM IN BETA RELEASE AR YB ET A . Gilles Ries <gries@glo.be> R DIN Shield 1 2 4 5 Mini-DIN Shield 5 1 3 4 RE DI ST RI BU TIO N. 6 PIN MINI-DIN MALE (PS/2 STYLE) to the computer. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.N OT FO Contributor: Joakim Ögren. DIN to Mini-DIN Keyboard Adapter 400 .

edu> PR EL IM IN BETA RELEASE AR YB ET A Please send any comments to Joakim Ögren.N OT ComputerKeyboardMouse 1 2 2 2 3 3 3 4 4 4 5 6 6 6 FO R RE 6 PIN MINI-DIN MALE (PS/2 STYLE) to the Computer. DI ST RI BU TIO N.vt. 6 PIN MINI-DIN FEMALE (PS/2 STYLE) to the Keyboard. . For Gateway computer. It may not be modified and re-distributed without the authors permission. may work with other computers (Let me know).cs. PS/2 Keyboard (Gateway) Y Adapter 401 .edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad. Gilles Ries <gries@glo.Chapter 4: Adapter Menu PS/2 Keyboard (Gateway) Y Adapter This adapter will enable you to use a keyboard and mouse at the same time. 6 PIN MINI-DIN FEMALE (PS/2 STYLE) to the Mouse.be> Source: Tommy's pinout Collection <http://csgrad. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.vt. (To the Computer) (To the Keyboard) (To the Mouse) Contributor: Joakim Ögren.cs.

Chapter 4: Adapter Menu PS/2 Keyboard (IBM Thinkpad) Y Adapter This adapter will enable you to use a keyboard and mouse at the same time. (To the Computer) (To the Keyboard) (To the Mouse) Contributor: Joakim Ögren. 6 PIN MINI-DIN FEMALE (PS/2 STYLE) to the Mouse. may work with other computers (Let me know).cs. DI ST RI BU TIO N.edu> PR EL IM IN BETA RELEASE AR YB ET A Please send any comments to Joakim Ögren.edu/~tjohnson/pinouts> by Tommy Johnson <tjohnson@csgrad.2 3 3 3 4 4 4 5 6 5 6 6 FO R RE 6 PIN MINI-DIN MALE (PS/2 STYLE) to the Computer.vt. PS/2 Keyboard (IBM Thinkpad) Y Adapter 402 . For IBM Thinkpad computer. 6 PIN MINI-DIN FEMALE (PS/2 STYLE) to the Keyboard.vt.be> Source: Tommy's pinout Collection <http://csgrad. Gilles Ries <gries@glo. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT ComputerKeyboardMouse 1 2 2 1. It may not be modified and re-distributed without the authors permission. .cs.

(To the computer) 6 PIN MINI-DIN FEMALE to the mouse.Chapter 4: Adapter Menu PS/2 to Serial Mouse Adapter This adapter will enable you to use a mouse with a 6 pin Mini-DIN (PS/2) connector to a computer with a 9 pin D-SUB (Serial) connector. PR EL IM IN BETA RELEASE AR YB ET A . 9 PIN D-SUB FEMALE to the computer.uni-erlangen. Tomas Ögren <stric@ts. It may not be modified and re-distributed without the authors permission. GND RxD TxD +5V Mini-DIN D-SUB 3 5 2 2 6 3 4 7 GND RxD TxD RTS Contributor: Joakim Ögren. Thomas Eschenbacher <Thomas.Eschenbacher@stud.N OT Source: ? FO R RE DI ST RI (To the mouse) BU TIO N. A mouse like this is sometimes referred to as a combo-mouse. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.se>. This requires that the mouse handles both protocols.umu.H.de> Please send any comments to Joakim Ögren. PS/2 to Serial Mouse Adapter 403 .

Thomas Eschenbacher <Thomas. Tomas Ögren <stric@ts.se>.N OT Source: ? FO R RE DI ST RI BU TIO N.Eschenbacher@stud. 6 PIN MINI-DIN MALE to the computer. It may not be modified and re-distributed without the authors permission. +5V Data Gnd Clock Mini-DIN D-SUB 4 4+7+9 1 1 3 3+5 5 6 DTR+RTS+RI CD TXD+GND DSR Contributor: Joakim Ögren.umu.de> Please send any comments to Joakim Ögren. A mouse like this is sometimes referred to as a combo-mouse.uni-erlangen. PR EL IM IN BETA RELEASE AR YB ET A . This requires that the mouse handles both protocols. (To the mouse) (To the computer) 9 PIN D-SUB MALE to the mouse. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.H. Serial to PS/2 Mouse Adapter 404 .Chapter 4: Adapter Menu Serial to PS/2 Mouse Adapter This adapter will enable you to use a mouse with a 9 pin D-SUB (Serial) connector to a computer with a 6 pin Mini-DIN (PS/2) connector.

9 PIN D-SUB MALE to the 2nd Joystick.Chapter 4: Adapter Menu Amiga 4 Joysticks Adapter This adapter will make it possible to connect 2 extra joysticks to the Amiga.com> Source: Tomi Engdahl's Joystick page <http://www.html> Please send any comments to Joakim Ögren. Rob Gill <gillr@mailcity. 25 PIN D-SUB MALE to the Parallelcable. It may not be modified and re-distributed without the authors permission. RE (To the Computer). Amiga 4 Joysticks adapter 405 . PR EL IM IN BETA RELEASE AR YB ET A Up 1 Down 1 Left 1 Right 1 Up 2 Down 2 Left 2 Right 2 Fire 2 Fire 1 Ground 2 Ground 1 Parport Joy 1 Joy 2 2 1 3 2 4 3 5 4 6 1 7 2 8 3 9 4 11 6 13 6 18 8 19 8 . This requires that the game is aware of this Multi-Joystick Extender in order to use it. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. The adapter is connected to the parallelport of the Amiga. (To the 2nd Joystick). (To the 1st Joystick). DI ST RI BU TIO N.hut.fi/~then/circuits/joystick. Contributor: Joakim Ögren .N OT FO R 9 PIN D-SUB MALE to the 1st Joystick.

X Ground Ground Joystick 1 . (To the Computer) (To the 1st Joystick) Note: Since pin 12 is often used for MIDI-signals on gameport equipped soundcards it's better to use the ground from pin 4 & 5. The gameport contains pins for two joysticks but you will need this adapter to be able to connect two joysticks to one connector.Y Button 2 +5 VDC +5 VDC Button 4 Joystick 2 .N OT FO R 15 PIN D-SUB MALE to the Computer.Chapter 4: Adapter Menu PC 2 Joysticks Adapter This adapter will make it possible to connect 1 extra joystick to the PC.html> Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission. pin 15 is also used for MIDI-signals. Contributor: Joakim Ögren Source: Tomi Engdahl's Joystick page <http://www. PC 2 Joysticks adapter 406 .hut.X Ground Joystick 2 . 15 PIN D-SUB FEMALE to the 1st Joystick.. RE (To the 2nd Joystick) DI ST RI BU TIO N.. 15 PIN D-SUB FEMALE to the 2nd Joystick.Y Button 3 +5 VDC PC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Joy 1 Joy 2 1 2 3 4 4 5 5 6 7 8 9 1 10 2 11 3 12 13 6 14 7 15 8 ET A .fi/~then/circuits/joystick. PR EL IM IN BETA RELEASE AR YB +5 VDC Button 1 Joystick 1 . The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

cse. (To the Monitor-cable) 15 PIN D-SUB MALE to the Computer.edu.Chapter 4: Adapter Menu Macintosh Video to VGA Adapter Use this adapter to connect a standard VGA (or higher) monitor to your Apple Macintosh. 15 PIN HIGHDENSITY D-SUB FEMALE to the Monitor-cable.rmit.au> Please send any comments to Joakim Ögren. Macintosh to VGA Video 407 . It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A . Description Red Ground Red Composite sync Monitor Sense 0 Green Green Ground Monitor Sense 1 No connection Blue Monitor sense 2 Sync Ground Vertical Sync Blue Ground Horizontal Sync Ground Horizontal Sync Source: ? Contributor: Joakim Ögren.N Mac 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VGA Dir 6 1 13 4 2 7 11 n/c 3 12 10 14 8 n/c n/c OT FO R RE DI ST RI BU (To the Computer) TIO N. Michael Van den Acker <rdsmv@huntsman. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.

Ground Ground Ground +5V n/c Reset A1000 14 15 16 23 24 25 Amiga 23 24 25 14 15 16 All other straight over.. A1000 to Amiga Parallel Adapter 408 . 1 to 1. (To the Amiga peripheral).Chapter 4: Adapter Menu A1000 to Amiga Parallel Adapter This adapter will enable you to connect normal Amiga peripherals to an Amiga 1000. The Amiga 1000 has a male connector at the computer instead of a normal female connector. PR EL IM IN BETA RELEASE AR YB ET A . 2 to 2. 25 PIN D-SUB FEMALE to the Amiga peripheral. The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST RI BU TIO N. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. (To the Amiga 1000). And some signals has changed places. 25 PIN D-SUB FEMALE to the Amiga 1000. It may not be modified and re-distributed without the authors permission..

Linkwitz 4th order Highpass (C) Joakim Ögren 1996.Bessel 4th order Lowpass .Linkwitz 4th order Lowpass .Bessel 2nd order Highpass .Bessel 2nd order Lowpass .Butterworth 1st order Lowpass .Butterworth 3rd order Lowpass . YB ET A . 409 .The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.Bessel 3rd order Highpass .Butterworth 1st order Highpass . Basic circuit blocks Active Filters: .Bessel 3rd order Lowpass . Chapter 5 Circuit Menu Need help with the circuits? See the tutorial.Bessel 4th order Highpass . It may not be modified and re-distributed without the authors permission.Butterworth 4th order Lowpass .Butterworth 2nd order Highpass .Butterworth 4th order Highpass .Butterworth 3rd order Highpass .Butterworth 2nd order Lowpass .1997 PR EL IM IN BETA RELEASE AR Last updated 1997-11-17.N OT FO R RE DI ST RI BU TIO N.

I illustrate this with the following advanced picture: DI (At the computer) ST RI After that there is at each page there is one or more pictures of the connectors. FO (At the computer) R RE There may be some pictures I haven't drawn yet.Chapter 5: Circuit Menu Circuit Tutorial Heading The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Sometimes there is some question marks only. Including the name of the physical connector.N OT Normally are one or more pictures. Look at the example below. BU Pictures of the connectors TIO N. It may not be modified and re-distributed without the authors permission. Pin table Pin 1 2 3 4 5 The pin table is perhaps the information you are looking for. YB ET A (At the videocard) . Should be simple to read. These are seen from the front. The texts insde parentheses will tell you at which kind of the device it will look like that. and NOT the soldside. First at each page there a short heading describing what the connector is. This means that I don't know what kind of connector it is or how it looks. Holes (female connectors usually) are darkened. Contains mostly the following three columns. Pin. (At the monitor cable) Texts describing the connectors 5 PIN DIN 180° (DIN41524) at the computer. The first is a female connector and the send a male. Name & Description. Name CLOCK GND DATA VCC n/c Description Key Clock GND Key Data +5 VDC Not connected Contributor & Source PR EL IM IN BETA RELEASE AR Below the pictures there is texts that describes the connectors. 410 Short tutorial .

but I will try to fill in these in the future.Chapter 5: Circuit Menu Circuit Tutorial Contributor: Joakim Ögren Source: Amiga 4000 User's Guide from Commodore The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . All persons that helped me or sent me information about the connector will be listed here. I must admit that I am bad at writing the source. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI ST RI BU TIO N. The source of the information is perhaps a book or another site. 411 .

000/(2*pi*Fc*R) RI BU TIO N. Lowpass) . Fc [Hz] Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. C [F]. It may not be modified and re-distributed without the authors permission.Chapter 5: Circuit Menu Active Filter: Butterworth 6dB Lowpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST R=4.7k-10 kOhm C=1. Units: R [Ohm]. PR EL IM IN BETA RELEASE AR YB ET A . 412 Active Filter: Butterworth (1st order. 6 dB/octave.

Highpass) .Chapter 5: Circuit Menu Active Filter: Butterworth 6dB Highpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. Units: R [Ohm].000/(2*pi*Fc*C) RI BU TIO N. Fc [Hz] Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. C [F]. 6 dB/octave. PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI ST C=4.7n-10nF R=1. 413 Active Filter: Butterworth (1st order.

7071/(2*pi*Fc*R) RI BU TIO N. Fc [Hz] ST R=4. Cx [F].Chapter 5: Circuit Menu Active Filter: Butterworth 12dB Lowpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI Units: R [Ohm]. 414 Active Filter: Butterworth (2nd order. 12 dB/octave.7k-10 kOhm Ca=1. PR EL IM IN BETA RELEASE AR YB ET A .414/(2*pi*Fc*R) Cb=0. It may not be modified and re-distributed without the authors permission. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. Lowpass) .

414/(2*pi*Fc*C) RI BU TIO N.Chapter 5: Circuit Menu Active Filter: Butterworth 12dB Highpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 415 Active Filter: Butterworth (2st order.7071/(2*pi*Fc*C) Rb=1. Highpass) . 12 dB/octave. Fc [Hz] ST C=4. C [F].7n-10nF Ra=0.N OT FO R RE DI Units: Rx [Ohm]. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . It may not be modified and re-distributed without the authors permission.

Chapter 5: Circuit Menu Active Filter: Butterworth 18dB Lowpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . 416 Active Filter: Butterworth (3st order.500/(2*pi*Fc*R) Cc=1. Lowpass) . Fc [Hz] Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.N OT FO R RE DI R=4.000/(2*pi*Fc*R) ST RI BU TIO N. Units: R [Ohm]. 18 dB/octave. It may not be modified and re-distributed without the authors permission.7k-10 kOhm Ca=2.000/(2*pi*Fc*R) Cb=0. Cx [F].

000/(2*pi*Fc*C) ST RI BU TIO N.7n-10nF Ra=0. Highpass) . C [F]. PR EL IM IN BETA RELEASE AR YB ET A .Chapter 5: Circuit Menu Active Filter: Butterworth 18dB Highpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 417 Active Filter: Butterworth (3st order. Units: Rx [Ohm]. 18 dB/octave.000/(2*pi*Fc*C) Rc=1. Fc [Hz] Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.N OT FO R RE DI C=4.500/(2*pi*Fc*C) Rb=2. It may not be modified and re-distributed without the authors permission.

It may not be modified and re-distributed without the authors permission.N OT FO R RE DI R=4.0824/(2*pi*Fc*R) Cb=0.3827/(2*pi*Fc*R) ST RI BU TIO N. PR EL IM IN BETA RELEASE AR YB ET A .6130/(2*pi*Fc*R) Cd=0. 418 Active Filter: Butterworth (4th order. Fc [Hz] Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. 24 dB/octave. Cx [F].7k-10 kOhm Ca=1. Units: R [Ohm]. Lowpass) .Chapter 5: Circuit Menu Active Filter: Butterworth 24dB Lowpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.9239/(2*pi*Fc*R) Cc=2.

9239/(2*pi*Fc*C) Rb=1. It may not be modified and re-distributed without the authors permission. Units: Rx [Ohm].0824/(2*pi*Fc*C) Rc=0.Chapter 5: Circuit Menu Active Filter: Butterworth 24dB Highpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Highpass) . PR EL IM IN BETA RELEASE AR YB ET A .3827/(2*pi*Fc*C) Rd=2. C [F].N OT FO R RE DI C=4. 24 dB/octave.6130/(2*pi*Fc*C) ST RI BU TIO N. 419 Active Filter: Butterworth (4th order.7n-10nF Ra=0. Fc [Hz] Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.

N OT FO R RE DI Units: R [Ohm]. PR EL IM IN BETA RELEASE AR YB ET A . Fc [Hz] ST R=4.Chapter 5: Circuit Menu Active Filter: Bessel 12dB Lowpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 420 Active Filter: Bessel (2nd order. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. Cx [F].9076/(2*pi*Fc*R) Cb=0. It may not be modified and re-distributed without the authors permission.6809/(2*pi*Fc*R) RI BU TIO N. 12 dB/octave.7k-10 kOhm Ca=0. Lowpass) .

Chapter 5: Circuit Menu Active Filter: Bessel 12dB Highpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Fc [Hz] ST C=4. Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. Highpass) .1017/(2*pi*Fc*C) Rb=1.N OT FO R RE DI Units: Rx [Ohm]. It may not be modified and re-distributed without the authors permission. 12 dB/octave. 421 Active Filter: Bessel (2st order.7n-10nF Ra=1. PR EL IM IN BETA RELEASE AR YB ET A .4688/(2*pi*Fc*C) RI BU TIO N. C [F].

422 Active Filter: Bessel (3st order. PR EL IM IN BETA RELEASE AR YB ET A . Cx [F]. Units: R [Ohm]. 18 dB/octave.4998/(2*pi*Fc*R) Cc=0.7560/(2*pi*Fc*R) ST RI BU TIO N. Lowpass) .Chapter 5: Circuit Menu Active Filter: Bessel 18dB Lowpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Fc [Hz] Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.N OT FO R RE DI R=4.7k-10 kOhm Ca=0.9548/(2*pi*Fc*R) Cb=0. It may not be modified and re-distributed without the authors permission.

Units: Rx [Ohm]. 18 dB/octave.0474/(2*pi*Fc*C) Rb=2.N OT FO R RE DI C=4.0008/(2*pi*Fc*C) Rc=1.7n-10nF Ra=1. C [F]. PR EL IM IN BETA RELEASE AR YB ET A . Fc [Hz] Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. It may not be modified and re-distributed without the authors permission.3228/(2*pi*Fc*C) ST RI BU TIO N. Highpass) .Chapter 5: Circuit Menu Active Filter: Bessel 18dB Highpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 423 Active Filter: Bessel (3st order.

It may not be modified and re-distributed without the authors permission. Cx [F]. Lowpass) .Chapter 5: Circuit Menu Active Filter: Bessel 24dB Lowpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.6699/(2*pi*Fc*R) Cc=1.0046/(2*pi*Fc*R) Cd=0. Units: R [Ohm].N OT FO R RE DI R=4. Fc [Hz] Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A . 424 Active Filter: Bessel (4th order.3872/(2*pi*Fc*R) ST RI BU TIO N.7k-10 kOhm Ca=0.7298/(2*pi*Fc*R) Cb=0. 24 dB/octave.

Units: Rx [Ohm]. Highpass) . Fc [Hz] Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. C [F].7n-10nF Ra=1.9952/(2*pi*Fc*C) Rd=2. 24 dB/octave. It may not be modified and re-distributed without the authors permission.N OT FO R RE DI C=4.5830/(2*pi*Fc*C) ST RI BU TIO N.4929/(2*pi*Fc*C) Rc=0.Chapter 5: Circuit Menu Active Filter: Bessel 24dB Highpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. 425 Active Filter: Bessel (4th order.3701/(2*pi*Fc*C) Rb=1. PR EL IM IN BETA RELEASE AR YB ET A .

Fc [Hz] Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. Lowpass) . 24 dB/octave.Chapter 5: Circuit Menu Active Filter: Linkwitz 24dB Lowpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.N OT FO R RE DI ST R=4.7k-10 kOhm Ca=Cc=2*Cb Cb=Cd=1/(2*sqr(2)*pi*Fc*R) RI BU TIO N. 426 Active Filter: Linkwitz (4th order. PR EL IM IN BETA RELEASE AR YB ET A . Cx [F]. Units: R [Ohm]. It may not be modified and re-distributed without the authors permission.

N OT FO R RE DI ST C=4.Chapter 5: Circuit Menu Active Filter: Linkwitz 24dB Highpass The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Fc [Hz] Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren. 427 Active Filter: Linkwitz (4st order. It may not be modified and re-distributed without the authors permission. 24 dB/octave. Units: Rx [Ohm]. C [F]. Highpass) . PR EL IM IN BETA RELEASE AR YB ET A .7n-10nF Ra=Rc=1/(2*sqr(2)*pi*Fc*C) Rb=Rd=2Ra RI BU TIO N.

PR EL IM IN YB ET A .N OT FO R RE DI Misc Menu Background & Information: AR Chapter 6 ST RI BU BETA RELEASE TIO N.The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.SCSI Information .DTE & DCE Definitions: (C) Joakim Ögren 1996. It may not be modified and re-distributed without the authors permission. .1997 Last updated 1997-11-17. 428 .

It allows you to connect harddisks.2 was formed. SCSI is in opposite to IDE/ATA very flexible. CD-R units. Contributors: Joakim Ögren Source: From the head of Joakim Ögren PR EL IM IN Please send any comments to Joakim Ögren. BETA RELEASE AR YB ET A . The protocol was named Shugart Associates Systems Interface.131-1996. Uses 16 bits instead of the original 8 bits. SCSI-II devices was released in 1988 and was an official standard in 1994. tape devices. BU It all started back in 1979 when the diskdrive manufacturer come with the bright idea to make a new transfer protocol.Chapter 6: Misc Menu SCSI Information Background The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. scanners and tapedrives. CD-ROMs. TIO N. printers and many other devices.N SCSI-II adds support for CD-ROM's. DVD. scanners. Usage SCSI Short for Small Computer Systems Interface. DI ST RI Common Command Set. OT FO R Definitions RE SCSI is used to connect peripherals to an computer. Today SCSI is most often used servers and other computers which require very good performance. SCSI-II Fast SCSI-II Wide SCSI-II Ultra SCSI-III Uses the busspeed of 10MHz instead of the original 5MHz. was added in 1985. This protocol wasn't an ANSI standard. Busspeed 5 MHz. Small Computer Systems Interface. ANSI standard X3. CCS. It may not be modified and re-distributed without the authors permission. The original SCSI protocol. so NCR join Shugart and the ANSI committee X3T9. Datawidth 8 bits. SASI. SCSI Information 429 . The new name for the protocol was. ANSI finished the SCSI standard in 1986. IDE/ATA is more popular due to the fact that IDE/ATA devices tend to be cheaper. SCSI-III is currently not yet official. SCSI. Uses the busspeed of 20MHz.

430 Definition: DTE & DCE . With opposite signals I mean for example Transmit & Receive. Rob Gill <gillr@mailcity. Examples of DTE is computers. Examples of DCE is modems. PR EL IM IN BETA RELEASE AR YB ET A . Lane <rlane@eastman. It may not be modified and re-distributed without the authors permission.com> . DTE is acronym for Data Terminal Equipment. printers & terminals.N OT FO Source: ? R Contributors: Joakim Ögren .com> RE But wiring a cable for DTE to DTE (nullmodem) or DCE to DCE requires that some wires are crossed.Chapter 6: Misc Menu Defintion: DTE & DCE DTE The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. Wiring Please send any comments to Joakim Ögren. Richard L. ST RI BU TIO N. DCE DCE is acronym for Data Communication Equipment. All wires goes straight from pin x to pin x. DI Wiring a cable for DTE to DCE communication is easy. A signal should be wired from pin x to the opposite signal at the other end.

American Wire Gauge standard .N OT FO R RE DI Table Menu . Is 1 kW equal 1000000mW ? AR Chapter 7 ST RI BU BETA RELEASE TIO N. It may not be modified and re-distributed without the authors permission. (C) Joakim Ögren 1996. 431 .The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.AWG. PR EL IM IN YB ET A .1997 Last updated 1997-11-17.SI Prefixes .

60 A 9. 432 AWG .64 0.95 1.17 0.08 0.04 0.013 0.0 A 7.85 0.2 1.1 2.30 0.57 6.33 0.16 A 38.0064 0.5 588 72.70 0. PR EL IM IN BETA RELEASE AR YB ET A .6 2.57 0.6 1.00 1.80 0.7 850 51.44 0.20 0.38 A 13.049 0.4 A RI BU TIO N.50 0.Chapter 7: Table Menu AWG Table AWG=American Wire Gauge standard The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.45 0.90 0.50 0.71 0.N OT FO R RE 34 DI 36 35 ST Gauge AWG 46 44 42 41 40 39 38 37 Diam mm 0.51 A 30.40 0.60 1.40 1.8 2.75 0.15 0.20 0.071 0.011 0.19 0.096 0.24 0.07 0.0 3.023 0.0 2.91 A 24.18 0.2 3.5 1.3 1.8 8750 6 6070 9 4460 12 3420 15 2700 19 2190 24 1810 28 1520 33 1300 40 1120 45 970 54 844 60 757 68 676 75 605 85 547 93 351 147 243 212 178 288 137 378 108 477 87.09 0.2 4.0078 0.031 0.55 0.70 5.78 0.0050 0.9 2.12 0.0013 0. It may not be modified and re-distributed without the authors permission.50 1.47 9.11 0.12 A 21.0020 0.30 A 8.5 A 5.32 A 34.60 0.10 0.7 A 6.0039 0.0095 0.10 1.65 0.95 1.80 1.05 8.28 0.13 0.54 6.1 R I at 3A/mm2 ohm/km mA 13700 3.16 0.20 1.3 715 60.76 7.1 1.05 0.90 2.9 1.00 Area mm2 0.16 0.026 0.85 A 15.7 1.0028 0.9 1.06 0.3 2.25 0.028 0.020 0.39 0. 33 32 30 29 27 26 25 24 22 20 19 18 16 14 13 12 Contributor: Joakim Ögren Source: ? Please send any comments to Joakim Ögren.3 2.97 A 11.6 A 6.1 1.0 A 44.30 1.70 1.015 0.36 A 18.13 0.14 0.018 0.70 A 26.35 0.8 3.

433 SI Prefixes . It may not be modified and re-distributed without the authors permission. Haudy Kazemi <hkazemi@geocities.com>.Chapter 7: Table Menu SI Prefixes Table Example: 1 TW=1000 GW (W=Watt) The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.de> .urz.uni-heidelberg. PR EL IM IN BETA RELEASE AR YB ET A Contributor: Joakim Ögren. Knut Kristan Weber <kweber@ix. Note: In the computer world things are a bit different: Symbol Prefix Factor Factor P peta 250 1125899906842624 T tera 240 1099511627776 G giga 230 1073741824 M Mega 220 1048576 k kilo 210 1024 Source: Farnell Components Catalogue Please send any comments to Joakim Ögren.N OT FO Symbol Prefix Factor Z Zetta 1021 E Exa 1018 P peta 1015 T tera 1012 G giga 109 M Mega 106 k kilo 103 h hecto 102 da deca 101 d deci 10-1 c centi 10-2 m milli 10-3 µ micro 10-6 n nano 10-9 p pico 10-12 f femto 10-15 a atto 10-18 z zepto 10-21 y yokto 10-24 R RE DI ST RI BU TIO N.

let me know. It may not be modified and re-distributed without the authors permission. if you like to see HwB in some other format.1997 PR EL IM IN BETA RELEASE AR YB ET A . 434 .blackdown. feel free to send an e-mail.N OT FO R Visit HwB at Internet <http://www. And btw. These versions is currently to be considered as beta. Since these are converted from HTML the result may sometimes look a little bit strange. DI ST RI BU TIO N.The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.html> to download these versions. RE The Hardware Book is available in some other formats as well.org/~hwb/hwb. Chapter 8 Download Menu (C) Joakim Ögren 1996. If there is some major visual errors or if a link does not work.

org> Note: It's a low traffic mailing list. 435 .blackdown.org <hwb-news-request@www.News concerning HwB. Joakim Ögren. . the HwB-News letter may be something for you.blackdown.1997 PR EL IM IN BETA RELEASE AR YB ET A . Unsubscribe whenever you want.blackdown.N The mailing list is not a discussion mailinglist.org <hwb-news-request@www. It only contains mail from me. every mail contains unsubscribe instructions. It may not be modified and re-distributed without the authors permission.Info about HwB errors/typos. . Chapter 9 HwB-News Menu To subscribe to the HwB-News mailinglist send a mail with the text SUBSCRIBE in the body to hwb-news-request@www.org> FO If you would like to be informed about what's happening with the Hardware Book.Updates of The Hardware Book .blackdown.The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It will contain: . (C) Joakim Ögren 1996.Related WWW Links R RE DI ST RI BU TIO N. OT To unsubscribe to the HwB-News mailinglist send a mail with the text UNSUBSCRIBE in the body to hwb-news-request@www.

Nec PC-FX connectors .1997 PR EL IM IN I am especially searching for the following standards: .The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. DI ST RI BU TIO N. 436 .Kenwood CD-Player RS232-port (For example DP-M7750).JVC bus? . Don't hesitate to send some strange pinout.N OT FO R RE Please help me make this reference guide larger.Qbus .GIO .PC-Engine/TurboGrafix 16 connectors .. SEND it to me :-) If it does not have one you could send me a circuit on how to add a serial-port to it.MULTIBUS .STEbus .MULTIBUS II . . It may not be modified and re-distributed without the authors permission.SA1000 .FutureBus+ . circuit or cable.Filters If you have any of the above listed please send an e-mail to Joakim Ögren .40 pin diskdrive connector (not IDE.IEEE1394 Firewire . (C) Joakim Ögren 1996.XTA Interface BETA RELEASE AR YB ET A . . :-) I have already heard from two people that has a serial port on their dish-washers :) Other information of value: .EIB .MTM-Bus .SMP16 .SBus . I guess there is much more to add.) .Epson Sample E04974 Diskdrive with Signals+Power in the usual 34 pin connector. Chapter 10 Wanted If you have a strange serial-port on your dish-washer.IBM PS/2 Motherboard Power connector .ECB .

Marco Budde maintainer of the HwB Linux Debian package. It may not be modified and re-distributed without the authors permission. With the help of many contributors HwB has grown. Rob Gill for sending me many nice pinouts etc.N OT FO R RE I would like to thank the following people: Niklas Edmundsson for helping me find some of the information in HwB and being a nice friend. Keep sending me mails. 437 . This is me.net. This also means that I can't guarantee that the presented information is correct. YB ET A . Tomas Ögren my brother. This makes it easier to find information for you. questions and information. I can't take the whole credit for HwB. AR I am looking for a sponsor. Joakim Ögren: Could it be even better? Perhaps if You help me. About Hardware Book The Hardware Book is a compilation of pinouts I've found from different sources. I am not trying to sell anything. I've tried to have the same style for all pages. Please send any material you have that might be of interest for this project. Karl Asha for letting me use his web-server to store HwB. Chapter 11 ST What about this? Your free reference guide to electronics.. Use it on you own risk.. BETA RELEASE DI and updated or changed RI BU TIO N. It has been developed on my sparetime and is made available to you for free. I have since the first release received a great lot of mails with suggestions.The Hardware Book is freely distributable but is copyrighted to Joakim Ögren.. PR EL IM IN All new information since the last update is marked information is marked . Send it to qtech@mailhost. for comments and helping me with HwB. if you are interested please let me know and I will tell you more. Petr Krc for sending me many nice pinouts etc.

438 .The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. (C) Joakim Ögren 1996.N OT FO R RE DI This is what I feel like doing when nothing works :-) Chapter 11: About Hardware Book AR BETA RELEASE ST RI BU TIO N.1997 PR EL IM IN YB ET A . It may not be modified and re-distributed without the authors permission.

The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. <hwb-cable@usa. Please help me categorize the e-mails: . <hwb@usa. Try DejaNews <http://www. 439 .net> .Circuits.dejanews. But please send me pinouts etc.Cable. It may not be modified and re-distributed without the authors permission.com> (C) Joakim Ögren 1996.General.net> .1997 PR EL IM IN BETA RELEASE AR YB ET A . DI RI BU TIO N.net> . Circuits for the coming Circuit-section.Pinout. General info for HwB. Chapter 12 ST Contacting the author HwB I receive many e-mails every day. <hwb-pinout@usa. Connector pinouts. <hwb-circuit@usa.N OT FO R RE I will not be able to answer any questions at the moment. please redirect these to a UseNet newsgroup instead. Cable & adapters descriptions.net> Please don't send questions like "Do you have the pinout to Xyz" or "Can you help me to repair my Xyz".

440 .5 mm Stereo Telephone plug 3.25 mm Mono Telephone plug 6.25" Power Connector 6.5 mm Mono Telephone plug 3.25 mm Stereo Telephone plug 64NET Cable 72 pin ECC SIMM Connector 72 pin SIMM Connector 72 pin SO DIMM Connector 8" Floppy Diskdrive Connector 9 to 15 pin VGA Cable 9 to 25 Serial Adapter A1000 to Amiga Parallel Adapter AT Backup Battery Connector AT LED/Keylock Connector AT&T 53D410 Connector AT&T 6300 Keyboard Connector AT&T 6300 Taxan Monitor Connector AT&T PC6300 Connector ATA (44) Internal Connector ATA Internal Connector AUI Connector AWG Table About Hardware Book Active Filter: Bessel 12dB Highpass Active Filter: Bessel 12dB Lowpass Active Filter: Bessel 18dB Highpass Active Filter: Bessel 18dB Lowpass Active Filter: Bessel 24dB Highpass Active Filter: Bessel 24dB Lowpass Active Filter: Butterworth 12dB Highpass Active Filter: Butterworth 12dB Lowpass Active Filter: Butterworth 18dB Highpass Active Filter: Butterworth 18dB Lowpass Active Filter: Butterworth 24dB Highpass Active Filter: Butterworth 24dB Lowpass Active Filter: Butterworth 6dB Highpass Active Filter: Butterworth 6dB Lowpass Active Filter: Linkwitz 24dB Highpass Active Filter: Linkwitz 24dB Lowpass Adapter Menu Adapter Tutorial Amiga 1000 RF Monitor Connector Amiga 1000 Ramex Connector Amiga 1200 CPU-port Connector Amiga 4 Joysticks Adapter Amiga External Diskdrive Connector Amiga Mouse/Joy Connector Amiga Video Connector Amiga Video Expansion Connector Amiga to C1084 Monitor Cable Amiga to SCART Cable Amstrad CPC6128 Diskdrive 2 Connector Amstrad CPC6128 Monitor Connector Amstrad CPC6128 Plus External Diskdrive Connector Amstrad CPC6128 Plus Monitor Connector Amstrad CPC6128 Printer Port Connector Amstrad CPC6128 Stereo Connector Amstrad CPC6128 Tape Connector Amstrad Digital Joystick Connector Atari 2600 Cartridge Connector Atari 2600 Joystick Connector Atari 5200 Cartridge Connector Atari 5200 Expansion Connector Atari 5200 Joystick Connector Atari 7800 Cartridge Connector Atari 7800 Expansion Connector Atari 7800 Joystick Connector Atari ACSI DMA Connector Atari Cartridge Port Connector Atari Enhanced Joystick Connector Atari Floppy Port Connector Atari Jaguar A/V Connector Atari Mouse/Joy Connector 315 260 263 267 280 281 285 253 176 284 282 283 357 256 254 258 213 381 397 408 288 289 178 211 179 180 236 234 295 432 437 421 420 423 422 425 424 415 414 417 416 419 418 413 412 427 426 393 394 162 91 88 405 214 191 161 93 382 380 216 171 217 172 144 332 252 202 296 199 297 298 200 299 300 201 151 301 198 219 168 197 Atari ST Monitor Connector C-bus II Connector C128 Expansion Bus Connector C128 RGBI Connector C128/C64C Video Connector C128/C64C to CBM 1902A Monitor Cable C128/C64C to SCART (S-Video) Cable C16/+4 Expansion Bus Connector C16/C116/+4 Audio/Video Connector C16/C116/+4 Cassette Connector C16/C116/+4 Joystick Connector C64 Audio/Video Connector C64 Cartridge Expansion Connector C64 Cassette Connector C64 Centronics Printer Cable C64 Control Port Connector C64 Power Supply Connector C64 RS232 User Port Connector C64 Serial I/O Connector C64 User Port Connector C65 Video Connector CBM 1902A Connector CD32 Expansion-port Connector CDTV Diagnostic Slot Connector CDTV Expansion Slot Connector CDTV Memory Card Connector CDTV Video Slot Connector CGA Connector CM-8/CoCo RGB Connector Cable Menu Cable Tutorial CardBus Connector Centronics Connector Centronics to LapLink Adapter Circuit Menu Circuit Tutorial Cisco Console (25) Cable Cisco Console (9) Cable Cisco Console Port Connector CoCo Cassette Connector CoCo Serial Printer Connector Commodore 1084 & 1084S (Analog) Connector Commodore 1084 & 1084S (Digital) Connector Commodore 1084d & 1084dS Connector CompactFlash Connector CompactPCI (Tech) Connector CompactPCI Connector Connector Menu Connector Top 10 Menu Connector Tutorial Conrad Electronics MM3610D (25) Cable Conrad Electronics MM3610D (9) Cable Conrad Electronics MM3610D Connector Contacting the author HwB DEC DLV11-J Serial Connector DEC Dual RS-232 Connector DIN Audio Connector DIN to Mini-DIN Keyboard Adapter Defintion: DTE & DCE Download Menu ECP Parallel (Tech) Connector ECP Parallel Connector EGA Connector EISA (Tech) Connector EISA Connector ESDI Cable ESDI Connector Ethernet 10/100Base-T Connector Ethernet 10/100Base-T Crossover Cable Ethernet 10/100Base-T Straight Thru Cable Ethernet 100Base-T4 Connector Ethernet 100Base-T4 Crossover Cable Floppy Cable GEOCable Cable GameBoy Cartridge Connector GeekPort Connector HwB-News Menu IDE Cable IDE Internal Connector ISA (Tech) Connector ISA Connector 173 109 311 184 185 383 384 313 186 248 193 182 308 247 354 192 331 130 150 310 183 187 95 316 318 271 163 155 177 335 337 99 141 398 409 410 360 359 132 249 134 165 166 167 107 55 48 2 333 8 362 361 135 439 131 126 279 400 430 434 140 139 156 29 26 376 237 293 386 387 294 388 370 358 303 148 435 371 232 13 10 The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission. PR EL IM IN BETA RELEASE AR YB ET A .N OT FO R RE DI ST RI BU TIO N.Index +4 User Port Connector 144 pin SO DIMM Connector 168 pin DRAM DIMM (Unbuffered) Connector 168 pin SDRAM DIMM (Unbuffered) Connector 3.5" Power Connector 30 pin SIMM Connector 3b1/7300 Video Connector 5.

N OT FO R RE DI ST RI BU TIO N. 441 . It may not be modified and re-distributed without the authors permission.Index IndustrialPCI Connector Internal Diskdrive Connector Keyboard (5 Amiga) Connector Keyboard (5 PC) Connector Keyboard (6 Amiga) Connector Keyboard (6 PC) Connector Keyboard (Amiga CD32) Connector Keyboard (XT) Connector LapLink/InterLink Parallel Cable MDA (Hercules) Connector MIDI Cable MIDI In Connector MIDI Out Connector MSX Cassette Connector MSX Expansion Connector MSX External Diskdrive Connector MSX Joystick Connector MSX Parallel Connector Mac to C64 Nullmodem Cable Mac to HP48 Cable Macintosh External Drive Connector Macintosh Keyboard Connector Macintosh Modem (With DTR) Cable Macintosh Modem (Without DTR) Cable Macintosh Mouse Connector Macintosh RS-422 Connector Macintosh Serial Connector Macintosh Video Connector Macintosh Video to VGA Adapter Mini-DIN to DIN Keyboard Adapter Miniature Card (Tech) Connector Miniature Card Connector Minuteman UPS Connector Misc Menu Misc Unsupported Cables Mitsumi CD-ROM Connector Modem (25-25) Cable Modem (9-15) Cable Modem (9-25) Cable Motherboard CPU Cooling fan Connector Motherboard IrDA Connector Motherboard Power Connector Mouse (PS/2) Connector NeoGeo Audio/Video Connector NeoGeo Joystick Connector NeoGeo to SCART Cable Novell and Procomp External SCSI Connector NuBus 90 Connector NuBus Connector Nullmodem (25-25) Cable Nullmodem (9-25) Cable Nullmodem (9-9) Cable Nullmodem Adapter PC 2 Joysticks Adapter PC Card ATA Connector PC Card Connector PC Gameport Connector PC Gameport+MIDI Connector PC Speaker Connector PC-Engine Cartridge Connector PC/104 Connector PCI (Tech) Connector PCI Connector PCMCIA Connector PGA Connector PS/2 Keyboard (Gateway) Y Adapter PS/2 Keyboard (IBM Thinkpad) Y Adapter PS/2 to Serial Mouse Adapter Panasonic CD-ROM Connector ParNet Parallel Cable ParaLoad Cable Parallel (Amiga 1000) Connector Parallel (Amiga) Connector Parallel (Olivetti M10) Connector Parallel (PC) Connector Parallel Port Loopback (CheckIt) Parallel Port Loopback (Norton) Paravision SX-1 External IDE Connector Paravision SX1 to IDE Cable PlayStation A/V Connector Printer Cable 58 212 207 204 208 205 209 206 355 158 391 329 328 250 304 215 194 142 342 363 218 210 347 348 196 127 129 160 407 399 76 74 330 428 392 242 344 350 343 292 291 286 124 170 203 385 231 81 78 341 340 339 396 406 103 101 189 190 290 319 114 37 33 105 157 401 402 403 244 356 389 138 137 143 136 365 364 241 378 164 351 RS232 Connector RS422 Connector RocketPort Serial (25) Cable RocketPort Serialport Connector S-Video Connector SCART Connector SCSI Cable (Amiga/Mac) SCSI Cable (D-Sub to Hi D-Sub) SCSI External Centronics 50 (Differential) Connector SCSI External Centronics 50 (Single-ended) Connector SCSI External D-Sub (Future Domain) Connector SCSI External D-Sub (PC/Amiga/Mac) Connector SCSI Information SCSI Internal (Differential) Connector SCSI Internal (Single-ended) Connector SCSI-II External Hi D-Sub (Differential) Connector SCSI-II External Hi D-Sub (Single-ended) Connector SGI Mouse (Model 021-0004-002) Connector SI Prefixes Table SNES Cartridge Connector SNES Video Connector SSFDC Connector ST506/412 Cable ST506/412 Connector Serial (15) Connector Serial (Amiga 1000) Connector Serial (Amiga) Connector Serial (MSX) Connector Serial (PC 25) Connector Serial (PC 9) Connector Serial (Printer) Connector Serial Port Loopback (25 CheckIt) Serial Port Loopback (25 Norton) Serial Port Loopback (9 CheckIt) Serial Port Loopback (9 Norton) Serial Printer (25-25) Cable Serial Printer (9-25) Cable Serial to PS/2 Mouse Adapter SmallPCI Connector SmartCard AFNOR Connector SmartCard ISO 7816-2 Connector SmartCard ISO Connector Sony CD-ROM Connector Spectravideo SVI318/328 Audio/Video Connector Spectravideo SVI318/328 Cassette Connector Spectravideo SVI318/328 Expansion Bus Connector Spectravideo SVI318/328 Game Cartridge Connector Sun Video Connector TG-16 Cartridge Connector Table Menu The Hardware Book (PDF) Turbo LED Connector Two-Wire Modem (25-25) Cable Two-Wire Modem (9-25) Cable Unibus Connector Universal Serial Bus (USB) (Tech) Connector Universal Serial Bus (USB) Connector VESA Feature Connector VESA LocalBus (VLB) (Tech) Connector VESA LocalBus (VLB) Connector VGA (15) Connector VGA (9) Connector VGA (VESA DDC) Connector Vic 20 Memory Expansion Connector Vic 20 Video Connector Video to TV SCART Cable Wanted X1541 Cable ZX Spectrum 128 RGB Connector ZX Spectrum AY-3-8912 Connector ZX Spectrum ULA Connector Zorro II Connector Zorro II/III Connector 117 128 349 133 278 276 372 373 224 223 229 230 429 221 220 227 226 195 433 320 169 113 374 239 125 120 121 122 119 118 123 369 367 368 366 353 352 404 73 273 274 275 246 188 251 325 327 174 322 431 1 287 346 345 115 146 145 159 45 42 153 154 152 306 181 379 436 390 175 323 324 84 86 The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. PR EL IM IN BETA RELEASE AR YB ET A .

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