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Chapters 8 Sequential Logic Design Principles Dr. Curtis Nelson

Sequential Logic Design Principles

In this chapter you will learn about: • Design techniques for circuits that use flip-flops • State diagrams • Clocked synchronous state-machines • Clocked synchronous state-machine design • Sequential circuit design using VHDL

Engr354 - Chapter 8, Brown

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Circuit Types • Combinational – output depends only on the input • Sequential – output depends on input and past behavior – Requires use of storage elements – Contents of the storage elements is called state – Circuit goes through a sequence of states as a result of changes in inputs • Synchronous – controlled by a clock Summary of Terminology • Basic cell – cross-coupled NAND/NOR • Gated latch – output may change when clk = 1 – Gated SR latch – Gated D latch – Gated JK latch • Flip-flop – output changes only on Clk edge – Master-slave – Edge-triggered – Three main types • D (very. very common. 74HC109) • Toggle (occasionally used by CAD programs) Engr354 . Brown 2 .Chapter 8. 74HC74) • JK (hardly ever used.

or more simply. state machines • A logic state is a unique set of binary values that characterize the logic status of a sequential machine at some point in time A Sequence of Logic Events Engr354 .Chapter 8. Brown 3 .Sequential Machines • Logic circuits that transition through a sequence of states are called synchronous sequential machines.

where the inputs act as a “look-up” address • Example – LUT’s.Basic Model for Sequential Machines • The most basic model contains memory. ROM’s. RAM’s. Basic Model for Sequential Machines • A model with no external inputs – the output sequence is controlled by the memory and clock only Engr354 . PLA’s.Chapter 8. Brown 4 . etc.

Basic Model for Sequential Machines • Next we add External Input capability Moore’s Model of a Sequential Machine • Next we add an Output Forming Logic block Engr354 .Chapter 8. Brown 5 .

conditional outputs.Mealy’s Model of a Sequential Machine • Next we route inputs to the output forming logic block Fully Documented State Diagram • • • • • Present states Next states Previous states Branching conditions. Brown 6 .Chapter 8. sum of branching conditions Engr354 . state code assignment Outputs. state identifier.

Chapter 8. Brown 7 .Fully Documented State Diagram • State identifier • State code assignment • Branching conditions (sum of = 1) Fully Documented State Diagram • Unconditional outputs • Conditional outputs Engr354 .

maximizing logical adjacencies in the K-maps Plot entered variable K-maps Read minimum next state decoder logic Develop output decoder logic by plotting the output K-maps Draw schematic Do a logic check by hand before wiring your circuit Design of a 2-bit Binary Up-Counter XY • Step 1 – definition (given above) • Step 2 – block diagram – no inputs (other than Clk) – 2-bit output (X. 5. 2. 7. Brown 8 .Chapter 8. 3. 4. 9. Get design specifications Make a block diagram specifying all inputs and outputs Design a state diagram using as few states as possible Make binary state assignments. 8. Y) X Clk Y 00 01 10 11 • Step 3 – state diagram State Diagram Engr354 . 6.State Machine Design Process 1.

Brown 9 .Chapter 8.Design of a 2-bit Binary Up-Counter XN+1 Next State Logic Clk 10 XY D XN 00 YN+1 D YN 01 • Step 4 – binary state assignments – same as output counting code in this example • Step 5 – truth table XN YN 0 0 1 1 0 1 0 1 XN+1 0 1 1 0 YN+1 1 0 1 0 Qn→Qn+1 0→0 0→1 1→0 1→1 D 0 1 0 1 11 State Diagram X N +1 = X N ⊕ YN YN +1 = YN Excitation Table Equations Other State Machine Design Examples • Design a 2-bit grey-code up counter • Design a 2-bit grey-code up-down counter • Use output decoder – Design a 00 → 11 → 10 → 11 and repeat counter • Use JK flip-flops • Alternative state machine architectures – Use state decoders – Use state decoders and fully addressed multiplexers for NS logic – Use state decoders and reduced order mux’s for NS logic Engr354 .

Sequential Logic Design Principles Summary In this chapter you learned about: • Design techniques for circuits that use flip-flops • State diagrams • Clocked synchronous state-machines • Clocked synchronous state-machine design • Sequential circuit design using VHDL Engr354 . Brown 10 .Chapter 8.

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