Low Power Design in CMOS

Digital Integrated Circuits

Low Power Design

© Prentice Hall 1995

Why worry about power? -- Heat Dissipation
microprocessor power dissipation source : arpa-esto
DEC 21164

Digital Integrated Circuits

Low Power Design

© Prentice Hall 1995

Evolution in Power Dissipation

Digital Integrated Circuits

Low Power Design

© Prentice Hall 1995

Why worry about power — Portability Nominal Capacity (Watt-hours / lb) 50 Rechargable Lithium 40 Ni-Metal Hydride 30 20 10 0 65 70 75 80 85 90 95 Nickel-Cadium BATTERY (40+ lbs) Year Multimedia Terminals Laptop Computers Digital Cellular Telephony Digital Integrated Circuits Low Power Design © Prentice Hall 1995 Expected Battery Lifetime increase over next 5 years: 30-40% .

Where Does Power Go in CMOS? • Dynamic Power Consumption Charging and Discharging Capacitors • Short Circuit Currents Short Circuit Path between Supply Rails during Switching •Leakage Leaking diodes and transistors Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

V dd . and f to reduce power. Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .Dynamic Power Consumption Vdd Vin CL V out E n e r g y / t r a n s i t i o n = C L * V d d2 Power = Energy/transition * f = C L * V dd 2 * f Not a function of transistor sizes! Need to reduce C L .

Revisited Power = Energy/transition * transition rate = CL * Vdd 2 * f0→ 1 = CL * Vdd2 * P0→ 1* f = CEFF * Vdd2 * f Power Dissipation is Data Dependent Function of Switching Activity CEFF = Effective Capacitance = CL * P 0→ 1 Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .Dynamic Power Consumption .

Power Consumption is Data Dependent Example: Static 2 Input NOR Gate Assume: P(A=1) = 1/2 P(B=1) = 1/2 Then: P(Out=1) = 1/4 P(0→ 1) = P(Out=0).P(Out=1) = 3/4 × 1/4 = 3/16 CEFF = 3/16 * CL Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

Transition Probabilities for Basic Gates Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

Transition Probability of 2-input NOR Gate Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

P(X=1 | B=1) Becomes complex and intractable real fast Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .Problem: Reconvergent Fanout A B Z X Reconvergence P(Z=1) = P(B=1) .

CL Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .How about Dynamic Circuits? VDD φ Mp Out In1 In2 In3 PDN φ Me Power is Only Dissipated when Out=0! CEFF = P(Out=0).

4-input NAND Gate Example: Dynamic 2 Input NOR Gate Assume: P(A=1) = 1/2 P(B=1) = 1/2 Then: P(Out=0) = 3/4 CEFF = 3/4 * CL Switching Activity Is Always Higher in Dynamic Circuits Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

Transition Probabilities for Dynamic Gates Switching Activity for Precharged Dynamic Gates P0→ 1 = P0 Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

Glitching in Static CMOS also called: dynamic hazards A B C X Z ABC X Z 101 000 U nit Delay Observe: No glitching in dynamic circuits Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

0 4..0 0 Digital Integrated Circuits 1 t (nsec) Low Power Design .0 out1 out3 out5 out7 2 3 © Prentice Hall 1995 0.0 V (Volt) out2 out4 out6 out8 2.Example 1: Chain of NOR Gates out1 1 .. out2 out3 out4 out5 6.

0 4 S15 6 2.0 0 5 10 2 3 S10 Time. ns Digital Integrated Circuits Low Power Design © Prentice Hall 1995 . Volts 4.Example 2: Adder Circuit Cin Add0 S0 Add1 S1 Add2 S2 Add14 S14 Add15 S15 Sum Output Voltage.0 Cin 5 S1 0.

How to Cope with Glitching? 0 F1 0 1 0 F2 0 2 0 F1 1 F3 0 F3 0 0 F2 1 Equalize Lengths of Timing Paths Through Design Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

0 3.0 Vin (V) 4.Short Circuit Currents Vdd Vin CL Vout 0.15 I VDD (mA) 0.0 1.0 2.05 0.0 Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .0 5.10 0.

Impact of rise/fall times on short-circuit currents VDD ISC ≈0 VDD ISC ≈IMAX Vin Vout CL Vin Vout CL Large capacitive load Small capacitive load Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

3 V 0 4 5 r 1 2 3 The power dissipation due to short circuit currents is minimized by matching the rise/fall times of the input and output signals.2 µm/1.2µm VDD = 3.Short-circuit energy as a function of slope ratio ∆E / E 8 7 6 5 4 3 2 1 0 VDD = 5 V W/L| P = 7.4µ m/1. Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .2 µm W/L| N = 2.

Static Power Consumption Vdd Istat V out CL V in=5V Pstat = P(In=1) . Istat •Dominates over dynamic consumption •Not a function of switching frequency Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .Vdd .

Leakage Vdd Vout Drain Junction Leakage Sub-Threshold Current Sub-Threshold Current Dominant Factor Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

Sub-Threshold in MOS √ ID VT =0.2 VT =0.6 VGS Lower Bound on Threshold to Prevent Leakage Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

Power Analysis in SPICE V DD i DD + Circuit Under Test Pav k i DD C R Equivalent Circuit for Measuring Power in SPICE Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

Design for Worst Case VDD V DD 1 A B 1 A F CL B 2 C D 2 4 4 2 B F 2 A A D 1 B 2 2C 2 Here it is assumed that Rp = Rn Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

1 0.30 0.5 1. Digital Integrated Circuits Low Power Design © Prentice Hall 1995 . Relatively independent of logic function and style.07 0.15 0.50 0.16 E(Vdd =5) 8-bit adder 0.20 0. Power Delay Product Improves with lowering VDD.70 0.05 P x td = E t = CL * Vdd 2 quadratic dependence 51 stage ring oscillator E(Vdd=2) E(Vdd=5) (CL) * (2) = 2 (CL) * (5) 2 E(Vdd=2) ≈0.03 1 2 5 Vdd (volts) Strong function of voltage (V 2 dependence).00 0.Reducing Vdd NORMALIZED POWER-DELAY PRODUCT 1.

00 3.50 3.00 4.7)2 Td(Vdd=5) ≈ 4 Relatively independent of logic function and style.0.00 ring oscillator multiplier clock generator 2.Lower Vdd Increases Delay 7.00 (2) * (5 .V t)2 Td(Vdd=2) microcoded DSP chip adder adder (SPICE) 2. Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .0µ m technology Td CL * V dd = I I ~ (V dd .50 5.00 4.7)2 = (5) * (2 .00 V dd (volts) 6.50 4.00 2.00 6.50 7.00 1.00 5.50 1.50 NORMALIZ ED DELAY 6.50 2.0.

But Increases Leakage Interesting Design Approach: DESIGN FOR PLeakage == PDynamic Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .Lowering the Threshold Delay I D 2V t Vdd Vt = 0 Vt = 0.2 V GS Reduces the Speed Loss.

Digital Integrated Circuits Low Power Design © Prentice Hall 1995 . Minimum sized devices are usually optimal for low-power.Transistor Sizing for Power Minimization Lower Capacitance Small W/L’ s Higher Voltage Large W/L’ s Higher Capacitance Lower Voltage Larger sized devices are useful only when interconnect dominated.

5 α=1 adder α = 1.5 1 3 W/L α=0 α = 0.0 0.7 0.5 α=2 10 © Prentice Hall 1995 LOW POWER W/L = 2 CP / (K CMIN) (if CP ≥ K CMIN ) ELSE W/L = 1 Digital Integrated Circuits Low Power Design .Transistor Sizing for Fixed Throughput I ∝ W/L CMIN Cg = W/L CMIN CMIN = Minimum sized gate (W/L=1) CP = Cwiring + CDF W /L after sizing α = CP / (K CMIN) 10 NORMALIZED ENERGY HIGH PERFORMANCE W/L >> C P / (K CMIN) 7 5 4 3 2 1.5 1.

Reducing Effective Capacitance Global bus architecture Local bus architecture Shared Resources incur Switching Overhead Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

Summary • Power Dissipation is becoming Prime Design Constraint • Low Power Design requires Optimization at all Levels • Sources of Power Dissipation are well characterized • Low Power Design requires operation at lowest possible voltage and clock speed Digital Integrated Circuits Low Power Design © Prentice Hall 1995 .

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