You are on page 1of 1

Reg. No.

I ?-ll \1.15 11 ijJ 41

f \'

d (

t~ ~

! Question Paper Code: 68357 I


M.E. DEGREE EXAMINATION~ JA..l\fUARY 2013. First Semester

VLSIDesign
VL 92121252102IVL 912110244 VL 104VLSI DESIGN TECID\~QUES

(Common to M.E. Applied Electronics) (Regulation Time : Three hours Answer ALL questions. PART A - (10 x 2 = 20 marks) 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Why is NMOS us~d as a pull dcwn-deviee? What is Fowler nordhium tunneling? Define pull-up pull-down ratio of NMOS inverter. Implement a positive latch using transmission Define charge sharing. gate,

2009/2010)

List the types of scaling of MOS devices.


Define booth recoding. List the timing parameters
Compare FPGA and CPLD.

associated with a register.

Differentiate

timing and functional simulationa,