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pART B 11.

(5 x 16 == 80 marks) Compare its result with \Vall'are


(1,..)

(a)

(1)

. 6 bit Dadda Multiplier. Deslgn a ~ 1 tree multiplier. Explain the Floor plan in detail. Or

(S)

(n)

(b)

(i) (ii)

Explain the power distribution Design a 4-bit barrel shifter.

of a chip.

(5J

(~ (~,

(ill) Design a 8 x 1 Multiplexer. 12. (a)


(i)

A precharge

bus has a loading of 10 pF. At a point in the clock eyde~ gates on their inputs turn on, T"ne is 1 pF. Calculate the change i::!(4)

64 registers with transmission input load of each register precharge voltage.

(li)

Explain design margining in detail. Or

(12

(b)

(i)

Explain the .various types of power dissipation ~ delay time of CMOS inverter in detail..

in detail,

(12)
(4)

(i)

- Explain

DC transfer characteristics of CMOS inverter in detail. (12 (4

(ii)

Discuss driving large capacitive load in detail. Or

(b)

(i) (ii)

Discuss super buffer in detail. Construct JK register operation in detail. using transmission gate-so Explain

(4) ils
8.,

(iii)

Explain dynamic CMOS design with an example. Discuss Change in threshold voltage due to body effect. Explain , . Id-Vds characteristics
uuvv.

14.

(a)

(i) (ii) (iii)

of NMOS' InveiLt.er. '''+-

(!1
Le t LU - {l8DL~ (4)
'L_ .

Determme small signal parameters VI),= 100 V, and P", =1.5- A-/HZ Or

of MOS d .'
eVlOO.

(bY

11'.....; ~plain

CMOS process technology in detail,

(16)