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Code: 9D06106c M.Tech - ΙΙ Semester Regular Examinations, November 2012 LOW POWER VLSI DESIGN (Electronics and Communication Engineering) Max Marks: 60 Answer any FIVE questions All questions carry equal marks *****

Time: 3 hours

1 2

What are the implications of low power design of IC fabrication? Explain. With the help of neat sketches explain about N-well CMOS process and standards buried collectors Bi-CMOS process and compare them in all respects. What are the different isolation techniques used in IC manufacture? Explain.

3 4

Explain about level 1, level 2, level 3 and level 4 modeling of MOSFET’s and compare them in all respects. Draw the circuits and explain about CE, GD and EF Bi-CMOS driver circuits.

5 6

Draw the circuit for two input basic full swing complementary MOS/Bipolar logic and explain its operation. What are the features of merged Bi-CMOS digital circuit? Explain with the help of any one logic gate circuit. Write short notes on evolution of latches and flip-flops.

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