FPGA Implementation of BASK-BFSK-BPSK Digital Modulators

C. Erdoğan, I. Myderrizi, and S. Minaei
Electronics and Communications Engineering Department Dogus University Zeamet Sokak 21, Acıbadem – Kadıköy, 34722 Istanbul, Turkey E-mail: imyderrizi@dogus.edu.tr, sminaei@dogus.edu.tr

Abstract
Field-programmable gate-array (FPGA) implementations of binary amplitude-shift keying (BASK), binary frequencyshift keying (BFSK), and binary phase-shift keying (BPSK) digital modulators are presented. The proposed designs are aimed at educational purposes in a digital communication course. They employ the minimum number of blocks necessary for achieving BASK, BFSK, and BPSK modulation, and for full integration with the other functional parts of the Altera Development and Education (DE2) FPGA board. The input carrier signal and the bit stream (modulating signal) are user controllable. These digital modulators were developed and compiled to a Verilog Hardware Description Language (HDL) netlist, and were later implemented into an Altera DE2 FPGA board. The functionality of these digital modulators was demonstrated through simulations using the Quartus II simulation software, and experimental measurements of the real-time modulated signal via an oscilloscope. Keywords: BASK; BFSK; BPSK; binary; digital modulator; FPGA; amplitude shift keying; frequency shift keying; phase shift keying; field programmable gate arrays

F

1. Introduction

ield-programmable gate arrays (FPGAs) are semiconductor devices containing programmable logic elements (LEs) and a hierarchy of reconfigurable interconnects to realize any complex combinational or sequential logic functions [1]. Hardware implemented in an FPGA can be reconfigured by programming the logic elements and interconnections for specific applications, even after the product has been installed in the field. Today’s FPGAs consist of configurable embedded static random-access memories (SRAMs), high-speed transceivers, high-speed input/output (I/O) elements, network interfaces, and even hard-embedded processors [1]. A literature survey shows that FPGAs are widely used in different applications, such as motor controllers [2], neuralnetwork implementations [3-5], finite-impulse-response (FIR) filter realization [6, 7], fuzzy-logic controllers [8], etc. On the other hand, implementation of digital modulation and demodulation using FPGAs has received considerable attention. Signal-processing systems such as software-defined radios (SDRs) can receive various kinds of modulated signals via software programming using digital signal processors (DSPs),

FPGAs, general purpose processors (GPPs), and applicationspecific integrated circuits (ASICs) [9, 10]. In this context, FPGAs are the best solution, due to their high flexibility, low cost, and high speed [10]. A block diagram of a software-defined radio transmitter employing binary amplitude-shift keying (BASK) or binary phase-shift keying (BPSK) modulation is shown in Figure 1. The input bit is transferred to G b as a “0” or “1” in BASK and as a −1 or 1 in BPSK. The D/A block converts the digital IF signal into the analog IF signal, the RF up converter transforms the analog IF signal to RF frequencies, and, finally, the poweramplifier block boosts the RF signal to the antenna [11]. Since digital modulation is less complex, more secure, and more efficient in long-distance transmission and noise detection/correction than its analog counterpart, it has an important place in modern communications. Several papers that include applications using digital-modulation techniques have been presented in the literature, including detectors [12], transmitters [10], and baseband processors [13] employing BPSK modulators; a digital receiver for software-defined radios based on quadrature phase-shift keying (QPSK) or quadrature amplitude-modulation (QAM) techniques [14, 15]; and BASK, BPSK, and binary frequency-shift keying (BFSK) digital

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Figure 1. A block diagram of a software-defined radio transmitter. modulators to be used in communications systems [16, 17]. All of these papers have in common the design of models in the MATLAB/SIMULINK® environment [10, 15, 16], Verilog HDL [12], or VHDL [14, 17], and implementations using FPGAs [10, 12-20]. In general, the design of an entire digital-modulator system includes basic functional blocks, such as a direct digital synthesizer (DDS) used for generating digital sine waves; blocks related to the modulation technique; and auxiliary blocks used for different tasks. The direct digital-synthesizer structure converts the phase values to corresponding digital words represented by the amplitude values [15, 16, 18]. A digital sine wave can be generated in different ways using basic trigonometric functions, or the COordinate Rotation DIgital Computer (CORDIC) algorithm, for more scalability or flexibility of the generated signal [19]. The proper blocks are selected depending on the type of modulator used in the design. Most of the previous work at least employs one multiplexer included in the block system [12, 15, 16]. The auxiliary blocks can be parallel-to-serial converters, phase-locked loops (PLLs), or blocks required for interfacing the described alldigital behavioral model with external FPGA boards. The aim of this paper is implementation of fully digital BASK, BFSK, and BPSK modulators that employ the minimum number of digital blocks suitable for software-defined radio systems and are integrable with the Altera FPGAs. Furthermore, the implemented FPGA designs can be used in a digital communication course to demonstrate BASK, BFSK, and BPSK digital-modulation techniques. The paper is organized as follows. In Section 2, the theory of the BASK, BFSK, and BPSK modulations are briefly presented. In Section 3, the building blocks of the all-digital design to be implemented in an FPGA are given, with details. The verification of the implemented digital modulators through simulations and real-time results acquired from the implementation into the Altera DE2 FPGA board are emphasized and evaluated in Section 4. Finally, in Section 5, conclusions are drawn.

keeping the frequency and phase constant. A block diagram of the BASK modulation and its signal waveforms are shown in Figures 2 and 3, respectively. Since there are sharp discontinuities at the transition points, the resulting BASK signal has an unnecessarily wide bandwidth. The bandpass filter shown in Figure 2 will remove the high-frequency components of the BASK signal. The output is a bandlimited signal, ready for transmission by a power amplifier. A BASK signal can be expressed as = S BASK ( t ) m ( t ) A sin ( 2π f c t + Φ 0 ) , 0 ≤ t ≤ T , (1) where m ( t ) = 0 or 1 (the binary message), T is the bit duration, and A, f c , and Φ 0 are the amplitude, frequency, and phase of the sinusoidal carrier signal. The modulated signal has a power P = A2 4 for equal-duration “0” and “1” states.

2.2 BFSK Modulation
In a BFSK (binary frequency-shift keying) modulation process, the frequency of the sinusoidal carrier signal is changed according to the message level (“0” or “1”) while keeping the amplitude and phase constant. A block diagram of the BFSK modulation and its signal waveforms are shown in Figures 4 and 5, respectively.

Figure 2. A block diagram of BASK modulation.

2. Theory of the Digital Modulations 2.1 BASK Modulation
In a BASK (binary amplitude-shift keying) modulation process, the amplitude of the sinusoidal carrier signal is changed according to the message level (“0” or “1”), while Figure 3. The modulating-signal (message) and the BASK signal waveforms. 263

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A BASK signal can be expressed as = S BFSK ( t ) A sin 2π   fc + m ( t ) f m   t + Φ0 , 0≤t ≤T ,

{

}

(2)

where m ( t ) = 0 or m ( t ) = 1 (the binary message), T is the bit duration, and A, f c , and Φ 0 are the amplitude, frequency, and phase of the sinusoidal carrier signal. The modulated signal has a power P = A2 2 .

Figure 4. A block diagram of BFSK modulation.

2.3 BPSK Modulation
In a BPSK (binary phase-shift keying) modulation process, the phase of the sinusoidal carrier signal is changed according to the message level (“0” or “1”) while keeping the amplitude and frequency constant. A block diagram of the BPSK modulation and its signal waveforms are shown in Figures 6 and 7, respectively. A BPSK signal can be expressed as = S BPSK (t ) A sin   2π f c t + m ( t ) π   , 0 ≤ t ≤ T , (3)

Figure 5. The modulating-signal (message) and the BFSK signal waveforms.

where m ( t ) = 0 or 1 (the binary message), T is the bit duration, and A, f c , and Φ 0 are the amplitude, frequency, and phase of the sinusoidal carrier signal. The modulated signal has a power P = A2 2 .

3. Digital-Modulator Building Blocks 3.1 Digital Sine-Wave Generator
A direct digital synthesizer that was used to generate a sinusoidal waveform was implemented by using two different parts: a phase generator (accumulator), and a phase-to-waveform converter, as shown in Figure 8. The first part of the directdigital-synthesizer process was a phase generator. The desired frequency of the output sinusoidal signal ( Fo ) was applied as an integer to the input of the phase generator. Here, it was assumed that the accumulator size was M bits, the period of the output signal was 2π , and the maximum phase was 2 M . The phase increment of the accumulator output, ∆ ACC , determined the frequency of the output signal. During each sampling period, Ts (sampling frequency Fs ), the phase was increased

Figure 6. A block diagram of BPSK modulation.

by ∆ ACC to reach its maximum phase value of 2 M . ∆ ACC could thus be found as ∆ ACC ( Fo ) = 2 M Fs Fo . Figure 7. The modulating-signal (message) and BPSKsignal waveforms. 264

(

)

(4)

In this case, the sampling frequency was Fs = 46875 Hz, and the maximum phase increment at the output of the phase gen-

IEEE Antennas and Propagation Magazine, Vol. 54, No. 2, April 2012

Figure 8. A block diagram of the direct digital-synthesizer process. erator was selected to be 232 . Thus, Selecting

∆ ACC = ( Fo )

(2

32

46875 Fo ≅ 91626 Fo .

)

Figure 9. BASK modulation using a two-to-one multiplexer.

Fo = 1000 N and changing N from one to four by means of a counter controlled with pushbuttons, a sinusoidal carrier signal with different frequencies of Fo = 1 , 2, 3, and 4 kHz could be obtained. The second part of the direct digital synthesizer was a phase-to-waveform converter, based on a lookup table (LUT). A lookup table with 2 K entries ( K ≤ M ) could be used for phase-to-amplitude conversion with a smaller memory. This could be accomplished by selecting the K most-significant bits (MSBs) of the total M bits. The amplitude values of the output waveform were stored in 16-bit registers. Since a lookup table intended for this implementation with K = 8 was selected, the conversion process was performed with 28 = 256 samples, each stored in a 16-bit register.

Figure 10. A BASK block diagram in Quartus II.

3.2 Modulation Circuitry
A two-to-one multiplexer was used to generate the BASK signal, as shown in Figure 9. The output was equal to the carrier signal (sinusoidal waveform) if the binary input was equal to “1,” while binary data equal to “0” resulted in a zero output. Therefore, the direct digital synthesizer (implemented using Verilog HDL) and a two-to-one multiplexer generated the required BASK modulated signal. The implementation of these two blocks in the Quartus II software is shown in Figure 10. Similarly, a two-to-one multiplexer was used to generate the BFSK signal, as shown in Figure 11, where two sinusoidal carrier signals with different frequencies were applied as inputs. The output was equal to the first carrier signal (sinusoidal waveform 1) if the binary input was equal to “1,” while binary data equal to “0” resulted in the second carrier signal (sinusoidal waveform 2) at the output. Therefore, the direct digital synthesizer (implemented using Verilog HDL) and a two-to-one multiplexer generated the required BFSK modulated signal. The implementation of these two blocks in Quartus II software is shown in Figure 12. A block diagram for generating the BPSK signal using a two-to-one multiplexer is shown in Figure 13. Two sinusoidal carrier signals with phases of 0° and 180° were applied as inputs to the multiplexer. The output was equal to the carrier signal (sinusoidal waveform with phase of 0°) if the binary input was equal to “1,” while binary data equal to “0” resulted in the second carrier signal (sinusoidal waveform with phase of 180°) at the output. Therefore, the direct digital synthesizer (implemented using Verilog HDL) and a two-to-one multi-

Figure 11. BFSK modulation using a two-to-one multiplexer.

Figure 12. A BFSK block diagram in Quartus II.

Figure 13. BPSK modulation using a two-to-one multiplexer. 265

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the video graphics array and audio phased-locked loop in the Quartus II software is shown in Figure 16. An input clock of 27 MHz (the internal clock of the Altera DE2 FPGA board) was applied to the phase-locked-loop block’s input, and later was multiplied by two-thirds, resulting in an output frequency of 18 MHz. Figure 14. A BPSK block diagram in Quartus II.

3.5 Clock Generator for DAC
From the Wolfson WM8731 datasheet, the sampling rate of the audio codec’s DAC was selected to be 48 kHz. This value was obtained from the 18.432 MHz clock pulse by means of a frequency divider. As previously mentioned, the audio codec frequency (AUD_XCK) was generated by the video graphics array audio phase-locked-loop tool. However, the audio codec’s DAC needed two different clock pulses: a parallel-to-serial-bit clock (AUD_BCLK), and a left-right channel-selection clock (AUD_LRCK). It must be noted that the audio codec’s DAC had serial input. Another clock pulse for parallel-to-serial input conversion was thus required. The output signals (BASK, BFSK, and BPSK) obtained from the FPGA board consisted of 16-bit word lengths. The division rates required for AUD_ BCLK and AUD_LRCK clock pulses were calculated as Figure 15. A parallel-to-serial converter in Quartus II. DRBIT = ( CLK REF )  ( SR )( DW ) ( NCH )  , DRL − R = ( CLK REF ) ( SR ) , plexer generated the required BPSK modulated signal. The implementation of these two blocks in the Quartus II software is shown in Figure 14. (5) (6)

3.3 Binary Sequence Parallel-to-Serial Converter
To produce the serial binary sequence (message) necessary for the digital modulation from 16-bit parallel binary data, a parallel-to-serial converter, implemented with a fourbit counter and a 16-to-1 multiplexer was used, as shown in Figure 15. The parallel binary input was provided using toggle switches available on the Altera DE2 FPGA board.

where CLK REF , SR, DW, and NCH are the reference clock, sample rate, data word length, and number of channels, respectively. In this case, the values for these parameters were selected to be CLK REF = 18 MHz, SSSR = 46.875 kHz, DW = 16 bits, and NCH = 2 . By substituting these values into Equations (5) and (6), the values of DRBIT and DRL − R were found to be 12 and 384, respectively. This calculation showed that the bit-clock frequency was 18 MHz 12 = 1.5 MHz, and the left-right clock frequency was 18 MHz 384 = 46.875 kHz, which was equal to the sampling rate. A block diagram of the clock generator (frequency divider) used for operating the DAC in the Quartus II software is shown in Figure 17.

3.4 VGA and Audio PLL
To observe the modulated signals on the oscilloscope screen, a digital-to-analog converter (DAC) was required. For this purpose, the 16-bit DAC available on the Wolfson WM8731 audio CODEC of the Altera DE2 FPGA board was used. This audio codec needs a specific clock pulse frequency of 18.432 MHz. The video graphics array (VGA) and audio phase-locked loop (PLL) blocks generated these clock pulses, using an input with arbitrary frequency. A block diagram of 266

3.6 Parallel-to-Serial Converter for Audio CODEC
The parallel-to-serial converter shown in Figure 18 was used to convert the modulated signal represented with a 16-bit word length from parallel form into the serial input required for the DAC. As can be seen from Figure 18, the AUD_BCLK and AUD_LRCK were used as the bit-clock and left-right channelselection clock, respectively. The positive and negative edges of the AUD_LRCK were used to send serial data either to the left channel’s DAC or to the right channel’s DAC in the audiocodec chipset.

IEEE Antennas and Propagation Magazine, Vol. 54, No. 2, April 2012

FPGA board. Note that 1000 stands for 1 kHz. In this case, Fo could be equal to 1 kHz, 2 kHz, 3 kHz, or 4 kHz. The binarysequence sampling-clock frequency was similarly set.

4. Simulation and Experimental Results
Figure 16. A block diagram of the VGA and audio phaselocked loop in Quartus II. Prior to the FPGA hardware implementation, the designed BASK, BFSK, and BPSK digital modulators were verified through simulations using the Quartus II software.

4.1 BASK Simulation Result
The design parameters used for the simulations were a 16-bit phase accumulator that generated a 16-bit digital sine wave with a frequency of 1 kHz (arbitrarily selected), and a 1010101...10 serial binary sequence (modulating signal) with a frequency of 500 Hz. The simulation results for the BASK modulator are shown in Figure 20. The input carrier signal was Sinusoidal_Wave, the input modulating signal was Binary_Sequence, and the output modulated signal was ASK_Signal.

Figure 17. The clock generator used for the DAC in Quartus II.

Figure 18. The audio CODEC parallel-to-serial converter in Quartus II.

4.2 BFSK Simulation Result
The design parameters used for the simulations were a 16-bit phase accumulator that generated two 16-bit digital sine waves with frequencies of 1 kHz and 2 kHz (the frequencies were arbitrarily selected), and a 1010101...10 serial binary sequence (modulating signal) with a frequency of 125 Hz. The simulation results for the BFSK modulator are shown in Figure 21. The input carrier signals were Sinusoidal_Wave_1 and Sinusoidal_Wave_2. The input modulating signal was Binary_Sequence, and the output modulated signal was FSK_Signal.

Figure 19. The button-controlled counters in Quartus II.

4.3 BPSK Simulation Result
The design parameters used for the simulations were a 16-bit phase accumulator that generated a 16-bit digital sine wave with a frequency of 1 kHz and phases of 0° and 180° (the

3.7 Pushbutton Counters for the DDS and Binary-Sequence-Sampling Clock Frequencies
The blocks shown in Figure 19 were counters that counted from one to four. The counters’ outputs determined the frequencies of the direct-digital-synthesizer sinusoidal wave generator and binary-sequence-sampling clocks. As previously defined, the direct-digital-synthesizer sinusoidal signal frequency was equal to Fo = 1000 N , where N is the direct digital synthesizer’s frequency multiple, which varied from one to four, and was controlled with a pushbutton on the Altera DE2

Figure 20. The simulation results for the BASK modulator. 267

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complements of each other), and a 1010101...10 serial binary sequence (modulating signal) with a frequency of 250 Hz. The simulation results for the BPSK modulator are shown in Figure 22. The input carrier signals were Sinusoidal_ Wave_1 and Sinusoidal_Wave_2, the input modulating signal was Binary_Sequence, and the output modulated signal was BPSK_Signal.

4.4 Experimental Results
Figure 21. The simulation results for the BFSK modulator. The experimental results were carried out in a laboratory using the Altera DE2 FPGA board and a digital oscilloscope, as shown in Figure 23. The programmed all-digital design was targeted for the Altera DE2 FPGA board. The 16-bit input binary sequence was controlled by toggle switches, and the frequencies of the input signals (carrier and message) were controlled by the pushbuttons on the board. As previously stated in Section 3, the pushbuttons controlled counters counting from one to four. To apply the same input signals as in the simulation, the counter for the carrier therefore counted one ( Fo = 1× 1000 = 1 kHz), while the counter for the binary sequence (message) counted, for example, two ( Fbs =× 2 125 = 250 Hz) for BPSK. It must be noted that the counters could be designed in accordance with the frequencies required for the carrier and message signals. The implementations of all digital modulators (BASK, BFSK, and BPSK) were performed using digital circuitry, as described in the above sections. The outputs of the modulators were applied through a parallel-to-serial converter to the input of the DAC of the audio CODEC on the Altera DE2 FPGA board. Finally, the output of the DAC was connected to the channel of a digital oscilloscope, in order to display the realtime analog BASK, BFSK, and BPSK signals, as shown in Figure 23. As could be seen, the real-time results obtained were in good agreement with the simulated signals.

Figure 22. The simulation results for the BPSK modulator.

5. Conclusions
FPGA implementations of BASK, BFSK, and BPSK digital modulators were demonstrated. The main advantages of the implementations were the minimum numbers of digital blocks used for performing digital modulations, the ability to integrate with modules in FPGA boards, and the user controllability of the input signals’ frequencies.

Figure 23. The Altera DE2 evaluation board and the realtime experimental results for the BASK, BFSK, and BPSK modulators.

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The implemented FPGA designs are suitable for realization of the digital baseband-modulation part of software-defined radio systems. In addition, usage of this kind of implementation for educational purposes in digital communications laboratories or courses clearly emphasizes the correlation between different courses in electronics engineering (in this case, digital design and digital communications).

11. R. H. Hosking, Software Defined Radio Handbook, Eighth Edition, Pentek, Inc., 2010, p. 9. 12. F. Ahamed and F. A. Scarpino, “An Educational Digital Communications Project Using FPGAs to Implement a BPSK Detector,” IEEE Transactions on Education, 48, 1, 2005, pp. 191-197. 13. F. Amaya-Fernandez and J. Velasco-Medina, “Design of Baseband Processor for Software Radio Using FPGAs,” Proceedings of the IEEE International Conference SOC (SOCC 08), September 17-20, 2008, pp. 315-318. 14. S. O. Popescu, G. Budura, and A. S. Gontean, “Review of PSK and QAM – Digital Modulation Techniques on FPGA,” Proceedings of the IEEE International Conference on Computational Cybernetics and Technical Informatics (ICCCCONTI 10), May 27-29, 2010, pp. 327-332. 15. M. Rice, C. Dick, and F. Harris, “Maximum Likelihood Carrier Phase Synchronization in FPGA-Based Software Defined Radios,” Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 01), May 7-11, 2001, pp. 889-892. 16. K. Li, X. Lu, W. Zhang, and F. Wang, “Design and Implementation of Digital Modulator Based on Improved Direct Digital Synthesizer Technology and DSP Builder,” Proceedings of the IEEE 5th International Conference on Wireless Communications, Networking and Mobile Computing (WiCom 09), September 24-26, 2009, pp. 1-5. 17. F. M. Demir, U. Kafadar, S. Dikmese, and H. Dincer, “FPGA Based Implementation of Communication Modulation,” Proceedings of the IEEE 15th Signal Processing and Communications Applications (SIU 07), June 11-13, 2007, pp. 1-4. 18. R. O. R. Cardoso, J. A. J. Ribeiro, and M. Silveira, “Direct Digital Synthesizer Using FPGA,” Proceedings of the Global Congress on Engineering and Technology Education (GCETE 05), March 13-16, 2005, pp. 290-293. 19. E. O. Garcia, R. Cumplido, and M. Arias, “Pipelined CORDIC Design on FPGA for a Digital Sine and Cosine Waves Generator,” Proceedings of the IEEE 3rd International Conference on Electrical and Electronics Engineering (ICEEE 06), September 6-8, 2006, pp. 1-4. 20. C. Quintans, M. D. Valdes, M. J. Moure, L. FernandezFerreira, and E. Mandado, “Digital Electronics Learning System Based on FPGA Applications,” Proceedings of the 35th Annual Conference on Frontiers in Education (FIE 05), October 19-22, 2005, pp. S2G-7-S2G-11.

6. References
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