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//******************************************************************************************************//

// Author
: IncMimi
// Module_name
: pulse_synchronizer.v
// Created_Date : 24/08/2013
// Revision
: 00.01
// Description
: samples the pulse in onc clock domain and drives the synchronized pulse
//
in another domain
//
//
+-----+ +------+
+--------+
+-------//
tx_clk ......| |......| |.......|
|........|
..........................
//
//
+--------------+
//
tx_pulse .................|
|....................................................
//
//
+...............+
+............+
+...........
//
rx_clk ______________|
|______________|
|_______________|
//
//
+............................+
//
rx_pulse _____________________________________________|
|____________
//
//
//*******************************************************************************************************//
module pulse_synchronizer
(
// Inputs
input wire
tx_clk
,
input wire
tx_reset_n ,
input wire
tx_pulse
,
input wire
input wire
// Outputs
output wire
);

rx_clk
,
rx_reset_n ,
rx_pulse

// Local Registers Decleration


reg
tx_pulse_latch
;
reg
reg
reg

rx_sync1
rx_sync2
rx_sync3

;
;
;

// Code Starts Here


always @(posedge tx_clk or negedge tx_reset_n) begin
if(!tx_reset_n) begin
tx_pulse_latch <= 1'b0
;
end
else if (tx_pulse) begin
tx_pulse_latch <= (!tx_pulse_latch) ? 1'b1 : 1'b0 ;
end
end

always @(posedge rx_clk or negedge rx_reset_n) begin


if(!rx_reset_n) begin
rx_sync1 <= 1'b0
;
rx_sync2 <= 1'b0
;
rx_sync3 <= 1'b0
;
end
else begin
rx_sync1 <= tx_pulse_latch ;
rx_sync2 <= rx_sync1
;
rx_sync3 <= rx_sync2
;
end
end
assign rx_pulse = rx_sync3 ^ rx_sync2 ;
endmodule