module behavior(la_in,data,ep,clk);

input clk,la_in;
input [7:0]data;
output [7:0]ep;

wire clk;
wire la_in;
wire [7:0]data;
reg [7:0]ep;

always @(clk or data or la_in)

begin
if(clk == 1'b0)
begin
ep = 8'b00000000;
end
else if(pos)
begin
// if(la_in == 1'b1)
//

begin

casex(data)
8'bxxxxxx01 : ep = 8'b00010001;
8'bxxxxxx10 : ep = 8'b00000010;
8'bxxxxx100 : ep = 8'b00000100;
8'bxxxx1000 : ep = 8'b00001000;
8'bxxx10000 : ep = 8'b00010000;
8'bxx100000 : ep = 8'b00100000;

8'bx1000000 : ep = 8'b01000000;
8'b10000000 : ep = 8'b10000000;
//8'bzzzzzzzz : ep = 8'b00000000;
default : ep = 8'b00000000;
endcase
//end
end
end
endmodule