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Alexander Ross 100789571
1) In Verilog, what is an always block used for? How is it different from an initial block? The always block can be run again after the beginning (time = 0) whereas the initial block only runs at the beginning. 2) What is the syntax for an If Then Else statement in Verilog? begin if (a) statement else statement end 3) What is the syntax for a Case statement? case (a) 0: statement; 1: statement; . . . default: statement; endcase 4) When is it necessary to use Begin/End statements? When can you skip using Begin/End? You can skip the Begin/End statement when you have only on condition, whereas you need the Begin/End statement when you have multiple conditions. 5) Review the code for the counter finite state machine. Is anything missing? If yes, what? In the case statements there is a 'default' case missing. 6) In English, describe the possible transitions from state S2. (For example: “If we are in S2 and pbr is pushed, but not pbl then…”) Be sure to catch all implied changes! If pbr is pushed but not pbl then count up. Or if pbl is pushed but not pbr then count down. Otherwise don't count.