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Design of High Speed Beaumont-Smith Based Carry Select Adder
Madhu Kumar Patnala2
PG Student, VLSI, Assistant Professor (senior grade), ECE Dept., SVEC, Tirupati, Chittoor, A.P, India,
Abstract- In this paper, we propose a high speed Carry Select Adder by replacing Ripple Carry Adders with Beaumont-Smith adders. Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adders (RCA) are usually preferred for addition of two multi-bit numbers as these RCAs offer fast design time among all types of adders. However RCAs are slowest adders as every full adder must wait till the carry is generated from previous full adder. On the other hand, Carry Look Ahead (CLA) adders are faster adders, but they required more area. The Carry Select Adder is a compromise on between the RCA and CLA in term of area and delay. CSLA is designed by using dual RCA: due to this arrangement the area and delay are still concerned factors. It is clear that there is a scope for reducing delay in such an arrangement. In this research, we have implemented CSLA with Beaumont-Smith adders. BeaumontSmith adders are tree structure based and are preferred to speed up the binary additions. This work estimates the performance of proposed design in terms of Logic and route delay. The experimental results show that the performance of CSLA with parallel prefix adder is faster and area efficient compared to conventional modified CSLA. Index Terms- Beaumont-Smith adder, CSLA, delay, Carry Operator, area-efficient.
different adder architectures were studied and proposed to speed up the binary additions. The details of Ripple Carry Adder and Carry Select Adder are discussed in section II, and the implementation of proposed system is described in section III. The performance and simulation results were presented and discussed in section IV.
CARRY SELECT ADDER (CSLA)
In Electronics, carry-select adder is a particular way to implement an adder. It is a logic element that computes the sum of two n-bit numbers. The carry-select adder generally composes of two ripple carry adders  and a multiplexer. Ripple Carry Adder The Ripple Carry Adder is used to compute addition of two N-bit numbers. It consists of N full adders to add N-bit numbers. From the second full adder, carry input of every full adder is the carry output of its previous full adder. This kind of adder is typically known as Ripple Carry Adder because carry ripples to next full adder. The layout  of Ripple Carry Adder is simple, which allows fast design time. The Ripple Carry Adder  is slowest among all the adders because every full adder must wait till the previous full adder generates the carry bit for its input. The 3-bit RCA is shown in Figure 1. Theoretically the Ripple Carry Adder has delay of o(n) and area of o(n).
In Digital Computer Design adder is an important component and it is used in multiple blocks of its architecture. In many Computers and in various classes of processor specialization, adders are not only used in Arithmetic Logic Units , but also used to calculate addresses and table indices. There exist multiple algorithms to carry on addition operation ranging from simple Ripple Carry Adders to complex CLA. The basic operations involved in any Digital Signal Processing systems are Multiplication, Addition and Accumulation. Addition is an indispensible operation in any Digital, DSP or control system. Therefore fast and accurate operation of digital system depends on the performance of adders . Hence improving the performance of adder is the main area of research in VLSI system design. Over the last decade many
Figure 1. 3-bit Ripple Carry Adder Multiplexer
ISSN: 2231-5381 http://www.ijettjournal.org
ijettjournal. The delay at cin input stage can be reduced using variable type of CSLA .. (3(ii)) Figure 3.... Execution of these operations is carried out in parallel .........processing stage 2.... Parallel prefix adders are fastest adders and these are used for high performance arithmetic circuits in industries..... but in variable Carry Select Adder block size is variable. Beaumont-Smith adder  can be represented as a parallel prefix graph consisting of carry operator nodes..... The 6:3 Multiplexer is shown in Figure 2... It is the fastest adder with focus on design time and is the common choice for high III... Parallel prefix adders  are obtained from Carry Look Ahead (CLA) structure.. It uses carry propagate and generate as intermediate signals which are given by the logic equations 3&4: CPi:j=Pi:k+1 and Pk:j.... (1) Gi=Ai and Bi.... These signals are given by the logic equations 1&2: Pi=Ai xor Bi..... (4) Si=Pi xor Ci-1........(4) Figure 2.......... (2) Carry generation network In this stage we compute carries corresponding to each bit. generate and propagate signals to each pair of inputs A and B. There are two types of Carry Select Adders one is uniform and another one is variable carry select adder . Figure 4.. (3(i)) CG0=(Pi and Gj) or Gi. Post processing Pre-possessing stage In this stage we compute.....(3) CGi:j=Gi:k+1 or (Pi:k+1 and Gk:j). PROPOSED CSLA Parallel prefix adders ISSN: 2231-5381 http://www.. Pre... data selector and universal parallel to serial converter.... In uniform Carry Select Adder each block size is fixed in all stages.April 2013 Multiplexer is a combinational circuit which has many inputs and single output... Depending on the select input combination the content on one of the selected input line is transferred on to the output line. Modified CSLA.. The construction of parallel prefix adder  involves three stages 1.. The time required to generate carry signals in this prefix adder is o(log n).............. Carry generation network 3.......... The parallel prefix adders  are more flexible and are used to speed up the binary additions.......................Volume4Issue4.... Carry operator The operations involved in this figure are given as: CP0=Pi and Pj....org Page 893 .. It is also widely known as many to one circuit................. (5) Beaumont-Smith (BS) adder Beaumont-Smith adder is a parallel prefix form of Carry Look-ahead Adder.................. After the computation of carries in parallel they are segmented into smaller pieces.. The modified CSLA  is shown in Figure 3.... It is common for all adders and the sum bits are computed by logic equation 5&6: Ci-1=(Pi and Cin) or Gi... Post processing This is the final step to compute the summation of input bits.....In this diagram the addition of two 16-bit numbers is done with two RCAs  of cin=0 and cin=1... 6:3 multiplexer Carry Select Adder The Carry Select Adder  consists of dual Ripple Carry Adders and a multiplexer.. After the calculation for two cases of carry... We use tree structure form to increase the speed  of arithmetic operation..... Theoretically delay and area of Carry Select Adder are o(√n) and o(2n) respectively..... the correct sum as well as correct carry is selected by using multiplexer once the correct carry is known..International Journal of Engineering Trends and Technology (IJETT) .
The BeaumontSmith adder concept was developed by Andrew Beaumont-Smith and Cheng-Chew Lim . ISSN: 2231-5381 http://www. Figure 9.787 2. 5-bit Beaumont-Smith adders. SIMULATION RESULTS AND COMPARISONS Figure 5.111 6. 5-bit Beaumont-Smith adder are shown below.236 4.org Page 894 .96 1. The modification is done by replacing 2.959 10.111 6.959 14. The simulated output of 16-bit proposed CSLA is shown in Figure 10. On the other side it occupies minimum silicon area.847 6. The better performance of Beaumont-Smith adder is because of its minimum logic depth and bounded fan-out. 4.898 8. 5-bit BS Adder Figure 9 shows the structure of modified CSLA.787 2. 3-bit BS Adder Various adders were designed using Verilog language in Xilinx ISE Navigator 10. 5-bit Beaumont-Smith adders were developed and corresponding values of logic and route delay were tracked.International Journal of Engineering Trends and Technology (IJETT) . 4.862 0. 3. Logic Delay (ns) 2-bit 3-bit 4-bit 5-bit Modified CSLA 2-bit 3-bit 4-bit 5-bit Modified CSLA 5. 4-bit BS Adder Ripple carry adder BeaumontSmith adder Figure 8. The performance of proposed CSLA is analyzed and compared against the conventional CSLA designs. 2-bit BS Adder Figure 6.499 6.898 8. IV. 3. 5-bit RCAs with 2.020 17.April 2013 performance adders in industry.ijettjournal. 5-bit Ripple Carry Adders logic and route delay. 3.562 Total delay 6.011 Adder type Figure 7.1 and all the simulations are performed using Xilinx ISE simulator.685 5. Logic and Route delay values of proposed CSLA and conventional CSLA.236 2.338 1.Volume4Issue4.481 5.837 7. Modified 16-b BS CSLA. which was published in 2001. Table 1 shows the comparison of CSLA with Ripple Carry Adders and CSLA with Beaumont-Smith adders in terms of logic and route delay. 4. 3.723 9. 4. 3.449 Route delay 1.887 5. Table 1. 4. the implementation code for 2. The construction of 2.338 1. In this proposed CSLA architecture.335 11.619 4.837 7.723 7. These values are compared to 2.499 6.
pp 90-98. 45th Midwest Symposium on Circuits and Systems. pp. T. Choi.  V. vol. May1990. May 2001. The compared result shows that the proposed CSLA greatly reduces delay. Youngjoon Kim and Lee-Sup Kim. ISSN: 2231-5381 http://www. Ramkumar. pp. “Low –Power and Area-Efficient Carry Select Adder”. Andrew Beaumont-Smith and Cheng-Chew Lim. Snir. “Digital Integrated Circuits. pp. His research areas are Embedded System Design.37. C. “A low power and reduced area Carry Select Adder”. 17th IEEE Symposium on Computer Arithmetic. Harish M Kittur. vol.. “Parallel Prefix Adder Design. Sixth International Symposium on Quality of Electronic Design. His interest includes Digital Design.-Y.Tech. March 1993. Prentice-Hall. Youngjoon Kim and Lee-Sup Kim.” Proc. pp.Thompson.    Figure 10.Pakkiraiah completed his B.Wei and Clark D. vol. pp. 2001. New Jersey. 340-346. 2001.ijettjournal. The proposed CSLA architecture is therefore. O.39.260-264. 666-675. October 1998. March 1982..A Design Perspective”. David Jeff Jackson and Sidney Joel Hannah. P.c-31. pp. April 2005. Behnam Amelifard. Belle W. May 2001. ASIC Design. India. Brent and H.Tech) in VLSI at Sree Vidyanikethan Engineering College.International Journal of Engineering Trends and Technology (IJETT) .255-258. P. vol. Tarek Darwish.4.Tech in Electronics and Communication Engineering from Sreenivasa Institute of Technology and management studies.org Page 895 .148152. The comparison between proposed and conventional CSLA in terms of total delay is shown in Figure 11.2.371-375.EC-11. IEEE transactions on Computers. Chang and M. IRE transactions on Electronics Computers. Madhu Kumar. 27th June 2005. Chittoor. Tirupati. Department of Electrical and Electronic Engineering. “A low power carry select adder with reduced area”. no. Kung. T. vol. Digital Signal Processors. Andhra Pradesh. “Closing the gap between Carry Select Adder and Ripple Carry Adder: a new class of lowpower high-performance adders”. “A Regular Layout for Parallel Adders”.1. and Magdy Bayoumi. M. Y. Rabaey. Simulated Output of 16-b BS CSLA. India in 2009. Akhilesh Tyagi.” in Journal of Algorithms 7.185– 201. CONCLUSION  A new approach is proposed in this paper to reduce the delay of SQRT CSLA. Total delay values of different adders. Sept 1990 M.-J. vol.34. Pakkiraiah would like to thank Mr. 467-470. is currently working as an Assistant Professor (Senior grade) in ECE department of Sree Vidyanikethan Engineering College. 25th South-eastern Symposium on System Theory. J. Hsiao. Mr.20. IEEE transactions on Computers.March 2002. Electronics letters. “Carry-Select Adder”. pp. “Parallel Prefix Adder Design”. The replacement of Beaumont-Smith adders in place of Ripple Carry Adders offers great advantage in the reduction of delay.614-615. Madhu Kumar. “Depth-size trade-offs for parallel prefix computation. It would be interesting to investigate the design of the proposed 128-b SQRT CSLA.“Carry-Select Adder using single Ripple-Carry Adder”. and VLSI Testing. vol. issue 10. the University of Adelaide. “Area-Time Optimal Adder Design”. “Modelling and Comparison of Adder Designs with Verilog HDL”. Andhra Pradesh. “64-bit carryselect adder with reduced area”. Tirupati. IEEE International Symposium on Circuits and Systems.   VI. Kuldeep Rawat. M. 1986. Farzan Fallah and Massoud Pedram. “A Reduced Area Scheme for CarrySelect Adders”. Feb 2012. pp.April 2013 REFERENCES  B. Bedrij.    16-bit CSLA 5-bit 4-bit 3-bit 2-bit 0 10 20  BeaumontSmith RCA    Figure 11.Y. J.406-410. faster because of less delay and area efficient for VLSI hardware implementations. pp. IEEE transaction on very large scale integration (VLSI) systems. Richard P. Electronics Letters. pp.2101-2103. pp. pp. vol.218-221.Volume4Issue4. ACKNOWLEDGEMENT C. He is now pursuing his Master of Technology (M. June1962. Assistant professor (senior grade) ECE Department who had been guiding throughout the project and supporting me in giving technical ideas about the paper and motivating me to complete the work efficiently and successfully. IEEE International Conference on Computer design.
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