VERILOG CODE FOR ALU

:
`timescale 1ns / 1ps
module logic_unit(d_out1,logic_unit,s0,s1,c0,A,B);
output [3:0] d_out1;
input s0,s1,c0,logic_unit;
input [3:0] A;
input [3:0] B;
reg [3:0] d_out1;
always @(s0,s1,A,B,logic_unit)
begin
if(logic_unit== 1'b1)
begin
if(s0 == 1'b0 & s1 == 1'b0)
begin
d_out1 = ( A & B);
end
else if(s0 == 1'b1 & s1 == 1'b0)
begin
d_out1 = ( A | B);
end
else if(s0 == 1'b0 & s1 == 1'b1)
begin
d_out1 = ( A ^ B);
end
else
begin
d_out1 = ( A ^~ B);
end
end

wire [3:0]K1. reg en. wire s0. input s0.M. reg cout.c0. output cout. reg [3:0] temp.s0.s1. wire [3:0] A.L1} = (A + (~B)). assign {K0.arithmetic_unit.K1} = ((~A) + B). reg [3:0] d_out2. inout [3:0] d_out.B.else begin d_out1 = 4'b0000. wire [3:0]L1.B. assign {L0. wire L0. wire [3:0]D1.s1. wire [3:0] d_out.B. input [3:0] A.M). wire D0.A.M.c0.D1} = A + B.arithmetic_unit. wire K0. .c0. assign {D0.arithmetic_unit. end end endmodule `timescale 1ns / 1ps module arithmetic(d_out.s1.cout.

c0. end else if(s1 == 1'b1 & s0 == 1'b0 & c0 == 1'b0) begin d_out2 = L1. cout = D0. cout = D0. end else if(s1 == 1'b0 & s0 == 1'b1 & c0 == 1'b1) begin d_out2 = D1 + 1'b1. end else if(s1 == 1'b0 & s0 == 1'b1 & c0 == 1'b0) begin d_out2 = D1. always @(s0. end else if(s1 == 1'b1 & s0 == 1'b0 & c0 == 1'b1) . end else if(s1 == 1'b0 & s0 == 1'b0 & c0 == 1'b1) begin d_out2 = A + 1'b1. cout = L0.s1.assign d_out = d_out2.arithmetic_unit) begin if(arithmetic_unit) begin if(s1 == 1'b0 & s0 == 1'b0 & c0 == 1'b0) begin d_out2 = A.

end end else begin d_out2 = 4'b0000. end else begin d_out2 = K1 + 1'b1.DATA_IN1. input CRY_IN. input SEL1.SEL2. .SEL1.MODE.DATA_OUT. input [3:0] DATA_IN1.DATA_IN2. output [3:0] DATA_OUT. cout = K0. cout = L0.CRY_IN. cout = K0.DATA_IN2. output CRY_OUT.begin d_out2 = L1 + 1'b1. end end endmodule `timescale 1ns / 1ps module alu(CRY_OUT.SEL2. end else if(s1 == 1'b1 & s0 == 1'b1 & c0 == 1'b0) begin d_out2 = K1.MODE).

.B(DATA_IN2). . . . . assign DATA_OUT = (MODE ? DATA_OUT1 : DATA_OUT2).c0(CRY_IN).SEL2. . .A(DATA_IN1). arithmetic_unit = 1'b0.arithmetic_unit(arithmetic_unit) ). . .c0(CRY_IN). .reg logic_unit.s1(SEL2).MODE) begin if(MODE == 1'b0) begin logic_unit = 1'b1.d_out1(DATA_OUT2). .s1(SEL2). .B(DATA_IN2). .cout(CRY_OUT). logic_unit logic_unit_ins(.s0(SEL1). .M(MODE). .A(DATA_IN1).logic_unit(logic_unit) ).d_out(DATA_OUT1). always @(SEL1. wire [3:0] DATA_OUT2. reg arithmetic_unit. wire [3:0] DATA_OUT1.s0(SEL1). arithmetic arithmetic_ins(.

. reg CRY_IN.CRY_IN. #500 SEL2 = 1'b0. #500 SEL2 = 1'b0. alu alu_ins(CRY_OUT.SEL2. CRY_IN = 1'b1.DATA_IN2 = 4'b0011. arithmetic_unit = 1'b1. #500 SEL2 = 1'b1. CRY_IN = 1'b1. reg [3:0] DATA_IN1.MODE). CRY_IN = 1'b1. SEL1 = 1'b0 .end else begin logic_unit = 1'b0. #500 MODE = 1'b0. CRY_IN = 1'b0. #500 SEL2 = 1'b1. CRY_IN = 1'b0. CRY_IN = 1'b0. #500 SEL2 = 1'b0. end end endmodule TEST BENCH FOR ALU: `timescale 1ns / 1ps module t_alu. SEL1 = 1'b1 . SEL1 = 1'b0 .DATA_IN2.DATA_OUT. initial begin DATA_IN1 = 4'b1011. #500 SEL2 = 1'b1.SEL1. SEL1 = 1'b1 . SEL1 = 1'b0 . #500 SEL2 = 1'b0. SEL1 = 1'b1 . CRY_IN = 1'b0. #500 SEL2 = 1'b1. SEL1 = 1'b0 .SEL2.DATA_IN2.MODE = 1'b1. wire [3:0] DATA_OUT.DATA_IN1.MODE. CRY_IN = 1'b1. reg SEL1. wire CRY_OUT. SEL1 = 1'b1 .

SEL2 = 1'b0. SEL2 = 1'b1. #500 SEL1 = 1'b1. #500 SEL1 = 1'b1. end endmodule . #500 SEL1 = 1'b0.#500 SEL1 = 1'b0. SEL2 = 1'b0. SEL2 = 1'b1.

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