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Inverter design

Inverter design

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Published by Kirthika Natarajan
Inverter Design using Mentor graphics EDA tool
Inverter Design using Mentor graphics EDA tool

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Published by: Kirthika Natarajan on Oct 07, 2013
Copyright:Attribution Non-commercial


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AIM: To design cmos inverter layout and from schematic entry to post layout simulation using mentor graphics EDA tools.

TOOLS REQUIRED: Mentor Graphics.

CMOS INVERTER THEORY: An inverter circuit outputs a voltage representing the opposite logic level to its input.inverters can be constructed using a single nmos transistor or a single pmos transistor coupled with a resistor.since this resistive drain approach uses only a single type of transistor it can be fabricated at low cost.However because current flows through the resistor in one of the two states ,the resistive drain configuration is disadvantaged for power consumption and processing speed.

CMOS inverter consists of a pull-up transistor and a pull-down transistor. Pull-up transistor is made up of p-type transistor and pull-down is of n-type. These pull-down and pull-up transistors are connected in series. When we are applying a low voltage (0v) n-type transistor will be off and p-type transistor will be conducting. Thus we will have vdd as the output (5V). When the input voltage is high the n-type transistor will conduct and p-type transistor will be in off state. Now we will get 0V as the output.


. From the library add pattern. vdd and gnd. Place and wire the input and output ports.To change the reference number (INST). and then select Properties > Modify Multiple. click the right mouse button.In the schematic_edit palette.Click on Generic Lib to place Portin. and Ground.After schematic is completed. Close all the windows. Instance > Alter Click on Check & Save in the schematic edit palette 6. In the box of Instance. Open a new file and add the symbol which is generated previously. select the component. In the schematic_edit palette.SCHEMATIC DIAGRAM OF CMOS INVERTER: For drawing a schematic diagram enter into pyxis schematic window and open a new schematic file. want to create a block symbol to represent this circuit. Enter into the simulation mode. To change the reference number automatically highlight all components. Select run eldo and view the waves. Select transient analysis and set the transient analysis times. Close all the windows.Again apply check and save. Portout. Click on Device Lib to place the transistors . INST.vdd and gnd from the library. In probes add the input output ports for analysis. 4.Change the instance name of the component 5. Pick and place 4-pin nmos . select Library. L. Wire all the compound and connect input output ports. SIMULATION: The electrical performance and the functionality of the circuit must be verified using a Simulation tool. For drawing a schematic diagram enter into pyxis schematic window and open a new schematic file. 1. D. 4-pin pmos . and W values . click right mouse button. For adding a wire between two points click once at the starting point and at all intermediate points to define the net route and double click at the end point to complete the routing.an NMOS(4-pin) and a PMOS(4-pin) 2. Open add -> Generate Symbol. change the ASIM_MODEL. This symbol can be used in other schematics to perform the same function as this circuit. 3. VDD. After check and save generate a symbol for the schematic and again apply check and save. dc source. The simulation phase also serves in detecting possible design errors that may have been created during the schematic entry step. Include the rule file and go to analysis. select WIRE (or press F3).


Instantiate nmos . If error exists check the design rule violations. . before the final design is saved. On the other hand. Use metal for wire the input . speed and power dissipation) since the physical structure determines the transconductances of the transistors.pmos . and make sure that all errors are eventually removed from the mask layout. output . The created mask layout must conform to a complex set of design rules. And repeat DRC. the detailed mask layout of logic gates requires a very intensive and time-consuming design effort. and obviously. Select the rule file and run DRC. vdd and gnd. using a Layout Editor. Select metal1. The checking result will be “the layout passed all checking”. Both schematic and layout window will open. Physical layout design is very tightly linked to overall circuit performance (area.input and output ports. Draw a 5*5 polysilicon and a 2*2 polycontact . The first check is a designrule check ( DRC ) to ensure that nothing has gone wrong in the process of assembling the logic cells and routing. the silicon area which is used to realize a certain function. DESIGN RULE CHECK: ASIC designers perform two major checks before fabrication. is used to detect any design rule violations during and after the mask layout design. in order to ensure a lower probability of fabrication defects. Place polycontact in side the 5*5 polysilicon and attach to the gates. the parasitic capacitances and resistances. Draw polysilicon to join the gates.DRC is used to check the layout whether that any violation have occurred with respect to rule file. The designer must perform DRC. Layout is constructed based on lambda based design rule and the technology . This is where the designer describes the detailed geometries and the relative positioning of each mask layer to be used in actual fabrication. Place the p-well and n-well contacts and save the layout. called Design Rule Checker.from the tools go to calibre and select DRC. A tool built into the Layout Editor.LAYOUT OF CMOS INVERTER: The creation of the mask layout is one of the most important steps in the full-custom (bottom-up) design flow. Enter into the IC station and open the simulation file of the inverter in new layout file. For the DRC . vdd and gnd. The physical design of cmos logic gates is an iterative process which starts with the circuit topology and the initial sizing of the transistors.


and ensures that the mask layout is a correct realization of the intended circuit topology. Select the rule file. In input select the . etc should be corrected in the mask layout . The circuit extractor is capable of identifying the individual transistors and their interconnections as well as the parasitic resistances and capacitances that are inevitably present between these layers. Go to tools and form calibre select LVS. The extracted net-list can provide a very accurate estimation of the actual device dimensions and device parasitics that ultimately determine circuit performance. The extracted net-list file and parameters are subsequently used in Layout-versus-Schematic comparison and in detailed transistor-level simulations (post-layout simulation). After the mask layout design of the circuit is completed.before proceeding to post-layout simulation. Add the rule file and . or missing connections/devices. From calibre select PEX. In other words. Any errors that may show up during LVS such as unintended connections between transistors. Reenter into the simulation mode and view waves and compare the results. Note that the LVS check only guarantees a topological match. By comparing the original network with the one extracted from the mask layout the designer can check that the two networks are indeed equivalent. The run RVE and check the results. PARASITIC EXTRACTION AND POST LAYOUT SIMULATION: Parasitic extraction is performed after the mask layout design is completed in order to create a detailed net-list for the simulation tool. The LVS step provides an additional level of confidence for the integrity of the design. the design should be checked against the schematic circuit description created earlier. Apply run LVS and check the result. An electrical schematic is extracted from the physical layout and compared to the netlist. From file go to GDSII and text on ports.spi file and in output select the parameters to be analyzed.LVS CHECKING: Layout versus schematic ( LVS ) check to ensure that what is about to be committed to silicon is what is really wanted.spi file for the input. . a successful LVS will not guarantee that the extracted circuit will actually satisfy the performance requirements. This closes a loop between the logical and physical design processes and ensures that both are the same.


RESULT: Thus designed cmos inverter layout and from schematic entry to post layout simulation using mentor graphics EDA tools is done. .

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