# ECE 301 – Digital Electronics

Flip-Flops and Registers
(Lecture #19)

The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

Flip-Flops
(continued)

Spring 2011

ECE 301 - Digital Electronics

2

SR Flip-Flop

The SR Flip-Flop has three inputs
– –

Clock (Ck) --- denoted by the small arrowhead Set (S) and Reset (R) S = 1 sets the flip-flop (Q+ = 1) R = 1 resets the flip-flop (Q+ = 0)

Similar to an SR Latch
– –

Like the D Flip-Flop, the Q output of an SR Flip-Flop only changes in response to an active clock edge.
– –

Positive edge-triggered Negative edge-triggered
ECE 301 - Digital Electronics 3

Spring 2011

SR Flip-Flop S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ 0 1 0 0 1 1 not allowed } } } Q+ = Q store Q+ = 0 reset positive edge-triggered SR Flip-Flop Q+ = 1 set State change occurs after active Clock edge Spring 2011 ECE 301 .Digital Electronics 4 .

SR Flip-Flop (master-slave) SR Latches Enabled on opposite levels of the clock Spring 2011 ECE 301 .Digital Electronics 5 .

Digital Electronics 6 .SR Flip-Flop: Timing Diagram Spring 2011 ECE 301 .

K = 1 is allowed.denoted by the small arrowhead J and K J corresponds to S: K corresponds to R: J = 1 → Q+ = 1 K = 1 → Q+ = 0 ● Similar to the SR Flip-Flop – – ● Different from the SR Flip-Flop in that the input combination J = 1. – J = K = 1 causes the Q output to toggle after an active clock edge.Digital Electronics 7 Spring 2011 . ECE 301 .JK Flip-Flop ● The JK Flip-Flop has three inputs – – Clock (Ck) --.

JK Flip-Flop } } } } Spring 2011 Q+ = Q store Q+ = 0 reset Q+ = 1 set + Characteristic Equation: Q+ = J.Q 8 Q = Q' toggle ECE 301 .Digital Electronics .Q' + K'.

Digital Electronics 9 .JK Flip-Flop (master-slave) SR Latches Enabled on opposite levels of the clock Spring 2011 ECE 301 .

Digital Electronics 10 .JK Flip-Flop: Timing Diagram Spring 2011 ECE 301 .

the state does not change (Q+ = Q) when T = 1.T Flip-Flop ● The Toggle (T) Flip-Flop has two inputs – – Clock (Ck) --. ECE 301 . the state changes following an active clock edge (Q+ = Q') ● The T input controls the state change – – ● T Flip-Flops are often used in the design of counters.denoted by the small arrowhead Toggle (T) when T = 0.Digital Electronics 11 Spring 2011 .

Digital Electronics 12 .Q = T xor Q Spring 2011 ECE 301 .Q' + T'.T Flip-Flop Characteristic Equation: Q+ = T.

T Flip-Flop: Timing Diagram Spring 2011 ECE 301 .Digital Electronics 13 .

Building a T Flip-Flop Spring 2011 ECE 301 .Digital Electronics 14 .

Asynchronous Control Signals Spring 2011 ECE 301 .Digital Electronics 15 .

Asynchronous Control Signals: Timing Diagram Spring 2011 ECE 301 .Digital Electronics 16 .

D FF with Clock Enable Spring 2011 ECE 301 .Digital Electronics 17 .

Registers Spring 2011 ECE 301 .Digital Electronics 18 .

Registers Several D flip-flops may be grouped together with a common clock to form a register. A better approach is to use registers with clock enables if they are available. Spring 2011 ECE 301 .Digital Electronics 19 . a register with n D flip-flops can store n bits of information. A load signal can be ANDed with the clock to enable and disable loading the registers. Because each flip-flop can store one bit of information.

Register: 4 bits Spring 2011 ECE 301 .Digital Electronics 20 .

Digital Electronics 21 . Multiple registers can be interconnected using tri-state buffers.Data Transfer between Registers ● Data transfer between registers is a common operation in computer (i. digital) systems. Data can be transferred between two registers by enabling the proper tri-state buffer. ● ● Spring 2011 ECE 301 .e.

Digital Electronics 22 .Data Transfer between Registers Spring 2011 ECE 301 .

Register with Tri-state Output Spring 2011 ECE 301 .Digital Electronics 23 .

Data Transfer using Tri-state Bus Spring 2011 ECE 301 .Digital Electronics 24 .

Spring 2011 ECE 301 .e. The data is shifted according to the applied shift signal. A shift register must be constructed using flip-flops (i. it cannot be constructed using latches or gated-latches (i. edgetriggered devices).e. often there is a left shift signal and a right shift signal.Digital Electronics 25 . level-sensitive devices).Shift Register A shift register is a register in which binary data can be stored and shifted either left or right.

Shift Register: 4 bits Spring 2011 ECE 301 .Digital Electronics 26 .

Shift Register (4 bits): Timing Diagram Spring 2011 ECE 301 .Digital Electronics 27 .

8-bit SI SO Shift Register Spring 2011 ECE 301 .Digital Electronics 28 .

Digital Electronics 29 .4-bit PI PO Shift Register Spring 2011 ECE 301 .

Digital Electronics 30 .4-bit PI PO Shift Register: Operation Spring 2011 ECE 301 .

Digital Electronics 31 .Parallel Adder with Accumulator Spring 2011 ECE 301 .

Digital Electronics 32 .Parallel Adder with Accumulator In computer circuits. Spring 2011 ECE 301 . leaving the result stored in the register. it is frequently desirable to store one number in a register (called an accumulator) and add a second number to it.

Digital Electronics 33 .n-bit Parallel Adder with Accumulator Spring 2011 ECE 301 .

Spring 2011 ECE 301 . The easiest way is to first clear the accumulator using the asynchronous clear inputs on the flip-flops. we could add multiplexers at the accumulator inputs so that we could select either the Y input data or the adder output to load into the accumulator. the accumulator must be loaded with X. This can be accomplished in several ways.Loading the Accumulator Before addition in the previous circuit can take place. Alternatively. and then put the X data on the Y inputs to the adder and add the accumulator in the normal way.Digital Electronics 34 .

Adder Cell with Multiplexer Spring 2011 ECE 301 .Digital Electronics 35 .

Digital Electronics 36 .Questions? Spring 2011 ECE 301 .