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Code No: D0605, D5509, D7701, D6801, D5701 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD M.Tech II - Semester Examinations, October 2011 SYSTEM ON CHIP ARCHITECTURE (COMMON TO DIGITAL SYSTEMS & COMPUTER ELECTRONICS, EMBEDDED SYSTEMS, EMBEDDED SYSTEMS & VLSI DESIGN, VLSI & EMBEDDED SYSTEMS, VLSI SYSTEM DESIGN) Time: 3hours Max. Marks: 60 Answer any five questions All questions carry equal marks --1. a) Draw the schematic of MUO Processor and explain its operations. b) Discuss about processor design Trade offs.

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2. a) With an example, explain about ARM Programming Model. b) Selecting certain instructions, explain about ARM instruction execution and implementation. [12] 3. 4. Explain about 3 and 5 stage Pipeline ARM organization in detail.

Giving examples, explain about i) Expressions ii) Loops iii) Conditional Statements in the use of High Level Language. With respect to sub threshold current reduction explain the following terms: i) Memory-call current ii) Peripheral -Circuit current iii) Shower Memory cycle tone iv) Iterative Circuit blocks v) Infant Predetermined Logic.

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6. a) Give the Dynamic VT Scheme by Well or source Driving of Chip. b) Give the scheme for single Power-Supply operation and explain about Power-Supply standardization. 7. a) Explain about CP15 Protection unit registers for ARM Processor. b) Give the ARM MMU & Architecture and explain about the same. How is Synchronization carried out? Explain. 8. Write notes on any Two a) Hardware systems Prototyping Tools b) Advanced Microcontroller bus architecture c) So I DRAM cell. ********

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