ECE 474A/57A Computer-Aided Logic Design

Lecture 6 Algorithmic State Machines (ASMs)

ECE 474a/575a Susan Lysecky

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Control and Datapath Interaction
ƒ Binary information in digital system can be classified into two categories
Control Signals Input data

ƒ

Data
ƒ Discrete elements of information manipulated by arithmetic, logic, shift, and other data processing ƒ Operations implemented via digital components such as adders, decoders, muxes, etc.

Input signal (external)

Controller (FSM)
Status Signals

Datapath

Output data

ƒ

Control
ƒ Provides command signals that coordinate the execution of various operations in data section to accomplish desired task
ECE 474a/575a Susan Lysecky 2 of 21

What Control Path Implements?
ƒ ƒ Sequencing of control signals to execute algorithm implemented by circuit Algorithm
ƒ Finite set of instructions/steps to solve a problem ƒ Terminates in finite time at a known end state

ƒ

Many representations
Ingredients ƒ 1/3 cup unsweetened cocoa ƒ 1/4 cup cornstarch ƒ 2 tablespoons butter ƒ 2 2/3 cups skim milk Steps 1. 2. Lamp doesn’t work int fib(int n) { if (n < 2) return n; else return fib(n-1) + fib(n-2); }

Lamp plugged in?
Yes

No

Plug in lamp

3.

Combine all ingredients in a small saucepan. Heat over low heat, stirring constantly, until mixture boils. Boil gently, stirring constantly, for one minute. Pour into serving dishes and chill until thickened.

Yes

Bulb burned out?
No

Replace bulb

Buy new lamp

Recipe

Flowchart
ECE 474a/575a Susan Lysecky

Computer Program
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1

Flowcharts and Algorithmic State Machines (ASM) ƒ Flowchart ƒ Convenient way to graphically specify sequence of procedural steps and decision paths for algorithm ƒ Enumerates sequence of operations and conditions necessary for execution ƒ Algorithmic State Machine (ASM) ƒ Flowchart defined specifically for digital hardware algorithms ƒ Flowchart vs. ASM ƒ Conventional flowchart ƒ Sequential way of representing procedural steps and decision paths for algorithm ƒ No time relations incorporated ƒ ASM chart ƒ Representation of sequence of events together with timing relations between states of sequential controller and events occurring while moving between steps ECE 474a/575a Susan Lysecky 4 of 21 ASM Chart ƒ Three basic elements ƒ State box ƒ Decision box ƒ Conditional box ƒ State and decision boxes used in conventional flowcharts ƒ Conditional box characteristic to ASM From exit path of decision box State name Binary code Condition Register operations Mealy-type output signals Exit path Exit path Exit path Register operations Moore-type output signals State Box Decision Box Conditional Box ECE 474a/575a Susan Lysecky 5 of 21 State box ƒ Used to indicate states in control sequence ƒ State name and binary code placed on top of box ƒ Register operations and names of output signals generated in state placed inside box State name Binary code Register operations Moore-type output signals ƒ Example ƒ State name: S_pause ƒ Binary encoding: 0101 ƒ Register operation: R ← 0 ƒ Register R is to be cleared to 0 S_pause R←0 Start_OP 0101 ƒ Output signal asserted: Start_OP = 1 ƒ Launches some operation in datapath ECE 474a/575a Susan Lysecky 6 of 21 2 .

take path marked 0 ECE 474a/575a Susan Lysecky 7 of 21 Conditional Box ƒ ƒ ƒ Unique to ASM From exit path of decision box Inputs come from one of exit paths of decision boxes Register operation or outputs listed inside box generated during given state ƒ Generated as Mealy-type signals ƒ Associated with the state transition Register operations Mealy-type output signals ƒ Example ƒ Status of input B checked ƒ Conditional operation executed depending on result coming from decision box ƒ If B = 1.Decision Box ƒ Reflects the effect of an input ƒ external or internal. take path marked 1 ƒ If B is false (=0). assert Incr_Reg signal ƒ Otherwise Incr_Reg remains unchanged 1 B 0 Incr_Reg ECE 474a/575a Susan Lysecky 8 of 21 ASM Block ƒ Structure consisting of ƒ One state box ƒ All decision and conditional boxes associated with its exit paths Reset_b S_0 A←A+1 001 ƒ ƒ Block has one entrance and any number of exits paths Each block in ASM dedicated to state of system during one clock cycle S_1 0 F E 1 Clear_B 0 1 010 S_2 011 S_3 100 ƒ Simplifications ƒ ASM Block not usually drawn because blocks are well defined ƒ Can label just the “1” and omit the “0” ƒ ASM chart consists of one or more interconnect ASM Blocks ECE 474a/575a Susan Lysecky 9 of 21 3 . input or status Condition ƒ Diamond shaped box ƒ Condition to be tested inside ƒ Two or more outputs represent exit paths dependant on value tested ƒ In binary case one path represents true the other false. represented by 1 and 0 respectively Exit path Exit path Exit path 1 B 0 ƒ Example ƒ Check B ƒ If B is true (=1).

F = ones. if(Input[1] == 1) ones ++. S_2. F = ones. goto S3 S3: busy = 0. if(Input[1] == 1) ones ++. goto S0 ECE 474a/575a Susan Lysecky 11 of 21 ASM Example Continued Reset_b S_0 busy = 0 ones = 0 start == 1 1 S_1 busy = 1 001 S0: busy = 0. ones = 0. if(start == 1) goto S1 else goto S0 S1: busy = 1.Interpretation of Timing Operations ƒ Conventional flowchart. or S_3 during transition of next clock S_1 010 S_2 011 S_3 100 ECE 474a/575a Susan Lysecky 10 of 21 ASM Example ƒ ƒ Convert pseudo code to ASM chart Example ƒ Want to detect the number of 1’s in a 2bit register called Input ƒ start input indicates when to begin comparison ƒ busy output indicates when comparison in progress ƒ ones hold count value ƒ F outputs result S0: busy = 0. if(Input[0] == 1) ones ++. ones = 0. if(Input[0] == 1) ones ++. goto S3 S3: busy = 0. evaluation of each follows one another ƒ Reg A incremented ƒ Condition E evaluated ƒ If E= 1 Reset_b S_0 A←A+1 001 ƒ clear B ƒ Go to state S_3 0 F E 1 Clear_B 0 1 ƒ In ASM the entire block considered as one unit ƒ All operations within block occurring during single edge transition ƒ The next state evaluated during the same clock ƒ System enters next state S_1. 1 ones++ 010 Input[1] == 1 goto S2 S2: busy = 1. if(start == 1) goto S1 else goto S0 S1: busy = 1. goto S2 S2: busy = 1. goto S0 S_2 busy = 1 011 S_3 111 Input[0] == 1 1 ones++ busy = 0 F = ones ECE 474a/575a Susan Lysecky 12 of 21 4 .

reasonable size for 4-bit: 4*4 = 16 partial product AND terms.p0 ECE 474a/575a Susan Lysecky 15 of 21 a b3 . and 31 adders here (big adders) 5 ... 3 adders ƒ Rather big for 32-bit: 32*32 = 1024 AND terms.ASM – Mux ƒ Describe a 4x1 MUX using a ASM S_0 001 x1 x2 x3 x4 s1 s0 0 0 1 1 0 1 0 1 f x1 x2 x3 x4 1 s0 1 s0 1 s1 s0 s1 0 1 2 3 f 4x1 mux F = x4 F = x3 F = x2 F = x1 ECE 474a/575a Susan Lysecky 13 of 21 ASM – Full Adder ƒ Describe a 1-bit full adder using an ASM chart A B S_0 cin 1 F 1 a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 cin 0 1 0 1 0 1 0 1 f cout 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 cin 1 cin 1 cin 1 cin b 1 b a 001 cout FA f=1 cout = 1 f=0 cout = 1 f=0 cout = 1 f=1 cout = 0 f=0 cout = 1 f=1 cout = 0 f=1 cout = 0 f=0 cout = 0 ECE 474a/575a Susan Lysecky 14 of 21 Smaller Multiplier ƒ Multiplier in array style ƒ Fast. and 31 adders a 32-bit adder would have 1024 gates here a3 b0 a2 a1 a0 b1 pp4 pp3 pp2 pp1 0 0 + (5-bit) b2 00 + (6-bit) 000 + (7-bit) p7..

compute one at a time (similar to by hand). adds to running sum ƒ Note that shifting running sum right (relative to partial product) after each step ensures partial product added to correct running sum bits multiplier start mdld multiplicand multiplicand register (4) load controller mrld mr3 mr2 mr1 mr0 rsload rsclear rsshr multiplier register (4) load 4-bit adder load clear shr running sum register (8) Step 1 0110 + 001 1 0000 + 0110 00110 Step 2 0110 + 0011 00110 +0110 010010 Step 3 0110 + 0011 010010 + 0000 0010010 Step 4 0110 + 0011 (running sum) 0010010 (partial product) + 0000 0 0 0 1 0 0 1 0 (new running sum) ECE 474a/575a Susan Lysecky product 17 of 21 Smaller Multiplier -.Sequential (Add-and-Shift) Style ƒ Smaller multiplier: Basic idea ƒ ƒ Don’t compute all partial products simultaneously Rather. add multiplicand to running sum Step 3 • Check multiplier bit 2 (mr2) • Shift running sum right 1 position Step 4 • Check multiplier bit 3 (mr3) • Shift running sum right 1 position running sum register (8) 00000000 00010010 00100100 01001000 10010000 00110000 01100000 product ECE 474a/575a Susan Lysecky 18 of 21 6 .Sequential (Add-and-Shift) Style Step 0 • Set running sum to 0 • Load values Step 1 • Check multiplier bit 0 (mr0) • • multiplier start mdld multiplicand multiplicand register (4) load 0110 controller Shift running sum right 1 position mr0=1.Sequential (Add-and-Shift) Style ƒ Design circuit that computes one partial product at a time. add multiplicand to running sum mrld mr3 mr2 mr1 mr0 rsload rsclear rsshr load clear shr multiplier register (4) load Step 2 • Check multiplier bit 1 (mr1) • • 0011 4-bit adder Shift running sum right 1 position mr0=1. maintain running sum Step 1 0110 + 0 0 11 (running sum) 0000 (partial product) + 0 1 1 0 (new running sum) 0 0 1 1 0 Step 2 0110 + 0 01 1 00110 +0 1 1 0 010010 Step 3 0110 + 00 1 1 010010 + 0000 0010010 Step 4 0110 + 0011 0010010 + 0000 00010010 a ECE 474a/575a Susan Lysecky 16 of 21 Smaller Multiplier -.Smaller Multiplier -.

we’ve already seen how to implement in hardware S_pause R←0 Start_OP 1 B 0 Incr_Reg S_1 0 0 F 010 S_2 0101 A1 0101 Reset_b S_0 001 A←A+1 E 1 1 Clear_B 011 S_3 100 S_0 S_pause R=0 Start_OP = 1 B A1 B’ / Incr_Reg = 1 S_1 E’F’ E’F S_2 A=A+1 E / Clear_B = 1 S_3 ECE 474a/575a Susan Lysecky 20 of 21 Not Used Much. Inc.ASM – Sequential Multiplier multiplier Reset_b S_0 start mdld multiplicand multiplicand register (4) load mr1 1 rsload = 1 controller start 1 S_1 mdld = 1 mrld = 1 rsclear = 1 S_2 S_5 mr0 1 rsload = 1 S_3 rsshr = 1 S_6 S_4 mrld mr3 mr2 mr1 mr0 rsload rsclear rsshr multiplier register (4) load 4-bit adder rsshr = 1 1 rsload = 1 mr2 load clear shr running sum register (8) rsshr = 1 product mr3 1 rsload = 1 rsshr = 1 ECE 474a/575a Susan Lysecky 19 of 21 ASMs to FSMDs ƒ ƒ Able to convert between formats Once we have a FSMD. ƒ Others… ECE 474a/575a Susan Lysecky 21 of 21 7 . But … ƒ There are commerical ASM Editors ƒ Mentor Graphics ƒ Summit Design.

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