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Source: Phase-Locked Loops

Chapter

1

Introduction to PLLs

1.1 Operating Principles of the PLL The phase-locked loop (PLL) helps keep parts of our world orderly. If we turn on a television set, a PLL will keep heads at the top of the screen and feet at the bottom. In color television, another PLL makes sure that green remains green and red remains red (even if the politicians claim that the reverse is true). A PLL is a circuit that causes a particular system to track with another one. More precisely, a PLL is a circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in frequency as well as in phase. In the synchronized—often called locked—state the phase error between the oscillator’s output signal and the reference signal is zero, or remains constant. If a phase error builds up, a control mechanism acts on the oscillator in such a way that the phase error is again reduced to a minimum. In such a control system the phase of the output signal is actually locked to the phase of the reference signal. This is why it is referred to as a phase-locked loop. The operating principle of the PLL is explained by the example of the linear PLL (LPLL). As will be pointed out in Sec. 1.2, there exist other types of PLLs, e.g., digital PLLs (DPLLs), all-digital PLLs (ADPLLs), and software PLLs (SPLLs). Its block diagram is shown in Fig. 1.1a. The PLL consists of three basic functional blocks: 1. A voltage-controlled oscillator (VCO) 2. A phase detector (PD) 3. A loop ﬁlter (LF) In this simple example, there is no down-scaler between output of VCO [u2(t)] and lower input of the phase detector [w2]. Systems using down-scalers are discussed in the following chapters. In some PLL circuits a current-controlled oscillator (CCO) is used instead of the VCO. In this case the output signal of the phase detector is a controlled

1

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Introduction to PLLs

2

Chapter One

input signal u1 (t) (w1) (w2) phase detector

ud(t) loop filter

uf (t) FM-output

output signal u2(t)

**voltage controlled oscillator
**

(a)

w2

ud

wo uf qe

(b) (c) Figure 1.1

(a) Block diagram of the PLL. (b) Transfer function of the VCO. (uf = control voltage; w2 = angular frequency of the output signal.) (c) Transfer function of the PD. ( ud = average value of the phase-detector output signal; qe = phase error.)

current source rather than a voltage source. However, the operating principle remains the same. The signals of interest within the PLL circuit are deﬁned as follows:

The reference (or input) signal u1(t) The angular frequency w1 of the reference signal The output signal u2(t) of the VCO The angular frequency w2 of the output signal The output signal ud(t) of the phase detector The output signal uf (t) of the loop ﬁlter The phase error qe, deﬁned as the phase difference between signals u1(t) and u2(t)

Let us now look at the operation of the three functional blocks in Fig. 1.1a. The VCO oscillates at an angular frequency w2, which is determined by the output signal uf of the loop ﬁlter. The angular frequency w2 is given by

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Introduction to PLLs

Introduction to PLLs

3

w 2 (t) = w 0 + K 0uf (t)

(1.1)

where w0 is the center (angular) frequency of the VCO and K0 is the VCO gain in rad · s-1 · V-1. Equation (1.1) is plotted in Fig. 1.1b. Because the rad (radian) is a dimensionless quantity, we will drop it mostly in this text. (Note, however, that any phase variables used in this book will have to be measured in radians and not in degrees!) Therefore, in the equations a phase shift of 180° must always be speciﬁed as a value of p. The PD—also referred to as phase comparator—compares the phase of the output signal with the phase of the reference signal and develops an output signal ud(t) that is approximately proportional to the phase error qe, at least within a limited range of the latter: ud (t) = K dq e (1.2)

Here Kd represents the gain of the PD. The physical unit of Kd is volts per radian. Figure 1.1c is a graphical representation of Eq. (1.2). The output signal ud(t) of the PD consists of a dc component and a superimposed ac component. The latter is undesired; hence it is canceled by the loop ﬁlter. In most cases a ﬁrst-order, low-pass ﬁlter is used. Let us now see how the three building blocks work together. First we assume that the angular frequency of the input signal u1(t) is equal to the center frequency w0. The VCO then operates at its center frequency w0. As we see, the phase error qe is zero. If qe is zero, the output signal ud of the PD must also be zero. Consequently the output signal of the loop ﬁlter uf will also be zero. This is the condition that permits the VCO to operate at its center frequency. If the phase error qe were not zero initially, the PD would develop a nonzero output signal ud. After some delay the loop ﬁlter would also produce a ﬁnite signal uf. This would cause the VCO to change its operating frequency in such a way that the phase error ﬁnally vanishes. Assume now that the frequency of the input signal is changed suddenly at time t0 by the amount Dw. As shown in Fig. 1.2, the phase of the input signal then starts leading the phase of the output signal. A phase error is built up and increases with time. The PD develops a signal ud(t), which also increases with time. With a delay given by the loop ﬁlter, uf (t) will also rise. This causes the VCO to increase its frequency. The phase error becomes smaller now, and after some settling time the VCO will oscillate at a frequency that is exactly the frequency of the input signal. Depending on the type of loop ﬁlter used, the ﬁnal phase error will have been reduced to zero or to a ﬁnite value. The VCO now operates at a frequency that is greater than its center frequency w0 by an amount Dw. This will force the signal uf(t) to settle at a ﬁnal value of uf = Dw/K0. If the center frequency of the input signal is frequency modulated by an arbitrary low-frequency signal, then the output signal of the loop ﬁlter is the demodulated signal. The PLL can consequently be used as an

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Introduction to PLLs

4

Chapter One

**u1(t) frequency step
**

(a)

to

t

u2(t)

(b)

t

qe, ud

(c)

qe = 0

qe

qe

qe

qe

t u f, w 2

(d)

t w1 w0

(e)

Dw t

Figure 1.2

Transient response of a PLL onto a step variation of the reference frequency. (a) Reference signal u1(t). (b) Output signal u2(t) of the VCO. (c) Signals ud (t) and qe(t) as a function of time. (d) Angular frequency w2 of the VCO as a function of time. (e) Angular frequency w1 of the reference signal u1(t).

FM detector. As we shall see later, it can be further applied as an AM or PM detector. One of the most intriguing capabilities of the PLL is its ability to suppress noise superimposed on its input signal. Let us suppose that the input signal of the PLL is buried in noise. The PD tries to measure the phase error between input and output signals. The noise at the input causes the zero crossings of the input signal u1(t) to be advanced or delayed in a stochastic manner. This causes the PD output signal ud(t) to jitter around an average value. If the corner frequency of the loop ﬁlter is low enough, almost no noise will be noticeable in the signal uf (t), and the VCO will operate in such a way that the phase of the signal u2(t) is equal to the average phase of the input signal u1(t). Therefore, we can state that the PLL is able to detect a signal that is buried in noise. These

Introduction to PLLs

Introduction to PLLs

5

simpliﬁed considerations have shown that the PLL is nothing but a servo system that controls the phase of the output signal u2(t). As shown in Fig. 1.2, the PLL was always able to track the phase of the output signal to the phase of the reference signal; this system was locked at all times. This is not necessarily the case, however, because a larger frequency step applied to the input signal could cause the system to ‘‘unlock.’’ The control mechanism inherent in the PLL will then try to become locked again, but will the system indeed lock again? We shall deal with this problem in the following chapters. Basically two kinds of problems have to be considered:

The PLL is initially locked. Under what conditions will the PLL remain locked? The PLL is initially unlocked. Under what conditions will the PLL become locked?

If we try to answer these questions, we notice that different PLLs behave quite differently in this regard. We ﬁnd that there are some fundamentally different types of PLLs. Therefore, we ﬁrst identify these various types. 1.2 Classiﬁcation of PLL Types The very ﬁrst phase-locked loops (PLLs) were implemented as early as 1932 by de Bellescize22; this French engineer is considered the inventor of “coherent communication.” The PLL found broader industrial applications only when it became available as an integrated circuit. The ﬁrst PLL ICs appeared around 1965 and were purely analog devices. An analog multiplier (four-quadrant multiplier) was used as the phase detector, the loop ﬁlter was built from a passive or active RC ﬁlter, and the well-known voltage-controlled oscillator (VCO) was used to generate the output signal of the PLL. This type of PLL is referred to as the “linear PLL ” (LPLL) today. In the following years the PLL drifted slowly but steadily into digital territory. The very ﬁrst digital PLL (DPLL), which appeared around 1970, was in effect a hybrid device: only the phase detector was built from a digital circuit, e.g., from an EXOR gate or a JK-ﬂipﬂop, but the remaining blocks were still analog. A few years later, the “all-digital” PLL (ADPLL) was invented. The ADPLL is exclusively built from digital function blocks and hence doesn’t contain any passive components like resistors and capacitors. Analogous to ﬁlters, PLLs can also be implemented by software. In this case, the function of the PLL is no longer performed by a piece of specialized hardware, but rather by a computer program. This last type of PLL is referred to as SPLL. Different types of PLLs behave differently, so there is no common theory that covers all kinds of PLLs. The performance of LPLLs and DPLLs is similar, however; hence we can develop a theory that is valid for both categories. We will deal with LPLLs and DPLLs in Chap. 2, “Mixed-Signal PLLs.” The term

or an ADPLL. The ADPLL behaves very differently from mixed-signal PLLs and hence is treated in a separate chapter (Chap. a DPLL. Strictly speaking. This offers the greatest ﬂexibility. . Any use is subject to the Terms of Use as given at the website. an SPLL can be programmed to behave like an LPLL. because a vast number of different algorithms can be developed. We will deal with SPLLs in Chap. 6). The software PLL is normally implemented by a hardware platform such as a microcontroller or a digital signal processor (DSP). For example.digitalengineeringlibrary.Introduction to PLLs 6 Chapter One “mixed” indicates that these PLLs are mostly hybrids built from linear and digital circuits. the LPLL is purely analog.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. 8. Downloaded from Digital Engineering Library @ McGraw-Hill (www. only the DPLL is a mixed-signal circuit. The PLL function is realized by software.

Again. 1. As shown in Sec. In most cases the divider ratio N is made programmable. u2¢.2. Obviously.g. 1.digitalengineeringlibrary. These PLLs are therefore second-order systems.1). In a few cases the ﬁlter may be omitted.com) Copyright © 2004 The McGraw-Hill Companies. 2.1. 3. as shown in Fig. we introduce two different terms for center (radian) frequency: we will use the symbol w0 to denote the center frequency at the output of the VCO. another block is added: a divide-by-N counter. When the VCO does not operate at its center frequency (uf π 0). the order (number of poles of the transfer function) of a PLL is equal to the order of the loop ﬁlter + 1. We will deal extensively with frequency synthesizers in Chap. the mixed-signal PLL includes circuits that are hybrids of both linear and digital circuits. Assuming that the counter divides by a factor N.and second-order PLLs. When a down-scaler is inserted..1 Block Diagram of the Mixed-Signal PLL As mentioned in Sec. w0 and w0¢ are related by w0¢ = w0/N. 2. Higher-order loops come into play when suppression of 7 Downloaded from Digital Engineering Library @ McGraw-Hill (www. and voltage-controlled oscillator (VCO). the term center frequency becomes ambiguous: the center (radian) frequency w0 can be related to the output of the VCO (as done in Sec. but it could also be related to the output of the downscaler. For the down-scaled frequency. or in other words. . ﬁrst-order loop ﬁlters are applied. its output radian frequency is denoted w2. In this chapter we will deal exclusively with ﬁrst. to the input of the PLL. the quantities related to the output signal of the down-scaler are characterized by a prime (¢ symbol). 2. To see which parts of the system are linear and which are digital. To remove this dilemma. All rights reserved. When the PLL is used as a frequency synthesizer. we have w2¢ = w2/N. the symbol w2¢ is used. e. and the symbol w0¢ to denote the center radian frequency at the input of the PLL. we consider the general block diagram in Fig. As will be demonstrated later in this chapter.Source: Phase-Locked Loops Chapter 2 Mixed-Signal PLLs 2. 1. loop ﬁlter. In most practical PLLs.1 every PLL consists of the three blocks: phase detector.1. Any use is subject to the Terms of Use as given at the website. w2¢.1. the frequency of the VCO output signal is forced then to be N times the reference frequency (the frequency of the input signal u1). such a PLL is a ﬁrst-order loop. As seen from Fig.

Mixed-Signal PLLs

8

Chapter Two

u1, w1 ¢ , w2 ¢ u2 Phase Detector

ud

Loop Filter

uf VCO

u 2 , w2

:N Counter

Figure 2.1

Block diagram of the mixed-signal PLL. The symbols deﬁned here are used throughout this chapter. The divide-by-N counter is optional.

spurious sidebands (also called “spurs”) becomes an issue. The designer of the PLL then has to provide higher-order loop ﬁlters,10 i.e., loop ﬁlters of order 2, 3, or even 4. Increasing the order also increases the phase shift of such ﬁlters; thus higher-order PLLs are prone to become unstable. We will deal with higher order (>2) PLLs in a separate chapter (Chap. 4) where we will show how to specify the poles and zeros of higher-order loop ﬁlters in order to maintain stable operation. As was explained in Sec. 1.1, the PLL is nothing more than a control system that acts on the VCO in such a way that the frequency of the signal u2¢ is identical to the frequency of signal u1. Moreover, the phase of signal u2¢ is nearly identical with the phase of signal u1 or is offset by a nearly constant value from the latter. The PLL can therefore be considered as a control system for phase signals. Because phase signals are less frequently found in control theory than, for example, voltage or current signals, we will consider the nature of phase signals in more detail in Sec. 2.2. The properties of the PLL’s building blocks will be discussed in Sec. 2.3. 2.2 A Note on Phase Signals Dynamic analysis of a control system is normally performed by means of its transfer function H(s). H(s) relates the input and output signals of the system; in conventional electrical networks the input and the output are represented by voltage signals u1(t) and u2(t), respectively, so H(s) is given by H (s) = U 2 (s) U1 (s) (2.1)

where U1(s) and U2(s) are the Laplace transforms of u1(t) and u2(t), respectively, and s is the Laplace operator. In the case of the PLL, the input and output signals are phase signals, however, which are less familiar to many electronic engineers. To see what phase signals really are, we assume for the moment that both input and output signals of the PLL (Fig. 2.1) are sine waves:

Mixed-Signal PLLs

Mixed-Signal PLLs

9

u1 (t) = U10 sin[w 1t + q1 (t)] u2 ¢(t) = U 20 sin[w 2 ¢ t + q2 ¢(t)]

(2.2)

The information carried by these signals is neither the amplitude (U10 or U20, respectively) nor the frequency (w1 or w2¢, respectively) but the phases q1(t) and q2¢(t). (Note: because we used the symbol w2¢ for the radian frequency at the output of the down-scaler (Fig. 2.1), we use the symbol q2¢ for the phase of signal u2¢ and not q2; the latter is used to specify the phase of the VCO output signal u2.) Let us consider now some simple phase signals; Fig. 2.2 lists a number of phase signals q1(t) that are frequently used to excite a PLL. Figure 2.2a shows the simplest case: the phase q1(t) performs a step change at time t = 0, hence is given by q1 (t) = DF ◊ u(t) (2.3)

where u(t) is the unit step function. This case is an example of phase modulation. Let us consider next an example of frequency modulation (Fig. 2.2b). Assume the angular frequency of the reference signal is w0¢ for t < 0. At t = 0 the angular frequency is abruptly changed by the increment Dw. For t ≥ 0 the reference signal is consequently given by u1 (t) = U10 sin(w 0 ¢ t + Dwt) = U10 sin(w 0 ¢ t + q1 ) In this case the phase q1(t) can be written as q1 (t) = Dw ◊ t (2.5) (2.4)

Consequently the phase q1(t) is a ramp signal. As a last example, consider a reference signal whose angular frequency is w0¢ for t < 0 and increases linearly with time for t ≥ 0 (Fig. 2.2c). For t ≥ 0 its angular frequency is therefore ˙ ◊t w 1 (t) = w 0 ¢ + Dw (2.6)

˙ the rate of change of angular frequency. Remember that the angular where D w frequency of a signal is deﬁned as the ﬁrst derivative of its phase with respect to time: w 1 (t) = dq1 dt (2.7)

Hence the phase of a signal at time t is the integral of its angular frequency over the time interval 0 < t < t, where t denotes elapsed time. The reference signal can be written as t2 ˙ ◊ t)dt = U10 sinÊ w 0 ¢ t + Dw ˙ ˆ u1 (t) = U10 sin Ú (w 0 ¢ + Dw Ë 2¯ 0

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t

(2.8)

Mixed-Signal PLLs

10

Chapter Two

u1

t

q1 t

(a)

u1

t

w1 Dw t q1 t

(b)

u1

t

w1 t q1 t

(c)

Some typical exciting functions as applied to the reference input of a PLL. (a) Phase step applied at t = 0; q1(t) = DF·u(t). (b) Frequency step Dw applied at t = 0; q1(t) = Dw·t. (c) Frequency ramp starting at t = 0; ˙ t2/2. q1(t) = D w

Figure 2.2

Mixed-Signal PLLs

Mixed-Signal PLLs

11

Consequently the corresponding phase signal q1(t) is given by ˙ q1 (t) = Dw i.e., it is a quadratic function of time. 2.3 Building Blocks of Mixed-Signal PLLs The building blocks of a PLL have been deﬁned in Fig. 2.1. In the following sections we are going to discuss the properties of various phase detectors, loop ﬁlters, controlled oscillators, and down-scalers.

2.3.1 Phase detectors

t2 2

(2.9)

A phase detector is a circuit capable of delivering an output signal that is proportional to the phase difference between its two input signals u1 and u2¢ (Fig. 2.1). Many circuits could be applied. In mixed-signal PLLs, mainly four types of phase detectors are used. The ﬁrst phase detector in the history of the PLL was the linear multiplier (also referred to as four-quadrant multiplier). When the PLL moved into digital territory, digital phase detectors become popular, such as the EXOR gate, the edge-triggered JK-ﬂipﬂop, and the so-called phase-frequency detector (PFD). Let us start with the discussion of the multiplier phase detector.

Type 1: Multiplier phase detector.

The multiplier phase detector is used exclusively in linear PLLs (LPLLs). In an LPLL, the input signal u1 is mostly a sine wave, given by u1 (t) = U10 sin(w 1t + q1 ) (2.10a)

where U10 is the amplitude of the signal, w1 is its radian frequency, and q1 its phase. The second input signal u2¢ (Fig. 2.1) is usually a symmetrical square wave signal (sometimes also called Walsh function) 21 and is given by u2 ¢(t) = U 20 rect (w 2 ¢ t + q2 ¢) (2.10b)

where rect stands for rectangular (square wave) and U20 is the amplitude, w2¢ the radian frequency, and q2¢ the phase. These signals are shown in Fig. 2.3. The dashed curve in Fig. 2.3a is a sine wave having a phase of q1 = 0; the solid line has a nonzero phase q1. For simplicity we assume here that the phase is constant over time. The dashed curve in Fig. 2.3b shows a symmetrical square wave having a phase q2¢ = 0; the solid line has a nonzero phase. The output signal of the four-quadrant multiplier is obtained by multiplying the signals u1 and u2¢. To simplify the analysis the square wave signal is replaced by its Fourier series. For u2¢(t) we then get

Mixed-Signal PLLs

12

Chapter Two

u1

q1 t

(a)

¢ u2 1 ¢ q2

t 1

(b) Figure 2.3

Input signals of the multiplier phase detector. (a) Signal u1(t) is a sine wave. Dashed line: phase q1 = 0; solid line: phase q1 > 0. (b) Signal u2¢(t) is a symmetrical square wave signal. Dashed line: q2¢ = 0; solid line: q2¢ > 0.

4 4 u2 ¢(t) = U 20 È cos(w 2 ¢ + q2 ¢) + cos(3w 2 ¢ t + q2 ¢) ◊ ◊ ◊ ˘ Í ˙ 3p Îp ˚

(2.11)

The ﬁrst term in square brackets is the fundamental component; the remaining terms are odd harmonics. For the output signal ud(t), therefore, we get ud (t) = u1 (t) ◊ u2 ¢(t) 4 4 cos(w 2 ¢ t + q2 ¢) + cos(3w 2 ¢ t + q2 ¢) + ◊ ◊ ◊ ˘ = U10U 20 sin(w 1t + q1 )È Í ˙ 3p Îp ˚ (2.12)

When the PLL is locked, the frequencies w1 and w2¢ are identical, and ud(t) becomes 2 ud (t) = U10U 20 Ê sin q e ◊ ◊ ◊ ˆ Ëp ¯ (2.13)

Mixed-Signal PLLs

Mixed-Signal PLLs

13

where qe = q1 - q2¢ is the phase error. The ﬁrst term of this series is the wanted “dc” term, whereas the higher-frequency terms will be eliminated by the loop ﬁlter. Setting Kd = 2U10U20/p and neglecting higher-frequency terms we get ud (t) ª K d sin(q e ) (2.14)

where Kd is called detector gain. When the phase error is small, the sine function can be replaced by its argument, and we have ud (t) ª K dq e (2.15)

This equation represents the linearized model of the phase detector. The dimension of Kd is radians per volt (rad/V). As shown above, Kd is proportional to both amplitudes U10 and U20. Normally, U20 is constant, so Kd becomes a linear function of the input signal level U10. This is plotted in Fig. 2.4. Because the multiplier saturates when its output signal comes close to the power supply rails, this function ﬂattens out at large signal levels, and Kd approaches a limiting value. To conclude the analysis of the four-quadrant multiplier we state that—in the locked state of the PLL—the phase detector represents a zero-order block having a gain of Kd. To complete the discussion of the multiplier-type phase detector we look at its behavior in the unlocked state of the PLL. When the PLL is out of lock, the radian frequencies w1 and w2¢ are different. The output signal of the multiplier then can be written as ud (t) = K d sin(w 1t - w 2 ¢ t + q1 - q2 ¢) + higher harmonics (2.16)

The higher harmonics are almost entirely suppresed by the loop ﬁlter; hence there remains one ac term whose frequency equals the difference w1 - w2¢.

Kd

ˆ U 10

**Phase-detector gain Kd as a function of the amplitude U10 of the reference signal.
**

Figure 2.4

ud will be approximately 2. this case is shown in Fig. the ac signal ud(t) is an asymmetric “sine wave”. we are tempted to conclude that its average is zero. Because the high-frequency component of this signal will be ﬁltered out by the loop ﬁlter.2.e. we consider only the average value of ud. 2. 2. We continue the discussion of phase detectors with the EXOR (exclusive-OR) gate. provided the initial difference of radian frequencies w1 . The operation of the EXOR phase detector (Fig.. i. i. This would imply that the average output signal of the loop ﬁlter would also be zero (cf. the durations of the positive and negative half waves are different.5) is similar to that of the linear multiplier.5 EXOR phase detector. square waves.digitalengineeringlibrary. Nevertheless. the phase error qe becomes positive by deﬁnition. . 2.5 V . This voltage level is considered the quiescent point of the EXOR and will be denoted as ud = 0 from now on.Mixed-Signal PLLs 14 Chapter Two Because the output is an ac signal. 2.e. because its output signal is not only phase sensitive.. the average value of ud is considered positive. At zero phase error the signals u1 and u2¢ are out of phase by exactly 90°.6a. Downloaded from Digital Engineering Library @ McGraw-Hill (www. Clearly.e. All rights reserved.1). 2. Then the output signal ud is a square wave whose frequency is twice the reference frequency. We assume for the moment that both signals u1 and u2¢ are symmetrical square waves.6a. Figure 2. i. let us note that this pull-in process is quite slow. as shown in Fig.w2¢ is less than a limiting value called pull-in range DwP. 2. as shown by the dashed line in the ud waveform. When the output signal u2¢ lags the reference signal u1. It will be demonstrated later in this section that another type of phase detector—the so called phase-frequency detector—enables much faster acquisition.6b. Fig. The signals in DPLLs are always binary signals. This would make it impossible for the loop to acquire lock because the frequency of the VCO output signal would permanently stay hung up at its center frequency w0. u1 ud ¢ u2 Figure 2.6. but also frequency sensitive (in the unlocked state). if the EXOR is powered from an asymmetrical 5-V power supply. The average value (denoted ud ) is the arithmetic mean of the two logical levels. as shown by the dashed line in Fig.. the duty cycle of the ud signal is exactly 50 percent.com) Copyright © 2004 The McGraw-Hill Companies. Consequently there will be a nonzero dc component that will pull the average output frequency of the VCO up or down until lock is acquired. As we will see in “Pull-out Range DwPO” in Sec. the mean of ud reaches its maximum value for a phase error of Type 2: EXOR phase detector. however. Now the duty cycle of ud becomes larger than 50 percent.6 depicts the waveforms of the EXOR phase detector for different phase errors qe. Any use is subject to the Terms of Use as given at the website. with a superimposed frequency modulation.

2.6 Waveforms of the signals for the EXOR phase detector. and when we assume that the logic levels are UB and 0. ud is exactly proportional to qe and can be written as ud = K dq e (2. When the supply voltages of the EXOR are UB and 0.18) When the output signal of the EXOR does not reach the supply rails but rather saturates at some higher level Usat+ (in the high state) and some lower level Usat(in the low state). All rights reserved. (b) Waveforms at positive phase error (qe > 0). Kd must be calculated from Downloaded from Digital Engineering Library @ McGraw-Hill (www.7a. qe = 90° and its minimum value for qe = -90°. Any use is subject to the Terms of Use as given at the website.com) Copyright © 2004 The McGraw-Hill Companies. respectively. the phase detector gain Kd is constant. If we plot the mean of ud versus phase error qe. Kd is given by Kd = UB p (2. (a) Waveforms at zero phase error (qe = 0). Whereas the output signal of the four-quadrant multiplier varied with the sine of phase error. the average output of the EXOR is a triangular function of phase error. Within a phase error range of -90° < qe < 90°. .digitalengineeringlibrary. we get the characteristic shown in Fig.Mixed-Signal PLLs Mixed-Signal PLLs qe = 0 u1 15 u2 ¢ ud = 0 ud (a) u1 u2 ¢ qe > 0 ud > 0 ud (b) Figure 2.17) In case of the EXOR phase detector.

Mixed-Signal PLLs 16 Chapter Two Kd = U sat + . Downloaded from Digital Engineering Library @ McGraw-Hill (www. . the radian frequencies w1 and w2¢ are different.19) Like the four-quadrant multiplier. the pull-in process becomes slow. Any use is subject to the Terms of Use as given at the website. as we did in the case of the multiplier phase detector. If this happens. 2.w2¢. i. It is important to look also at the performance of the EXOR phase detector in the unlocked state of the PLL.7 90 180 qe (deg) Plot of averaged phase detector output signal ud versus phase error qe. the EXOR phase detector can maintain phase tracking when the phase error is conﬁned to the range p 2 < qe < p 2 The performance of the EXOR phase detector becomes severely impaired if the signals u1 and u2¢ become asymmetrical. etc. pull-out range. (a) Normal case: waveforms u1 and u2¢ in Fig.e..6 are symmetrical square waves.com) Copyright © 2004 The McGraw-Hill Companies.digitalengineeringlibrary. (b) Waveforms u1 and u2¢ are asymmetrical. The EXOR therefore performs very much like the multiplier phase detector. the output signal gets clipped at some intermediate level. the higher harmonics will be ﬁltered out by the loop ﬁlter. 2.7b.U sat p (2. This reduces the loop gain of the PLL and results in smaller lock range. as shown by Fig. The output signal of the EXOR then contains an ac term whose fundamental radian frequency is the difference w1 . When the PLL is out of lock. All rights reserved. and acqui- ud Kd p 2 –180 –90 0 90 180 qe (deg) –Kd p 2 (a) ud –90 –180 0 (b) Figure 2. The characteristic of the phase detector is clipped.

Mixed-Signal PLLs Mixed-Signal PLLs 17 sition is realized only when the difference w1 and w2¢ is less than the pull-in frequency DwP.6. (b) Waveforms at positive phase error.digitalengineeringlibrary. The JK-ﬂipﬂop phase detector is shown in Fig. With no phase error.2. This will be discussed in more detail in “Pull-in Range DwP and Pull-in Time TP” in Sec. Type 3: JK-ﬂipﬂop phase detector. A positive edge appearing at the J input triggers the ﬂipﬂop into its “high” state (Q = 1). All rights reserved. Figure 2. This type of JK-ﬂipﬂop differs from conventional JK-ﬂipﬂops. The output u1 J FF Q ud u2 ¢ Figure 2.9 Waveforms of the signals for the JK-ﬂipﬂop phase detector. qe = 0 u1 u2 ¢ ud = 0 (a) ud u1 u2 ¢ qe > 0 ud > 0 ud (b) Figure 2. u1 and u2¢ have opposite phase. Downloaded from Digital Engineering Library @ McGraw-Hill (www.9a shows the waveforms of the JK-ﬂipﬂop phase detector for the case qe = 0. Any use is subject to the Terms of Use as given at the website. a positive edge at the K input into its “low” state (Q = 0).8. 2. . because it is edge triggered.8 K Q JK-ﬂipﬂop phase detector. (a) Waveforms at zero phase error.com) Copyright © 2004 The McGraw-Hill Companies. 2.

All rights reserved. Within a phase error range of -p < qe < p the average signal ud is proportional to qe and is given by ud = K dq e (2.U sat 2p (2.21) when the logic levels are UB or 0. This condition is considered as ud being zero. By an analogous consideration.20) Obviously the JK-ﬂipﬂop phase detector is able to maintain phase tracking for phase errors within the range -p < qe < p. In contrast to the EXOR. ud does not depend on the duty cycle of the signals. Downloaded from Digital Engineering Library @ McGraw-Hill (www. the phase detector gain of the JK-ﬂipﬂop phase detector is given by Kd = UB 2p (2.22) In contrast to that for the EXOR gate. ud becomes maximum when the phase error reaches 180° and minimum when the phase error is -180°. because the state of the JK-ﬂipﬂop is altered only by the positive transitions of these signals. phase detector gain must be computed from Kd = U sat + . the duty cycle of the ud signal becomes greater than 50 percent.com) Copyright © 2004 The McGraw-Hill Companies. ud Kdp –180 0 180 qe (deg) –Kdp Figure 2.9b). ud becomes positive. Clearly.e. Any use is subject to the Terms of Use as given at the website. If. 2.Mixed-Signal PLLs 18 Chapter Two signal ud then represents a symmetrical square wave whose frequency is identical with the reference frequency (and not twice the reference frequency). If the mean value of ud is plotted versus phase error qe. respectively.10 Plot of averaged phase detector output signal ud versus phase error qe.digitalengineeringlibrary. the symmetry of the u1 and u2¢ signals is irrelevant. 2. If the phase error becomes positive (Fig.. i. the sawtooth characteristic of Fig.10 is obtained. . however. these levels are limited by saturation.

All rights reserved. The PFD can be in one of four states: Type 4: Phase-frequency detector (PFD). 2.6.com) Copyright © 2004 The McGraw-Hill Companies. DN = 0 UP = 0. 2. DN = 1 UB UP D CP FF Q P “1” u1 CD Ud CD u2 ¢ “1” CP FF DN D Q N Figure 2.2. The PFD differs greatly from the phase detector types discussed hitherto. As its name implies.w2¢. Any use is subject to the Terms of Use as given at the website. respectively. The pull-in process of the PLL containing a JK-ﬂipﬂop phase detector will be discussed in more detail in “Pullin Range DwP and Pull-in Time TP” in Sec. the output signal ud(t) of the JK-ﬂipﬂop phase detector contains a term whose fundamental radian frequency is w1 . when the PLL has not yet acquired lock. The PFD is built from two D-ﬂipﬂops.w2¢. whose outputs are denoted UP and DN (down).Mixed-Signal PLLs Mixed-Signal PLLs 19 In the unlocked state the JK-ﬂipﬂop phase detector behaves very much the same as the EXOR and the multiplier phase detectors. UP = 0.digitalengineeringlibrary.11. Downloaded from Digital Engineering Library @ McGraw-Hill (www. . its output signal depends not only on phase error qe but also on frequency error Dw = w1 .11 Schematic diagram of the PFD. The schematic diagram of the PFD is shown in Fig. DN = 0 UP = 1. Higher harmonics are removed by the loop ﬁlter. When radian frequencies w1 and w2¢ are different. DN = 1 UP = 1.

ud is a ternary signal. a logic high level appears at their CD (clear direct) inputs. Fig.Mixed-Signal PLLs 20 Chapter Two The fourth state is inhibited. DN = 0 Æ state = 0 UP = 1. We assign the symbols -1. the Nchannel MOS transistor conducts. and the output signal ﬂoats. which resets both ﬂipﬂops. and when it is in the 0 state. a positive edge of u2¢ forces the PFD into its next lower state. Downloaded from Digital Engineering Library @ McGraw-Hill (www. Consequently the device acts as a tristable device (“triﬂop”). however. Whenever both ﬂipﬂops are in the 1 state. When the UP signal is high. This drawing shows the events causing the PFD to change its current state. when it is in the -1 state. 2.12.) As Fig. we could have reversed the deﬁnition by saying that the PFD acts on the negative transitions only. the P-channel MOS transistor conducts..11 shows how the ud signal is generated. Most logic circuits used today generate binary signals. All rights reserved. When the PFD is in the 1 state. DN = 0 Æ state = 1 The actual state of the PFD is determined by the positive-going transients of the signals u1 and u2¢. 0. If neither signal is high.12 shows. ud must be positive. The output signal ud is a logical function of the PFD state.e. 2. (In this example we assumed that the PFD acts on the positive edges of these signals exclusively. and 1 to these three states: DN = 1. unless it is already in the -1 state. 2. The circuitry within the dashed box of Fig. When the DN signal is high. unless it is already in the 1 state. however. Theoretically. as explained by the state diagram. Any use is subject to the Terms of Use as given at the website. UP = 0 Æ state = -1 UP = 0. i. ud must be zero.12 u2 ¢ State diagram for the phase-frequency detector (PFD). . both MOS transistors are off. In analogy. ud must be negative. by an additional AND gate.digitalengineeringlibrary. is in the u1 u2 ¢ –1 o u1 u1 +1 u2 ¢ Figure 2. so ud equals the positive supply voltage UB. but the third state (ud = 0) can be substituted by a “high-impedance” state.com) Copyright © 2004 The McGraw-Hill Companies. so ud is on ground potential. a positive transition of u1 forces the PFD to go into its next higher state.

The signals u1 and u2¢ are “exactly” in phase here. When the phase error is restricted to the range -2p < qe < 2p. Figure 2.U sat 4p (2. We con- Downloaded from Digital Engineering Library @ McGraw-Hill (www. 2. 2. 2. the PFD will toggle between the states -1 and 0. The u1 signal then generates more positive transitions per unit of time than the signal u2¢. 2. the average signal ud becomes ud = K dq e In analogy to the JK-ﬂipﬂop.14. The PFD now toggles between the states 0 and 1. If u1 lags as shown in Fig. these levels are limited by saturation. phase detector gain must be computed from Kd = U sat + .23) when the logic levels are UB or 0. hence their effects will cancel. phase detector gain is computed by Kd = UB 4p (2. All rights reserved. however. An analogous consideration can be made for phase errors smaller than -2p.13.14 also shows the average detector output signal for phase errors greater than 2p or smaller than -2p. hence the characteristic curve of the PFD becomes periodic with period 2p. the output signal ud represents a tristate signal.24) (2. Looking at Fig.Mixed-Signal PLLs Mixed-Signal PLLs 21 high-impedance state.13b) and smallest when the phase error is negative and approaches -360° (Fig. If we plot the average signal ud versus phase error qe. the PFD toggles between states -1 and 0. To see how the PFD works in a real PLL system.25) A comparison of the PFD characteristic (Fig. we get a sawtooth function as shown in Fig. It is easily seen from the waveforms in Fig. both positive edges of u1 and u2¢ occur “at the same time”. Furthermore. we consider the waveforms in Fig. however. When w1 is smaller than w2¢. If w1 is much higher than w2¢.12.13c). respectively. we see that the PFD can toggle only between the states 0 and 1 under this condition but will never go into the -1 state. the PFD will be in the 1 state most of the time. Consequently.13b and c that ud becomes largest when the phase error is positive and approaches 360° (Fig.com) Copyright © 2004 The McGraw-Hill Companies.13a shows the (rather theoretical) case where the phase error is zero. When w1 is much lower than w2¢.10) does not yet reveal exciting properties. Figure 2. If. the PFD behaves as if the phase error recycled at zero.digitalengineeringlibrary. 2. the PFD will be in the -1 state most of the time. we make the assumption that the reference frequency w1 is higher that the output frequency w2¢. 2. 2. Any use is subject to the Terms of Use as given at the website. The PFD then will stay in the 0 state forever. .14) with the characteristic of the JK-ﬂipﬂop (Fig. Figure 2. furthermore. 2. To recognize the bonus offered by the PFD. 2. It is assumed that the PFD has been in the 0 state initially. we must assume that the PLL is unlocked initially.13b shows the case where u1 leads.13c. When the phase error qe exceeds 2p.

.13 Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies. (b) Waveforms for positive phase error. The output signal of the PFD is permanently in the 0 state (high impedance). (c) Waveforms for negative phase error. The PFD output signal is pulsed to the 1 state. (a) Waveforms for zero phase error.digitalengineeringlibrary. Figure 2. Any use is subject to the Terms of Use as given at the website. All rights reserved. The PFD output signal is pulsed to the -1 state.Mixed-Signal PLLs 22 Chapter Two qe = 0 u1 u2 ¢ ud = 0 PFD state +1 0 –1 (a) qe > 0 u1 u2 ¢ qe PFD state +1 0 –1 (b) qe < 0 u1 u2 ¢ qe PFD state +1 0 –1 (c) Waveforms of the signals for the PFD.

2. Furthermore. Any use is subject to the Terms of Use as given at the website. It must be emphasized that no such characteristic (Fig.14 Plot of the averaged PFD output signal ud versus phase error qe. they are ﬁltered out by the loop ﬁlter. clude.2). It is possible to calculate the duty cycle of the ud signal as a function of the frequency ratio w1/w2¢ 23.3. . 2. a PLL that uses the PFD will lock under any condition.3.15) can be deﬁned for the EXOR and for the JK-ﬂipﬂop. 2. d is nearly 0. This property will greatly simplify the determination of the pull-in range (see “Pull-in Range DwP and Pull-in Time TP” in Sec. the result of this analysis is shown in Fig. irrespective of the type of loop ﬁlter used.5 when w1 is greater than w2¢ but both frequencies are close together. d is by deﬁnition minus the average fraction of time the PFD is in the -1 state. .w2¢ when the PLL is out of lock. 4 w1.5 when w1 is lower than w2¢ but both frequencies are close together.Mixed-Signal PLLs Mixed-Signal PLLs 23 ud Kd2p –4p –2p 0 2p 4p qe –Kd2p Figure 2. 2. and d is nearly -0. the remaining terms are “ac” components having frequencies of 2 w1.digitalengineeringlibrary. in the locked state of the PLL the ﬁrst of these is a “dc” component and is roughly proportional to the phase error qe. This leads to the term phase-frequency detector.6. . therefore.com) Copyright © 2004 The McGraw-Hill Companies. Because the output signal ud of the PFD depends on phase error in the locked state of the PLL and on the frequency error in the unlocked state. . the output signal ud(t) of the phase detector consists of a number of terms. d approaches 1 when w1 >> w2¢ and -1 when w1 << w2¢. 2.15. As expected. that the average output signal ud of the PFD varies monotonically with the frequency error Dw = w1 . Because the loop ﬁlter must pass the lower frequencies and Downloaded from Digital Engineering Library @ McGraw-Hill (www.2 Loop ﬁlters (ﬁrst order) As we have seen in Sec. All rights reserved. ud does not depend on the duty cycle of u1 and u2. . For the case w1 > w2¢ the duty cycle d is deﬁned as the average fraction of time the PFD is in the 1 state. for w1 < w2¢. Because these higher frequencies are unwanted signals. For this reason the PFD is the preferred phase detector in PLLs.1.

Type 1: Passive lead-lag ﬁlter. Figure 2.2..15 Plot of the averaged duty cycle of the PFD output signal ud versus frequency ratio w1/w2’.e. 2.26) where t1 = R1C and t2 = R2C. the pole) produces the phase lag. from the zero) in the transfer function in Eq.16 lists the versions which are most frequently encountered.com) Copyright © 2004 The McGraw-Hill Companies. . it must be a low-pass ﬁlter.e. All ﬁlters that will be used as loop ﬁlters are lead-lag ﬁlters. which can be chosen greater than 1.Mixed-Signal PLLs 24 Chapter Two d 1 0 1 2 ¢ w 1 / w2 –1 Figure 2. Its transfer function F(s) is given by F (s) = 1 + st 2 1 + s(t 1 + t 2 ) (2. This curve depicts the behavior of the PFD in the unlocked state of the DPLL. Its transfer function F(s) is given by F (s) = K a 1 + st 2 1 + st 1 (2.26). Any use is subject to the Terms of Use as given at the website. the zero of this ﬁlter is crucial because it has a strong inﬂuence on the damping factor z of the PLL system. 2.digitalengineeringlibrary. Its transfer function is very similar to the passive but has an additional gain term Ka. The phase-leading action comes from the numerator (i.4. whereas the denominator (i. (2.16b shows an active lead-lag ﬁlter. All rights reserved. [A note on terminology: a lead-lag (also called lag-lead) ﬁlter combines a phase-leading with a phase-lagging network.17a. Figure 2.. suppress the higher.27) Downloaded from Digital Engineering Library @ McGraw-Hill (www. As we will see in Sec.16a is a passive lead-lag ﬁlter having one pole and one zero. Type 2: Active lead-lag ﬁlter. Figure 2.] The amplitude response of this ﬁlter is shown in Fig. In most PLL designs a ﬁrst-order low-pass ﬁlter is used.

(b) Active lead-lag ﬁlter.16c shows another active low-pass ﬁlter. Finally. (a) Passive lead-lag ﬁlter. where it stands for “proportional + integral” action.com) Copyright © 2004 The McGraw-Hill Companies. and Ka = C1/C2.28) Downloaded from Digital Engineering Library @ McGraw-Hill (www. Figure 2. The term PI is taken from control theory. (c) Active PI ﬁlter. 2.17b. Type 3: Active PI ﬁlter. Fig. 2. (c) Active PI ﬁlter. which is commonly referred to as a PI ﬁlter. (a) Passive lead-lag ﬁlter.digitalengineeringlibrary. (b) Active lead-lag ﬁlter. . The amplitude response of the active lag ﬁlter is given in Fig.Mixed-Signal PLLs Mixed-Signal PLLs 25 |F| 1 –20 dB / dec R1 w uf 1 t1+t2 (a) ud R2 C 1 t2 |F| (a) Ka R1 C1 C2 R2 –20 dB / dec ud uf 1 t1 (b) w 1 t2 (b) |F| –20 dB / dec R1 R2 C ud uf 1 t2 (c) (c) w Figure 2.17 Bode diagram of the three ﬁlter types shown in Fig. All rights reserved. t2 = R2C. where t1 = R1C. It is a lead-lag ﬁlter as well.16. 2. The transfer function of the PI ﬁlter is given by F (s) = 1 + st 2 st 1 (2. Any use is subject to the Terms of Use as given at the website.16 Schematic diagram of loop ﬁlters used in linear PLLs.

and the output current of the voltage-current converter ﬂows into the left terminal of C. 2.3.17c. Fig. They differ only in the fact that for the ﬁrst the input (control) signal is a voltage signal. furthermore.2 Controlled oscillators There are two types of controlled oscillators in use: voltage-controlled oscillators (VCOs) and current-controlled oscillators.digitalengineeringlibrary. P-channel MOS transistor P1 is on and N-channel MOS transistor N1 is off. 2. whereas for the second it is a current signal. thus the voltage at that terminal ramps up in a positive direction. Consequently. It has—at least theoretically—inﬁnite gain at zero frequency. The voltage at the right side of C Input U I Current Out P2 P1 C N1 N2 VCO Out Figure 2. . All rights reserved. 2. First the control signal (input) is converted into a current signal.18 Simpliﬁed schematic of a VCO. The PI ﬁlter has a pole at s = 0 and therefore behaves like an integrator.18 shows a simpliﬁed schematic of a VCO that is found in the popular digital PLL IC 74HC/HCT4046. Assume that the output signal of the left NOR gate is H (high) and the output signal of the right NOR gate is L (low). the RS latch changes state. Its amplitude response is depicted in Fig. Therefore the right terminal of capacitor C is grounded. P2 is off and N2 is on. The cross-coupled NOR gates form an RS latch. When the voltage at the left side of C exceeds that threshold. Now the left terminal of C becomes grounded. The operation of this circuit is as follows. and the output current of the voltage-current converter ﬂows into the right terminal of C. Downloaded from Digital Engineering Library @ McGraw-Hill (www. The upper threshold of the Schmitt triggers (drawn by a triangle with a hysteresis symbol in its center) is set at half the supply voltage UDD/2.Mixed-Signal PLLs 26 Chapter Two where again t1 = R1C and t2 = R2C. Any use is subject to the Terms of Use as given at the website.com) Copyright © 2004 The McGraw-Hill Companies.

until the right Schmitt trigger switches into the H state.29) K0 is called VCO gain. UDD. .Mixed-Signal PLLs Mixed-Signal PLLs 27 ramps up now. i. To be mathematically correct. w2 2w0 w0 0 ufmin Figure 2. its unit is rad s-1 V-1.19 shows an idealized characteristic (w2 versus uf) of a VCO. most VCOs are powered from a unipolar power supply.. Below the lower threshold the VCO behavior is unpredictable. For this ideal VCO.e. we understand that uf is half the supply voltage. Figure 2. This process repeats inﬁnitely. Above the upper threshold the VCO creates a very high frequency that is independent of the control signal. The unit rad is often omitted because it is a dimensionless quantity. the lower treshold is around 1 V and the upper is around 4 V . The radian frequency w2 of the VCO output signal is proportional to the control signal uf and is given by w 2 = w 0 + K 0 uf (2. Practical VCOs show still another limitation. . Between these thresholds the characteristic curve is linear. but this range is restricted between a lower and an upper threshold. for unipolar power supplies Eq. we would observe a triangular waveform. w2 versus uf. however. the range of uf must be within 0 . uf = UDD/2. in case of the 74HC/HCT4046. for example. It is assumed that the range of the control signal is symmetrical around uf = 0.29) should read w 2 = w 0 + K 0 (uf . Assuming that the supply voltage is UDD. Real VCOs operate at their center frequency when the control signal is at half the supply voltage. (2. Downloaded from Digital Engineering Library @ McGraw-Hill (www.U DD 2) In the following we discard that offset.19 uf ufmax 0 Characteristic of a VCO. Any use is subject to the Terms of Use as given at the website. Whenever we state uf = 0. Practical VCOs behave differently. If we were to measure the voltage across the capacitor differentially. Their output frequency does not vary in proportion to the control signal over its full range from 0 to UDD.com) Copyright © 2004 The McGraw-Hill Companies. the output frequency would be 0 for uf = ufmin and 2 w0 for uf = ufmax. First of all. .digitalengineeringlibrary. w0 is the (radian) center frequency of the PLL. All rights reserved. the output frequency drops to a value near zero. For a typical VCO implemented in CMOS technology with UDD = 5 V .

.digitalengineeringlibrary. The supply voltage is chosen as UDD = 5 V in this example. Figure 2.e. For a supply voltage of UDD = 5 V this offset is approximatively Dw offset ª 50 R1C w2 w2max w0 w2min Figure 2. we read from the data sheet that the radian center frequency is approximately given by w0 ª 25 R1C When the product R1C is speciﬁed.. For a supply voltage of UDD = 5 V . All rights reserved. one capacitor C and two resistors R1 and R2. This resistor introduces an offset. Any use is subject to the Terms of Use as given at the website. by resistors and capacitors. 2.20 demonstrates how this is done in the popular PLL IC of type 74HC/HCT4046. i. the upper and lower limits of the VCO output frequency are set automatically (see w2min and w2max in Fig.e. i. This is accomplished by adding another resistor R2.Mixed-Signal PLLs 28 Chapter Two The designer of a PLL system must determine two VCO parameters: the center frequency w0 and the VCO gain K0. 2..com) Copyright © 2004 The McGraw-Hill Companies.e. Let us ﬁrst consider the case where R2 is chosen inﬁnite. The 74HC/HCT4046 uses three external components to set the parameters of the VCO. But we want to specify K0 independently of center frequency w0. these parameters are set by external components. R2 is an open circuit.20). The center radian frequency w0 of the VCO is determined by the product R1C. In practical VCO circuits.19. The resistors are not shown in the schematic of Fig. Downloaded from Digital Engineering Library @ McGraw-Hill (www.20 Offset 0 UDD /2 5 uf [V] Characteristics of a typical VCO. 2. i. We conclude therefore that the VCO gain—which is simply the slope of the solid curve—is automatically ﬁxed as soon as the product R1C has been speciﬁed. refer to the solid transfer curve in Fig..20.

e. we are in a position to ﬁx w0 and K0 independently of each other. say. by a factor of 5 or 6. its parameters (e. Furthermore the symbol Q2¢(s) is used for the Downloaded from Digital Engineering Library @ McGraw-Hill (www. Arbitrary scaling factors (i. Of course the down-scalers used in such synthesizers are not able to divide immediately by 5.g. Because the VCO is an analog circuit. which is programmable in most cases.. etc. Any use is subject to the Terms of Use as given at the website. Nevertheless there exist so-called fractional-N frequency synthesizers. JK-ﬂipﬂops. w0) are subject to parts spread. respectively.10. which is normally given as parts per million (ppm) per degree Centigrade.4 PLL Perfomance in the Locked State If we assume that the PLL has locked and stays locked for the near future.. It is obvious that a counter can scale down by an integer number only. This has been explained in great detail by Rohde. 3. by using two resistors. Certainly a counter cannot divide by. the down-scaler divides the output frequency created by the VCO by a factor N.48 for example. 2. e. All rights reserved. Down-scalers are usually built from a cascade of ﬂipﬂops (e. 2. for example.. Hence. 2. . 5.. One single JK-ﬂipﬂop scales down the frequency applied to its clock input by 2. scaling factors that are not an integer power of 2) can be realized by adding gates to the counting circuit. Two cascaded JK-ﬂipﬂops scale down that frequency by 4. or toggle ﬂipﬂops). temperature drift.4 Down-scalers Down-scalers (frequency dividers) come into play when the PLL is used as a frequency synthesizer.2.3 times the reference frequency. Fractional-N ratios are realized rather by a technique referred to as pulse removal.3.20 upward (the dashed line). we can develop a linear mathematical model for the system. and will not be discussed further here.com) Copyright © 2004 The McGraw-Hill Companies.digitalengineeringlibrary. These are synthesizers that are indeed capable of creating an output frequency that is.g. 5. Most data sheets specify the temperature coefﬁcient of w0. This will be discussed in more detail in Sec. the mathematical model is used to calculate a phase-transfer function H(s) that relates the phase q1 of the input signal to the phase q2¢ of the output signal (of the down-scaler): H (s) = Q 2 ¢(s) Q1 (s) (2. this also applies to Greek letters. (Note that we are using lowercase symbols for time functions and uppercase symbols for their Laplace transforms throughout the text. 10 kW) shifts the transfer curve in Fig.Mixed-Signal PLLs Mixed-Signal PLLs 29 Using a resistor R2 that has a ﬁnite value (e.3. 2. RSﬂipﬂops.g. As shown in Fig.3. As will be shown in this section.30) where Q1(s) and Q2¢(s) are the Laplace transforms of the phase signals q1(t) and q2¢(t).2..1.g. and aging.

the phase q2 is given by the integral over the frequency variation Dw2: q2 (t) = Ú Dw 2 (t)dt = K 0 Ú uf (t)dt (2. the angular frequency of the VCO is given by w 2 (t) = w 0 + Dw 2 (t) = w 0 + K duf (t) (2. . 2.1. 2. As stated in Eq. All rights reserved.1 Mathematical model for the locked state As derived in Sec.31) where s is the Laplace operator. This transfer function will be calculated from a mathematical model that will be derived in Sec. Any use is subject to the Terms of Use as given at the website. integration over time corresponds to division by s. The model of the VCO should yield the output phase q2.34) Downloaded from Digital Engineering Library @ McGraw-Hill (www.2 and is denoted here with F(s).3. (1.3. 2.Mixed-Signal PLLs 30 Chapter Two Laplace transform of phase q2¢. and not the output frequency w2.4. By deﬁnition.) H(s) is called phase-transfer function.digitalengineeringlibrary.33b) The transfer function of the VCO is therefore given by Q 2 (s) K 0 = s U f (s) For phase signals the VCO simply represents an integrator. so the Laplace transform of the output phase q2 is given by Q 2 (s) = K0 U (s) s f (2. however.4.) The transfer function of the loop ﬁlter has already been derived in Sec. Let us look now at the transfer function of the VCO.33a) In the Laplace transform. 2. The transfer function of the phase detector is therefore given by U d (s) = Kd Q e (s) (2.1. in the locked state the output signal ud of the phase detector can be approximated by ud ª K dq e hence the mathematical model of the phase detector is simply a zero-order block with gain Kd (also referred to as a gain block). To get an expression for H(s) we must know the transfer functions of the individual building blocks in Fig. 2.1). (2. (Appendix B provides an introduction to Laplace transforms.1.32) where K0 is called VCO gain (dimension: rad s-1 V-1).com) Copyright © 2004 The McGraw-Hill Companies.

Between He(s) and H(s) we have the simple relation H e (s) = 1 .35) In addition to the phase-transfer function.2 Deﬁnition of transfer functions The model in Fig.36) He(s) relates phase error qe to the input phase q1.28)] into Eq. i. an error-transfer function He(s) has been deﬁned.16) we get q1 (s) q2 ¢ (s) PD Kd LF F (s) VCD Ko s q2 (s) 1 N ÷ N Counter Figure 2.35). All rights reserved. From the model. 2. 2. We get H (s) = Q 2 ¢(s) K 0 K d F (s) N = ( ) Q1 s s + K 0 K d F (s) N (2. (2. frequency steps.Mixed-Signal PLLs Mixed-Signal PLLs 31 Last we must also know the mathematical model of the (optional) divideby-N counter (see Fig. it also scales down the output phase of the VCO by N. 2.26) to (2. or other excitation signals. the phase-transfer function H(s) is computed. On the basis of this model we are going to derive a number of transfer functions and related parameters (see Sec. For the three different loop ﬁlters (Fig.digitalengineeringlibrary.4.4.e. 2. the ability of the system to maintain phase tracking when excited by phase steps. (2.21 Mathematical model for the locked state of the PLL. . He(s) is deﬁned by H e (s) = Q e (s) s = Q1 (s) s + K 0 K d F (s) N (2.21 enables us to analyze the tracking performance of the PLL. Fig. Because this counter divides the frequency created by the VCO by a factor N.2). Hence the down-scaler is nothing more than a “gain block” having gain 1/N. 2..37) To analyze the phase-transfer function we have to insert the loop ﬁlter transfer function [Eqs. 2. We are now in the position to draw the mathematical model of the locked state.21.H (s) (2. Any use is subject to the Terms of Use as given at the website.com) Copyright © 2004 The McGraw-Hill Companies. Downloaded from Digital Engineering Library @ McGraw-Hill (www.1).

(2. z= 2 Nt 1 (2.38) to (2.com) Copyright © 2004 The McGraw-Hill Companies.40) In circuit and control theory it is common practice to write the denominator of the transfer function in the so-called normalized form3 Denominator = s2 + 2zw n s + w 2 n where wn is the natural frequency and z is the damping factor.38) For the active lead-lag ﬁlter K 0 K d K a 1 + st 2 t1 N H (s) = 1 t + K K K N K0 K d K a N 0 d a 2 s2 + s + t1 t1 (2. . z= Ë N (t 1 + t 2 ) K0 K d ¯ 2 (2.42) For the active PI ﬁlter wn = wn K0 K d t2 . Any use is subject to the Terms of Use as given at the website.Mixed-Signal PLLs 32 Chapter Two For the passive lead-lag ﬁlter K 0 K d 1 + st 2 N t1 + t 2 H (s) = 1 + K K0 K d N 0 K dt2 N s2 + s + t1 + t 2 t1 + t 2 (2.41) For the active lead-lag ﬁlter wn = K0 K d K a N wn Ê ˆ . The denominator of Eqs.39) For the active PI ﬁlter K 0 K d 1 + st 2 N t1 H (s) = 1 + K0 K dt2 N K0 K d N s2 + s + t1 t1 + t 2 (2.43) Downloaded from Digital Engineering Library @ McGraw-Hill (www. All rights reserved. z= t2 + Ë N (t 1 + t 2 ) 2 K0 K dK a ¯ (2.digitalengineeringlibrary.40) will take this form if the following substitutions are made: For the passive lead-lag ﬁlter wn = K0 K d N ˆ wn Ê t2 + .

the system is called a low-gain loop. Both scales are usually logarithmic.Mixed-Signal PLLs Mixed-Signal PLLs 33 (The natural frequency wn must never be confused with the center frequency w0 of the PLL. Eqs. For high-gain loops. we get the following phase-transfer functions: For the passive lead-lag ﬁlter wn ˆ sw n Ê 2z Ë K0 K d N ¯ H (s) = s2 + 2 szw n + w 2 n (2.40).46). Any use is subject to the Terms of Use as given at the website.45) For the active PI ﬁlter H (s) = 2 szw n + w 2 n s2 + 2 szw n + w 2 n (2.digitalengineeringlibrary. (2. Ka. (2. 2. The Bode diagram of the phasetransfer function is obtained by putting s = jw in Eq. (2. only the parameters Kd. The term KdK0/N in Eqs.22).46) become approximately identical and read H (s) ª 2 szw n + w 2 n s2 + 2 szw n + w 2 n (2.38) to (2. (2. If the condition K d K 0 N >> w n or K d K 0 K a N >> w n is true. 2.44) to (2. the PLL system is said to be a high-gain loop. the term KdK0Ka/N is called loop gain. Most practical PLLs are high-gain loops. (2. K0.47) for all ﬁlters shown in Fig.46) Aside from the parameters wn and z. assuming a high-gain loop.44) and (2.16.44 to 2. The frequency scale is further nor- Downloaded from Digital Engineering Library @ McGraw-Hill (www.47) and by plotting the magnitude (absolute value) |H(w)| as a function of angular frequency w (Fig.46) is called loop gain and has the dimension of angular frequency (rad s-1). we get for the error-transfer function He(s) for all three ﬁlter types the approximate expression H e (s) ª s2 s2 + 2 szw n + w 2 n (2.) Inserting these substitutions into Eqs. In Eq. If the reverse is true. it is customary to plot a Bode diagram of its transfer function.44) For the active lead-lag ﬁlter wn ˆ sw n Ê 2z Ë K0 K d K a N ¯ H (s) = 2 s + 2 szw n + w 2 n (2. All rights reserved.48) To investigate the transient response of a control system. and N appear in Eqs.45).com) Copyright © 2004 The McGraw-Hill Companies. Similarly. (2. .

For z = 1. For larger frequencies. We can see from Fig. This means that the second-order PLL is able to track for phase and frequency modulations of the reference signal as long as the modulation frequencies remain within an angular frequency band roughly between zero and wn. for modulation frequencies smaller than the natural frequency wn.0 2 3 4 6 8 10 w / wn Bode diagram of the phase-transfer function H(w). . 2. All rights reserved.0 6 z = 5.0 0.0 5 z = 2. the transient response becomes oscillatory. and the dynamic response becomes sluggish. however. The transfer function is optimally ﬂat for z = 1 / 2 .Mixed-Signal PLLs 34 Chapter Two 8 6 4 20 dB/ decade 2 + – ΩH (jw)Ω (dB) 0 2 4 6 8 10 12 14 16 18 20 0.22 that the second-order PLL is actually a low-pass ﬁlter for input phase signals q1(t) whose frequency spectrum is ﬂat between zero and approximately the natural frequency wn.5 3 z = 0. the larger becomes the overshoot. If z is made smaller than unity. which means that the PLL is no longer able to maintain phase tracking. The value of 0. The damping factor z has an important inﬂuence on the dynamic performance of the PLL.23. If z is made considerably larger than unity. the transfer function ﬂattens out. The diagram shows that.707 4 z = 1. Downloaded from Digital Engineering Library @ McGraw-Hill (www.) malized to the natural frequency wn. 2.22 6 5 1 z = 0.4 0.707 has been chosen for z. the phase error remains relatively small. an optimally ﬂat frequency-transfer function is the goal.6 0.8 1. Any use is subject to the Terms of Use as given at the website.3 4 1 2 3 2 z = 0.2 0. the phase error qe becomes as large as the reference phase q1. the smaller the damping factor.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. which corresponds to a secondorder Butterworth low-pass ﬁlter. A Bode plot of He(s) is shown in Fig. In most practical systems.3 0.1 Figure 2. (Adapted from Gardner1 with permission. Thus the graph is valid for every secondorder PLL system. the system is critically damped.

however.2 0. w3dB is given by w 3dB 2 È ˘ = w n Í 1 + 2z 2 + (1 + 2z 2 ) + 1 ˙ Î ˚ 12 (2. If the PLL is initially unlocked. In this model the reference phase q1 is represented by the shaft position of the reference potentiometer G. a servo ampliﬁer. As in ampliﬁers. w3dB becomes w3dB = 2.6 0. The model consists of a reference potentiometer G. 2. Any use is subject to the Terms of Use as given at the website.23 0.06wn.4 0. we can plot a simple model for the locked PLL (Fig. the servo system will lose tracking and large phase errors qe will result. the bandwidth of a PLL is often speciﬁed by the 3-dB corner frequency w3dB.7.8 1. Knowing that a second-order PLL in the locked state behaves very much like a servo or follow-up control system. the servo system will be able to maintain tracking of the follow-up potentiometer.24).49) For a damping factor z = 0. . If the shaft position of the reference potentiometer is varied slowly.0 2 3 4 6 8 10 w / wn Bode diagram of the error-transfer function He(w).digitalengineeringlibrary.3 0.Mixed-Signal PLLs Mixed-Signal PLLs 35 0 –10 ΩHe (jw)Ω (dB) –20 –30 –40 0. So far we have seen that a linear model is best suited to explain the tracking performance of the PLL if it is assumed that the PLL is initially locked. which is about twice the natural frequency. the phase error qe can take on arbitrarily Downloaded from Digital Engineering Library @ McGraw-Hill (www.1 Figure 2. If q1(t) is changed too abruptly. and a follow-up potentiometer F whose shaft is driven by an electric motor. All rights reserved. This is the radian frequency where the closed-loop gain has dropped by 3 dB referred to the closed loop gain at dc. The phase of the output signal of the VCO q2(t) is represented by the shaft position of the follow-up potentiometer.com) Copyright © 2004 The McGraw-Hill Companies.

This will be done in Sec. of the PLL system.50) where u(t) is the unit step function and DF is the size of the phase step. we can calculate its response on the most important excitation signals. respectively. Any use is subject to the Terms of Use as given at the website. 2. Phase step applied to the reference input.2a. we can calculate its response on the most important excitation signals. the angles q1 and q2¢ correspond to the phases q1 and q2¢. q1 (t) = u(t) ◊ DF (2.24 Simple electromechanical analogy of the linearized second-order PLL.4.52) .3 Transient response of the PLL in the locked state Knowing the phase transfer function H(s) and the error transfer function He(s) of the PLL. In this case the phase signal q1(t) is a step function.51) (2. When we try to calculate the acquisition process of the PLL itself.3. All rights reserved. and the linear model is no longer valid. For the Laplace transform Q1(s) we get therefore Q1 (s) = DF s The phase error qe is obtained from Q e (s) = H e (s)Q1 (s) = H e (s) ◊ DF s Downloaded from Digital Engineering Library @ McGraw-Hill (www. Knowing the phase-transfer function H(s) and the error-transfer function He(s) of the PLL. A reference signal performing a phase step at time t = 0 has been shown in Fig.com) Copyright © 2004 The McGraw-Hill Companies. 2. (2.6. We therefore analyze the PLLs answer to A phase step A frequency step A frequency ramp applied to its reference input. In this servo system. we must use a model that also accounts for the nonlinear effect of the phase detector. 2. large values.Mixed-Signal PLLs 36 Chapter Two G q1 2d order PLL ¢ q2 corresponds to q1 +A – Motor F ¢ q2 Figure 2.digitalengineeringlibrary.4.1. 2. This will be dealt with in Sec.

55) where Dw is the magnitude of the frequency step.56) That is.digitalengineeringlibrary. All rights reserved.707 5 ˜ 0.5 6 ˜ 0. the phase is a ramp function now.25 Transient response of a linear second-order PLL to a phase step DF applied at t = 0.0 3 ˜ 1.7 0.54) Frequency step applied to the reference input. the angular frequency of the reference signal becomes w 1 (t) = w 0 ¢ + Dw ◊ u(t) (2. The PLL is assumed to be a high-gain loop.48) into Eq.0 2 ˜ 2.) Downloaded from Digital Engineering Library @ McGraw-Hill (www. Any use is subject to the Terms of Use as given at the website.3 which reads q e (•) = lim sQ e (s) = 0 s Æ0 (2. The phase error has been normalized to the phase step DF.3 0.5 0. we have q1 (t) = Dw ◊ t (2.0 0.0 4 ˜ 0.8 0. we get the phase-error functions qe(t) shown in Fig. 2. This can also be shown by the ﬁnal value theorem of the Laplace transform.52) yields Q e (s) = DF s2 s s2 + 2 szw n + w 2 n (2.9 0.1 0 –0.2 0.3 1 2 3 5 6 1 2 3 4 5 6 7 8 4 wnt Figure 2.6 0. (Adapted from Gardner1 with permission. For t Æ (•) the phase error qe(•) approaches zero. .3 –0. Phase-error functions have been plotted for different damping factors.53) Applying the inverse Laplace transform to Eq.25. (2.4 0. The initial phase error qe(0) equals DF or any value of z.com) Copyright © 2004 The McGraw-Hill Companies.Mixed-Signal PLLs Mixed-Signal PLLs 37 Inserting Eq. For the Laplace transform Q1(s) we get therefore 1.5 2 e Df 1 z = 5.1 –0.2 –0. (2. Because the phase q1(t) is the integral over the frequency variation Dw. If a frequency step is applied to the input of the PLL.4 –0. (2.53).

If we again apply the ﬁnal value theorem to Eq.1 0 0.0 4 ˜ 0.3 0. the angular frequency w1 is given by ˙ ◊t w 1 (t) = w 0 ¢ + Dw (2.0 2 ˜ 2.61) t2 2 (2. Frequency ramp applied to the reference input.1 0. All rights reserved.3 0 1 6 5 4 3 2 1 1 z = 5. we get the phase error curves shown in Fig. it turns out that the phase error approaches 0 when t Æ •. (2.58). . (2. we get ˙ q1 (t) = Dw The Laplace transform Q1(s) now becomes Q1 (s) = ˙ Dw 3 s (2.7 0.com) Copyright © 2004 The McGraw-Hill Companies.26 Transient response of a linear second-order PLL to a frequency step Dw applied to its reference input at t = 0. hence the phase error qe(•) becomes nonzero.4 0.58) would have an additional ﬁrst-order term in s. (2.digitalengineeringlibrary. Any use is subject to the Terms of Use as given at the website. only for high-gain loops.58) Applying the inverse Laplace transform to Eq. we get for the phase error Q e (s) = Dw s2 s2 s2 + 2 szw n + w 2 n (2.59) ˙ is the rate of change of the reference frequency. If a frequency ramp is applied to the PLL’s reference input.60) 0. 2.5 6 ˜ 0.8 0.58). Because the phase where Dw q1(t) is the integral over the frequency variation. however.6 0.) Downloaded from Digital Engineering Library @ McGraw-Hill (www.3 qe (t) Dw/wn 2 3 4 5 6 7 8 Figure 2.707 5 ˜ 0. This is true. For low-gain loops.2 0. the numerator of Eq.0 3 ˜ 1.26.Mixed-Signal PLLs 38 Chapter Two Q1 (s) = Dw s2 Performing the same calculation as above.57) (2.2 0. (Adapted from Gardner1 with permission.5 0.

digitalengineeringlibrary. the rate at which an initially unlocked PLL 2 can become locked is markedly less than wn .48). we will calculate the steady-state error for a phase step. (2. It turns out that the steady-state error depends largely on the number of “integrators” that are present in the control system.62) Now we remember that our linear model is valid for small phase errors only. and a frequency ramp. If the reference frequency is swept in the presence of noise.63) Because the sine function cannot exceed unity.. but to the sine of the phase error. For the PLL. When the input phase q1(t) is given. Practical experience with PLLs has shown that Eq. on the number of poles at s = 0 of the open- Downloaded from Digital Engineering Library @ McGraw-Hill (www. the ﬁnal phase error qe(•) is q e (•) = lim sH e (s)Q1 (s) = sÆ 0 ˙ Dw w2 n (2. (2. Any use is subject to the Terms of Use as given at the website. .64) 2. the last equation can be shown to read actually1 sin q e (•) = ˙ Dw w2 n (2. the phase error qe(t) is computed from the error transfer function He(s) as deﬁned in Eq.64) presents a theoretical limit which is normally not practicable. the system will unlock. the maximum rate of change of the reference frequency that does not cause lockout is ˙ max = w 2 Dw n This result has two consequences: 2 1.4. i.e.Mixed-Signal PLLs Mixed-Signal PLLs 39 Assuming a high-gain loop again and applying the ﬁnal value theorem of the Laplace transform. If the system is initially unlocked. a frequency step. To see how the PLL settles on various excitation signals applied to its input. it cannot become locked if the reference 2 frequency is simultaneously swept at a rate larger than wn . the steady-state error is deﬁned as the deviation of the controlled variable from the setpoint after the transient response has died out. the steady-state error is simply the phase error qe(•). (2. All rights reserved. A more practical design limit for 1 ˙ max is considered to be Dw ˙ max = Dw w2 n 2 (2.4 Steady-state error of the PLL In control systems.65) 2.com) Copyright © 2004 The McGraw-Hill Companies. If the reference frequency is swept at a rate larger than wn . Because for large phase errors the output signal of the phase detector is not proportional to the phase error.

Sec.3.4. we choose a generalized expression F (s) = P (s) Q(s)s M where P(s) and Q(s) can be any polynomials in s and M is the number of poles at s = 0. Case study 1.4. (2. P(s) is a ﬁrst-order polynomial.e.28). Any use is subject to the Terms of Use as given at the website.com) Copyright © 2004 The McGraw-Hill Companies. Case study 2. (2. If a phase step of size DF is applied to the reference input. but the larger the number of integrators..digitalengineeringlibrary. and Q(s) is a polynomial of order 0 or 1. even for M = 0. In case of a frequency step. M = 1. we can write qe(•) as q e (•) = lim sQ1 (s) sÆ 0 s s + K 0 K d F (s) N For the transfer function F(s) of the loop ﬁlter. B. M = 0. Hence the phase error settles to zero for any type of loop ﬁlter. i.19)]. the more difﬁcult it becomes to get a stable system. Using Eq. we have (cf. 2.Mixed-Signal PLLs 40 Chapter Two loop transfer function. Phase step applied to the reference input.3) Q1 (s) = Hence the steady-state error becomes q e (•) = lim sÆ 0 DF s s2 s M Q(s)DF s(s ◊ s M Q(s) + K 0 K d P (s) N ) This quantity becomes 0 for any M. In most cases. For the active PI loop ﬁlter as deﬁned in Eq. All rights reserved. (B. Frequency step applied to the reference input. For many loop ﬁlters. and for its Laplace transform we get Q1 (s) = Dw s2 Downloaded from Digital Engineering Library @ McGraw-Hill (www. 2. Eq. . the phase q1(t) becomes a ramp function as shown in Sec.36) and the ﬁnal value theorem of the Laplace transform [see App. we get q e (•) = lim sÆ 0 s2 s M Q(s)Q1 (s) s(s ◊ s Q(s) + K 0 K d P (s) N ) M Let us calculate now the steady-state error for different excitations at the reference input of the PLL. It is possible to build loop ﬁlters having more than one pole at s = 0. When inserting F(s) into the equation for the steady-state error.

com) Copyright © 2004 The McGraw-Hill Companies. the order of the PLL becomes 3.3. of course. if the output of the phase detector directly controls the VCO. As mentioned. so the whole system had two poles. if the loop ﬁlter has at least one pole at s = 0. the overall phase shift can approach 2700.. i. i.1 Number of poles Most PLLs considered hitherto were second-order PLLs. Case study 3. the open-loop transfer function of the PLL must have at least 2 poles at s = 0 if the steady-state error caused by a frequency step must become zero. ﬁrst-order systems are rarely used. 2.e.Mixed-Signal PLLs Mixed-Signal PLLs 41 where Dw is the size of the (angular) frequency step.5. If the loop ﬁlter is omitted. Downloaded from Digital Engineering Library @ McGraw-Hill (www. All rights reserved. In PLL applications. and the VCO had a pole at s = 0. We will discuss the ﬁrst-order PLL in Sec. To get a stable loop. .3 2. For the steady-state error where Dw we get q e (•) = lim sÆ 0 ˙ s2 s M Q(s)Dw M 3 ( ( ) s s ◊ s Q s + K 0 K d P (s) N ) Here the steady-state error approaches zero only if the loop ﬁlter has at least 2 poles at s = 0. The steady-state error is given by q e (•) = lim sÆ 0 s2 s M Q(s)Dw s2 (s ◊ s M Q(s) + K 0 K d P (s) N ) This becomes 0 only if M is greater than or equal to 1.5 The Order of the PLL System 2. 4. The loop ﬁlter had one pole. for a frequency ramp the Laplace transform of the phase signal q1(t) becomes Q1 (s) = ˙ Dw 3 s ˙ is the rate of change of angular frequency. For M = 2 and Q(s) = 1.digitalengineeringlibrary.5. As shown in Sec. which means that the system can get unstable. Frequency ramp applied to the reference input. it is much more difﬁcult to obtain a stable higher-order system than a lower-order one. Because each pole of the transfer function causes a phase shift of nearly 900 at higher frequencies. Generally the order of a PLL is always by 1 higher than the order of the loop ﬁlter.4. Any use is subject to the Terms of Use as given at the website. We will deal with higher-order loops in Chap.e. the poles must be compensated for by zeros. the loop ﬁlter must have at least one zero.. loop ﬁlters of order 2 and more are used in critical applications.. 2. i.2. because they offer little noise suppression (more about noise in later sections). we obtain a ﬁrst-order PLL. In other words. which must be correctly placed. Because higher-order loop ﬁlters offer better noise cancellation.e.

The analogy should answer the following questions: Under what conditions will the PLL get locked? How much time does the lock-in process need? Under what conditions will the PLL lose lock? 2. Because of its high bandwidth. its model becomes much more complicated and is nonlinear.1 Mathematical model for the unlocked state The mathematical model depends somewhat on the types of phase detectors and loop ﬁlters that are used in a particular PLL conﬁguration. 2. F(s) in Eq.com) Copyright © 2004 The McGraw-Hill Companies. . When we omit the loop ﬁlter. Any use is subject to the Terms of Use as given at the website. For the following analysis.digitalengineeringlibrary. It can be shown that the behavior of the PLL in the unlocked state is described by a nonlinear differential equation of the form4 Downloaded from Digital Engineering Library @ McGraw-Hill (www.6.5. we assume that the PLL contains a type 1 phase detector (multiplier) and a type 1 loop ﬁlter (passive lead-lag ﬁlter). the linear model of the LPLL is valid only when the PLL is in the locked state.2 A special case: The ﬁrst-order PLL The ﬁrst-order PLL is an extremely simple system.2. In this section we are going to develop a mathematical model that is valid in the unlocked state of the PLL. All rights reserved. As we will see in Sec.6. In Chap. of course.Mixed-Signal PLLs 42 Chapter Two 2. the ﬁrst-order PLL does not suppress noise superimposed on the input signal. 2. the ﬁrst-order PLL has large bandwidth and hence tracks phase and frequency variations of the input signal very rapidly.66) This is the transfer function of a ﬁrst-order low-pass ﬁlter having a 3-dB angular corner frequency w3dB = K0Kd/N.4. 6 we will deal with a ﬁrst-order all-digital PLL system that is frequently used in FSK modems. however. Because this is an undesirable property in most PLL applications. and for the phase transfer function we obtain H (s) = 1 sN 1+ K0 K d (2. the ﬁrst-order PLL is rarely utilized here. the term K0Kd/N is identical with the hold range of the PLL. When the PLL is out of lock.35) becomes 1. On the basis of that model. First-order PLLs do really exist in applications where noise is not a primary concern. (2. Because the hold range is generally much larger than the natural frequency wn of second-order PLLs.6 PLL Performance in the Unlocked State As we have seen in Sec. 2. we will develop a mechanical analogy that is much simpler to analyze and will help us to derive the relevant parameters that describe the acquisition and lockout processes of PLLs.

Mixed-Signal PLLs Mixed-Signal PLLs 43 1 + K 0 K d t 2 cos q e N K 0 K d N 1 ˙ ˙e + ˙ ˙1 + ˙ + q qe sin q e = ˙ q q1 t1 + t 2 t1 + t 2 t1 + t 2 (2. the substitutions of Eq. A beam A P JE JR JA r je M a g G Figure 2.com) Copyright © 2004 The McGraw-Hill Companies.41) are made for t1 and t2. Next.68) holds. All rights reserved. there is no exact solution for this problem. This leads to the simpliﬁed differential equation ˙ ˙e + 2zw n˙ ˙ ˙ ˙ q q e cos q e + w 2 n sin q e = q1 + q1 w2 n K0 K d N (2.27. (Symbols deﬁned in text. in most practical cases the inequality 1 t2 << K 0 K d N (2.digitalengineeringlibrary. (2. as shown in Fig. As already stated. however. Any use is subject to the Terms of Use as given at the website. that Eq.27 Mechanical analogy illustrating the linear and the nonlinear performance of the PLL. .69) The nonlinearities in this equation stem from the trigonometric terms sin qe and cos qe.67) This equation can be simpliﬁed. 2. We ﬁnd.69) is almost identical to the differential equation of a somewhat special mathematical pendulum.) Downloaded from Digital Engineering Library @ McGraw-Hill (www. First. (2.

(2.71) is converted into 2 ˙ ˙e + 2z ¢w ¢ ˙ e + w¢ j nj n sin j e = 12 (2. Three different torques can be identiﬁed in the mechanical system of Fig. The dynamic response of the pendulum can be calculated by Newton’s third law. where a is the length of the beam and g is acceleration due to gravity.Mixed-Signal PLLs 44 Chapter Two having a mass M is rigidly ﬁxed to the shaft of a cylinder that can rotate freely around its axis.70) where T is the moment of inertia of the pendulum plus cylinder. The torque JE generated by gravitation of the mass M. JA = rG.73) This nonlinear differential equation for the deﬂection angle je looks very much like the nonlinear differential equation of the PLL according to Eq. A thin rope is attached at point P to the surface of the cylinder and is then wound several times around the latter. 2. JR = -r j 3. The torque JA generated by the gravity of the weight G. . 2. where r is the radius of the cylinder. All rights reserved. where r is the coefﬁcient of friction.70) yields ˙ ˙e + j r T ˙e + j Mag r sin j e = G(t) T T (2. If some weight G is placed on the platform. velocity (viscous friction).69). the pendulum is assumed to be in a vertical position with je = 0. Downloaded from Digital Engineering Library @ McGraw-Hill (www. (2.71) As in the case of the PLL. Any use is subject to the Terms of Use as given at the website. and Ji is a driving torque. If there is no weight on the platform. the pendulum will be deﬂected from its quiescent position and will eventually settle at a ﬁnal deﬂection angle je. (2.72) r 2 MagT r G(t) ª G(t) T (2.com) Copyright © 2004 The McGraw-Hill Companies. which is assumed to be proportional to the angular ˙ e. je is the angle of deﬂection.27: 1. JE = -Mag sin je. Introducing these individual torques into Eq. If we introduce the substitutions Ê Mag ˆ w¢ n = Ë T ¯ z¢ = Eq. we can write this equation in a normalized form.digitalengineeringlibrary. A friction torque JR. ˙e = Â J i j T˙ i (2. The outer end of the rope hangs down freely and is attached to a weighing platform.

During the time when the pendulum swings through the lower half of the circle (-p/2 < je < p/2). The weight G on the platform corresponds to a reference phase disturbance according to the relation Downloaded from Digital Engineering Library @ McGraw-Hill (www. In the case of the PLL the second term contains the factor cos qe. . All rights reserved. The damping factor z of the PLL corresponds to the damping factor z¢ of the pendulum. Imagine further that the weight G is large enough to make the pendulum tip over and continue to rotate forever around its axis (provided the rope is long enough). As a consequence. Strictly speaking. Comparing the PLL with this mathematical pendulum. its average angular velocity is greater than its velocity during the time when it swings through the upper half (p/2 < je < 3p/2). The natural frequency wn of the PLL corresponds to the natural (or resonant) frequency of the pendulum wn¢. A negative friction is hard to imagine. 2.com) Copyright © 2004 The McGraw-Hill Companies. Because of the nonconstant torque generated by the mass M of the pendulum. hence it is acceptable to state that the coefﬁcient of friction z¢ varies with the cosine of je. of course. which results from viscous friction. This would be true if the damping factor z¢ were not a constant but would vary with cos je. Any use is subject to the Terms of Use as given at the website.digitalengineeringlibrary. the momentary friction torque would be positive for p p < je < 2 2 that is. when the position of the pendulum is in the upper half of this circle. the pendulum of Fig. 3. 4.Mixed-Signal PLLs Mixed-Signal PLLs 45 There is a slight difference in the second term. we ﬁnd the following analogies: 1. This means that the friction torque averaged over one full revolution stays positive. the momentary friction torque would be negative for p 3p < je < 2 2 that is.27 would be an accurate analogy of the PLL only if the friction varied with the cosine of the deﬂection angle. when the position of the pendulum is in the lower half of a circle around the cylinder shaft. 2. The mathematical pendulum is therefore a reasonable approximation for the PLL. On the other hand. this oscillation will be nonharmonic. The positive friction torque averaged over the lower semicircle is therefore greater in magnitude than the negative friction torque averaged over the upper semicircle. The phase error qe of the PLL corresponds to the angle of deﬂection je of the pendulum. but let us assume for the moment that z¢ ª cos je is valid. whereas for the pendulum the coefﬁcient of the second term is the constant 2z¢wn¢. however.

75) This simple correspondence paves the way toward understanding the quite complex dynamic performance of a PLL in the locked and unlocked states. Downloaded from Digital Engineering Library @ McGraw-Hill (www. we have to place the corresponding weight G(t) given by Eq. . To see what happens to a PLL when phase and/or frequency steps of arbitrary size are applied to its reference input.74). We assume ﬁrst that the frequency of the reference signal has an arbitrary value: w 1 = w 0 ¢ + Dw(t) where Dw(t) can be considered the frequency offset of the reference signal. but can also be a function of time.75) on the platform and observe the response of the pendulum. The reference signal u1(t) can therefore be written in the form Ï ¸ u1 (t) = U10 sin ÌÚ [w 0 ¢ + Dw(t)]dt = U10 sin[w 0 ¢ t + q1 (t)]˝ Ó0 ˛ Consequently the phase q1(t) is given by q1 (t) = Ú Dw(t) dt 0 t t From this it becomes immediately evident that the ﬁrst derivative represents the momentary frequency offset: ˙ q1 (t) = Dw(t) whereas the second derivative signiﬁes the rate of change of the frequency offset: ˙ ˙1 (t) = d Dw(t) = Dw ˙ q dt The weight G placed on the platform is thus equivalent to a weighted sum of ˙ (t): the frequency offset Dw(t) and its rate of change Dw ˙+ G(t) ϳ Dw w2 n Dw K0 K d N (2. as would be the case when an impulse is applied. Any use is subject to the Terms of Use as given at the website. All rights reserved. (2. The notation G(t) should emphasize that G must not necessarily be a constant.74) Let us now see what is the physical meaning of the term ˙ ˙1 + ˙ q q1w 2 n / ( K 0 K d / N ) in Eq.digitalengineeringlibrary. (2.Mixed-Signal PLLs 46 Chapter Two ˙ ˙1 + ˙ q q1 w2 n K0 K d N ϳ G(t) (2.com) Copyright © 2004 The McGraw-Hill Companies.

This corresponds to the case where the PLL is no longer able to maintain phase tracking and consequently unlocks. the phase error increases toward inﬁnity. the ﬁnal deﬂection of the pendulum will be the same as if the weight had been placed smoothly onto the platform.com) Copyright © 2004 The McGraw-Hill Companies. the pendulum will show a transient response. The pendulum is then at rest in a vertical position. its peak ˆ e will be considerably greater than its ﬁnal deﬂection. . Any use is subject to the Terms of Use as given at the website. A slow variation of the reference freative term Dw quency corresponds to a slow increase of weight G. Another interesting case is given by a step change of the reference frequency at the input of the PLL. the angular frequency of the reference signal is w 1 (t) = w 0 ¢ + Dw ◊ u(t) ˙ (t) therefore shows where u(t) is the unit-step function. 2. The ﬁrst derivative Dw a delta function at t = 0. For small offsets of the reference frequency the phase error qe will be proportional to Dw. This is the static limit of stability. (2. called the hold range. the weight function should be a superposition of a step function and a delta (impulse) function. The impulse is generated when the weight hits the platform. however. If this is so. If a relatively small weight is dropped onto the platform. To get a narrow and steep impulse. mostly in the form of damped oscillation. When a frequency step of the size Dw is applied at t = 0.28. The analogy is given in this case by G(t) ϳ w2 n Dw K0 K d N The pendulum now starts to deﬂect. If the frequency offset reaches a critical value. This corresponds to the PLL operating at its center frequency w0¢ with zero frequency offset (Dw = 0) and zero phase error (qe = 0). What will now be the weight G(t) required to simulate this condition? As also shown in Fig.28. If the pendulum is not heavily overdamped. One full revolution of the pendulum equals a phase error of 2p. indicating that a ﬁnite phase error is established within the PLL. the stroke should be elastic. 2. With the slightest disturbance the pendulum would now tip over and rotate around its axis forever. this is written ˙ (t) = Dw d(t) Dw and is plotted in Fig. What happens if the frequency of the reference signal is changed slowly? The rate of change of the reference frequency is assumed to be so low that the deriv˙ in Eq. achieved by very carefully pouring a ﬁne powder onto the platform.digitalengineeringlibrary. je = 0. If we increase deﬂection j the weight to be dropped onto the platform. All rights reserved.75) is negligible. In practice this can be simulated by dropping an appropriate weight from some height onto the platform. the deﬂection of the pendulum is just 90°. we will observe a situation where Downloaded from Digital Engineering Library @ McGraw-Hill (www.Mixed-Signal PLLs Mixed-Signal PLLs 47 Let us ﬁrst consider the trivial case of no weight on the platform. Because the pendulum is now rotating permanently.

. . the peak deﬂection exceeds 90°. This frequency step is called the pull-out range.Mixed-Signal PLLs 48 Chapter Two w1(t) ¢ Dw w0 . we have ˙ ◊t Dw(t) = Dw ˙ is the rate of change of the angular frequency. but not 180°.com) Copyright © 2004 The McGraw-Hill Companies. The pendulum now tips over and performs a number of revolutions around its axis. i. All rights reserved. We thus conclude that a linear PLL can operate stably when the phase error qe momentarily exceeds the value of 90°. the peak deﬂection will exceed 180°. If the frequency of the reference signal is increased linearly with time. w1(t) • 0 G(t) • 0 Figure 2.e. If the weight dropped onto the platform is increased ever further. We therefore have to deﬁne another critical frequency offset. Dw = frequency step applied at t = 0). There is a third way to cause a PLL to unlock from an initially stable operating point. Keep in mind that the pull-out range of a PLL is markedly smaller than its hold range.digitalengineeringlibrary. the offset that causes the PLL to unlock when it is applied as a step.28 Weight function G(t) required to simulate a frequency step applied to the reference input of the PLL (w1 = angular frequency of the reference signal. The pull-out range may be considered the dynamic limit of stability. In the mechanical where Dw analogy this corresponds to a weight G that also builds up linearly with time. The weight that caused the system to unlock (at least temporarily) is observed to be considerably smaller than the weight that represented the hold range. The PLL always stays locked as long as the frequency steps applied to the system do not exceed the pull-out range. Any use is subject to the Terms of Use as given at the website. Downloaded from Digital Engineering Library @ McGraw-Hill (www. but it will probably come to rest again after some time. and the ﬁnal deﬂection is less than 90°.

the pendulum in our analogy tipped over and started rotating around its axis.3. The lock-in process is much faster than the pull-in process. The angular frequency of the reference signal must be within the hold range. the (down-scaled) frequency w2¢ of the VCO more and more approaches the frequency of the reference signal. the rate of change of the 2 reference frequency must always be smaller than wn to keep the system locked: ˙ < w2 Dw n These examples have demonstrated that three conditions are necessary if a PLL system is to maintain phase tracking: 1. As has been shown in Sec. the pull-in frequency. It becomes evident that too rapid a feed rate acts on the pendulum like the impulse that was generated in the last example by dropping a weight onto the platform. All rights reserved. this means that buildup of the phase error will decelerate if the reference-frequency offset is decreased below another critical value. the pendulum would continue to rotate even if the weight G were reduced to zero. and the system will ﬁnally lock. 2 3. the question arises whether it will return to stable operation when all the necessary conditions are met again. If there were no friction at all. the pendulum would nevertheless continue to rotate because there is enough kinetic energy stored in the mass to maintain the oscillation. If the slope of the average phase error becomes smaller.Mixed-Signal PLLs Mixed-Signal PLLs 49 This can be realized by feeding a material onto the platform at an appropriate feed rate. 2. Any use is subject to the Terms of Use as given at the website.com) Copyright © 2004 The McGraw-Hill Companies. Suppose again that the weight put on the platform of the mechanical model is large enough to cause sustained rotation of the pendulum. 2.2. If the weight on the platform were reduced to a value slightly less than the critical limit that caused instability. as can be expected from the mechanical analogy. This latter process is called the lock-in process.6.4. The pull-in process is a relatively slow one. The answer is clearly no. so the pendulum will decelerate if the weight is decreased to an appropriate level. When the reference frequency exceeded the hold range. but the lock range is smaller than the pull-in range. In most practical applications it is desired that the locked state be obtained within a short time period. . This implies that a PLL can become locked within one single beat note between reference frequency and output frequency. provided the frequency offset Dw is reduced below a critical value called the lock range. Downloaded from Digital Engineering Library @ McGraw-Hill (www. For a PLL. Fortunately. 2.digitalengineeringlibrary. Whenever a PLL has lost tracking because one of these conditions has not been fulﬁlled. It is easily shown that the pendulum can be brought to rest within one single revolution if the weight is suddenly decreased below another critical value. as will be demonstrated in “Pull-in Range DwP and Pull-in Time TP” in Sec. The pull-in frequency DwP is markedly smaller than the hold range. friction exists. The maximum frequency step applied to the reference input of a PLL must be smaller than the pull-out range. The rate of change of the reference frequency must be lower than wn .

Mixed-Signal PLLs 50 Chapter Two static limits of stability dynamic limits of stability ± DwH Hold-in range ± DwP Pull-in range ± DwPO Pull-out range ± DwL Lock range = normal operating range wO w conditionally stable dynamically unstable Figure 2. The pull-out range DwPO. Normally the operating-frequency range of a PLL is restricted to the lock range. The hold range DwH. If tracking is lost within this range.6.29 for most practical cases. The lock range DwL. We can state in advance that the hold range DwH is greater than the three remaining parameters. The four key parameters can be summarized as follows: 1. 3. we know that the pull-in range DwP must be greater than the lock range DwL. but the process can be rather slow. A PLL is conditionally stable only within this range.digitalengineeringlibrary. This is the frequency range within which a PLL locks within one single beat note between reference frequency and output frequency. Furthermore. but this process can be slow if it is a pull-in process.com) Copyright © 2004 The McGraw-Hill Companies. The mechanical model has shown that there are four key parameters specifying the frequency range in which the PLL can be operated. The pull-in range DwP. All rights reserved. . 4. Figure 2. This is the range within which a PLL will always become locked. Any use is subject to the Terms of Use as given at the website.2. The discussion of the mechanical analogy did not provide numerical solutions for these four key parameters. We will derive such expressions in Sec. This is the frequency range in which a PLL can statically maintain phase tracking. 2. The quantitative relationships among these four parameters are plotted in Fig.29 is a graphical representation of these parameters.29 Scope of the static and dynamic limits of stability of a linear second-order PLL. a PLL normally will lock again. 2. 2. This is the dynamic limit for stable operation of a PLL. The pull-in range Downloaded from Digital Engineering Library @ McGraw-Hill (www.

com) Copyright © 2004 The McGraw-Hill Companies.1 2. In most cases capture range is an alternative expression for lock range. .1..e. Any use is subject to the Terms of Use as given at the website. these equations depend on the types of phase detector and loop ﬁlter used.1 it has been demonstrated that the dynamic performance of the PLL is governed by a set of key parameters: The lock range DwL The pull-out range DwPO The pull-in range DwP The hold range DwH In addition we will deﬁne parameters relating to the time required for the PLL to get locked: The lock time TL. this Downloaded from Digital Engineering Library @ McGraw-Hill (www. K0. the PLL locks out forever when the frequency of the input signal exceeds the hold range. Hold range DwH. but we will maintain it throughout this text. All rights reserved. 2. we need equations that tell us how these key parameters depend on the parameters of the circuit. Unfortunately. the results will be shown in tables. The hold range is the frequency range in which a PLL is able to maintain lock statically. so most practitioners don’t even worry about the actual value of this parameter.digitalengineeringlibrary. The differentiation between lock-in and pull-in ranges is not clearly established in some books. The magnitude of the hold range is obtained by calculating that frequency where the phase error is at its maximum.2 Key parameters of the PLL In Sec. Moreover. 5 that the design can be performed by a dedicated computer program developed by the author. so we get the simple inequality Dw L < Dw PO < Dw P < Dw H In many texts the term capture range can also be found. As we have seen in Sec. sometimes it is also used to mean pull-in range. 2. This is the time the PLL needs to get locked when the acquisition process is a (fast) lock-in process. let us state that the hold range is a parameter of more academic interest. To make the design easier.Mixed-Signal PLLs Mixed-Signal PLLs 51 DwP is greater than the pull-out range DwPO in most practical designs.3. and Ka (when the active lead-lag ﬁlter is used).1. First of all. The pull-in time TP. 2. In the following we will derive a number of approximate design equations for these parameters.6. This is the time the PLL needs to get locked when the acquisition process is a (slow) pull-in process. the gain factors Kd. the time constants t1 and t2 of the loop ﬁlter. As we have seen in Sec.6. i. and the divider ratio N of an optional down-scaler.6. we will demonstrate in Chap. To design a PLL system.

76) Remember that the PLL network was linearized when the Laplace transform was introduced.76) is valid for small values of qe only.48): Q e (s) = Q1 (s) H e (s) = Dw H s s2 s + K 0 K d F (s) N Using the ﬁnal-value theorem of the Laplace transform. Consequently Eq. the dc Downloaded from Digital Engineering Library @ McGraw-Hill (www. Let us ﬁrst analyze the hold range for the multiplier phase detector.digitalengineeringlibrary.Mixed-Signal PLLs 52 Chapter Two maximum value depends on the type of phase detector used. the PLL can stay locked up to a phase error of 180°. Phase detector type 1. For the active lead-lag ﬁlter. we obtain for the hold range the expression Dw H = K 0 K d F (s) N The dc gain F(0) of the loop ﬁlter depends on the ﬁlter type. Therefore. When the JK-ﬂipﬂop phase detector is used. . we calculate the ﬁnal phase error qe(•) in the time domain as q e (•) = lim sQ e (s) = sÆ 0 Dw H K 0 K d F (s) N (2. qe = p/2 and sin qe = 1. (2. At the limit of the hold range the input frequency w1 is given by w 1 = w 0 ¢ + Dw H For the phase signal q1(t) we get therefore q1 (t) = Dw H ◊ t The Laplace transform of the phase signal then becomes Q1 (s) = Dw H s2 The phase error can now be calculated according to Eq. All rights reserved. we must determine the frequency for which the steady-state phase error becomes 90°. For greater values of phase error we would have to write sin q e (•) = lim sQ e (s) = sÆ 0 Dw H K 0 K d F (s) N At the limit of the hold range. For the passive lead-lag ﬁlter the dc gain F(0) = 1. The equation for the hold range DwH will therefore be different for each type of phase detector. Any use is subject to the Terms of Use as given at the website. To get the hold range DwH. however. With a multiplier phase detector the PLL can maintain lock at a phase error slightly less than 90°. (2. The same holds true for the EXOR phase detector.com) Copyright © 2004 The McGraw-Hill Companies. and for the PFD this value is even 360°.

78) Note again that F(0)—the loop ﬁlter gain at dc—depends on the type of loop ﬁlter chosen. When the PFD is used. we get for the hold range Dw H = K 0 K d N = K0 K d K a N =• (passive lead-lag ) (active lead-lag ) (active PI) (2. the actual hold range is limited by the frequency range covered by the VCO. Hence we get for the hold range Dw H = K 0 K d F (0)2 p N (2. the equation ud = Kdqe is valid for all values of qe in the range -p/2 < qe < p/2. Hence we get from Eq. By an analogous argumentation we get for the hold range Dw H = K 0 K d F (0)p N (2. When the EXOR phase detector is chosen. the maximum phase error in the steady state can be p/2. F(0) = •. When the JK-ﬂipﬂop phase detector is chosen.77) When the active PI ﬁlter is used.digitalengineeringlibrary. Phase detector type 2.80) Lock range DwL and lock time TL. Phase detector type 1.76) Dw H = K 0 K d F (0)p 2 N (2. .com) Copyright © 2004 The McGraw-Hill Companies.Mixed-Signal PLLs Mixed-Signal PLLs 53 gain is F(0) = Ka. In contrast to phase detector type 1. For the active PI ﬁlter. the average phase detector output ud is proportional to the phase error over the range -2p < qe < 2p. As in the previous section. When phase detector type 1 is used. at least theoretically.79) Phase detector type 4. the average phase detector output ud is proportional to the phase error qe over the whole range p < qe < p. We assume that the PLL is initially not locked and that the reference frequency is w1 = w0¢ + Dw. (2. we analyze the lock range separately for each type of phase detector. as desribed above. Any use is subject to the Terms of Use as given at the website. The magnitude of the lock range can be obtained by a simple consideration. The reference signal of the PLL is then given by u1 (t) = U10 sin(w 0 ¢ t + Dw ◊ t) Downloaded from Digital Engineering Library @ McGraw-Hill (www. Phase detector type 3. All rights reserved.

the frequency w2¢ of the VCO is plotted against time for two cases. however. 2. (2.30b shows a special case. and we have K0 K d F (Dw L ) = Dw L N For the lock range we obtain Dw L = K0 K d F (Dw L ) N This is a nonlinear equation for DwL.1). the phase detector will deliver an output signal given by ud (t) = K d sin(Dw ◊ t) + higher-frequency terms The higher-frequency terms can be discarded because they will be almost entirely ﬁltered out by the loop ﬁlter. In Fig. Consequently the PLL locks within one single-beat note between the reference and output frequencies. this frequency deviation is scaled down by factor N. at least not instantaneously. At the output of the loop ﬁlter there appears a signal uf (t) given by uf (t) = K d F (Dw) sin(Dw ◊ t) This is an ac signal that causes a frequency modulation of the VCO. For the ﬁlter gain F(DwL) we can therefore make the following approximations: Downloaded from Digital Engineering Library @ McGraw-Hill (www.30. All rights reserved.Mixed-Signal PLLs 54 Chapter Two and the output signal by u2 (t) = U 20 rect (w 0 ¢ t) where rect denotes a symmetrical square wave signal.com) Copyright © 2004 The McGraw-Hill Companies. Hence a lock-in process will not take place. if an approximation is introduced for F(DwL).16). w2¢ exactly meets the value of the reference frequency w1.digitalengineeringlibrary. This corresponds exactly to the lock-in process described in the discussion of lock range in the following subsection by means of the mechanical analogy. When a down-scaler is used (Fig. The peak frequency deviation is equal to KdK0|F(Dw)|. Using Eq. It follows from practical considerations that the lock range is always much greater than the corner frequencies 1/t1 and 1/t2 of the loop ﬁlter. 2. Figure 2.30a the peak frequency deviation is less than the offset Dw between the reference frequency w1 and the downscaled frequency w0¢. . When the frequency deviation is at its largest. 2. Its solution becomes very simple. Any use is subject to the Terms of Use as given at the website. where the peak frequency deviation is just as large as the frequency offset Dw. Under this condition the difference Dw is identical with the lock range DwL. The peak frequency deviation appearing at the lower input of the phase detector (Fig. In Fig. 2.1) is therefore given by KdK0|F(Dw)|/N. The frequency w2¢ of the VCO output signal develops as shown by the solid line. however.

we get Downloaded from Digital Engineering Library @ McGraw-Hill (www. Note: in this example the divider ratio is assumed to be N = 1 (no down-scaler used). (a) The peak frequency deviation is smaller than the offset Dw. F (Dw L ) ª t2 t1 + t 2 t2 F (Dw L ) ª K a t1 t2 F (Dw L ) ª t1 for the passive lead-lag ﬁlter for the active lead-lag ﬁlter for the active PI ﬁlter Moreover.30 Lock-in process. . thus the PLL will become locked after a very short time. t2 is normally much smaller than t1. Any use is subject to the Terms of Use as given at the website.Mixed-Signal PLLs Mixed-Signal PLLs ¢ w2 w1 Dw w0 ¢ ¢(t) w2 t (a) 55 frequency deviation Dw = KoKdΩF( jDw)Ω ¢ w2 w1 w0 ¢ Dw ¢(t) w2 frequency deviation Dw = KoKdΩF( jDw)Ω t (b) Figure 2. All rights reserved. (b) The peak frequency deviation is exactly as large as the actual frequency offset. therefore a fast lock-in process cannot take place.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies.41) and assuming high-gain loops. so we can use the simpliﬁed relationships F (Dw L ) ª t 2 t 1 F (Dw L ) ª K a t 2 t 1 F (Dw L ) ª t 2 t 1 for the passive lead-lag ﬁlter for the active lead-lag ﬁlter for the active PI ﬁlter Making use of the substitutions Eq. (2.

16. Any use is subject to the Terms of Use as given at the website. Knowing the approximate size of the lock range. The phases q1 and q2¢ are then given by q1 (t) = w 0 ¢ t + Dw ◊ t q2 (t) = w 0 ¢ t The phase error qe therefore is q e = Dw ◊ t which is a ramp function.26 shows. The reference frequency w1 is offset from the center frequency w0¢ by Dw. Phase detector type 2. When the PLL locks in quickly. hence it is reasonable to state that the lockin time is TL ª 2p wn (2. 2. All rights reserved. its peak amplitude being Kdp/2. Therefore ud can be written as ud (t) = K d p tri (Dw ◊ t) 2 where tri stands for triangular waveform. Checking Fig. 2. When the EXOR phase detector is chosen. the signals ud and uf perform (for z < 1) a damped oscillation.7 again we note that the average phase detector output signal ud represents a triangular signal when the phase error ramps up linearly with time. the transients die out in about one cycle of this oscillation. 2. This signal is depicted in the upper trace of Fig. 2. As Fig.82) which is valid for any type of loop ﬁlter.81) for all types of loop ﬁlters in Fig. The average output signal of the loop ﬁlter is now given by uf (t) = F (Dw) K d p tri (Dw ◊ t) 2 Downloaded from Digital Engineering Library @ McGraw-Hill (www.31. Then for u1 and u2¢ we have u1 (t) = U10 rect (w 0 ¢ t + Dw ◊ t) u2 (t) = U 20 rect (w 0 ¢ t) where U10 and U20 are the amplitudes of the square wave signals. TL is also referred to as settling time. we are certainly interested in having some indication of the lock-in time.com) Copyright © 2004 The McGraw-Hill Companies.digitalengineeringlibrary. the lock range can be determined by considerations analogous to those made for the multiplier phase detector.Mixed-Signal PLLs 56 Chapter Two Dw L ª 2zw n (2. whose angular frequency is approximately wn. . We assume that the PLL is initially out of lock and that both signals u1 and u2¢ are symmetrical square waves.

the peak frequency ˆ 2 /N.1) gets D w ˆ 2 /N easily seen now that the PLL acquires lock within one beat note when D w equals the radian frequency offset Dw: ˆ 2 N = Dw Dw (2. 2.84) Under this condition Dw is identical with the lock range DwL.31. All rights reserved. It is deviation at the lower input of the phase detector (Fig.83) and (2. 2.Mixed-Signal PLLs Mixed-Signal PLLs 57 ud Kd p 2 t –Kd p 2 2p/∆w w2¢ w1 ∆w w2¢(t) w0¢ t Figure 2. (2.com) Copyright © 2004 The McGraw-Hill Companies. An EXOR phase detector is used. This signal modulates the frequency of the VCO such that its peak deviation becomes ˆ 2 = F (Dw) K 0 K d Dw p 2 (2.83) When the division ratio of the (optional) down-scaler is N.84).31 Waveforms of the average phase detector output signal ud (t) (upper trace) and the scaled down radian frequency w2¢ (lower trace) for the case where the radian frequency offset Dw is identical with the lock range DwL.digitalengineeringlibrary. Any use is subject to the Terms of Use as given at the website. we get the simpliﬁed expression Downloaded from Digital Engineering Library @ McGraw-Hill (www. Combining Eqs. This signal is shown in the lower trace of Fig. . we obtain the nonlinear equation F (Dw L ) K 0 K d p N = Dw L 2 Using the same substitutions as for the type 1 phase detector.

Any use is subject to the Terms of Use as given at the website.digitalengineeringlibrary.82). All rights reserved. as shown in the upper curve of Fig. we observe that DwL for the EXOR is larger by a factor of p/2.32 Waveforms of the average phase detector output signal ud (t) (upper trace) and the scaled down radian frequency w2¢ (lower trace) for the case where the radian frequency offset Dw is identical with the lock range DwL. Because the average output signal of the JK-ﬂipﬂop ud varies in a sawtooth-like fashion with phase error (Fig. 2.85) for high-gain loops. 2. 2. A JK-ﬂipﬂop phase detector is used. The lock range of the PLL with a type 3 phase detector can be computed by an analysis similar to that for type 2 (EXOR).10).Mixed-Signal PLLs 58 Chapter Two Dw L ª pzw n (2.com) Copyright © 2004 The McGraw-Hill Companies. When we compare the lock range obtained for the EXOR phase detector with the lock range obtained for the multiplier phase detector. If the frequency offset Dw is chosen such that the curve ud Kdp t –Kdp 2p/∆w ¢ w2 w1 ∆w w0 ¢ ¢ (t) w2 t Figure 2. the average signal ud will also be a sawtooth function. Downloaded from Digital Engineering Library @ McGraw-Hill (www. For the lock time TL we obtain the same approximation we obtained for the type 1 phase detector (Eq. Phase detector type 3. see lower curve of Fig.32. Now the frequency of the VCO is modulated in a sawtooth-like manner. 2. If we assume again that the PLL is initially out of lock and that the offset between reference frequency w1 and center frequency w0¢ is again Dw. . the phase error becomes a ramp function again.85) is valid for any type of loop ﬁlter. Equation (2.32.

33. Again the frequency of the VCO output signal is modulated in a sawtooth-like manner. For the lock-in time Eq.Mixed-Signal PLLs Mixed-Signal PLLs 59 just touches the w1 line. Eq.com) Copyright © 2004 The McGraw-Hill Companies. Dw equals the lock range DwL. Downloaded from Digital Engineering Library @ McGraw-Hill (www.82) still holds true. The PFD is used as phase detector.82) is still valid. In analogy to the preceding sections (EXOR and JK-ﬂipﬂop phase detector) we get the following approximation for the lock range: Dw L ª 4 pzw n For the lock-in time approximation. Phase detector type 4. (2. (2. By analogy. All rights reserved. ud 2pKd (2. Any use is subject to the Terms of Use as given at the website. 2.86) The lock range is larger by a factor of 2 than the lock range of a PLL using the EXOR phase detector. The waveforms for ud and w2¢ versus time for the PFD are shown in Fig. .87) t –2pKd 4p/∆w w2¢ w1 ∆w w 0¢ w2¢(t) Figure 2.33 Waveforms of the average phase detector output signal ud (t) (upper trace) and the scaled-down radian frequency w2¢ (lower trace) for the case where the radian frequency offset Dw is identical with the lock range DwL. we get the approximation Dw L ª 2 pzw n (2.digitalengineeringlibrary.

2. if w2¢(t) is modulated in the negative direction.e. that the frequency of the reference signal is w1 = w0¢ + Dw.. hence the average output frequency of the VCO would stay stuck at its center frequency w0. If. A. the VCO frequency is pulled in the direction of the reference frequency. We now assume that the frequency offset Dw is so large that a lock-in process will not take place. the VCO frequency is modulated nonharmonically.34. and the uf signal will again modulate the frequency of the VCO output. it is also varied by the frequency modulation of the VCO output signal. To determine the size of the pull-in range DwP. The mathematical treatment of the pull-in process is quite cumbersome and is treated in more detail in App. here we give only the ﬁnal results. If the frequency w2¢(t) is modulated in the positive direction. The asymmetry of the waveform w2¢(t) is greatly dependent on the value of the average offset Dw. we assume that the PLL is not locked initially. As a consequence. we have overlooked the fact that the difference Dw between reference frequency w1 and scaled-down VCO output frequency w2¢(t) is not a constant. This in turn causes w 2 ¢ to be pulled even more in the positive direction. that is. Under these conditions the PLL would never pull in! Fortunately.com) Copyright © 2004 The McGraw-Hill Companies. Because the frequency offset Dw is generally much larger than the corner frequencies 1/t1 and 1/t2 of the loop ﬁlter. . as has been shown in Fig. If the average value of w2¢(t) is pulled somewhat in the direction of w1 (which is assumed to be greater than w 2 ¢ ). the difference Dw becomes smaller and reaches some minimum value Dwmin. Dw becomes greater and reaches some maximum value Dwmax. and that the VCO initially operates at the center frequency w0. i. the loop ﬁlter will attenuate the ud signal.30. It is very important to note that the pull-in range depends on the type of loop ﬁlter. the initial frequency offset Dw0 is larger than DwP. so that the scaled-down output frequency w2¢ ﬁnally reaches the reference frequency w1. the asymmetry of the w2¢(t) waveform becomes stronger.digitalengineeringlibrary. the asymmetry becomes more marked as Dw is decreased. This is shown graphically in Fig. This phenomenon is called the pull-in process (Fig.35). Because Dw(t) is not a constant. its average value uf would be 0. If uf were a perfect sine wave. Any use is subject to the Terms of Use as given at the website. All rights reserved. 2. on the other hand. The loop ﬁlter output signal will also be a sine wave with radian frequency Dw. the duration of the half-period in which Dw(t) is modulated in the positive direction becomes longer than that of the half-period in which Dw(t) is modulated in the negative sense. Here are the formulas for the pull-in range: Downloaded from Digital Engineering Library @ McGraw-Hill (www. however. 2. the pull-in range DwP. Consequently the average output signal ud of the phase detector is a sine wave having the frequency Dw and hence is an ‘‘ac’’ signal. Mathematical analysis shows that a pull-in process occurs whenever the initial frequency offset Dw0 is smaller than a critical value. the average frequency of the VCO w 2 is now higher than it was without any modulation. This process is regenerative under certain conditions.Mixed-Signal PLLs 60 Chapter Two Pull-in range DwP and pull-in time TP Phase detector type 1. a pull-in process does not take place because the pulling effect is not then regenerative.

the dc gain of this ﬁlter is (theoretically) inﬁnite. Any use is subject to the Terms of Use as given at the website.89a) high-gain loops 4 2 Dw P ª p For the active PI ﬁlter Dw P Æ • (2. All rights reserved.Mixed-Signal PLLs Mixed-Signal PLLs ¢ w2 61 w1 ∆wmin ∆wmax w2 ¢ (t) w0 ¢ w2 ¢ .w 2 n Ka zw n K 0 K d N low-gain loops (2.digitalengineeringlibrary. . For the passive lead-lag ﬁlter Dw P ª Dw P ª 4 p 2zw n K 0 K d N .88) high-gain loops 4 2 p For the active lead-lag ﬁlter Dw P ª 4 p 2zw n K 0 K d N .w 2 n zw n K 0 K d N low-gain loops (2. Downloaded from Digital Engineering Library @ McGraw-Hill (www. average of w2 ¢ (t) t Figure 2. This causes the average value of the VCO output frequency w 2 to be pulled in the direction of the reference frequency. the PLL pulls in under any conditions when the loop ﬁlter is an active PI ﬁlter. hence the slightest nonharmonicity of the ud signal is sufﬁcient to pull in the loop.com) Copyright © 2004 The McGraw-Hill Companies.89b) Obviously.34 In the unlocked state of the PLL the frequency modulation of the VCO output signal is nonharmonic. As we know.

Initially the frequency offset Dw0 is fairly large. 2.35 can be easily explained by the mechanical analogy of Fig.digitalengineeringlibrary. Any use is subject to the Terms of Use as given at the website.Mixed-Signal PLLs 62 w2¢ Chapter Two w1 ∆ w0 w2¢(t) w0¢ Tp t Figure 2.90) Downloaded from Digital Engineering Library @ McGraw-Hill (www. The result also slightly depends on the type of loop ﬁlter used. typically less than 0. The ‘‘pumping’’ of the instantaneous frequency w2¢(t) is characteristic of this process and is easily explained by the nonharmonic rotation of the pendulum caused by the gravity of its mass M.8 times the pullin range. and the pendulum comes to rest after some time. its angular velocity is greater at the lower ‘‘dead point’’ than at the higher one. and in the analogy the pendulum rotates at Dw0/2p revolutions per second. The analysis gives the results For the passive lead-lag ﬁlter TP ª p 2 Dw 2 0 16 zw 3 n (2. the pull-in time TP approaches inﬁnity. however. however. if the initial frequency offset Dw0 [difference between reference frequency and (scaled-down) initial frequency of the VCO] is distinctly smaller than the pull-in range. When Dw approaches the pull-in range DwP. The pull-in process depicted in Fig. The values given by the following formulas agree quite well with measurements on actual PLL circuits and with computer simulations. The angular velocity decelerates slowly. All rights reserved.27. . The duration of the pull-in process can also be computed from the mathematical analysis of the acquisition process (see App. 2. In fact.35 The pull-in process. A).com) Copyright © 2004 The McGraw-Hill Companies. They are valid only. thus the formula cannot be used.

The quadratic and cubic terms in Eqs. we get TL ª 0. i.e.. N = 1.Mixed-Signal PLLs Mixed-Signal PLLs 63 For the active lead-lag ﬁlter TP ª p 2 Dw 2 0Ka 16 zw 3 n (2. This is demonstrated easily by a numerical example. The loop gain K0Kd/N is assumed to be 2p◊1000 rad/s.. The average output signal ud (t) is therefore a triangular signal. All rights reserved. Any use is subject to the Terms of Use as given at the website. and that the initial offset Dw0 between reference frequency w1 and (down-scaled) VCO frequency w0¢ is large. Numerical Example A second-order PLL having a passive lead-lag loop ﬁlter is assumed to operate at a center frequency f0 of 100 kHz. The phase error qe is the difference of the phases of these two signals.90). this is a very narrowband system.92) show that the pull-in process is highly nonlinear. The damping factor is chosen to be z = 0.7. Its natural frequency fn = wn/2p is 3 Hz. that the VCO operates at its center frequency w0.33 s TP ª 4.e. 2.67 s TP is much larger than TL. The signals u1 and u2¢ can then be represented by u1 (t) = U10 rect (w 0 ¢ t + Dw 0 t) u2 ¢(t) = U 20 rect (w 0 ¢ t) respectively. .91) For the active PI ﬁlter p 2 Dw 2 0 16 zw 3 n TP ª (2. (Let us ignore for the Downloaded from Digital Engineering Library @ McGraw-Hill (www.82) and (2.w2¢ for t = 0.36. q e (t) = Dw 0 ◊ t which is a ramp function. No down-scaler is used. i. The pull-in time TP is normally much longer than the lock-in time TL.92) In these formulas Dw0 is the initial frequency offset w1 . as shown in the upper trace of Fig. (2. We shall now calculate the lock-in time TL and the pull-in time TP for an initial frequency offset Df0 of 30 Hz.90) to (2. According to Eqs. (2. We assume that the PLL is out of lock initially. Phase detector type 2.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. where U10 and U20 are the amplitudes of the square wave signals. The pull-in range of a PLL using the EXOR phase detector can be calculated by performing a procedure similar that done for the multiplier phase detector.

the frequency offset Dw(t) is not constant but is given by the difference between reference frequency w1 and instantaneous (scaled-down) VCO frequency w2¢.com) Copyright © 2004 The McGraw-Hill Companies.36. Because the duration of the positive half-wave of ud is larger than the negative. i.e.36 This ﬁgure is used to explain the slow pull-in process of the PLL. As Fig.. Dw(t) becomes smaller during the positive half-wave of the ud signal and larger during the negative half-wave. i. If the loop gain of the PLL is sufﬁciently large.. however. The asymmetry of the waveforms is exaggerated. 2. different things can happen. the lower trace the down-scaled instantaneous radian frequency w2¢(t).digitalengineeringlibrary. — –Kd w1 — . the waveform becomes asymmetrical. Any use is subject to the Terms of Use as given at the website. Now. lower trace in Fig.36. the product KdK0F(0)/N. When the ud waveform is asymmetrical.e. If the loop gain. This causes the average frequency w 2 of the VCO to be pulled up. Therefore. All rights reserved. 2..36 demonstrates. The upper trace shows the averaged output signal ud of the EXOR gate. Downloaded from Digital Engineering Library @ McGraw-Hill (www. T1 = T2). the average frequency would remain constant and equal to w0¢. using the EXOR as phase detector. is ud T1 p 2 T2 Kd t p 2 T = 2p / w ¢ w2 w(t) ¢ (t) w2 ¢ w0 t Figure 2. If the triangular waveform were symmetrical (i. a dc offset is generated. Consequently. which is exaggerated in Fig. its mean value is no longer zero but becomes slightly positive.Mixed-Signal PLLs 64 Chapter Two moment the asymmetry of the waveform.) The output signal uf(t) of the loop ﬁlter will be some fraction of the signal ud(t) and will modulate the down-scaled instantaneous frequency w2¢(t) of the VCO. 2.e. the loop is pulled in. the peak value of w2¢ reaches w1 after some time.

Then a locking process will take place. the approximation of Eq. Computer simulations have shown that the approximation gives acceptable results when Dw0 is less than about 0. and the scaled-down VCO output frequency will be pulled up until it comes close to the reference frequency. ‘‘acceptDownloaded from Digital Engineering Library @ McGraw-Hill (www.95) is valid only when Dw0 is markedly less than DwP.Mixed-Signal PLLs Mixed-Signal PLLs 65 small. however.. the pull-in process becomes regenerative: the mean frequency w 2 is pulled up so much that the ud waveform becomes even more nonharmonic (i. the ratio of T1/T2 becomes signiﬁcantly greater). A pull-in process is initiated whenever the initial frequency offset Dw0 is smaller than the pull-in range DwP. The ﬁnal results are given here (for details refer to App. it is also possible to calculate an approximate value for the pull-in time TP.93) high-gain loops Loop ﬁlter = active lead-lag p 2zw n K 0 K d N . A): Loop ﬁlter = passive lead-lag p 2zw n K 0 K d N . (2. This causes the mean w 2 frequency to increase even more. and so forth.w 2 n Ka 2 p Dw P ª zw n K 0 K d N 2 Dw P ª low-gain loops (2. the pull-in time becomes inﬁnite when the initial frequency offset equals the pull-in range. . All rights reserved.8 DwP. Any use is subject to the Terms of Use as given at the website. A. the VCO frequency is pulled up by a small amount only and stays stuck at some ﬁnal value.95) As we know.w 2 n 2 p Dw P ª zw n K 0 K d N 2 Dw P ª low-gain loops (2. The ﬁnal result reads TP ª TP ª TP ª 4 Dw 2 0 p 2 zw 3 n 4 Dw 2 0Ka 2 p zw 3 n 4 Dw 2 0 p 2 zw 3 n passive lead-lag ﬁlter active lead-lag ﬁlter active PI ﬁlter (2.digitalengineeringlibrary.94) high-gain loops Loop ﬁlter = active PI Dw P Æ • As demonstrated in App.com) Copyright © 2004 The McGraw-Hill Companies.e. (In practical terms. If the loop gain is larger. When the passive or the active lead-lag ﬁlter is used.

Downloaded from Digital Engineering Library @ McGraw-Hill (www. 2. All rights reserved.digitalengineeringlibrary.) Phase detector type 3. The lower trace shows the down-scaled frequency w2¢ created by the VCO.Mixed-Signal PLLs 66 Chapter Two able’’ means that the error of the predicted result is not larger than about 10 percent.37. ud T1 T2 Kdp t –Kdp T = 2p / w — ¢ w2 w0 w0¢ Figure 2. — w(t) ¢ (t) w2 t . Any use is subject to the Terms of Use as given at the website. The upper trace shows the average phase detector output signal ud . the waveforms of the average ud (t) signal and the instantaneous (down-scaled) output frequency w2¢ look like those drawn in Fig. Now we analyze the pull-in process for the case where the JK-ﬂipﬂop is used as phase detector.37 This ﬁgure explains the pull-in process of a PLL using the JK-ﬂipﬂop as phase detector. Making the same assumptions as for the EXOR gate.com) Copyright © 2004 The McGraw-Hill Companies.

i.99) When the passive or the active lead-lag ﬁlter is used.15). the output signal of the PFD depends on the frequency error (Fig. the output is in the high-impedance state.98) The pull-in time becomes TP ª TP ª TP ª 1 Dw 2 0 p 2 zw 3 n 1 Dw 2 0Ka 2 p zw 3 n 1 Dw 2 0 p 2 zw 3 n passive lead-lag ﬁlter active lead-lag ﬁlter active PI ﬁlter (2. . When the PLL is out of lock. however.11) are reset. As we have already seen.) This implies that the passive lead-lag ﬁlter behaves like a real integrator when driven by a tristate signal! In other words. All rights reserved.w 2 n Dw P ª p 2 zw n K 0 K d N low-gain loops high-gain loops (2. As explained in Sec. we have to develop another model for the pull-in process.digitalengineeringlibrary. When both ﬂipﬂops (Fig.e.w 2 n Ka Dw P ª p 2 zw n K 0 K d N low-gain loops high-gain loops (2.1 the PFD has a tristate output.Mixed-Signal PLLs Mixed-Signal PLLs 67 Instead of triangular waves.. the output signal of the PFD depends on the phase error in the locked state of the PLL. the charge on the capacitor remains unchanged. When the PFD is used as phase detector. When the PFD output ﬂoats. Performing an analog computation as above. we obtain sawtooth waves now.3. (In practice the capacitor would be discharged by leakage currents. Any use is subject to the Terms of Use as given at the website. the voltage on the capacitor stays constant. we get for the pull-in range For the passive lead-lag ﬁlter Dw P ª p 2zw n K 0 K d N . this formula gives acceptable results when Dw0 is less than about 0. of course.96) For the active lead-lag ﬁlter Dw P ª p 2zw n K 0 K d N . the passive lead-lag ﬁlter has inﬁnite gain at f = 0 under this condition. Volgers has shown15 that the transfer function of the passive lead-lag ﬁlter must be Downloaded from Digital Engineering Library @ McGraw-Hill (www. Assume for the moment that a passive lead-lag loop ﬁlter is used in the PLL under consideration. 2.97) For the active PI ﬁlter Dw P Æ • (2.8 DwP. Phase detector type 4. 2. 2.com) Copyright © 2004 The McGraw-Hill Companies. because the dynamic behavior of the PFD differs greatly from that of all other phase detectors.

The pull-in time remains ﬁnite. It was assumed that the PFD is powered by a unipolar supply so that the logical high level is UB and the low level is 0 V (ground).16b).100) When the active lead-lag ﬁlter is used. 2. The average ud signal is nothing else than the duty cycle of the PFD output. this equivalent signal is also represented in Fig. The average ud signal is drawn as a dashed line.38. the PI ﬁlter acts as an integrator whose transfer function is given by F (s) ª 1 + st 2 st 1 Because all loop ﬁlters behave as real integrators now. it does not matter whether the ﬁlter is driven by a “normal” signal source or by a device having a tristate output.w0¢.101) where Ka = C1/C2 (Fig. It shows that the transfer function is approximately given by F (s) ª 1 + st 2 s(t 1 + t 2 ) (2. . All rights reserved. Because the time constant t1 of the loop ﬁlter is much larger than the period of the u1 signal in Fig. The third trace shows the waveform of ud.3. 2. the output signal ud of the PFD then toggles between the states 0 and 1.38. In any case. In practice. If the equivalent signal ueq had a duty cycle of 100 percent. The centerline of the ud signal represents the high-impedance state of the PFD (Hi-Z). Obviously.38.12. When the active PI ﬁlter is chosen.digitalengineeringlibrary. capacitor C of the loop ﬁlter would simply charge toward the supply voltage UB with time constant t1 + t2 = Downloaded from Digital Engineering Library @ McGraw-Hill (www. of course. the average duty cycle d varies very little with the ratio w1/w2¢ and can be considered constant for this analysis. 2. 2. The initial radian frequency offset is denoted Dw0 with Dw0 = w1 . the average duty cycle of ud is 50 percent. As explained in Sec.Mixed-Signal PLLs 68 Chapter Two modiﬁed when it is driven by the PFD.1 and Fig. The input radian frequency w1 is assumed to be markedly higher than the down-scaled VCO output frequency w0/N = w0¢. As Fig. the pull-in range corresponds to the range of frequencies the VCO is able to generate. It has the shape of a sawtooth signal. an equivalent signal ueq having a constant duty cycle of 50 percent would have the same effect on the loop ﬁlter. Any use is subject to the Terms of Use as given at the website. 2. It periodically ramps up from 0 to 1 and is a sawtooth function as well. the transfer function is approximated by F (s) ª -K a 1 + st 2 st 1 (2. however. 2. 2. We assume again that the PLL is initially out of lock and the VCO operates at its center frequency w0.15 shows. so we need a suitable approximation for TP. the pull-in range DwP becomes theoretically inﬁnite. This situation is sketched by the upper two waveforms in Fig. First we are going to calculate the pull-in time TP for the case where the passive lead-lag loop ﬁlter is used.com) Copyright © 2004 The McGraw-Hill Companies.

2. The pull-in time TP now is simply the time after which the voltage on capacitor C has reached that level. Since the VCO of the PLL was assumed to operate at its center frequency w0 at the start of the pull-in process.39 can now be used to compute the signal uf across capacitor C. This greatly facilitates the computation of the averaged loop ﬁlter output signal uf.digitalengineeringlibrary. however.32)]. as explained in the text. Because the duty cycle is only 50 percent. For the passive lead-lag ﬁlter the calculation yields Downloaded from Digital Engineering Library @ McGraw-Hill (www.38 ∆ω KO TP The waveforms shown in this ﬁgure demonstrate the pull-in process of a PLL that uses the PFD. (2. 2.39 is therefore UB/2. ud toggles between the states 0 and 1 (third trace). . The frequency w1 of the input signal u1 is assumed to be higher than the (scaled-down) frequency w2¢ of the VCO output signal. the voltage on capacitor C must be increased by N Dw0/K0 [compare with Eq. the capacitor will try to charge from UB/2 to UB during the pull-in process. All rights reserved. Therefore the loop ﬁlter acts like a simple RC ﬁlter whose time constant is not t1 + t2 but 2(t1 + t2). Consequently. The average ud signal has the same effect as an equivalent signal ueq with constant duty cycle of 50 percent. Consequently. The equivalent model of Fig. the VCO must create an output frequency that is offset from the center frequency w0 by the amount N Dw0.16a for symbol deﬁnitions). 2. (R1 + R2)C. The actual source voltage for the RC ﬁlter in Fig. the capacitor needs twice as much time to charge. Any use is subject to the Terms of Use as given at the website.com) Copyright © 2004 The McGraw-Hill Companies. see bottom trace. To obtain that frequency. because C is charged through the series connection of resistors R1 and R2 (compare Fig. the initial value of uf is UB/2. To get locked.Mixed-Signal PLLs Mixed-Signal PLLs 69 u1 ¢ u2 UB ud Hi–Z 0 UB ueq Hi–Z 0 ud UB uf UB 2 Figure 2.

the PFD could be driven from a bipolar supply. . where the positive and negative supply voltages are UB+ and UB-.36.Mixed-Signal PLLs 70 Chapter Two PD UB 2 ud LF R1 + R2 2C uf Figure 2. In the most general case.(negative). the output signal of the PFD output signal could be clipped at the saturation levels Usat+ (positive) and Usat. This is to be expected.digitalengineeringlibrary.102) where Dw0 is the initial frequency offset.39 Charging of capacitor C in the loop ﬁlter is calculated by this equivalent model. All rights reserved. as seen in the lower trace of Fig.103) An analog computation can be performed for the case where the active PI is used: Loop ﬁlter = active PI TP ª 4 t 1 Dw 0 N K 0UB (2. Any use is subject to the Terms of Use as given at the website. (2. If the phase detector is an EXOR gate. Detailed explanations are in the text. For the active lead-lag ﬁlter. Furthermore.Usat-)/2. for Downloaded from Digital Engineering Library @ McGraw-Hill (www.102) by (Usat+ .104) It is worth considering a major difference of the pull-in processes for different types of phase detectors. 2. Loop ﬁlter = passive lead-lag TP ª 2(t 1 + t 2 ) ln 1 2 N Dw 0 1UB K 0 (2.w0¢. Dw0 = w1 . respectively. To account for clipping. a similar analysis yields the result Loop ﬁlter = active lead-lag TP ª 2 t 1 ln 1 2 N Dw 0 1U B K0 K a (2. respectively. the instantaneous frequency of the VCO is modulated in both directions around its average value. This formula has been derived under the premise that the PFD is driven by a unipolar power supply.com) Copyright © 2004 The McGraw-Hill Companies. we simply have to replace UB/2 in Eq.

It turns out that the full pull-in range can be realized only when either type 3 or type 4 phase detectors are chosen. The instantaneous frequency of the VCO approaches the ﬁnal value from one side only. Indeed it is locked. the pull-in range cannot be larger than the range of frequencies the VCO is able to create. has odd harmonics. All rights reserved. when the PFD is used. When the VCO oscillates at 120 kHz. Any use is subject to the Terms of Use as given at the website. The third harmonic is 120 kHz.Mixed-Signal PLLs Mixed-Signal PLLs 71 the ud signal is an ac signal. 2.” Theory suggests that the pull-in range becomes inﬁnite whenever the loop ﬁlter is an active PI ﬁlter.e. which is assumed to be a symmetrical square wave. a ﬁlter having “inﬁnite gain” at dc).37). The truth about “inﬁnite pull-in range. i.39). We would expect the VCO to pull down its frequency to 50 kHz. i. i. third. Now f1 suddenly jumps down to 40 kHz. the frequency of the VCO is slowly “pumped up. Assume that the reference frequency is f1 = 100 kHz initially. No pumping occurs. however. Again the center frequency is f0 = 100 kHz. We would expect the VCO to pull down its frequency to 40 kHz as well. Only then does the output frequency perform a damped oscillation. it slightly overshoots the ﬁnal value and settles after the transient has died out. etc. The reference frequency f1 is assumed to be 100 kHz initially.. charge is pumped into the ﬁlter capacitor in one direction only. Let the center frequency be f0 = 100 kHz. the PLL can false-lock onto a harmonic of the reference frequency. 2.com) Copyright © 2004 The McGraw-Hill Companies. 5). Since the driving signal for the loop ﬁlter is unipolar here (Fig. so that the frequency of the VCO is moved in the “right” way at any time. But it ramps up to 120 kHz and stays locked there! What happened now? The PLL locked onto the third harmonic of the reference frequency.digitalengineeringlibrary.35 for the multiplier phase detector. a lock-in process follows. ﬁfth.e. but on the wrong frequency. The lower sideband (50 kHz) has exactly the reference frequency. the EXOR phase detector thinks that the PLL is perfectly locked. Provided a pull-in process starts. In effect the reference signal. We will have a closer look at these phenomena when we perform computer simulations (Chap. When phase detector type 1 or 2 is used.e. Example 1 Consider a PLL with type 1 phase detector (multiplier) and no downscaler. even more stringent restriction. . Now the reference frequency suddenly jumps to 50 kHz. The frequency modulation generated by the 50-kHz component creates sidebands at 50 and 150 kHz. Let us explain that phenomenon by two examples.. The phase detector therefore “believes” that the PLL is perfectly locked. Because phase detector type 4 is not Downloaded from Digital Engineering Library @ McGraw-Hill (www. A similar pumping is observed when the phase detector is a JK-ﬂipﬂop (Fig. 150 kHz and 50 kHz. The frequency of the VCO is thus modulated by a 50-kHz and a 150-kHz component. a ﬁlter having a pole at s = 0 (or in other words.” as has been shown in Fig. but in effect it is locked to twice the reference frequency. As we already have seen. When the pull-in process is completed. 2. But there is another. which causes the phase detector to output a dc signal that depends on the phase shift between these two 50-kHz signals. but it remains locked at 100 kHz. What happened? With f1 = 100 kHz and f2 = 50 kHz the multiplier generates the sum and difference of these two frequencies.. Example 2 Consider a PLL with type 2 phase detector (EXOR) and no down-scaler.

the PLL is pulled out by too large a frequency step. the pull-out frequency corresponds to that weight that causes the pendulum to tip over if the weight is suddenly dropped onto the platform. With the EXOR phase detector the average output signal ud versus phase error is a triangular function.106) If.21).27.Mixed-Signal PLLs 72 Chapter Two only phase. Phase detector type 3. In the mechanical analogy of Fig. simulations on an analog computer6 have led to an approximation: Dw PO ª 1.7.27 to tip over. Any use is subject to the Terms of Use as given at the website.1 < z < 3.w0¢ is smaller than DwP. If the corresponding pull-in time is considered to be too long. 2. All rights reserved. Pull-out Range DwPO Phase detector type 1.107) As could be expected. as shown in Fig. the peak frequency deviation Dw must be conﬁned to the lock range DwL. Phase detector type 2. using damping factors in the range 0.65) (2. An exact calculation of the pull-out range is not possible for the linear PLL. In the case of the JK-ﬂipﬂop.1 By using the rules of differential calculus. the pull-out range was determined by simulation.digitalengineeringlibrary. Because the average output signal ud of the JK-ﬂipﬂop actually is linear in the range -p < qe < p. in an FM system.8w n (z + 1) (2.46w n (z + 0. 2.com) Copyright © 2004 The McGraw-Hill Companies. this result is not far away from that for phase detector type 1. the pull-out range can be computed explicitly. By using the linear model of the PLL (Fig. The pull-out range is by deﬁnition that frequency step that causes a lockout if applied to the reference input of the PLL. we can expect that PLL to come back to stable operation—by means of a relatively slow pull-in process—provided the frequency offset Dw = w1 . it is not possible to calculate explicitely the pull-out frequency. 2. the pull-in process is much faster if type 4 is selected. A different procedure is used to compute the pull-out range of the PLLs using a JK-ﬂipﬂop or a PFD as phase detector.but also frequency-sensitive. .105) In most practical cases the pull-out range is between the lock range and the pull-in range: Dw L < Dw PO < Dw P (2. The result is a damped oscillation. Then a least-squares ﬁt gave the approximation Dw PO ª 2. 2. However. the pull-out range also is the frequency step that causes the pendulum in the model of Fig. When the EXOR phase detector is chosen. Because this is a nonlinear function. phase error qe is calculated for a frequency step Dw applied to the reference input. With the PLL design program distributed with this book. the pull-out range is the frequency step causing the peak phase error to exceed p. it is straight- Downloaded from Digital Engineering Library @ McGraw-Hill (www.

2. because tables for inverse hyperbolic tangent. the least-squares ﬁt gave the linear approximation Dw PO ª 11. the pull-out range can be computed explicitly as done for phase detector type 3. Because the average output signal ud of the JK-ﬂipﬂop actually is linear in the range -2p < qe < 2p. for example.6. we notice that the curve becomes rather ﬂat and could easily be replaced by a linear function. one table for each type of phase detector.108) z z . This would ease the computation of the pull-out range considerably. and Table 2.6 are summarized in four tables. Table 2.7 Phase Detectors with Charge Pump Output When analyzing the pull-in range of the PLL (Sec. are not always at hand.4 for phase detector 4. Table 2.1ˆ pw n expÊ 2 tanh -1 Ë z -1 z ¯ 2 If DwPO is plotted against z.55w n (z + 0.2 contains the corresponding equations for the Exor phase detector. we found that a wide pull-in range is most easily achieved by using the PFD as phase detector.z2 z ¯ 2 pw n e 2 z <1 z =1 z >1 (2.z2 z ¯ pw n e 2 z <1 z =1 z >1 (2. the pull-out range is the frequency step causing the peak phase error to exceed 2p. (2. A least-squares ﬁt performed with Eq.1ˆ 2 pw n expÊ 2 tanh -1 Ë z -1 z ¯ 2 Here.109) Phase detector type 4.Mixed-Signal PLLs Mixed-Signal PLLs 73 forward to calculate the maximum of the phase error. An analogous computation yields z 1-z ˆ Dw PO = 2 pw n expÊ tan -1 Ë 1 . From there it is quite easy to calculate the size of frequency step that leads to a peak phase error of p.5) (2.3 for phase detector 3. Table 2. All rights reserved.1).108) gave the approximation Dw PO ª 5.1 lists the formulas for the most important key parameters for PLLs using phase detector type 1.78w n (z + 0.com) Copyright © 2004 The McGraw-Hill Companies.5) (2.110) z z . Downloaded from Digital Engineering Library @ McGraw-Hill (www.111) To ease the design of mixed-signal PLLs. 2. Any use is subject to the Terms of Use as given at the website. .digitalengineeringlibrary. In the case of the PFD. Assuming that the PLL is a high-gain loop. we get z 1-z ˆ Dw PO = pw n expÊ tan -1 Ë 1 . 2. the equations derived in Sec.

When the PLL has become locked.100)]. . i. By “operating point” we mean the average loop ﬁlter output signal uf that is required to create the desired output frequency w2 of the VCO. This is because the charge on the loop ﬁlter capacitor remains unchanged when the output of the PFD is in the high-impedance state (if we discard leakage currents for the moment).5 V .5 V . but varies with the “operating point” of the loop.e. Therefore in most digital PLLs the combination of PFD and passive lead-lag ﬁlter is the preferred arrangement (Fig. Capacitor C therefore gets charged to 2.8w n (z + 1) Moreover. As reported by Volgers15 this circuit has a property that can be disturbing in critical applications: the phase detector gain Kd of the PFD is not constant as predicted by theory.com) Copyright © 2004 The McGraw-Hill Companies. Phase Detector Type 1 (Multiplier) Loop ﬁlter Key parameter Natural frequency wn Damping factor z Hold range DwH Lock range DwL Lock time TL Pull-in range DwP Low-gain loops Passive lead-lag Active lead-lag Active PI K0 K d N ( t1 + t 2 ) wn Ê N ˆ t2 + 2 Ë K0 K d ¯ K0Kd/N K0 K d K a Nt 1 wn Ê N ˆ t2 + 2 Ë K0 K d K a ¯ K0KdKa/N ª 2zwn K0 K d Nt 1 w n t2 2 • ª 2p wn All loops Low-gain loops 4 p 2zw n K 0 K d N .. and that the PLL initially operates at its center frequency w0.w 2 n 4 p 2zw n K 0 K d K a N - w2 n Ka • High-gain loops High-gain loops 4 2 p Pull-in time TP Pull-out range DwPO zw n K 0 K d N 4 2 p ª 16 zw n K 0 K d N ª p 2 Dw 2 0 16 zw 3 n ª p 2 Dw 2 0 16 zw 3 n p 2 Dw 2 0Ka zw 3 n ª 1. the output of the PFD will be in the high-impedance state most of the time. Let us explain that by a simple consideration. it showed that the passive lead-lag loop ﬁlter performs like a real integrator when driven by the PFD [Eq.1 Summary of Parameters of the Mixed-Signal PLL.Mixed-Signal PLLs 74 Chapter Two TABLE 2. 2. All rights reserved. The PFD will Downloaded from Digital Engineering Library @ McGraw-Hill (www. at uf = 2. Under this condition.40a).digitalengineeringlibrary. Assume that the PLL is powered from a unipolar supply with UB = 5 V . the output signal uf of the loop ﬁlter will settle at half the supply voltage. (2. Any use is subject to the Terms of Use as given at the website.

4.e. its output voltage will become ud ª 5 V for some time. . i. Capacitor C will then be charged to a higher voltage through the series connection of resistors R1 and R2. but that its output frequency was offset so much that the average loop ﬁlter output signal uf had to be pulled up to.4 = 1 V across Downloaded from Digital Engineering Library @ McGraw-Hill (www.5 kW.0 V to maintain the desired output frequency w2. a current of 2.2 Summary of Parameters of the Mixed-Signal PLL. Suppose now that the PLL is required to pull up the output frequency w2 to a much higher level. Again. If we assume that the sum R1 + R2 equals 2.com) Copyright © 2004 The McGraw-Hill Companies. Phase Detector Type 2 (EXOR) Loop ﬁlter Key parameter Natural frequency wn Damping factor z Hold range DwH Lock range DwL Lock time TL Pull-in range DwP Low-gain loops Passive lead-lag Active lead-lag Active PI K0 K d N ( t1 + t 2 ) wn Ê N ˆ t2 + 2 Ë K0 K d ¯ K0 K dp 2 N K0 K d K a Nt 1 wn Ê N ˆ t2 + 2 Ë K0 K d K a ¯ K0 K d K ap 2 N ª pzwn K0 K d Nt 1 w n t2 2 • ª 2p wn All loops Low-gain Loops p 2 2zw n K 0 K d N .46w n (z + 0.w 2 n p 2 2zw n K 0 K d K a N - w2 n Ka • High-gain loops High-gain loops p 2 Pull-in time TP Pull-out range DwPO zw n K 0 K d N p 2 ª p2 zw n K 0 K d N ª 4 Dw 2 0 p 2 zw 3 n ª 4 Dw 2 0 p 2 zw 3 n 4 Dw 2 0Ka zw 3 n ª 2. The PFD will therefore switch to the high state. Any use is subject to the Terms of Use as given at the website. but the current that initially ﬂows into capacitor C now is much smaller now than in the former example. All rights reserved.5 kW = 1 mA will initially ﬂow into capacitor C.65) occasionally switch into the high or low state during very short intervals of time just to keep the voltage on capacitor C at the proper level. Because there is a voltage difference of only 5 .digitalengineeringlibrary. The capacitor will charge toward UB with a time constant (R1 + R2)C..Mixed-Signal PLLs Mixed-Signal PLLs 75 TABLE 2. capacitor C will charge with time constant (R1 + R2)C toward 5 V .5 V/2. If the PLL is required now to pull up its output frequency even more. say. Let us suppose now that the PLL did not operate at its center frequency initially. the PFD will switch again into the high state (ud ~ 5 V).

5 kW = 1.4 mA now.40b. All rights reserved. .w 2 n High-gain loops p 2zw n K 0 K d K a N High-gain loops w2 n Ka • p 2 zw n K 0 K d N Pull-in time TP Pull-out range DwPO p 2 zw n K 0 K d N ª 1 Dw 2 0Ka p 2 ª 1 Dw 2 0 p zw 2 3 n zw 3 n ª 1 Dw 2 0 p 2 zw 3 n ª5. Any use is subject to the Terms of Use as given at the website. When the phase detector gain Kd is reduced. Phase Detector Type 3 (JK-Flipﬂop) Loop ﬁlter Key parameter Natural frequency wn Damping factor z Hold range DwH Lock range DwL Lock time TL Pull-in range DwP Low-gain loops Passive lead-lag Active lead-lag Active PI K0 K d N ( t1 + t 2 ) wn Ê N ˆ t2 + 2 Ë K0 K d ¯ K0 K dp N K0 K d K a Nt 1 wn Ê N ˆ t2 + 2 Ë K0 K d K a ¯ K0 K d K ap N ª 2pzwn K0 K d Nt 1 w n t2 2 • ª 2p wn All loops Low-gain Loops p 2zw n K 0 K d N . When the PLL is required to increase its output frequency. the current ﬂowing into C is only 1 V/2. Here the loop gain is higher by a factor 1.78w n (z + 0.6 when compared with the ﬁrst case. In this circuit the output current delivered by Downloaded from Digital Engineering Library @ McGraw-Hill (www.5 in this situation. A lower loop gain leads to a smaller natural frequency wn and a smaller damping factor z. the average uf signal would have been set to perhaps 1. as shown in Figure 2. This simple example demonstrates that the phase detector gain Kd of the PFD is not a constant.5 kW = 0.5) resistors R1 + R2.6 mA. When we consider the opposite case where the PLL initially operated at a frequency much below the center frequency.3 Summary of Parameters of the Mixed-Signal PLL. This implies that the loop gain of the PLL has become smaller by a factor 2. but varies with the initial output signal uf . which could produce unacceptable overshoot. the loop gain (which is given by KdK0/N) is reduced as well.digitalengineeringlibrary. the initial current ﬂowing into capacitor C would be increased to 4 V/2.com) Copyright © 2004 The McGraw-Hill Companies.0 V . One option would be to use the active PI ﬁlter instead of the passive leadlag.Mixed-Signal PLLs 76 Chapter Two TABLE 2. There are several ways to overcome the problem of varying phase detector gain.

40a (a) LF Most digital PLLs use the PFD combined with the passive lead-lag loop ﬁlter.digitalengineeringlibrary.Mixed-Signal PLLs Mixed-Signal PLLs 77 TABLE 2.5) UB UP "1" u1 D CP FF CD Q P ud R1 uf R2 CD u2 ' "1" CP D C Q DN N FF PD Figure 2.55w n (z + 0. Phase Detector Type 4 (PFD) Loop ﬁlter Key parameter Natural frequency wn Damping factor z Hold range DwH Lock range DwL Lock time TL Pull-in range DwP Pull-in time TP Passive lead-lag Active lead-lag Active PI K0 K d N ( t1 + t 2 ) K0 K d K a Nt 1 w n t2 2 • ª 4pzwn K0 K d Nt 1 ª • 2p wn 1 12 NDw 0 UB K0 K a 4 t1 Dw 0 N K 0U B 2( t1 + t 2 ) ln 1- 1 2 NDw 0 UB K0 2t1 ln Pull-out range DwPO ª11.com) Copyright © 2004 The McGraw-Hill Companies. .4 Summary of Parameters of the Mixed-Signal PLL. All rights reserved. Any use is subject to the Terms of Use as given at the website. Downloaded from Digital Engineering Library @ McGraw-Hill (www.

but the outputs of the UP and DN ﬂipﬂops are controlling two current sources. Such phase detectors are said to have a charge pump output. .40c shows the cascade of a charge pump PFD with a passive lead-lag loop ﬁlter. 2. where ud is the average voltage output signal that would be delivered by a conventional PFD (i. e. which is simply the sum of resistor R2 and the reactance 1/sC of capacitor C.digitalengineeringlibrary. All rights reserved. For the loop ﬁlter output signal we get Downloaded from Digital Engineering Library @ McGraw-Hill (www.5 V. To get the average loop ﬁlter output signal uf . When the UP ﬂipﬂop is set. however. by a PFD having voltage output). as explained. The average current output versus phase error is given by iout = Kdqe/Rb. the PFD always ﬂows into the summing junction of the operational ampliﬁer. The PFD shown on the left side is built up like a conventional PFD. Figure 2. we must multiply the PFD output current by the impedance of the loop ﬁlter.40b (b) LF Combination of the PFD with the active PI loop ﬁlter.e.g. 51. The transimpedance Rb is usually set by an external resistor.. which is at a constant level of UB/2 = 2.Mixed-Signal PLLs 78 Chapter Two UB "1" u1 D CP FF CD Q UP P ud R1 R2 C uf CD u2 ' "1" CP D FF Q DN N UB/2 PD Figure 2. hence that current does not depend on the output level uf. and Rb is the transimpedance of the voltage-to-current converter inherent in this type of PFD.40c) sources current into the output terminal. the lower current source sinks current from the output terminal.. Any use is subject to the Terms of Use as given at the website. There is another way to go around that problem: the application of a phase detector having a current output instead of voltage output. the upper current source (right top in Fig.com) Copyright © 2004 The McGraw-Hill Companies. in Ref. When the DN ﬂipﬂop is set. The PFD output current iout averaged over one reference cycle is given by ud /Rb.

Phase detectors with charge pump output can be combined with any kind of loop ﬁlters. followed by passive lead-lag loop ﬁlter. There are a number of commercially available PLLs utilizing a PFD having a charge pump output. because the current output signal of the charge pump is a tristate Downloaded from Digital Engineering Library @ McGraw-Hill (www.4 for the active PI loop ﬁlter to compute the relevant key parameters of the PLL such as lock range. pull-in range.1). and the like. . we get the simple expression U f (s) = Q e (s) K d 1 + st 2 st 1 This result is identical with that obtained for a digital PLL built from a voltage output PFD followed by an active PI loop ﬁlter. e. Passive ﬁlters are preferred in most cases. the 74HCT9046A manufactured by Philips51 (see also Table 10.com) Copyright © 2004 The McGraw-Hill Companies. passive or active.g.Mixed-Signal PLLs Mixed-Signal PLLs 79 UB UP "1" U1 D FF Q CP CD iout uf CD U2' "1" R2 CP FF DN C Q D PD Figure 2.40c (c) LF PFD with charge pump output. Consequently we can use the formulas given in Table 2. All rights reserved. U f (s) = Q e (s) K d 1 + sR2C sRbC Putting t1 = RbC and t2 = R2C.digitalengineeringlibrary.. Any use is subject to the Terms of Use as given at the website.

.48 Also.e. by Gardner and Viterbi. Exact solutions for noise performance have been derived for ﬁrstorder PLLs only4. i.. For an arbitrary sequence of bits. 3). 2. 4. 2. a passive RD ﬁlter connected to the charge pump output behaves like a real integrator.. This is sketched by Fig.g. 2.1 Sources and types of noise in a PLL As was demonstrated by Rohde. In applications of communication. the transmitted signal picks up noise.5 We deal here only with the simpliﬁed noise theory. and from many other sources. The received signal therefore is a sine wave in this case. . at least not for ﬁrst-order ﬁlters. the waveform gets more complex. PLLs using a type 1 phase detector). only the fundamental is transmitted. from atmospheric noise. This property is made use of extensively in the whole ﬁeld of communications. In Sec. the noise superimposed to the input signal (reference signal) is predominant. Noise can be generated in repeaters. . Hence an active ﬁlter would not bring additional beneﬁt.41 for the trivial case that the data signal is a bit stream of the form 10101010. so we will restrict ourselves to reference noise. There are many types of additive noise. When the PLL is used as a frequency synthesizer (see Chap. which have provided approximate results.8. . would be represented as a symmetrical square wave.. as presented. . digital signals are transmitted. however. for second-order PLLs. The theory of noise in PLLs is extremely cumbersome. In most communications systems in which the PLL is made use of.” and the received signal must be considerer “analog. Because of the harmonics. As shown by Rohde even the highestquality oscillators can create noise. of course. due to thermal noise of transistors and resistors within the oscillator circuit. the bandwidth requirements would become excessive it the pure square wave signal were sent.” In every communication link. Anyway.7 we will discuss higher-order loop ﬁlters that can be cascaded with charge pump outputs. we ﬁrst want to identify the sources and types of noise in PLL systems. computer simulations have been made. e. A binary sequence of 10101010 .g. e.24 Before entering into details. all that noise is added algebraically to the (analog) data signal.8 PLL Performance in the Presence of Noise One of the most intriguing properties of the PLL is its ability to extract signals from an extremely noisy environment.1.e.com) Copyright © 2004 The McGraw-Hill Companies. but the transitions still look like “sine waves. All rights reserved. The most common is Downloaded from Digital Engineering Library @ McGraw-Hill (www.Mixed-Signal PLLs 80 Chapter Two signal. the baseband signals consist of pulses or square wave signals.4 Whereas Gardner and Viterbi analyzed noise performance of linear PLLs (i. To save bandwidth. but it also can be created by crosstalk from other channels. . the reference source is normally a high-quality oscillator whose frequency is usually determined by a quartz crystal.. here the noise source is the reference signal itself. . Selle and coworkers investigated noise in digital PLLs in more detail.48 every building block of the PLL can contribute to noise. Any use is subject to the Terms of Use as given at the website.digitalengineeringlibrary.

“high” and “low.Mixed-Signal PLLs Mixed-Signal PLLs 81 1 0. called added white gaussian noise (AWGN).” as shown in Fig. The solid curve in Fig. we now shall deﬁne the most important parameters that describe noise.com) Copyright © 2004 The McGraw-Hill Companies.5 time [s] Figure 2. (b) A random noise signal. Downloaded from Digital Engineering Library @ McGraw-Hill (www. All rights reserved.5 4 4. (a) A very simple signal (a sequence of binary 101010 . 2.5 3 3. every frequency interval df contains the same noise power dPn.5 3 3. To cope with the effects of superimposed noise.5 1 1. its amplitude can take only two levels. The noise shown in Fig.).” The noise superimposed on the data signal now causes the zero crossings of the square wave to become “jittered. indicating that the probability density function of the noise amplitude is normally distributed (a Gauss function).5 a) carrier signal 2 2.5 0 –0.41 0. 2.digitalengineeringlibrary.5 1 1.42. .5 5 Added noise to information signal. The converted signal is then a square wave.5 –1 0 1 0. .5 5 c) signal + noise 3 3. a Schmitt trigger.5 2 2. dPn/df is constant. for example. For a binary signal.41 is referred to as amplitude noise because it modulates the amplitude of the data signal.5 4 4. The term gaussian characterizes the amplitude distribution of the signal. i. and the thinner lines represent the jittered transients.e.42 is the undistorted data signal. In the receiver a band-limited data signal is usually reshaped by using. . Any use is subject to the Terms of Use as given at the website.5 5 b) random noise 0.. The term white refers to the spectrum of noise and indicates that within the socalled noise bandwidth of the channel. 2.5 0 0 2 1 0 –1 0 0. This kind of noise is called phase noise or phase jitter.5 1 1.5 2 2.5 4 4. (c) The sum of both.

The noise spectrum usually is also symmetrical around the center frequency and is broadband in most cases.4. 2. this term will be deﬁned in Sec.22.digitalengineeringlibrary. H(w) is a lowpass ﬁlter function. Signal power is denoted Ps in this ﬁgure.2 Deﬁning Noise Parameters To analyze noise performance of the PLL.8. labeled Ps) and of noise (dashed curve. 2. .8. We remember that the phase transfer function H(s) relates the Laplace transform Q2¢(s) of the phase q2¢(t) to the Laplace transform Q1(s) of the phase q1(t). As will be explained in the following section. its one-sided bandwidth is labelled Bi/2. labeled Pn). H(w) is the phase frequency response of the PLL. we get a bandpass function as seen from the lower trace in Fig. 2. hence w adds to the carrier frequency.) This simply means that the PLL is able to track frequencies within a passband centered at the down-scaled center frequency f0¢ ( f0¢ = w0¢/2p). there are two important parameters describing noise performance: The signal-to-noise ratio SNRi = Ps/Pn at the input of the PLL The ratio Bi/BL of input noise bandwidth Bi to PLL noise bandwidth BL Downloaded from Digital Engineering Library @ McGraw-Hill (www. If we plot H( f ) versus the sum of carrier + modulation frequency. Now the variable w in H(w) is the (radian) frequency of the phase signal that modulates the carrier frequency w0¢. All rights reserved.Mixed-Signal PLLs 82 Chapter Two Carrier Phase jitter t Figure 2. amplitude noise is converted to phase noise (phase jitter). The lower part of the ﬁgure shows the phase frequency response H( f ) of the PLL. Fig. the noise spectrum that is outside of the passband of the PLL will be suppressed by the loop.43.com) Copyright © 2004 The McGraw-Hill Companies. As we easily recognize from Fig. 2. hence only the part of the noise spectrum within the noise bandwidth is able to corrupt PLL performance. and its one-sided bandwidth is denoted Bs/2. Let us state for the moment that the one-sided noise bandwidth BL/2 is approximately equal to the earlier-deﬁned 3-dB bandwidth f3dB ( f3dB = w3dB/2p). 2. (Note that H is plotted versus frequency f here and not versus radian frequency w.43.42 When a data signal is reshaped. The signal spectrum is centered at the down-scaled center frequency f0¢ of the VCO. The symbol BL stands for noise bandwidth. As we see from the plot in Fig. For s = jw. Any use is subject to the Terms of Use as given at the website. it is most convenient to describe signals and noise by their power density spectra.43. noise power is denoted Pn. 2. The upper part shows the spectra of the signal (solid curve.

for meaning of symbols see text.43 Deﬁnition of noise parameters. Assuming that the noise spectrum is “white” as explained in the preceding section. of course.1 We are going to consider amplitude and power density spectra of information signals and noise signals. When two-sided power spectra are used. because there is always a preﬁlter or preampliﬁer in the system that limits noise bandwidth. but the two-sided spectrum would have two spectral lines at f0 and at -f0. Note that Bi is ﬁnite in all practical cases. All rights reserved. 2. The noise spectrum has a bandwidth of Bi. Any use is subject to the Terms of Use as given at the website. . The same applies for noise spectra. where input signal and input noise are plotted once again. Gardner found the mean 1 square value of input phase jitter q2 n1 to be q2 n1 = Pn 2 Ps (2. 2. Noise analysis is explained by Fig. the one-sided power density spectrum shows a line at f0. respectively.digitalengineeringlibrary. We now calculate the phase jitter created by the noise at the reference input of the PLL (see input u1 in Fig. Note that q2 n1 is simply the square of the rms value of input phase jitter. Here we assume for simplicity that the input signal consists of one spectral line at the down-scaled center frequency f0¢.44. onesided and two-sided.Mixed-Signal PLLs Mixed-Signal PLLs 83 P Bi /2 Bs /2 Ps ' f0 BL H (f) ' f0 f Pn f H Figure 2. If an information signal has a single spectral line at a frequency f0.1). Downloaded from Digital Engineering Library @ McGraw-Hill (www.112) with Ps = signal power (W) and Pn = noise power (W).3 The impact of noise on PLL performance The noise analysis presented here is based on the work of Gardner. It is a matter of taste whether to use onesided or two-sided power spectra. For one-sided spectra. total power of a signal can be calculated by integrating its power density spectrum over the frequency interval -• < f < •. however. Two types of power density spectra have been deﬁned. this interval becomes 0 < f < •.8. 2.com) Copyright © 2004 The McGraw-Hill Companies. We follow Gardner’s terminology in the following and use one-sided spectra only.

All rights reserved. Downloaded from Digital Engineering Library @ McGraw-Hill (www. (c) Bode plot of the phase-transfer function H(w).Mixed-Signal PLLs 84 Chapter Two Spectral Power Density Area = Ps Bi Area = Pn Wi f fo (a) Qn1 (w)2 2 Area = qn1 f f Bi/2 (b) ΩH (w)Ω z = Parameter BL (c) f ¢ (w)2 Qn2 ¢ Area = qn2 2 BL (d) Figure 2.44 f 2 Method of calculating the phase jitter q¢ n2 at the down-scaled output of the PLL.com) Copyright © 2004 The McGraw-Hill Companies. (d) Spectrum of the phase noise at the down-scaled output of the PLL. Any use is subject to the Terms of Use as given at the website. (a) Power spectra of the reference signal u1(t) and the superimposed noise signal un(t).digitalengineeringlibrary. . (b) Spectrum of the phase noise at the input of the PLL.

1 Fig. .44b shows the mean square of input phase jitter: Q2 n1 (w) = F = q2 n1 Bi 2 rad 2 ◊ Hz -1 (2. All rights reserved.com) Copyright © 2004 The McGraw-Hill Companies.116) and (2. 2.Mixed-Signal PLLs Mixed-Signal PLLs 85 We now deﬁne the SNR at the input of the PLL as (SNR )i = Ps Pn (2. Consequently the spectrum Qn1(w) of input phase jitter is identical with the input noise spectrum shifted down by f0¢. Knowing the spectrum of input phase jitter. which is simply the multiplication of curves (b) and (c) in the ﬁgure. we use the Parseval theorem to get 2 q2 n2 ¢ = Ú Q n2 ¢(2 pf ) df 0 • (2. the mean square Q 2 n1 (w) has the constant value F.digitalengineeringlibrary. (2.117) where 2pf = w. 2.44c plots the Bode diagram of H(w).113) For the phase jitter at the input of the PLL we get the simple relation q2 n1 = 1 2(SNR )i rad 2 (2.114) That is. Any use is subject to the Terms of Use as given at the website.44d shows the mean square Q2 n2 ¢(w) of the output phase noise spectrum. We remember that q2 n1 is the mean square of the phase noise that modulates the carrier frequency f0¢ of the PLL (f0¢ = w0¢/2p).118) The integral Ú H (2pf ) 0 2 df is called noise bandwidth BL. and Fig.117). we can compute the spectrum Q 2 n2 ¢(w) of the down-scaled output phase jitter from 2 Q2 n1 ¢(w) = H (w) ◊ Q n1 (w) = H (w ) F 2 2 (2. To compute the mean square of output phase jitter q2 n2 ¢. 2. the square of the rms value of the phase jitter is inversely proportional to the SNR at the input of the PLL. Making use of Eqs. we get q2 n2 ¢ = Ú F H (2 pf ) df = 0 • • 2 2 F H (w) dw Ú 2p 0 • (2. q2 n2 ¢ is the area under the curve in Fig.44d. 2.115) Since the noise spectrum has been assumed white.116) Fig. Downloaded from Digital Engineering Library @ McGraw-Hill (www.

the choice of z = 0. (Adapted from Gardner1 with permission.122) 2. For the output phase jitter q2 n2 ¢ we can now write q2 n2 ¢ = FBL 2.0 1.5 BL / w n 1. BL is 0.5wn. .5 1. it depends on the damping factor z.5 0 0 0.3 we showed that the transient response of the PLL is best at z = 0.119) The solution of this integral reads1 BL = wn Ê 1 z+ ˆ Ë 2 4z ¯ (2. Figure 2.5.5 Noise bandwidth of a second-order PLL as a function of the damping factor z.0 0.53wn instead of the minimum value 0.0 2.5.7 is chosen for most applications.121) In Sec.com) Copyright © 2004 The McGraw-Hill Companies.Mixed-Signal PLLs 86 Chapter Two BL = Ú H (2 pf ) df 0 • 2 (2. Any use is subject to the Terms of Use as given at the website.45 2. furthermore. For this reason z = 0.0 1. In this case we have BL = BL min = wn 2 (2.) Downloaded from Digital Engineering Library @ McGraw-Hill (www.5 (2.5 3. All rights reserved. Because the function BL(z) is fairly ﬂat in the neighborhood of z = 0. For z = 0.0 3.120) Thus BL is proportional to the natural frequency wn of the PLL. 2.45 is a plot of BL versus z. and BL has a minimum at z = 0.5 z Figure 2.7.7.digitalengineeringlibrary.7 does not noticeably worsen the noise performance.

125) says that the PLL improves the SNR of the input signal by a factor of Bi/2BL. (2. Let us therefore look at some numerical data.com) Copyright © 2004 The McGraw-Hill Companies. At (SNR)L = 2 (3 dB). lock-in is eventually possible.123) We saw in Eq.112).digitalengineeringlibrary. In quantitative terms. Combining Eqs. (2.115). (2. By analogy we can also deﬁne a signal-to-noise ratio at the output. In radio and television the SNR is used to specify the quality of information transmission.124).115). We deﬁne this analogy in Eq. for (SNR)L = 4 the output phase noise becomes q2 n2 ¢ = Hence the rms value 1 1 = 2◊ 4 8 rad 2 q2 n2 ¢ becomes q2 n2 ¢ = 1 8 = 0. (2.114) that the phase jitter at the input of the PLL is inversely proportional to the (SNR)i. The narrower the noise bandwidth BL of the PLL.Mixed-Signal PLLs Mixed-Signal PLLs 87 where F is already known from Eq. For (SNR)L = 4 (6 dB).353 rad Since the rms value of phase jitter is about 20°.124). 3. Any use is subject to the Terms of Use as given at the website. the value of 180° (limit of dynamic stability) is rarely exceeded. All this sounds very theoretical. For (SNR)L = 1 (0 dB). we get (SNR ) L = Ps BL Bi ◊ = (SNR ) L ◊ Pn Bi 2 BL (2. (2. For a stereo receiver a minimum SNR of 20 dB is considered a fair design goal.122).124) Comparing Eqs. . and (2. according to Eq. the greater the improvement. (2. Consequently the PLL does not unlock Downloaded from Digital Engineering Library @ McGraw-Hill (www. stable operation is generally possible. (2. which will be denoted by (SNR)L (SNR of the loop). All rights reserved.125) Equation (2. The same holds true for PLLs. Practical experiments performed with second-order PLLs have demonstrated some very useful results1: 1. q2 n2 ¢ = 1 2(SNR ) L (2. 2. a lock-in process will not occur because the output phase noise q2 n2 ¢ is excessive.124). we obtain q2 n2 ¢ = Pn BL ◊ Ps Bi (2.123) and (2.

com) Copyright © 2004 The McGraw-Hill Companies. This means that the PLL unlocks about 300 times per second.Mixed-Signal PLLs 88 Chapter Two frequently. let us calculate a numerical example. (SNR ) L ≥ 4 (6 dB) (2. However. 2.126) is a convenient design goal. on the average.5 From Fig. For second-order PLLs. and the dynamic limit of stability of would be exceeded on every major noise peak. 2.46. Any use is subject to the Terms of Use as given at the website. Numerical Example A second-order PLL is assumed to have the following speciﬁcations: f n = 10 kHz w n = 62. if Tav = 100 ms. To illustrate the theory. Summary of noise theory. (2. a system will temporarily unlock. that is. 2. the PLL nevertheless is locked for 97 percent of the total time. which looks quite bad.82) to be TL ª 2p/wn = 100 ms.1 The resulting curve is plotted in Fig. For example. respectively. Stable operation of the PLL is possible if (SNR)L is approximately 4. the effective value of output phase jitter would be as large as 40°.digitalengineeringlibrary. the PLL unlocks on an average 10 times per second. Consequently Tav = 3 ms. (SNR)L is calculated from Downloaded from Digital Engineering Library @ McGraw-Hill (www. The designer of practical PLL circuits is vitally interested in how often. The probability of unlocking is decreased with increasing (SNR)L.46 we read wnTav = 200. for practical design purposes it sufﬁces to remember some rules of thumb: 1. At (SNR)L = 1. We now deﬁne Tav to be the average time interval between two lockouts. As a rule of thumb. Note: The SNR of a signal can be speciﬁed either numerically or in decibels. however.8 ◊ 103 s -1 (SNR) L = 1. Although the noise theory of the PLL is difﬁcult. thus making stable operation impossible. . All rights reserved. the lockin time TL is found from Eq. The numerical value SNR is computed from SNR = 2 (rms) Ps U s = 2 Pn U s (rms) whereas the (SNR)dB is calculated from (SNR )dB = 10 log 10 Ps U s (rms) = 20 log 10 Pn U n (rms) where Us (rms) and Un (rms) are the rms values of signal and noise. Tav has been found experimentally as a function of (SNR)L.

Downloaded from Digital Engineering Library @ McGraw-Hill (www. Any use is subject to the Terms of Use as given at the website.53 wn. antenna.7.46 Average time Tav between two succeeding unlocking events plotted as a function of the (SNR)L at the output of the PLL. if any.5 2. (Adapted from Gardner1 with permission. The average time interval Tav between two unlocking events gets longer as (SNR)L increases. Bi is the bandwidth of the signal source (e. BL = 0. The noise bandwidth BL is a function of wn and z.com) Copyright © 2004 The McGraw-Hill Companies. . Note that this result is valid only for linear second-order PLLs.digitalengineeringlibrary. For z = 0.0 (SNR)L 1.Mixed-Signal PLLs Mixed-Signal PLLs 89 500 200 100 50 wnTav 20 10 5 0 0.5 1. if no preﬁlter is used. Tav is normalized to the natural frequency wn of the PLL. 4.g.0 Figure 2.. repeater) BL = noise bandwidth of the PLL 3. All rights reserved.) (SNR ) L = Ps Bi ◊ Pn 2 BL where Ps = signal power at the reference input Pn = noise power at the reference input Bi = bandwidth of the preﬁlter.

Again. As soon as the reference signal fades away. Consequently the output signal of the EXOR is identical to either the down-scaled VCO output signal u2¢ or the logically inverted signal u2¢. In many applications of communication this condition is not met: the reference signal can almost disappear in some time intervals because of fading.e. the phase detector output hangs up at a logic low level after the reference signal disappears. the loop ﬁlter has also some. and the VCO output frequency also runs away quickly. We conclude that in cases where the reference signal can drop out. the active PI loop ﬁlter (type 3) offers the best performance relating to runaway of the VCO output frequency. As we will see. Some critical remarks on noise theory. . the situation is worse. then the capacitor C (Fig. thus the instantaneous output frequency of the VCO is held nearly constant. With a zero input. and only noise is left. The same holds true for the PFD. the loop surely will get out of lock. When comparing the four types of phase detectors discussed in this chapter. for example..1). All rights reserved. With the edge-sensitive phase detector types. the PFD will go into its -1 state (output at logic low). If the input signal u1 fades away. inﬂuence. Moreover. Consequently the output signal of the loop ﬁlter will be quickly pulled down to its minimum level. The situation is about the same when the EXOR is utilized. What happens now with the output signal of the loop ﬁlter? The situation is similar for the passive and the active leadlag ﬁlter. If the active PI ﬁlter were used. When the input signal of a PLL gets momentarily lost. the VCO output frequency will run away quickly. 2. The term stationary means that the statistical parameters of signal and noise do not change with time. When the reference signal disappears for an extended period of time. There is a good chance that the loop is still in lock when the reference signal reappears. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary. phase detector type 1 or 2 is the better choice. we note that the multiplier and EXOR phase detectors are level-sensitive. i. Assume the PLL uses the multiplier phase detector.16c) has been charged to that voltage that was required to create the appropriate VCO frequency before the reference input faded away. the average output signal ud is zero. The average value ud is zero again. the voltage across capacitor C remains nearly unchanged. the output is also pulled toward zero with a time constant t1 + t2 for the passive or with a time constant t1 for the active lead-lag ﬁlter.com) Copyright © 2004 The McGraw-Hill Companies. When the reference signal u1 disappears. Any use is subject to the Terms of Use as given at the website. the signal at the reference input (after reshaping) hangs up at either a low or a high level. 2. that the power spectrum of noise remains always the same. In case of the JK-ﬂipﬂop. whereas the JK-ﬂipﬂop and PFD are edge-sensitive. Hence the frequency created by the VCO will relatively slowly drift away toward the center frequency w0. it becomes nearly zero. performance of the PLL depends largely on the type of phase detector used. though minor.Mixed-Signal PLLs 90 Chapter Two The noise theory presented in this section is based on the assumption that signal and noise at the reference input of the PLL are stationary. Because that noise is uncorrelated with the (downscaled) output signal u2¢ of the VCO (Fig. With zero input signal.

Such a control signal is generated by the in-lock detector shown in Fig. The sweep signal should now be frozen at its present value (otherwise the VCO frequency would run away).65). As soon as the frequency of the VCO approaches the frequency of the input signal. If the PLL is locked.4 Pull-in techniques for noisy signals In this section we summarize the most popular pull-in techniques.com) Copyright © 2004 The McGraw-Hill Companies. The integrator is in its RUN mode. If the PLL is not in the locked state. To eliminate ac components and to inhibit false triggering. The average value of the output signal of the multiplier uM = u1¢u2 is positive. which is nearly in phase with the VCO output signal u2. Thus the output signal of the multiplier is a clear indication of lock. the uM signal is conditioned by a low-pass ﬁlter. The in-lock detector is a cascade connection of a 90° phase shifter.47. .digitalengineeringlibrary. however.) The phase shifter then outputs a signal u1¢. 2. To avoid this effect. the PLL suddenly locks.47. 2. Of course. Assume the PLL has not yet locked. 2. the noise bandwidth BL is made so small that the SNR of the loop. 2. the center frequency of the VCO is swept by means of a sweeping signal usweep (Fig.Mixed-Signal PLLs Mixed-Signal PLLs 91 2. a low-pass ﬁlter. If the PLL has locked. A linear sawtooth signal generated by a simple RC integrator is used as the sweep signal. and the average value of uM is zero. If this procedure is chosen. an analog integrator would drift away after some time. (SNR)L. the center frequency of the VCO can be tuned by the signal applied to its sweep input.47 to the HOLD position. and a Schmitt trigger. an antidrift circuit has to be added. To control the analog switch. there is a phase offset of approximately 90° between input signal u1 and VCO output signal u2.8. the integrator is kept in the HOLD mode. (2. we need a signal that tells us whether the PLL is in the locked state.47. 2. Any use is subject to the Terms of Use as given at the website.4. For other phase detectors the phase relationship would be different. in the case considered here the reference frequency is assumed to be constant. and hence the sweep signal builds up in the positive direction. the signals u1¢ and u2 are uncorrelated. (In Sec. Downloaded from Digital Engineering Library @ McGraw-Hill (www. This is realized by throwing the analog switch in Fig. A special pull-in procedure becomes mandatory if the noise bandwidth of a PLL system must be made so narrow that the signal may possibly not be captured at all. All rights reserved. an analog multiplier.) As shown in the block diagram of Fig. this is not shown.w0¢ is the only parameter of importance. As a consequence the lock range DwL might become smaller than the frequency interval Dw within which the input signal is expected to be. whereas the center frequency is swept. (Note: It is assumed here that the phase detector is either type 1 or 2. The ﬁltered signal is applied to the input of the Schmitt trigger. as mentioned. the sweep rate must be held within the limits speciﬁed by Eq. because the frequency offset Dw = w1 . For the PLL both situations are equivalent.47) over the frequency range of interest. is sufﬁciently large to provide stable operation. otherwise the PLL could not become locked. To solve the locking problem. 2. The sweep technique. however. in Fig.3 we considered the case where the center frequency w0 was constant and the reference frequency w1 was swept. Of course.

47 Simpliﬁed block diagram of a PLL using the sweep technique for the acquisition of signals buried in noise. Any use is subject to the Terms of Use as given at the website. All rights reserved.) .Integrator RUN SA Uref HOLD t Downloaded from Digital Engineering Library @ McGraw-Hill (www. (SA = analog switch.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. u2 Q Filter Schmitt-Trigger Phase shifter 90˚ u2 output PD LF u1 u2 VCO uSweep Sweep Input HOLD N RU Mixed-Signal PLLs RC .92 In-lock-Detector ¢ u1 Multiplier uM=u1¢ . Figure 2.

the ﬁlter bandwidth has to be reduced instantaneously to a value where the noise bandwidth BL is small enough to provide stable operation.digitalengineeringlibrary. There are PLL applications in communications where the system is used to extract the clock from a (possibly noisy) information signal. reference noise is not of concern. In this state the bandwidth of the loop ﬁlter is so large that the lock range exceeds the frequency range within which the input signal is expected. An entirely different application of the PLL is frequency synthesis. All rights reserved. the output signal Q of the in-lock detector is zero.) Downloaded from Digital Engineering Library @ McGraw-Hill (www. but the synthesizer should be able to switch rapidly from one frequency to another. . In such an application. Any use is subject to the Terms of Use as given at the website. 2.9 Design Procedure for Mixed-Signal PLLs The mixed-signal PLL can be built in many variants.com) Copyright © 2004 The McGraw-Hill Companies. (SA = analog switch. as shown in the previous example.47) low R: not locked u1 PD SA high R: In-lock Switched Loop Filter VCO Figure 2. 2.48. This locking method is depicted in Fig. The noise bandwidth is then too large to enable stable operation of the loop.Mixed-Signal PLLs Mixed-Signal PLLs 93 The switched-ﬁlter technique. This is done by switching the loop ﬁlter to its low-bandwidth position by means of the Q signal.48 Simpliﬁed block diagram of a PLL using a switched loop ﬁlter for the acquisition of noisy signals. There is nevertheless a high probability that the PLL will lock spontaneously at some time. In the unlocked state of the PLL. and the spectrum of applications is very broad as well. In-lock-Detector Q (see Fig. To avoid repeated unlocking of the loop. Here. The control signal for the switched ﬁlter is also derived from an in-lock detector. noise suppression is of importance. 2. hence pull-in time is the most relevant parameter. This conﬁguration uses a loop ﬁlter whose bandwidth can be switched by a binary signal.

and z will vary in the range zmin < z < zmax. When N is variable. Consequently wn will vary in the range wn min < wn < wn max.1 to 2. etc.4. Table 2. 2.1–2. until the ﬁnal design appears acceptable. Manufacturers of PLL ICs have already provided design tools running on the PC. 74HC/HCT7046A. . We may start with some initial assumptions but end up perhaps with a design that is not acceptable. but the output frequency is variable.com) Copyright © 2004 The McGraw-Hill Companies. In this step the scaler ratio must be determined. As mentioned. natural frequency wn and damping factor z will vary with N. is used to design PLL systems using the popular integrated circuits 74HC/HCT4046A. When the PLL is used to build a frequency synthesizer..4. In the ﬁrst step. Downloaded from Digital Engineering Library @ McGraw-Hill (www. in many cases the design of a PLL will be an iterative process.2 presents the same information. the ratio of output to reference frequency is variable.Mixed-Signal PLLs 94 Chapter Two For these reasons it appears difﬁcult to give a design procedure that yields an optimum solution for every PLL system. A program distributed by Philips. 2. Tables 2.52 for example. Table 2. For these ranges we get approximately Step 2. as seen from the corresponding equations in Tables 2. All rights reserved.digitalengineeringlibrary. N = 1. lock range. In this section we present a PLL design prcedure that is based on a ﬂowchart.. which was originally introduced by RCA. because one or more key parameters (e. Any use is subject to the Terms of Use as given at the website.) The individual steps are described in the following. pull-in time) are outside the planned range. and 74HCT9046A. Both of these parameters will vary approximately with 1 / N . There are cases where both input frequency and output frequency are constant but not necessarily identical. Fig. Moreover. There are cases where the ratio of output to reference frequency is greater than 1 but remains ﬁxed. thus a range for N must be deﬁned (Nmin £ N £ Nmax). both input and output frequencies could be variable. all are based on the old industry standard CD4046 IC (from the 4000 CMOS series).49 should not be considered as a universal tool for the thousand and one uses of the PLL but rather as a series of design hints. Here no down-scaler is needed. Step 1. There are PLL applications where the output frequency f2 always equals the reference frequency f1.1 shows the equations for hold range. but for an EXOR phase detector. frequency synthesizers) the input frequency is always the same. Here.49.e. The step-by-step design procedure of Fig. a downscaler with constant divider ratio N is required. To help in computing the relevant entities in the PLL design. i.1.g. In other applications (e.. In such a situation we restart with altered premises and repeat the procedure. the input and output frequencies of the PLL must be speciﬁed. etc.. As a last variant. respectively.4. the often used formulas for the PLL key parameters are listed in four tables. (For details of PLL ICs refer to Table 10. for a PLL using a type 1 phase detector. most of the formulas used to design the PLL are listed in Tables 2.1 to 2. Let f1 min and f1 max be the minimum and maximum input frequencies and f2 min and f2 max the minimum and maximum output frequencies.g.

Mixed-Signal PLLs Mixed-Signal PLLs 95 START Step 1 Specify ranges of input and output frequencies (f1. All rights reserved. z TP Step 16 Step 11 Select type of loop filter Calculate loop filter parameters t1. t2 (Ka) Calculate t1 (or the sum t1 + t2) from max frequency step Dwo Determine dynamic properties of DPLL User specified DwPO Step 20 Calculate wn from DwPO. .49 Flowchart of the mixed-signal PLL design procedure. z Step 18 Calculate t2 from wn.com) Copyright © 2004 The McGraw-Hill Companies.digitalengineeringlibrary. Downloaded from Digital Engineering Library @ McGraw-Hill (www. Any use is subject to the Terms of Use as given at the website. f2) Step 2 Determine divider ratio (or range of N) Step 3 Determine damping factor z (or range of z) y Step 4 Noise suppression required n Step 5 y Missing edges in reference signal u1 n Step 6 Choose EXOR phase detector Calculate Kd Step 7 Choose JK-flipflop or PFD Calculate Kd Step 12 Choose PFD Calculate Kd Step 13 Step 8 Specify noise bandwidth BL Specify VCO characteristic Calculate KO Determine external components of VCO Step 9 Specify VCO characteristic Calculate KO Determine external components of VCO Step 14 Specify type of loop filter Step 15 Step 10 Calculate wn from BL. z Step 19 Calculate loop filter components END Figure 2. z TL Step 21 Calculate wn from TL Step 17 Estimate wn from t1 etc Step 22 Calculate t1 (or the sum t1 + t2) from wn.

and parameters such as noise bandwidth BL must not be considered. because the loop then would get oscillatory for the smallest and sluggish for the largest damping factor. the various digital phase detectors behave differently in the presence of noise.8.digitalengineeringlibrary.129) (For constant N. z varies by about a factor of 3.4.128) respectively. for example.7 for N = 32 would yield a minimum damping factor of zmin = 0.127) N max N min (2.5 and 1 is considered optimum. however. In this step the question must be answered whether the PLL should offer noise suppression or not. if N varies by a factor of 10. To ease the design in the case of variable N. which is a fair compromise. for example.g. As long as the ratio Nmax/Nmin is not too large.2.7. it is recommended to choose z = 0. 2. a damping factor between 0. Step 3. as explained in Sec. . noise can be discarded.6 Æ 32. Choosing z = 0. however. it is often mandatory to deﬁne more than one frequency range for the PLL and switch the range accordingly. For constant N. the PLL then has the Butterworth response. 1 to 100).) If Nmin = 10 and Nmax = 100. for example.Mixed-Signal PLLs 96 Chapter Two w n max = w n min and z max = z min N max N min (2. As we know. as explained in step 2. When N varies over a large range (e. If a digital frequency synthesizer has to be built. Determine the damping factor z.7 for N = Nmean. otherwise it continues at step 12. z remains constant too and can be chosen arbitrarily. which is given by the geometric mean of Nmax and Nmin. As discussed in Sec. Much larger variations of z. If noise must be suppressed.4. Noise must be suppressed by this PLL. Nmean would be 31. Nmean = N. edgesensitive phase detectors such as the JK-ﬂipﬂop or the PFD then can hang up in one particular state: the output of the JK-ﬂipﬂop will switch into the low Downloaded from Digital Engineering Library @ McGraw-Hill (www. N mean = N min N max (2. BL and related parameters must be taken into account. Step 4.com) Copyright © 2004 The McGraw-Hill Companies. the procedure continues at step 5. the variation of the damping factor can be accepted. of course. 2. Any use is subject to the Terms of Use as given at the website. however. If noise is of concern.4 and a maximum of zmax = 1.. we specify the parameters of the PLL such that z becomes optimum for a divider ratio Nmean. Step 5. it is optimum to select z = 0. All rights reserved.2. In a situation where edges of the reference (input) signal u1 can get lost. which can be tolerated. When N is constant. If N is variable. have to be avoided.

2. the PFD offers superior performance. When a bipolar power supply is used. All rights reserved. otherwise it continues at step 7. Step 6. so this type of phase detector is normally preferred.130) BL should be chosen such that (SNR)L becomes larger than some minimum value. The JK-ﬂipﬂop or the PFD can be chosen for the phase detector. inﬁnite pullin range. which reads BL = wn Ê 1 z+ ˆ 2 Ë 4z ¯ (2. Consequently. The procedure continues with step 8.130).3.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. will stay at 0 when edges of u1 are missing.19). Another option would be the multiplier phase detector.3. the noise bandwidth Bi at the input of the PLL must also be known. The average output signal ud of the EXOR phase detector.120). the detector gain must be taken from the data sheet of the corresponding device.1 should be used. Kd is given by Kd = UB/p. (2.131) Downloaded from Digital Engineering Library @ McGraw-Hill (www. which is certainly undesirable. We know from noise theory that BL is also related to wn and z by Eq. (2. and the output of the PFD will switch to the state -1 after a very short time. (2.digitalengineeringlibrary. When the EXOR is chosen and runs from a unipolar power supply.4. typically larger than 4 (which corresponds to 6 dB). BL can be calculated from Eq. Kd = UB/2p for the JK-ﬂipﬂop or Kd = UB/4p for the PFD (UB = supply voltage). The procedure continues at step 8. Bi is nothing other than the bandwidth of the signal source or the bandwidth of an optional preﬁlter. In case of the multiplier PD. The noise bandwidth BL must now be speciﬁed. or when the phase detector saturates at voltage levels that differ substantially from the power-supply rails.8. The EXOR phase detector (or the multiplier) should be selected. If edges of u1 are likely to get lost. where UB is the supply voltage. Step 8. When a unipolar power supply is used. As shown in Sec. because this detector is also level-sensitive and performs similarly to the EXOR. After (SNR)i and Bi are determined. Step 7. or when the EXOR saturates at levels which differ substantially from the power-supply rails. When a bipolar power supply is used. An additional problem arises when the scaler ratio N must be variable. 2. e. As explained in Sec.Mixed-Signal PLLs Mixed-Signal PLLs 97 state. .. the corresponding equation given in Sec. The phase detector gain Kd can now be determined. If (SNR)i is not known. however.g. 2. the procedure continues at step 6. use Eq.1. the frequency of the VCO will run away quickly. it must be estimated or eventually measured. BL is related to the signal-to-noise ratio of the loop (SNR)L by (SNR ) L = (SNR )i Bi 2 BL (2.17 Finally.

e. w2 w2max w0 w2min uf 0 Figure 2. Note that the useful voltage range is less than the supply voltage.131). the data sheet indicates the usable range of control voltage uf. respectively. we can calculate the range of output (angular) frequencies that must be generated by the VCO. The VCO is now designed such that it generates the output frequency w2 = w2 min for uf = uf min and the output frequency w2 = w2 max for uf = uf max. typically an integrated circuit. Usually the data sheets tell you how to calculate the values of these elements. we should check its values at the extremes of the scaler ratio N. Given the supply voltage(s) of the VCO. (2. In this step the characteristic of the VCO will be determined. using Eq..uf min Now the external components of the VCO can be determined also. All rights reserved. Step 9.w 2 min uf max .digitalengineeringlibrary.) Let uf min and uf max be the lower and upper limit of that range. Any use is subject to the Terms of Use as given at the website. . respectively. In such a case we specify BL for the case N = Nmean. both wn and z vary with N. hence BL also becomes dependent on N.50 ufmin UB / 2 ufmax UB Characteristic of the VCO. Downloaded from Digital Engineering Library @ McGraw-Hill (www. the VCO will be part of the PLL system.50. Now the VCO gain K0 is calculated from the slope of this curve.com) Copyright © 2004 The McGraw-Hill Companies. In most cases. The curve shows angular frequency w2 versus control voltage uf. i. K0 = w 2 max . as pointed out in step 2. (For a unipolar power supply with UB = 5 V this range is typically 1 to 4 V . 2. If BL becomes too small at one of the extremes of N. A suitable VCO must be selected ﬁrst. The corresponding VCO characteristic is plotted in Fig. To make sure that BL does not fall below the minimum acceptable value. the initial value assumed for N = Nmean should be increased correspondingly. Because the center frequency w0 (or the range of w0) is known and the range of the divider ratio N is also given. Let w2 min and w2 max be the minimum and maximum output frequencies of the VCO.Mixed-Signal PLLs 98 Chapter Two When the divider ratio N is variable.

Only values of Ka > 1 are reasonable. Kd. use the general formula given in Sec. EXOR. In most cases. Speciﬁcation of the loop ﬁlter. Given the supply voltage(s) of the VCO. respectively.) Let uf min and uf max be the lower and upper limit of that range. both BL and z have been determined for N = Nmean. if it is combined with a multiplier.uf min Downloaded from Digital Engineering Library @ McGraw-Hill (www.3. the active PI loop ﬁlter should be selected. When the PFD runs from a unipolar power supply with supply voltage UB. Typically. Let w2 min and w2 max be the minimum and maximum output frequencies of the VCO. All rights reserved. Ka is in the range from 2 to 10.w 2 min uf max .1.1 to 2. The appropriate type of loop ﬁlter must be chosen ﬁrst. Calculate the natural frequency wn. . In this step the characteristic of the VCO will be determined (refer also to Fig. Given wn. When a bipolar power supply is used or when the logic levels differ substantially from the voltages of the supply rails. 2.4 are used to calculate the two time constants t1 and t2. the data sheet indicates the usable range of control voltage uf. (For a unipolar power supply with UB = 5 V this range is typically 1 to 4 V . Step 12. The passive lead-lag loop ﬁlter is the simplest. wn can be calculated from BL = wn Ê 1 z+ ˆ 2 Ë 4z ¯ When the divider ratio N is variable. The VCO is now designed such that it generates the output frequency w2 = w2 min for uf = uf min and the output frequency w2 = w2 max for uf = uf max. thus the value obtained for wn is valid only for N = Nmean (see the notes in step 2).. If “inﬁnite pull-in range” is desired. its detector gain Kd is given by Kd = UB/4p. however.50). or JK-ﬂipﬂop phase detector.Mixed-Signal PLLs Mixed-Signal PLLs 99 Step 10. i. of course. respectively.e. Because noise at the reference input can be discarded. and N. the best choice for the phase detector is the PFD. the VCO will be part of the PLL system. K0. The design proceeds with step 19. z.digitalengineeringlibrary. a suitable value for Ka must be chosen in addition. Step 11. the equations for wn and z in Tables 2. Given noise bandwidth BL and damping factor z. When the active lead-lag ﬁlter is used.com) Copyright © 2004 The McGraw-Hill Companies. Step 13. A suitable VCO must be selected ﬁrst. the pull-in range becomes limited. K0 = w 2 max . 2.50. 2. typically an integrated circuit. Any use is subject to the Terms of Use as given at the website. we can calculate the range of output (angular) frequencies that must be generated by the VCO. Because the center frequency w0 (or the range of w0) is known and the range of the divider ratio N is also given. (Continued from step 4). respectively. Now the VCO gain K0 is calculated from the slope of this curve. The corresponding VCO characteristic is plotted in Fig.

Speciﬁcation of dynamic properties strongly depends on the intended use of the PLL system.e. The user then would probably specify a maximum value for the pull-in time TP the system needs to lock onto the new output frequency. Any use is subject to the Terms of Use as given at the website. Given the maximum pull-in time TP allowed for the greatest frequency step at the output of the VCO. Because the PFD is used as phase detector. If the third case is chosen.2. the design proceeds with step 21. where N is variable. e. or the like. Other types of loop ﬁlters do not bring signiﬁcant beneﬁts. the PLL is also used as a digital frequency synthesizer. This combination of phase detector and loop ﬁlter offers inﬁnite pull-in range and hold range. If the difference |f21 . the procedure continues at step 16. on a variation of the divider factor N. the time constant t1 (or the sum of both time constants t1 + t2) of the loop ﬁlter is calculated using the formula for TP given in Tables 2. the PLL will probably lock out when switching from one frequency to the other..g.” i. The third case of this decision step represents the more general situation where neither the pull-in time nor the pull-out range is of primary interest. TP is then used to determine the remaining parameters of the PLL. i. if f2 changes from N0 fref to (N0 + 1) fref.4.Mixed-Signal PLLs 100 Chapter Two Now the external components of the VCO can be determined also. the frequency at the output of the VCO is given by f2 = N fref. Here the user must resort to a speciﬁcation that makes as much sense as possible. this design step is a decision block having three outputs. we can determine Downloaded from Digital Engineering Library @ McGraw-Hill (www. it is desired that the PLL does not lock out if the output frequency changes from one frequency “channel” to an adjacent “channel..e. This synthesizer will generate integer multiples of a reference frequency fref. Probably the simplest way to develop such a speciﬁcation is to make an assumption on the lock-in time TL (also referred to as settling time) or even to specify the natural frequency immediately.1 to 2. Step 15.digitalengineeringlibrary. Specify the type of loop ﬁlter. the procedure continues at step 20. .6.e. on frequency steps applied to the reference input. we must have an idea of how the PLL should react on dynamic events. If the user decides to use DwPO as a key parameter. as explained in “Pull-in Range DwP and Pull-in Time TP” in Sec. In many synthesizer applications. When the loop ﬁlter is a passive lead-lag. 2. the PLL is used as a digital frequency synthesizer. In the ﬁrst case. In the second case. there are (at least) three different ways of specifying dynamic performance of the PLL.com) Copyright © 2004 The McGraw-Hill Companies. To select an appropriate value for the natural frequency wn. i. All rights reserved. Step 14. If the user decides to specify TP as a key parameter.. Usually the data sheets tell you how to calculate the values of these elements. Here it could be desirable that the PLL switches very quickly from one output frequency f21 to another output frequency f22. the passive lead-lag ﬁlter will be used in most cases. Determine the dynamic properties of the PLL. In this case. Step 16.. Because different goals can be envisaged. the pull-out range DwPO is required to be less than fref.f22| is large.

Step 22. and ﬁnally we would compute R2 from t2 = R2C2.4.. strange things may happen at this point: we perhaps obtained t1 + t2 = 300 ms in a previous step and computed t2 = 400 ms right now! To realize the intended system.4 is used to calculate the natural frequency wn. The design proceeds with step 18. In that case.4. If the passive lead-lag ﬁlter is chosen. Any use is subject to the Terms of Use as given at the website.1 to 2. C can be chosen arbitrarily. which increases t1 + t2. The design proceeds with step 18. the time constant t1 can be calculated by using the formula for wn in Tables 2.1 to 2. When the loop ﬁlter is a passive lead-lag.4. the natural frequency wn is calculated from the formula for TL in Tables 2. The procedure continues with step 22. we computed the sum t1 + t2 in step 16. Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies.4. Given t1 and t2 (plus eventually Ka). we would have to choose t1 = -100 ms. Whenever we meet that situation. As with the passive leadlag ﬁlter. it should be speciﬁed such that we get “reasonable” values for R1 and R2. Here we should ﬁrst specify C1 so as to get a reasonable value for R1. however. For the active PI ﬁlter. the components of the loop ﬁlter can be determined. For Dw0 the maximum (angular) frequency step at the VCO output must be entered. When the sum t1 + t2 has been computed in step 16. When a passive lead-lag ﬁlter is used. The design proceeds with step 17. t1 was computed in step 16. we would ﬁrst select C to get reasonable values for R1 and R2. only the sum t1 + t2 can be computed from the formula for wn. All rights reserved. the ﬁnal value for t1 will be known after t2 has been calculated in step 18. Given the lock-in time TL. For the other loop ﬁlter types. The design proceeds with step 22. for example. or if we specify a lower z. . the system cannot be realized with the desired goals (i.. Step 19. which is impossible.1 to 2. t1 can be computed directly. Hence we can calculate wn immediately from the corresponding equation in Tables 2.e. Step 18. When the passive lead-lag ﬁlter is used. we have R1C = t1 and R2C = t2.digitalengineeringlibrary.Mixed-Signal PLLs Mixed-Signal PLLs 101 only the sum t1 + t2. Given pull-out range DwPO and damping factor z.1 to 2. with the desired values for wn and/or z). when the loop ﬁlter is either an active lead-lag or a PI ﬁlter. Step 17. which decreases t2. and t2 = R2C2. Given wn. For the other types of loop ﬁlters. the formula for DwPO given in Tables 2. t1 = R1C1. now the time constant t2 has to be calculated by using the formula for z given in Tables 2.4.e. i. Given wn and z. we have R1C = t1 and R2C = t2.1 to 2.1 to 2. in the range of kilohms to megohms. wn can be computed now by using the appropriate equation in Tables 2. t1 can now be determined. Step 21. Then we would compute C2 from Ka = C1/C2. For the active lead-lag ﬁlter. we have Ka = C1/C2. It only becomes realizable if we choose a lower wn. Step 20.

3). e. the digital signal is directly sent over the link. an arbitrary sequence of 0s and 1s. and phase (PM) modulation are used here. Some more special parameters are not at all taken into account. This simplest data format is sketched in the ﬁrst row of Fig. respectively. There are basically two different principles of transmitting digital data. it would seem obvious to transmit the signal such that the 1s are represented as a “high” voltage level and the 0s as a “low” voltage level. 9. or it is even possible to combine different modulation techniques. The data bits are headed by a start Downloaded from Digital Engineering Library @ McGraw-Hill (www. only one single character (an ASCII character in most cases) is transmitted in one message. 3. frequency (FM).10.e.. 2. In baseband transmission. An overview of these digital modulation schemes is given in Chap.com) Copyright © 2004 The McGraw-Hill Companies.4. RS-422. however. it would be premature to consider it universal. namely.51 and is referred to as NRZ code (NRZ = non return to zero). the data are clocked. In any case. 2.e. We have to consider such effects when discussing the most important PLL applications. First of all. Amplitude (AM). the digital signal is ﬁrst modulated onto a carrier.28 As we will immediately see. For this reason PLL frequency synthesizers will be discussed in a separate chapter (Chap. such as spectral purity of the output signal of frequency synthesizers and related quantities. 5 V and 0 V . In this section we deal only with baseband systems. hence the bandwidth of carrier systems can be much larger than the bandwidth of baseband systems.digitalengineeringlibrary. this is the most commonly used code in asynchronous communications. 2.Mixed-Signal PLLs 102 Chapter Two Though the design procedure seems quite complex. In this section we are going to consider some other typical PLL applications. Thus the receiver is forced to extract the clock information out of the received signal. has to be transmitted over a serial link. baseband and carrier-based transmission. such as AM + PM. Digital data can be transmitted over serial or parallel data channels. when a carrier system is used. usually a highfrequency signal. A practical design example that makes use of the design procedure will be presented in Sec. Any use is subject to the Terms of Use as given at the website. which is normally not transmitted. the familiar RS-232. In effect. using. they are sent in synchronism with a clock signal. In asynchronous communication.g.10 Mixed-Signal PLL Applications One of the most important applications of the mixed-signal PLL is frequency synthesis.1 Retiming and clock signal recovery The PLL is used in almost every digital communication link. a number of digital signals can be modulated onto different carriers. In the design of PLL frequency synthesizers we are confronted with a number of problems that are speciﬁc for that topic. . for example. All rights reserved.. or RS-485 standard.20 In carrier systems. i. Such a character mostly consists of a series of 8 data bits. i.. Let us assume that a digital signal. this problem is more serious than would be expected at ﬁrst glance.

but the stop bit is always high. All rights reserved. a stop bit is transmitted after the data bits.51 Review of the most commonly used binary and pseudo-ternary formats. bit.digitalengineeringlibrary. . The start bit is always a low level.Mixed-Signal PLLs Mixed-Signal PLLs 103 FORMAT 1 0 Bit cell INFORMATION 1 1 0 0 1 0 DEFINITION NRZ-Level 1 = High. but with definitions inverted 1 = Transition in the center of a bit cell 0 after 1 = no transition 0 after 0 = Transition at the beginning of a bit cell 0 = Transition in the center 1 after 0 = no transition 1 after 1 = Transition at the beginning Bi-Phase-Space Delay-ModulationMark Delay-ModulationSpace Figure 2. 0 = Low NRZ-Mark 1 = Transition at the beginning of a bit cell 0 = no transition NRZ-Space 0 = Transition at the beginning of a bit cell 1 = no transition 1 = High – Low 0 = no transition RZ Bi-Phase-Level 1 = High – Low 0 = Low – High Bi-Phase-Mark 1 = Transition at the beginning and in the center of a bit cell 0 = Transition only at beginning of a bit cell As By-phase-Mark.com) Copyright © 2004 The McGraw-Hill Companies. The data bits can be high or low. and eventually a parity bit is used to enable the receiver to detect single-bit errors. The voltage level on the transmission line is usually high when no data are transmitted. Any use is subject to the Terms of Use as given at the website. This ensures that every message starts with a high-to-low transition of Downloaded from Digital Engineering Library @ McGraw-Hill (www.

Mixed-Signal PLLs 104 Chapter Two the data signal. Any use is subject to the Terms of Use as given at the website. From this discussion it becomes evident that the methods of extracting clock information must depend on the particular code used. for the positive transitions of the VCO output signal can be used to strobe the data signal. the NRZ-mark code readily fails when a long sequence of 0s is sent. as seen from the waveforms in Fig. which combines the advantages of the biphase and NRZ codes. 1000. the NRZ-mark code produces a level transition whenever a 1 is transmitted. a transition at the start of the next bit cell is generated. (A bit cell is the time interval in which one bit is transmitted. no clocking information would be available during that interval. 2. the VCO generates a square wave signal u*. as shown in Fig.52. the receiver will not be able to decide whether 999. z which is in quadrature to the demodulated data signal. called the delay-modulation code. or 1001 ones have been sent. Let us have a look at the most important recovery techniques. If another 0 follows the ﬁrst 0. The corresponding block diagram is shown in Fig. no transition takes place in the next bit cell. Let us start with recovering the clock signal for the RZ format (Fig. 2. . 2. the same problem occurs with the NRZ-space code when a series of 1s are transmitted. the VCO continues to oscillate at its instantaneous frequency. Clock signal recovery is accomplished by one PLL.52. a transition in the center of a bit cell is generated on the transmission of a 1.51. On the other hand. If the clock generator within the data receiver drifts only slightly away. a number of other codes have been devised. The situation becomes more serious.52.com) Copyright © 2004 The McGraw-Hill Companies. the NRZ-space code generates an edge on the transmission of a 0. Extended sequences of 0s have to be Downloaded from Digital Engineering Library @ McGraw-Hill (www. If the NRZ code were used and say 1000 ones were transmitted in succession. so the receiver knows exactly when the transmission of a character starts.51). A better choice is the biphase-level code.digitalengineeringlibrary. To start with the simplest.20 There is another code. This code shows at least one edge in every bit cell. All rights reserved. As is easily seen. If an EXOR PD is used. 2. The RZ code (return to zero) generates a sequence of “high-low” whenever a 1 is transmitted. In the delay-modulation-mark code. The center frequency of this PLL is chosen to be approximately equal to the baud rate of the data signal. as shown in Fig. The PLL is synchronized by the transitions of the demodulated data signal. To provide more clocking information. when not a few but hundreds or thousands of bits have to be transmitted in succession.) Because clock recovery is very simple with this code. This phase relationship is advantageous. The bandwidth of this code is almost the same as for the NRZ code. the biphase code is the most often used in high-speed data communications. which produces a sequence high-low for a 1 and a sequence low-high for a 0. A drawback of this code is in the fact that the required bandwidth to transmit a given number of bits per second is twice the bandwidth of the NRZ code. This code is prone to failure if long sequences of 0s occur in the data stream. If a 0 follows a 1. however. During a succession of logic 0s. however. Synchronization of the clock-recovery PLL takes place on every logic 1 contained in the data signal. 2.

2. . Many analogdifferentiator and absolute-value circuits have been developed. Then.digitalengineeringlibrary. The choice of odd parity then ensures that in every sequence of 9 bits there is at least 1 bit that is not a 0. avoided since the frequency of the VCO could drift away to the extent that synchronization gets lost. Hence it can be used to synchronize a PLL. a situation that is identical to a long sequence of 0s in the case of the RZ code.20 One method of extracting the clock frequency from the NRZ signal is shown in Fig.com) Copyright © 2004 The McGraw-Hill Companies. the rectiﬁed signal contains a frequency component synchronous with the clock. including the parity bit. 2. but clock-signal recovery is slightly more difﬁcult because the frequency spectrum of the NRZ does not necessarily contain a spectral line at the clock frequency. In the case of the RZ code. The demodulated NRZ signal u* z is ﬁrst differentiated.34 As seen in the waveforms in Fig. When odd parity is chosen. All rights reserved. During the pause no signal is transmitted. this is done by a ﬁxed preamble that precedes every message. both operations can be performed alternatively by one single digital circuit. In parity checking an additional bit of information is added to each group of. eight successive data bits. One problem still needs attention: the problem of initialization. say. Downloaded from Digital Engineering Library @ McGraw-Hill (www. synchronization is likely to be lost.52 Operating principle for clock recovery in the RZ format.Mixed-Signal PLLs Mixed-Signal PLLs 105 Demodulated Signal uZ* PD PLL LF VCO Clock Signal uT 1 uZ (t) 0 1 1 0 0 0 1 uT (t) Figure 2.1. Any use is subject to the Terms of Use as given at the website. a typical preamble consists of a series of 1s.20.53.53. Synchronization must be reestablished. Every message is ﬁnished and a pause will follow the message. The NRZ format needs about half that bandwidth. the output signal of its VCO is the recovered clock signal uT. When a new message is started. must be odd. the total number of 1s. the differentiated signal udiff is rectiﬁed by an absolute-value circuit. As stated earlier. Longer sequences of 0s are avoided if parity checking is used. the major drawback of the RZ format is the large bandwidth required.

27 The waveforms produced by this device are depicted in Fig. Downloaded from Digital Engineering Library @ McGraw-Hill (www.51.digitalengineeringlibrary. As in the circuits in Figs.com) Copyright © 2004 The McGraw-Hill Companies. 2. Figure 2.53.55.54 The function of an analog differentiator followed by an absolute-value circuit can be alternatively performed by a digital edge detector.Mixed-Signal PLLs 106 Chapter Two Demodulated * NRZ Signal uz d dt udiff Absolute value * udiff PD LF 1 0 0 1 1 1 0 1 0 0 VCO Clock Signal uT udiff * udiff uT Figure 2. If this condition is not met. a Schmitt trigger must be used to clean up the transition. All rights reserved.56. the demodulated signal u* z can be used here to synchronize a PLL operating at twice the clock frequency.54 shows a so-called edge-detector circuit.52 and 2. 2. If the biphase or the delay-modulation format is utilized. as pointed out in Fig. Any use is subject to the Terms of Use as given at the website. 2. 2. the demodulated data signal u* z can have transitions at the beginning and in the center of a bit cell. uz udiff uz udiff Figure 2.53 Operating principle for clock recovery in the NRZ format. A circuit recovering the clock signal for the delaymodulation (DM) format is shown in Fig. in which propagation delays of gates are used to produce a pulse on each transition of the input signal. The rise and fall times of the input signal must be shorter than the cumulative propagation delay of the four cascaded inverters. .

All ﬂipﬂops are triggered onto the negative-going edge of the clock signal C. inputs A1 and A2 trigger on the negative-going edge. 107 . Inputs A1 and A2 are unused here. All rights reserved. Input B of the monostable multivibrator triggers on the positive-going edge.Transition Detector ufl PD LF PLL (2f ) uz* 2f VCO ¢¢ J C K R Q K R Q K R Q FF C FF Q Z1 J Q Z3 1¢¢ 101-Detector Z 2 J Q FF C 1¢¢ ¢¢ J C K Scaler ÷ 2 Q FF R Q uT Mixed-Signal PLLs Reset B A1 A2 Monostable Q Q Multivibrator Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary. Any use is subject to the Terms of Use as given at the website.com) Copyright © 2004 The McGraw-Hill Companies. Figure 2.55 Circuit for clock signal recovery with the DM (delay modulation) format.

2.5. its content never exceeds 4. This would result in a faulty interpretation of the received data.55.55 is used for this purpose. it is necessary initially to reset the JK-ﬂipﬂop at the right time. An interval longer than 2 periods is impossible.55) is used to count the (negative) transitions of the signal 2f.56.56. . All rights reserved. We can see from Fig. or 2 periods of a bit cell. which takes corrective action. The output signal of the VCO (2f ) is scaled down in frequency by a factor of 2.56). 2. If a threestage binary UP counter (labeled as the 101 detector in Fig. For clarity assume that the recovered clock signal uT really has the wrong phase at the beginning. 2. An additional circuit is needed.com) Copyright © 2004 The McGraw-Hill Companies. The time interval between any two consecutive pulses of uf 1 is not constant. Consider again the signal uf 1 in Fig. 2. 2. The clock signal uT is now deﬁned to be low in the ﬁrst half of every bit cell and high in the second half. Any use is subject to the Terms of Use as given at the website. Moreover. as shown in Fig. 1. An edge-detector circuit produces a short positive pulse uf1 on every transition (positive and negative) of the demodulated signal u*. 2.55 that the circuit could also settle at the opposite phase (uT being high in the ﬁrst half of the bit cells). z The signal uf1 is used to synchronize a PLL that operates at twice the clock frequency 2f (Fig. 2. To establish the correct phase of the recovered clock signal. the right-most JK-ﬂipﬂop of Fig.Mixed-Signal PLLs 108 Chapter Two 1 uz* uf1 2f Z1 Z2 Z3 Contents 67 0 1 of the Counter Reset uT 0 1 0 1 1 0 0 2 3 4 0 1 2 3 4 0 1 20 1 2 30 1 2 wrong phase Figure 2. because the start and the center of every bit cell are erroneously exchanged.56 correct phase Waveforms of the circuit of Fig. as we can clearly see in Downloaded from Digital Engineering Library @ McGraw-Hill (www. but can show the values of 1.digitalengineeringlibrary. and if this counter is reset by every uf 1 pulse.

Downloaded from Digital Engineering Library @ McGraw-Hill (www. Any use is subject to the Terms of Use as given at the website. 2. 2. a preamble of the form 101 . the PLL is the key element in each of the applications. To enable the corrective action. As seen from the three examples discussed. 2. Other sources of errors are nonlinearities of the tachometer and drift of the servo ampliﬁer. The setpoint for the motor speed is given by the signal u1. as shown in Fig.58. 2. its output signal u2 is proportional to the motor speed n.57. . to drive the motor.56. should precede every message. a nonzero error must exist. 2.58 is the block diagram of a PLL-based motor-speed control system.Mixed-Signal PLLs Mixed-Signal PLLs 109 Fig. The advantages offered by the PLL technique become evident if the PLL motorspeed controls are ﬁrst compared with conventional motor-speed controls. 2. never in the second half.com) Copyright © 2004 The McGraw-Hill Companies. The optocoupler is usually fabricated from a light-emitting diode (LED) and a silicon phototransistor.59. . The gain of the servo ampliﬁer is usually high but ﬁnite. The PLL technique offers a much more elegant solution. the Setpoint (Shaft Speed) u1 Servo Amplifier Motor Measured Shaft Speed u2~n Tacho Generator Figure 2. the content of 4 can be obtained only in the ﬁrst half of a bit cell. A further drawback is the relatively high cost of the tachometer itself. As shown by the waveforms. The tachometer signal is generated by a fork-shaped optocoupler in which the light beam is chopped by a sector disk. Figure 2. a monostable multivibrator (single-shot) is triggered. The shaft speed of the motor is measured with a tachometer. the detailed circuit is shown in Fig. The entire control system is just a PLL in which the VCO is replaced by a combination of a motor and optical tachometer. Whenever the 3-bit counter reaches 4.57 Block diagram of a conventional motor-speed control system.2 Motor-speed control Very precise motor-speed controls at low cost are possible with the PLL.55. the phase of the recovered clock is set to its correct state. A classical scheme for motor-speed control is sketched in Fig. .digitalengineeringlibrary. This resets the JK-ﬂipﬂop. This fact is used to properly reset the divide-by-2 ﬂipﬂop in Fig. All rights reserved. In order to obtain a clean square wave output. Any deviation of the actual speed from the setpoint is ampliﬁed by the servo ampliﬁer whose output stage drives the motor.10. It is no major problem to conceive clock-recovering circuits for other formats.

the transfer functions of all blocks in Fig. q2 Frequency u sensitive PD d (Type 4) Loop Filter Power Amplifier uf Number of Segments = Kz Measured Shaft Speed Optocoupler (Ga As) corresponds to VCO Figure 2. If the motor is excited by a voltage step of amplitude uf.T ¯ ˚ ˙ Î m Downloaded from Digital Engineering Library @ McGraw-Hill (www. Any use is subject to the Terms of Use as given at the website. q1 w2. 2. its angular speed w(t) will be given by Ê t ˆ˘ w(t) = K muf È Í1 .com) Copyright © 2004 The McGraw-Hill Companies. To enable locking at every initial condition. the PFD is used as phase detector. 2. but the transfer function of the motor-tachometer combination still must be determined.Mixed-Signal PLLs 110 Chapter Two Setpoint (Shaft Speed) w1. All rights reserved.digitalengineeringlibrary. The signal generated by the optocoupler has a frequency proportional to the speed of the motor.132) . +5V 74HC14 f2 Figure 2.58.58 must be known. (2. Because the phase detector compares not only the frequencies w1 and w2 of the reference and the tachometer signals but also their phases. the system settles at zero velocity error.59 Circuit of the optical tachometer generator shown in Fig. The transfer functions of the PD and of the loop ﬁlter are known. phototransistor stage is normally followed by a Schmitt trigger. To analyze the stability of the system. such as a 74HC/HCT14-type CMOS device.58 Block diagram of a motor-speed control system based on PLL techniques.expË .

we get for its Laplace transform F(s) the expression F(s) = U f (s) Km s(1 + sTm ) (2.60.133) The phase angle w of the motor is the time integral of the angular speed w. q2 uf uf M w. 2. Consequently we obtain for Q2(s) Q 2 (s) = KmKZ U f (s) s(1 + sTm ) (2. Any use is subject to the Terms of Use as given at the website. Applying the Laplace transform to Eq.and the motor a second-order system.Mixed-Signal PLLs Mixed-Signal PLLs 111 where Km is the proportional gain and Tm is the mechanical time constant of the motor. Equation (2. 2.60 The step response of an ordinary VCO compared with that of a motor. (2.com) Copyright © 2004 The McGraw-Hill Companies.132) indicates that w will settle at a value proportional to uf after some time. j t w2 w2 t w (t) = Kmuf (1 – e–t/Tm) t W2 (s) = KoUf (s) KoUf (s) s W (s) = Tm KmUf (s) 1+sTm t Q2 (s) = F (s) = KmUf (s) s (1+sTm) Figure 2. Note that the VCO is a ﬁrst.digitalengineeringlibrary.136) uf uf VCO w2. This implies that the phase of the tachometer signal is equal to phase f multiplied by KZ.58 has KZ teeth. All rights reserved.135) The transfer function Hm(s) of the motor is therefore given by H m (s) = KmKZ s(1 + sTm ) (2. Downloaded from Digital Engineering Library @ McGraw-Hill (www.134) The sector disk shown in Fig.132) yields W(s) = U f (s) Km 1 + sTm (2. . The step response of the motor is plotted on the right in Fig. Therefore.

more practical methods are preferred.62. 2. Any use is subject to the Terms of Use as given at the website. In this system the transfer function of the forward path is deﬁned by G(s). The closed system has three poles. From Fig.58. It is possible to calculate the hitherto unspeciﬁed parameters by purely mathematical methods. The remaining parameters (Ka and t2) then have to be chosen for best dynamic performance and maximum stability of the system. In Fig. . Therefore. whereas the transfer function of the feedback network (motor) is given by H(s). amplitude and phase response of the open-loop gain of the system are plotted. The motor-speed control system of Fig.61).digitalengineeringlibrary. a result which yields the simpler block diagram of Fig. 2. Downloaded from Digital Engineering Library @ McGraw-Hill (www. The mathematical model of the control system can now be plotted (Fig. There are many ways to solve this problem.34)] was a ﬁrst-order system only. whereas the VCO [according to Eq. we optimize PLL performance by the Bode diagram. The active PI ﬁlter is chosen here for the loop ﬁlter.61 Mathematical model of the motor-speed control system of Fig. otherwise the phase of the closed-loop transfer function would exceed 180° at higher frequencies and the system would become unstable.3 In the Bode diagram.61 can be combined into fewer blocks. 2. (2.137) PD Q1 (s) Kd Ud (s) LF 1+st2 st1 Servo Amplifier U (s) f Ka Q2 (s) Motor KmKz s(1+sTm) Figure 2. 2. 2.58 is therefore a third-order system. All rights reserved.Mixed-Signal PLLs 112 Chapter Two The motor is evidently a second-order system. 2. The individual blocks in Fig. 2.60 the transient response of the motor is compared with that of an ordinary VCO. such as the motor parameters Km and Tm or the number of teeth KZ of the sector disk. the open-loop gain G0(s) is given by G0 (s) = G(s) H (s) = K 1 + st 2 s2 (1 + sTm ) (2.63. however. some parameters are initially given. To use the simplest one.com) Copyright © 2004 The McGraw-Hill Companies. The servo ampliﬁer is supposed to be a zero-order gain block with proportional gain Ka. a ﬁlter with a zero must be speciﬁed for the loop ﬁlter. The poles of this ampliﬁer normally can be neglected because they are at much higher frequencies than the poles of the motor. In control engineering. When a motor-speed control system is designed practically.

2. Magnitude plot 100 magnitude [db] 50 0 –50 10–1 –120 phase [deg] –140 –160 –180 10–1 Figure 2. where K contains the gain factors of the individual blocks. K= KdKa KmK Z t1 (2.63 100 101 angular frequency [s^–1] Phase plot 102 100 101 angular frequency [s^–1] 102 Bode diagram for the open-loop gain of the motor-speed control system according to Fig. number of teeth KZ. .com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website.Mixed-Signal PLLs Mixed-Signal PLLs 113 Q1 (s) Q2 (s) G(s) = KaKd 1+ st2 st1 Uf (s) H (s) = KmKz s(1+sTm) Figure 2. All rights reserved.58. The remaining parameters Ka Downloaded from Digital Engineering Library @ McGraw-Hill (www. phase detector gain Kd.digitalengineeringlibrary. and motor time constant Tm are given.138) In a practical design. motor gain Km.62 Condensed mathematical model of the motor-speed control system.

2. which is sufﬁcient for good transient response. A value of K = 50 was required to attain this goal.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. Therefore. We assume here that Tm = 0. and the phase margin is about 40°.25 Looking at Eq. All rights reserved. say. . The zero of the transfer function must be placed such that the phase stays well below 180° at the frequency where the magnitude curve goes through the 0-dB line.digitalengineeringlibrary.Mixed-Signal PLLs 114 Chapter Two (ampliﬁer gain) and the two time constants t1 and t2 can be chosen freely. so at higher frequencies the phase would approach 270°. This causes the phase curve to increase from -180° toward -90°. we require a phase margin3 of at least 30°. by a factor of 10.5 s. as is seen from the phase plot. t2 is tentatively set to 0. The magnitude curve starts with -40 dB/decade at low frequencies.. Using the Control System Toolbox. We conclude that the break frequency of the zero term (1 + st2) must be well below the break frequency 1/Tm. (2. the slope will become -60 dB/decade. the slope of the magnitude curve becomes -40 dB/decade again. due to the term s2 in the denominator. Downloaded from Digital Engineering Library @ McGraw-Hill (www. the ampliﬁer gain Ka and the remaining time constant t1 can be speciﬁed as soon as the number of teeth KZ is given. Above angular frequency wm = 1/Tm. The transfer function zero at w = 1/t2 = 2 s-1 causes the slope to change to -20 dB/decade. The magnitude crosses the 0-dB line at about w = 20 s-1.e. we see that the magnitude response will start with a slope of -40 dB/decade at low frequencies. At the break frequency w = 1/Tm = 20 s-1.137).63. i. if there were no zero in the transfer function. we vary the overall gain such that the magnitude is just 0 dB at the break frequency w = 1/Tm. The resulting Bode diagram is shown in Fig. the magnitude curve bends up.05 s Km = 1 We use MathWorks Control System Toolbox26 to plot and optimize the Bode diagram of our control system. To get acceptable stability of the loop. Knowing total gain K.

In military communications it turned out that such constant-carrier-frequency links could easily be corrupted by “jammers.49 115 Downloaded from Digital Engineering Library @ McGraw-Hill (www. mainly in spreadspectrum applications. Whereas fractional-N synthesizers have been considered rather exotic in the past. The receiver. this novel device is able to create frequencies that are N.. within about 100 ms. Each individual carrier frequency is called a “chip” in the frequency hopping vocabulatory. Conventional communications used one single carrier whose frequency was ﬁxed. Any use is subject to the Terms of Use as given at the website. . Frequency hopping has gained increased importance in civil communications.digitalengineeringlibrary. This means that the transmitter repeatedly jumps through these N carrier frequencies.1 Synthesizers in Wireless and RF Applications PLL frequency synthesizers play an ever-increasing role in the ﬁeld of communications. Later the fractionalN synthesizer was developed. In contrast to the integer-N frequency synthesizer. This implies that the receiver must be able to switch the carrier frequency very fast. i. All rights reserved. and the like. has to track the carrier frequency at any time. The duration of such a chip is usually in the order of several hundred microseconds.” In frequency hopping applications. Such synthesizers (referred to as integer-N frequency synthesizers) are found in every FM radio receiver. the single carrier is replaced by a large set of carrier frequencies.e. TV receiver. since it is used in the newer generations of mobile phones. Originally. they suddenly have gained increased interest.”20 This led to the development of “frequency hopping. Radio and TV transmitters are examples for this category. which must know the carrier frequency sequence of course. where N is the integer part and f the fractional part of an arbitrary number.Source: Phase-Locked Loops Chapter 3 3 PLL Frequency Synthesizers 3. This set consists of a number N of carrier frequencies that are switched in a pseudo-random manner. It will be demonstrated in the next section that fractional-N synthesizers can switch their output frequency more rapidly than conventional integerN synthesizers.com) Copyright © 2004 The McGraw-Hill Companies.f times a reference frequency. the frequency synthesizer was a system creating a set of frequencies that were an integer multiple of a mostly ﬁxed reference frequency.

If a channel spacing of 10 kHz is desired. CB transceivers. the VCO creates an output frequency given by f2 = f1 PD Divider ∏ N LF VCO N fosc = Nf1 R Nf1 (3. 3. When the scaling factor of the reference divider is denoted R and the scaling factor of the other divider N. or even 1 kHz. All rights reserved.2 PLL Synthesizer Fundamentals This section is subdivided into two subsections: Integer-N frequency synthesizers Fractional-N frequency synthesizers Fractional-N synthesizers are based on the simpler integer-N synthesizers. a reference frequency of 10 kHz is normally chosen. In these applications there is a need for generating a great number of frequencies with a narrow spacing of 50. 2. 3.digitalengineeringlibrary. 10.com) Copyright © 2004 The McGraw-Hill Companies. In Fig.2. and to scale it down to the desired reference frequency. 25. Any use is subject to the Terms of Use as given at the website. where it is shown that the scaling factor N is usually set by an external digital signal. but include a number of additional circuits.1.1. in many frequency synthesizers this signal can also be serial.1) Scale factor N Figure 3. It is therefore more convenient to generate a higher frequency.1 Integer-N frequency synthesizers A very simple frequency synthesizer has already been shown in Fig. as shown in Fig. Frequency synthesizers are found in FM receivers. Most oscillators are quartz-crystal-stabilized. Hence we start the discussion with the integer-N systems. 3. television receivers. . and the like. 3. In this drawing the reference frequency is denoted f1.PLL Frequency Synthesizers 116 Chapter Three 3. typically in the region of 5 to 10 MHz. In most of the frequency-synthesizer ICs presently available. In this simple arrangement the VCO creates an output frequency f2 which is simply Nf1. a reference divider is integrated on the chip. A quartz crystal oscillating in the kilohertz region is quite a bulky component. The oscillator circuitry is also included on most of these ICs. Downloaded from Digital Engineering Library @ McGraw-Hill (www. 5.1 Basic frequency synthesizer system.2.1 this control signal has been plotted as a parallel digital input. This circuit is redrawn in Fig.

3. Because of its low power consumption.com) Copyright © 2004 The McGraw-Hill Companies. To generate higher frequencies. Osc. 3.3 Frequency synthesizer extends the upper frequency range by using an additional high-speed prescaler.PLL Frequency Synthesizers PLL Frequency Synthesizers 117 f-Synthesizer . Such prescalers extend the range of frequencies into the microwave frequency bands.2 System equal in performance to Fig. GaAs (gallium arsenide). All rights reserved.digitalengineeringlibrary. The channel spacing is increased to Vf1. normally a quartz oscillator. One seeks to include as many functions on the chip as possible. Any use is subject to the Terms of Use as given at the website. where fosc is the frequency of the oscillator. and so on.1 but with an additional reference divider that makes it possible to use a higher-frequency reference.2.3). the output frequency of the synthesizer becomes fout = NVf1 Downloaded from Digital Engineering Library @ McGraw-Hill (www. CMOS is the preferred technology today. . prescalers are used. 3.IC Osc. these are built with other IC technologies such as ECL. Reference divider f1 PD LF VCO NVf1 Divider ∏ N Prescaler ∏V Scale factor N (digital) Figure 3. high noise immunity. such as oscillators.3). or SiGe (silicon-germanium compound) (Fig.37 If the scaling factor of the prescaler is V (Fig. phase detectors. It is no major problem to implement all the digital functions on the chip. and large range of supply voltages. Schottky TTL. frequency dividers. The limited speed of CMOS devices precludes their application for directly generating frequencies in the range of 100 MHz or more (at least at the time of this writing). as indicated by the dashed enclosure in Fig. 3.7. fosc Reference divider f1 PD Divider ∏ N LF VCO Nf1 Scale factor N (digital) Figure 3.

3. 5.4 Frequency synthesizer using a dual-modulus prescaler. can be generated. further counting pulses are inhibited.4 can divide by a factor of 11 when the applied control signal is high. 3. As shown by the AND gate in Fig. If this counter has counted down to 0. only output frequencies of 10f1. 4. N1 is always greater than or equal to N2. The output signal of both of these counters is high if the content of the corresponding counters has not yet reached the value 0. or by a factor of 10 when the control signal is low. .4 becomes clearer if we assume that the ∏N1 counter has just counted down to 0 and both counters have just been loaded with their preset values N1 and N2. respectively. This disadvantage can be circumvented by using a so-called dual-modulus prescaler. All rights reserved. 30f1.PLL Frequency Synthesizers 118 Chapter Three Obviously the scaling factor V of the prescaler is much greater than 1 in most cases. 2. 20f1. The following conventions are used with respect to Fig. underﬂow below 0 is inhibited in the case of the ∏N2 counter. This implies that it is no longer possible to generate every desired integer multiple of the reference frequency f1. . . as shown in Fig. It can be demonstrated that the dual-modulus prescaler makes it possible to generate a number of output frequencies that are spaced only by f1 and not by a multiple of f1.com) Copyright © 2004 The McGraw-Hill Companies.11.38 A dual-modulus prescaler is a counter whose division ratio can be switched from one value to another by an external control signal. 3. Both programmable ∏N1 and ∏N2 counters are downcounters.4: 1. The channel spacing becomes f1. respectively. .digitalengineeringlibrary. if V is say.4.4. Downloaded from Digital Engineering Library @ McGraw-Hill (www. 10. The operation of the system shown in Fig. 3. 3. We now have to f-Synthesizer-IC Osc. As an example. the prescaler in Fig. 3. Any use is subject to the Terms of Use as given at the website. its output goes low and it immediately loads both counters to their preset values N1 and N2. When the ∏N1 counter has counted down to 0. Reference divider f1 PD Divider ∏ N1 LOAD LOAD Divider ∏ N2 LF VCO (N1V+N2)f1 Control:Add+1 2-modulus OUT Prescaler V/V+1 IN Figure 3.

4. 3.2) As stated above.min would be 240. The ∏N2 counter will therefore step down to 0 when the VCO has generated N2(V + 1) pulses. and both counters would then be reloaded to their preset values. that is. How many pulses Ntot did the VCO produce in order to run through one full cycle? Ntot is given by N tut = N 2 (V + 1) + ( N1 . N1min = 9. When the content of N1 becomes 0. Eq. 3. As long as the ∏N2 counter has not yet counted down to 0. All rights reserved. The scaling factor of the dual-modulus prescaler is now switched to the value V.com) Copyright © 2004 The McGraw-Hill Companies. the ∏N1 counter would be stepped down to 0 earlier than the ∏N2 counter. The dual-modulus prescaler never would be switched from V + 1 to V. Then N2 must be in the range of 0 to 9. the smallest realizable division ratio Ntot. If V = 16.N2.digitalengineeringlibrary. the prescaler is dividing by V + 1.N2)V pulses until the ∏N1 counter will step to 0. the dual-modulus prescaler would divide by 16 or 17. In this case.PLL Frequency Synthesizers PLL Frequency Synthesizers 119 ﬁnd the number of cycles the VCO must produce until the same logic state is reached again. both the ∏N1 and the ∏N2 counters are reloaded to their preset values. The VCO will have to generate additional (N1 .2) becomes N tot = 10 N1 + N 2 (3. and the minimum value of N1 would be N1min = 15. . N2 represents the units and N1 the tens of the overall division ratio Ntot. (3. and the cycle is repeated. that is. The smallest realizable division ratio is therefore N tot. Consequently both the ∏N1 and the ∏N2 counters will step down by one count when the VCO has generated V + 1 pulses.min = N1 min V = 90 The synthesizer of Fig. N1 must always be greater than or equal to N2.3) In this expression. and N1 can assume any value greater than or equal to 9. Downloaded from Digital Engineering Library @ McGraw-Hill (www. its content is N1 . If V = 10. Any use is subject to the Terms of Use as given at the website. At that moment the ∏N1 counter has stepped down by N2 counts. The overall division ratio would then be N tot = 16 N1 + N 2 Now N2 would be required to have a range of 0 to 15. so the system could not work in the intended way. Other factors can of course be chosen for V.N 2 )V Factoring out yields the simple expression N tut = N1V + N 2 (3. If this were not the case. This number is the overall scaling factor Ntot of the arrangement shown in Fig.4 is thus able to generate all integer multiples of the reference frequency f1 starting from Ntot = 90.

there is another way. and that the (scaled-down) reference frequency f1 of the system in Fig. The solution is the four-modulus prescaler (Fig. so with these devices a maximum frequency of only about 30 MHz could be realized for a prescaler ratio of V = 10.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. For the circuits inside the dashed enclosure CMOS devices are normally used. It offers four f-Synthesizer Osc. Reference divider f1 (100N1+10N2+N3)f1 PD LF VCO Divider ∏ N1 LOAD LOAD Divider ∏ N2 LOAD Divider ∏ N3 Add+1 Add+10 4-modulus Prescaler IN OUT 100/101/110/111 Figure 3.PLL Frequency Synthesizers 120 Chapter Three Let us again assume that V is chosen at 10. Fortunately.5). To extend the frequency range.digitalengineeringlibrary. The smallest output frequency would then be 90f1 = 900 kHz. The four-modulus prescaler is a logical extension of the dual-modulus prescaler. Downloaded from Digital Engineering Library @ McGraw-Hill (www. larger prescaler ratios. ratio Ntot would be N tot = 100 N1 + N 2 where N2 must now cover the range of 0 to 99 and N1 must be at least 99. For V = 100. say V = 100. while allowing lower frequencies than those obtainable from a synthesizer with a dual-modulus prescaler. . This extends the high end of the frequency range. 3. the lowest frequency to be synthesized is now 99 MHz. The counting frequency of older CMOS ICs (such as the old series 74Cxxx) has been limited to approximately 3 MHz.min is no longer 90 but has been increased to N tot = 100 N1 min = 100 ◊ 99 = 9900 If the reference frequency f1 is still 10 kHz. however. All rights reserved.4 is 10 kHz.5 Frequency synthesizer using a four-modulus prescaler. that now the lowest division ratio Ntot. It should be noted. became desirable. 3. which extends the upper frequency range of a frequency synthesizer but still allows the synthesis of lower frequencies.

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PLL Frequency Synthesizers

121

different scaling factors, and two control signals are required to select one of the four available scaling factors. As an example, the four-modulus prescaler shown in Fig. 3.5 can divide by factors of 100, 101, 110, and 111.11,36 By deﬁnition it scales down by 100 when both control inputs are low. The internal logic of the four-modulus prescaler is designed so that the scaling factor is increased by 1 when one of the control signals is high, or increased by 10 when the other control signal is high. If both control signals are high, the scaling factor is increased by 1 + 10 = 11. As seen from Fig. 3.5 there are no longer two programmable ∏N counters in the system, but three: ∏N1, ∏N2, and ∏N3 dividers. The overall division ratio Ntot of this arrangement is given by N tot = 100 N1 + 10 N 2 + N 3 In this equation N3 represents the units, N2 the tens, and N1 the hundreds of the division ratio Ntot. Here N2 and N3 must be in the range 0 to 9, and N1 must be at least as large as both N2 and N3 for the reasons explained in the previous example (N1min = 9). The smallest realizable division ratio is consequently N tot, min = 100 ◊ 9 = 900 which is lower roughly by a factor of 10 than in the previous example. For a reference frequency f1 of 10 kHz, the lowest frequency to be synthesized is therefore 900f1 = 9 MHz. Let us examine the operation of the system in Fig. 3.5 by giving a numerical example.

Numerical Example We wish to generate a frequency that is 1023 times the reference frequency. The division ratio Ntot is then 1023; hence N1 = 10, N2 = 2, and N3 = 3 are chosen. Furthermore, we assume that the ∏N1 counter has just stepped down to 0, so all three counters are now loaded to their preset values. Both outputs of the ∏N2 and ∏N3 counters are now high, a condition that causes the four-modulus prescaler to divide initially by 111. Solution After N2 · 111 = 2 · 111 = 222 pulses generated by the VCO, the ∏N2 counter steps down to 0. Consequently, the prescaler will divide by 101. At this moment the content of the ∏N3 counter is 3 - 2 = 1. After another 101 pulses have been generated by the VCO, the ∏N3 counter also steps down to 0. The division ratio of the fourmodulus prescaler is now 100. The content of the ∏N1 counter is now 7. After another 700 pulses have been generated by the VCO, the ∏N1 counter also steps down to 0, and the cycle is repeated. To step through an entire cycle, the VCO had to produce a total of

**N tot = 2 ◊ 111 + 1 ◊ 101 + 7 ◊ 100 = 1023
**

pulses, which is exactly the number desired.

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Chapter Three

In all frequency synthesizer systems previously considered, multiples of a reference frequency have been generated exclusively by scaling down the VCO output signal by various counter conﬁgurations. To produce frequencies in the range of 98.7 to 118.7 MHz with a spacing of 100 kHz, a synthesizer circuit would have had to be designed to offer an overall division ratio of 987 to 1187. As an alternative, one could ﬁrst generate output frequencies in the range of 8.7 to 18.7 MHz, using a division ratio of 87 to 187, and then mix up the obtained frequency band to the desired band. An additional local oscillator operating at a frequency of 90 MHz would be required in this case. A frequency synthesizer system using an up-mixer is shown in Fig. 3.6. The basic synthesizer circuit employed here corresponds to the simple system shown in Fig. 3.2. Of course, all synthesizer systems using dual- and four-modulus prescalers can be combined with a mixer. In the system of Fig. 3.6 the frequency of the local oscillator is fM. Consequently the synthesizer produces output frequencies given by fout = Nf1 + f M The mixer is used here to mix down these frequencies in the baseband Nf1. The mixer also generates a number of further mixing products effectively, generally frequencies given by fmix = ±nfout ± mf M where n and m are arbitrary positive integers. All these mixing products (excluding the baseband fout - fM) have frequencies that are very much higher than the baseband, so they are ﬁltered easily by either a low-pass ﬁlter or even the PLL system itself. An alternative arrangement using a mixer is shown in Fig. 3.7. In contrast to the previously discussed system, the mixer is not inside but outside the loop. The system generates output frequencies identical with those in Fig. 3.6, but for obvious reasons the desired frequency spectrum has to be ﬁltered out here by a bandpass ﬁlter. Still another way of extending the upper frequency range

Osc.

Reference divider

f1

PD Divider ∏N

LF

VCO

Nf1+fM

(Nf1)

Mixer fM

Scale factor N (digital)

Figure 3.6

Frequency synthesizer with a mixer to extend the high end of the frequency range.

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PLL Frequency Synthesizers

123

**fM Osc. Reference divider f1 Mixer PD Divider ∏N LF VCO
**

Bandpass

Nf1+fM

Scale factor N (digital)

Figure 3.7 Frequency synthesizer using a mixer to extend the upper end of the frequency range. In contrast to the circuit shown in Fig. 3.6, here the mixer is outside of the loop.

Osc.

Reference divider

f1 Multiplier XM

Bandpass

PD Divider ∏N

LF

VCO

NMf1

Scale factor N (digital)

Figure 3.8

Frequency synthesizer using a frequency multiplier to extend the upper end of the frequency range.

of frequency synthesizers is given by the frequency multiplier, as shown by Fig. 3.8. Frequency multipliers are normally built from nonlinear elements which produce harmonics, such as varactor diodes, step-recovery diodes, and similar devices. These elements produce a broad spectrum of harmonics. The desired frequency must therefore be ﬁltered out by a bandpass ﬁlter. If M is the frequency-multiplying factor, the output frequency of this synthesizer is fout = MNf1 It should be noted that now the channel spacing is not equal to the reference frequency f1, but to Mf1. To illustrate the theory of frequency synthesizers, we now will design an actual system that uses the design procedure described in Sec. 2.9 and by the ﬂowchart in Fig. 2.48.

3.2.2 Case study: Designing an integer-N PLL frequency synthesizer

The frequency synthesizer is required to produce a set of frequencies in the range from 1 to 2 MHz with a channel spacing of 10 kHz; i.e., frequencies of

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Chapter Three

1000, 1010, 1020, . . . , 2000 kHz will be generated. For this design we use the popular 74HC/HCT4076 CMOS device, which is based on the old industry standard CD 4046 originally introduced by RCA. This circuit contains three different phase detectors, an EXOR gate, a JK-ﬂipﬂop, and a PFD. Because noise must not be considered in this design, we use the PFD as phase detector. Because this detector offers inﬁnite pull-in range for any type of loop ﬁlter, we use the simplest of these, the passive lead-lag. The supply voltage UB is chosen as 5 V . With these assumptions we are ready to start the design, following the procedure shown in Fig. 2.48 (Sec. 2.9). Determine ranges of input and output frequencies. The input frequency is constant, f1 = 10 kHz. The output frequency is in the range from 1 to 2 MHz; thus f2min = 1 MHz, f2max = 2 MHz.

Step 1. Step 2.

The divider ratio must be variable in the range N = 100 to 200. The PLL will be optimized (z = 0.7) for the divider ratio N mean = N min N max = 141, as will be shown in step 3. Determination of damping factor z. Selecting z = 0.7 at N = Nmean yields the following minimum and maximum values for z: z min = 0.59 for N = 200 z max = 0.83 for N = 100 This range is acceptable.

Step 3.

Step 4.

Noise is not of concern in this PLL design, so the procedure continues with step 12. Selection of the phase detector type. The PFD is chosen, as noted in the introductory remarks. The phase detector gain becomes Kd = 5/4p = 0.4 V/rad.

Step 12.

Step 13.

VCO layout. According to the data sheet of the 74HC4046A IC, the VCO operates linearly in the voltage range of uf = 1.1 to 3.9 V approximately. Therefore, the characteristic of Fig. 3.9 can be plotted. If the VCO input voltage exceeds about 3.9 V , the VCO generates a very high frequency (around 30 MHz); if it falls below 1.1 V , the VCO frequency is extremely low, i.e., some hertz. From this characteristic, the VCO gain becomes K0 = 2.24 · 106 rad·s-1V-1. Following the rules indicated in the data sheet, resistors R1, R2, and capacitor C1 (Fig. 3.10) are found from graphs. The resistors must be chosen to be in the range 3 to 300 kW. The parallel connection of R1 and R2 should furthermore yield an equivalent resistance of more than 2.7 kW. We obtain

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PLL Frequency Synthesizers

125

2 f2(MHz) 1

0

1.1

3.9 uf(V)

5

Figure 3.9 Characteristic of the VCO for the CMOS IC type 74HC/HCT4046.

C1 100 pF C1A 10 kHz u1 SIGIN COMPIN u2' 74HC4046A C1B DATA N

**PC1 (Exor) PC2 (PFD) PC3 (JK)
**

PC2OUT R1 620 R2 1.3k C 0.33 mF VCOIN R1 R1 R2 47kW 130kW R2 VCOOUT CP

PO…P7 PE 74HC40102 (40103) TE PL MR +5V TC u ' 2

VCO PCPOUT

Figure 3.10

Schematic diagram of the PLL frequency synthesizer.

**R1 = 47 kW R2 = 130 kW C = 100 pF
**

Step 14.

Loop ﬁlter selection. As indicated above, we choose the passive lead-

lag ﬁlter.

Step 15.

Here we must make some assumptions on dynamic behavior of the PLL. It is reasonable to postulate that the PLL should lock within a sufﬁciently short time, e.g., within 2 ms. Hence we set TL = 2 ms. The procedure continues with step 21.

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Chapter Three

Step 21.

Given TL, the natural frequency wn is calculated: wn = 2p TL = 3140 s -1

**The procedure continues with step 22.
**

Step 22.

Because a passive loop ﬁlter is used, the formula for wn in Table 2.1 can be used only to calculate the sum t1 + t2. We obtain t 1 + t 2 = 644 ms

**The procedure continues with step 18.
**

Step 18.

Given wn, we use the formula for z in Table 2.1 to calculate t2. We t 2 = 445 ms

obtain

Now the time constant t1 can be computed. Because t1 + t2 = 644 ms (from step 22) and t2 = 455 ms, t1 becomes t 1 = 199 ms

Step 19.

We calculate the loop ﬁlter components. Given t1 and t2, the loop ﬁlter components R1, R2, and C can be determined. For optimum sideband suppression, capacitor C should be chosen as large and resistors R1 and R2 as low as possible. Selecting C = 0.33 mF gives the resistors (rounded to the next values of the R24 series) R1 = 620 W R2 = 1.3 kW The sum of R1 and R2 is higher than the minimum allowable load resistance (470 W). The ﬁnal design is shown in Fig. 3.10. The 74HC4046A PLL contains three phase detectors, PC1 (EXOR), PC2 (PFD), and PC3 (JK-ﬂipﬂop). PC2 has two outputs, PC2OUT and PCPOUT. PC2OUT is the phase PFD output, and PC2OUT is an in-lock detection signal, i.e., a logical signal that becomes high when the PLL has acquired lock. Only the PC2OUT is used in this application. For the down-scaler, an 8-bit presettable downcounter of type 74HC40102 or 74HC40103 is used. The 74HC40102 consists of two cascaded BDC counters, whereas the 74HC40103 is a binary counter. When the PE (preset enable) input is pulled low, the data on input ports P0 to P7 are loaded into the counter. The counter counts down on every positive transition at the CP (count pulse) input. If the counter has counted down to 0, the TC (terminal count) output goes low. Connecting TC with PE forces the counter to reload the data on the next counting pulse. If N

the Philips company provides a diskette with a design program for this type of PLL IC.g. typically 10 to 20 reference periods (a reference period has the duration 1/fref).e. Downloaded from Digital Engineering Library @ McGraw-Hill (www.82). To scale down by a factor of 100. 10. Actually there is an empirical relation between lock-in time TL and reference frequency fref. . . . 101. All rights reserved.g. Typically w0¢ is about 20 times the natural frequency. and the loop would be 10 times as fast as the “old” one.e.com) Copyright © 2004 The McGraw-Hill Companies. 3. .2. This is not extremely fast. etc. . for example. e. kHz. 110. in the type of synthesizer we considered hitherto—the output frequency has always been an integer multiple of the reference frequency. 10. but also by 10. .2..1.0.52 The author repeated the design using this program and got design parameters very similar to those obtained by his own procedure. we could create output frequencies of 10fref.digitalengineeringlibrary. the lock-in time corresponds to roughly 20 reference periods.3 Fractional-N frequency synthesizers In the design example of Sec. In a conventional synthesizer—i. we are forced—at least in conventional synthesizer circuits—to choose a low reference frequency.2fref..2 we realized a PLL frequency synthesizer capable of creating output frequencies that are an integer multiple of the reference frequency (10 kHz). 12fref. we now would be able to create the frequencies 100. we could create frequencies of 100. As we have seen. 120.1fref. Any use is subject to the Terms of Use as given at the website. 11. this results in a slow lock-in time.48 Where does that range stem from? In most practical PLL designs the down-scaled center frequency w0¢ is much larger than the natural frequency wn of the PLL. Now we remember that the lock-in time is approximately equal to one period of natural frequency. As mentioned earlier.PLL Frequency Synthesizers PLL Frequency Synthesizers 127 is the number represented by the data bus.2. . The synthesizer had a lock-in time of about 2 ms. Because the down-scaled center frequency is larger by the factor 20 than the natural frequency.. which is ten times the “old” reference frequency! So doing. Assuming fref = 10 kHz. 12. 11fref. kHz.. 10fref. TL ª 2p wn from Eq.. in the order of 1 kHz). i. 3. If such a down-scaler were realizable. we must therefore apply N = 99 to the input port.10. 10. Let us think now about a divide-by-N counter that is not only able to scale down by 10. Still using fref = 10 kHz. . . i. 102. . Note that in a PLL frequency synthesizer the downscaled center frequency w0¢ is identical with 2pfref. . etc.e. the counter divides by N + 1 (and not by N). the reference period equals one period of down-scaled center frequency. the natural frequency could also be increased by a factor of 10. To obtain a channel spacing of 10 kHz we now could choose fref = 100 kHz. which says that the lock-in time TL equals a number of reference periods. When the channel spacing of a frequency synthesizer must be narrow (e. (2. 10.

for example. During the succession of these two intervals the input of the counter received 101 pulses.F are stored in a buffer register as shown in the lower part of Fig. and 0. and to divide by 27 in 65 intervals having a duration of 27 input pulses. of course: there could be a demand to produce signals whose frequency can be any multiple of a precise frequency standard. hexadecimal. separated by a dashed line.4. 3. F can be stored in any code (binary. where the individual states are assigned weights of 0. The block labeled “pulse-removing circuit” and the summing block S should be disregarded for the moment. respectively) of the division ratio N.73 kHz.g. for example.2. shows an ordinary frequencysynthesizer system generating an output signal whose frequency is N times the reference frequency fref. We now investigate how a frequency synthesizer can divide its output frequency fout by fractional numbers. Any use is subject to the Terms of Use as given at the website. and refer to the waveforms u2** (VCO output signal) and u1 (reference signal) in Fig. the counter delivered 10 output pulses in the same period of time.2. Signal generators are an example for those applications. The upper portion of Fig. Let us see.digitalengineeringlibrary. 0.PLL Frequency Synthesizers 128 Chapter Three This is one of the ideas behind the so-called fractional-N frequency synthesizer. if the divide-by-N counter is made to scale down alternately by 10 and by 11.35 is obtained.11 shows the block diagram of a fractional-N loop. if the counter divides by 11 during an interval whose duration equals 11 input pulses and by 10 during an interval whose duration equals 90 input pulses.3fref. and so on). so it divided by 10.11. BCD. how the system can generate an output frequency fout = 5. becomes realizable. Since a down-scaler is always a digital circuit. if a ∏N counter is forced alternately to divide by 28 in 35 intervals having a duration of 28 input pulses. Dividing by 10. 3. For example. A frequency synthesizer capable of generating output frequencies which are a fractional multiple of a reference frequency is called a fractional N loop. Assume that the output frequency is already 5. On the average this counter effectively divides the input frequency by 10.47.5. 0.45 kHz or 146. . A ratio of 27. 3. if a division ratio of 26. becomes possible.11.1 on average! Fractional division ratios of any complexity can be realized (at least theoretically). 123. (In the following.10.02. for example.01 (hundredths register). The integer and fractional parts (N and F.5. however. Its division ratio is the number N. it can certainly not divide by fractional numbers like 10. e. and 0. for example. The F register stores a fractional number. then N = 26 and F = 0.12. however. All rights reserved. Dividing by 10.F. We can understand the operation of the fractional N loop by examining the waveforms shown in Fig. There are other reasons that lead to the design of fractional-N synthesizers. If F is represented as a two-digit fractional BCD number.47 is desired..com) Copyright © 2004 The McGraw-Hill Companies.04. The numbers N and F can be loaded via a serial or parallel data link from a microprocessor. the F register is an 8-bit register.08.1. but only either by 10 or by 11.12. 3. the term reference Downloaded from Digital Engineering Library @ McGraw-Hill (www.1 (tenths register) and 0.3 times the reference frequency. 0. where N is the integer part and F is the fractional part.8.39 Figure 3. 0. The signal u2** shows 53 cycles during the time interval when the reference signal u1 is executing 10 reference cycles.1 or 10.

11 Fractional-N frequency synthesizer block diagram. Any use is subject to the Terms of Use as given at the website.com) Copyright © 2004 The McGraw-Hill Companies.digitalengineeringlibrary.g.) ADD 129 Downloaded from Digital Engineering Library @ McGraw-Hill (www.register OVF u2 N . All rights reserved. uDAC qe + ACCU + DAC PD Load (from mC e.register LF u2* u1 (fref) Figure 3. .PLL Frequency Synthesizers u2**(fout) VCO u2** remove command OUT Pulse IN removing circuit DC level modulus control ∏N counter OUT IN F .

2 26.0 Downloaded from Digital Engineering Library @ McGraw-Hill (www.4 0.0 0.6 0. Figure 3.6 15.7 0.7 53.1 0.130 u2** 0 10 1 0 10.digitalengineeringlibrary.9 21.3 0. Waveforms explaining the operating principle of the fractional N loop.1) 1 pulse removed u2* 0 10 20 30 40 50 53 60 1 pulse removed 1 pulse removed Reference period Nr.0 0.9 (1. All rights reserved.8 37.com) Copyright © 2004 The McGraw-Hill Companies.12 .8 0.3 2 3 4 5 6 7 8 9 10 1 20 30 40 50 53 60 u1 (1.2) 1.1 42.2 0. Content of ACCU OVF PLL Frequency Synthesizers u2 0 qe (in fractions of a cycle) –1.5 0.0 5.4 47.3 0 0. Any use is subject to the Terms of Use as given at the website.5 31.

0. indicating that the synthesizer has “missed” 0. The content of the ACCU is now 0. and the next pulse generated by the VCO is removed from the ∏N counter. There is an elegant way to avoid this undesired frequency modulation: the waveforms of Fig. .3 cycle in the ﬁrst reference period.com) Copyright © 2004 The McGraw-Hill Companies. 3. Any use is subject to the Terms of Use as given at the website. and so on. consequently it overﬂows and generates an OVF signal (Fig.3 pulse during the ﬁrst reference period.3 pulse is then “missing. such as at the beginning of each reference period. As seen from Fig. All rights reserved.2. the ∏N counter is again required to divide by 5.3 cycle (or -0. so the ∏N counter will divide by 5 only. As Fig. In the third reference period the accumulated error is 0.3.12. however. The ACCU uses the same code as the F register.2 cycles.3 times the reference frequency fref.6 cycle.99. During the time interval where u1 generates its ﬁrst reference cycle. Such a staircase-shaped modulation of the VCO frequency is not desired. the phase error has increased to -0. If we assume that the initial content of the ACCU was zero at t = 0. the ∏N counter is required to divide the signal u2** by a factor of 5.12). an accumulator (ACCU) is used for this purpose.3) has to be memorized somewhere in the system. F supplied by the F register to its original content whenever the ADD signal performs a positive transition. The OVF pulse generated by the ACCU causes the pulseremoving circuit to become active.12.9 cycle. Thus the phase error has negative polarity because the reference signal u1 lags the signal u2. Because the ∏N counter divides by 5 forever. the ACCU is capable of storing fractional BCD numbers within a range of 0.12. The content of the ACCU is therefore Downloaded from Digital Engineering Library @ McGraw-Hill (www.3 cycles during one reference period. because the pulse-removing technique just discussed has already compensated for the phase error. This is exactly what was intended. In the second reference period. If a two-digit fractional BCD format is used. and in the fourth reference period. it produces 5. 3. 3. 3. as seen in Fig. 3.12 show that the content of the ACCU has the same amplitude as the phase error qe but opposite in polarity.3 · 2p rad) after the ﬁrst reference period in Fig. In the ﬁrst reference period.” This error (0.digitalengineeringlibrary. This phase error is applied to the input of the loop ﬁlter and will modulate the frequency of the VCO. The phase error qe is plotted versus time in Fig.) Let the system start at the time t = 0. the ACCU adds the fractional number 0. the ACCU will accumulate an error of 0. The PD in Fig.12 shows. 3.3 cycle during the ﬁrst reference period. Since it has already missed 0. it will continue to divide by 5 instead.PLL Frequency Synthesizers PLL Frequency Synthesizers 131 cycle or reference period will be used to designate one full oscillation of the reference signal u1.6 cycle. If the VCO oscillates at 5. After the second reference cycle. However. one problem has been overlooked. the ACCU overﬂows again in the seventh and tenth reference periods. 10 · 5 + 3 = 53 pulses are produced by the VCO during 10 reference periods. 3. 3.12. of course.00 to 0. its waveform looks like a staircase. it is 1. Because this is not possible. However. the total error has now accumulated to 0. the ACCU cannot store numbers greater than 1.12 will consequently measure a phase error of -0. This is impossible. This pulse removal has the same effect as if the ∏N counter had divided by 6 instead of 5.3. Three pulses will therefore be removed from the ∏N counter in a sequence of 10 reference periods.

the output signal uDAC is added to the output signal of the phase detector. We will see in this section that single-loop synthesizers can become impractical if it becomes necessary to generate a large range of frequencies with a very small channel spacing.1 having a reference frequency of 1 kHz and using a divide-by-N counter having a scaling factor N in the range from 100. . An extremely simple numerical example will demonstrate. however. the input signal to the loop ﬁlter is a dc level when the fractional N loop has reached a stable operating point. as will be shown in Sec.13). Second.PLL Frequency Synthesizers 132 Chapter Three converted to an analog signal by a DAC (digital-to-analog converter). Of course we could implement a synthesizer as shown in Fig.com) Copyright © 2004 The McGraw-Hill Companies. Since the two staircase signals cancel each other.e. 3. 3. 3.13 fm frequency f2. such synthesizers were capable of creating a set of frequencies that were an integer (or a fractional) multiple of a given reference frequency. it would probably have poor noise performance. that this simple arrangement would not work as expected. (We will see later that the ﬁne synthesizer must not necessarily be slow. for example.4. of a synthesizer that would be required to generate frequencies in the range from 100 to 200 MHz with a channel spacing of 1 kHz.001 MHz and a lower sideband with fre- f1 Mixer f2 Figure 3.) To add coarse and ﬁne frequencies we would use a mixer (Fig. that the coarse frequency f1 is 100 MHz and the ﬁne frequency f2 is 1 kHz. Any use is subject to the Terms of Use as given at the website. Assume. Think. An ideal mixer would multiply both input signals. i. Such a system would show up two ﬂaws: ﬁrst of all.3 Single-Loop and Multiloop Frequency Synthesizers In Section 3. 3.digitalengineeringlibrary. hence at its output we would have an upper sideband with frequency f1 + f2 = 100. Another idea would be to use two separate synthesizers.000.000 to 200. a coarse synthesizer creating the frequency range from 100 to 200 MHz in steps of 1 MHz. and a ﬁne synthesizer generating frequencies in the range 0 to 1 MHz in steps of 1 kHz.2 we exclusively considered frequency synthesizers that were built from one single loop. the phase jitter at the output of the VCO increases with the square of the scaling factor N. it would settle in a perhaps 20 ms. Using a mixer to add a coarse frequency f1 and a ﬁne Downloaded from Digital Engineering Library @ McGraw-Hill (www. All rights reserved. it would be slow because it needs about 10 to 20 reference cycles to switch from one channel to another. for example.

If we switch. The frequency offset has been chosen fofs = 75 MHz here. Then the maximum frequency in the upper sideband would be fumax = f1 max + fofs + f2 max and the minimum frequency in the upper sideband fumin = f1 min + fofs + f2 min For the lower sideband the maximum and minimum frequencies would be flmax = f1 max .f2 min flmin = f1 min . Figure 3.005 MHz and 129. i. In order to separate upper and lower sidebands. Let us consider the upper (coarse) synthesizer ﬁrst. We decided that both frequencies f1 and f2 should be variable. VCO1 is forced now to create an output Downloaded from Digital Engineering Library @ McGraw-Hill (www. Because we want to keep only the upper sideband.e. How large has fofs to be chosen in order to safely separate upper and lower sidebands at the mixer output? Let the minimum coarse frequency be f1min and the maximum coarse frequency be f1max. the ﬁlter now has to separate the sidebands 130. Because of the mixer.14 is a possible implementation of the intended synthesizer. hence is a dual-loop system. All rights reserved.digitalengineeringlibrary. we would have to ﬁlter out the lower.13 would not work. but reject the lower. Assume for the moment that f2 = 0. Such a ﬁlter is practically impossible to realize. Any use is subject to the Terms of Use as given at the website.fofs . Without mixer Mix1 this loop would create frequencies in the range 25 to 125 MHz with a channel spacing of 1 MHz. hence the transition region of the ﬁlter would have to be extremely narrow! There is still another reason why the circuit in Fig. . The circuit consists of two synthesizers.fofs . where fofs is the frequency offset.999 MHz. it should pass the upper frequency.f2 = 99. the frequency at the output of bandpass ﬁlter BP2 is exactly 75 MHz.f1 min 2 In our example fofs would have to chosen larger than 50 MHz.f2 max To separate the sidebands the minimum frequency of the upper sideband must be larger than the maximum frequency of the lower sideband. we will have to introduce a frequency offset at the f2 input. f1 to 130 MHz and f2 to 5 kHz. we would apply another ﬁne frequency f2¢ which is given by f2¢ = f2 + fofs.PLL Frequency Synthesizers PLL Frequency Synthesizers 133 quency f1 .995 MHz. this inequality leads to fofs > f1 max .. In analogy let the minimum ﬁne frequency be f2min and the maximum f2max. 3. Instead of applying f2 directly.com) Copyright © 2004 The McGraw-Hill Companies. hence we have the condition fumin > flmax Assuming f2min = 0. for example.

.. .. Again Mix2 generates an upper and a lower sideband.e.g.001 to 65 MHz...999 MHz PD1 LF1 VCO1 Mix1 75.5 MHz.999 MHz and the lower from 64.75. Basically we could use a synthesizer with a reference frequency of 1 kHz and a scaling factor in the range 75. hence Mix1 operates as a frequency subtractor.999 MHz :N Counter 25. A second mixer Mix2 is used now to add a frequency offset of 70 MHz. Looking at the synthesizer in the lower part of the ﬁgure. The upper ranges from 75 to 75.digitalengineeringlibrary..4 Noise in Frequency Synthesizers Having designed a PLL frequency synthesizer that uses a highly stable quartzcrystal reference oscillator..com) Copyright © 2004 The McGraw-Hill Companies.PLL Frequency Synthesizers 134 Chapter Three 1 MHz 100.200.49 3.990 MHz with channel spacing 10 kHz. we may hope to get a nicely clean output signal with Downloaded from Digital Engineering Library @ McGraw-Hill (www... Now the ﬁne frequency component must be added.76 MHz :M Counter 5000. The one-sided bandwidth must be somewhat larger than about 0. Multiloop synthesizers are frequently found in signal generators.. This synthesizer is a factor of 10 faster than a synthesizer using a 1-kHz reference.. the output frequency range of VCO1 is now 100 to 200 MHz.59.5 MHz. transmitters (e.125 MHz : 10 Counter 5. it is ﬁltered out by a bandpass ﬁlter with center frequency of about 75. upper part) and from another synthesizer creating ﬁne frequency steps (1 kHz.990 MHz 70 MHz Figure 3. Very sophisticated multiloop designs have been described by Rohde.999 MHz with a channel spacing of 1 kHz... With an offset of 75 MHz the ﬁne frequency f2¢ must be in the range 75 to 75... we recognize a synthesizer with reference 10 kHz instead of 1 kHz. receivers.000 to 75. but we remember that such a circuit would be slow and would have bad noise performance.. creating a frequency range from 50 to 59. All rights reserved. short wave). Bandpass ﬁltering ﬁlters out the lower sideband only. An external divide-by-10 counter scales down that range to 5 to 5.. Any use is subject to the Terms of Use as given at the website.5999 50.48. Because we use only the upper sideband.5.999 MHz with channel spacing 1 kHz.999 MHz Mix2 BP2 75.125 10 kHz PD2 LF2 VCO2 BP1 25. and the like. i. lower part).14 Dual-loop frequency synthesizer built from a synthesizer creating coarse frequency steps (1 MHz.999.. frequency that is higher by that offset.

the spectrum of the synthesizer’s output signal should consist of just one single line at the desired frequency. Unfortunately. the phase detector delivers an output signal that is proportional to the phase error qe of the loop. All rights reserved.15. The mathematical analysis is quite cumbersome. These unwanted ac components are partially suppressed by the loop ﬁlter. Downloaded from Digital Engineering Library @ McGraw-Hill (www. Even the highest-quality reference oscillator is not free from output phase jitter. Three sources of phase jitter and spurs can be recognized: 1.PLL Frequency Synthesizers PLL Frequency Synthesizers 135 high frequency stability and no phase jitter. This perturbation is denoted qn. 3. This signal is a “quasidc” signal. Mathematically.VCO ref feedthrough qn. .15 shows a simpliﬁed model for the determination of output phase jitter and spurious sidebands. and moreover. Basically. Phase jitter created by the VCO. In this section we will investigate the sources of those undesired noise components. reality shows another picture: when measuring the signal spectrum.ref in Fig. in case of the PFD there can even be an ac component that is a subharmonic of the reference frequency. which is the case for the EXOR. Phase jitter created by the reference oscillator. each part of the synthesizer circuit can contribute to output phase jitter. Any use is subject to the Terms of Use as given at the website.15 synthesizer. 3.digitalengineeringlibrary. but the residual signal still will frequency- qn. This perturbation is denoted qn.3.com) Copyright © 2004 The McGraw-Hill Companies. we may observe quite some phase jitter.out :N Model for analysis of output phase jitter qn. Because the VCO is nothing else than an oscillator.ref PD LF + uft VCO + Â qn. As we have seen in Chap.1. Figure 3. In addition the phase detector creates ac components at higher frequencies. 2. 2.48 In the following we will concentrate on the dominant ones.out in a PLL frequency Figure 3. it also will contribute to phase jitter. but fortunately there are a number of models available today that greatly simplify the analysis. As we will see later in this section. there may be an ac signal component at the reference frequency or at twice the reference frequency.15 3. we can detect a couple of sidebands (so-called spurs) around the desired center frequency.VCO in Fig. Depending on the type of phase detector chosen.

fm.44 has shown the relationships between signal power Ps.4. . Eq. In Fig. and input phase jitter qn1.112) gave the relationship q2 n1 = Pn 2 Ps [rad 2 ] (3.6) 2 Downloaded from Digital Engineering Library @ McGraw-Hill (www. 2. Any use is subject to the Terms of Use as given at the website. q2 n1 = Pn Ps rad 2 (3. But when there is a phase jitter component at frequency fm. When the frequency of that ac signal is equal to the reference frequency fref.ref of the reference oscillator To analyze phase noise at the output of the reference oscillator. This power spectrum has one-sided bandwidth Bi/2 and is symmetrical around the center frequency f0 of the PLL. . 2.out in Fig.5) q2 n1 represents the mean square input phase jitter. . (2. 2. and Pn is noise power (in W). The noise signal is denoted n(t). All rights reserved. this is identical with the shaded area under the squared phase spectrum |Qn1|2(f ) in Fig. In the following we are therefore going to analyze the three mentioned effects.44b.4) [see Eq. 3. 2. for example.1 Phase jitter qn. The signal causing those spurs is denoted uft (ft = feedthrough) in Fig. . there is a correlated component at -fm also.e.44a). 2.8. one line being at frequency f0 + fm.44b represented the PSD of input phase jitter qn1. and noise power is given by Pn = n(t) . 2. we will observe “spurs” at a distance of ±fref.PLL Frequency Synthesizers 136 Chapter Three modulate the VCO output. When the input phase jitter contains a component at frequency fm. i. the other at f0 . Fig. Ps is signal power (in W). q2 n1 is the mean square input phase jitter resulting from the one-sided power spectrum |Qn1|2(f ). All these noise sources contribute to output phase jitter (labeled qn. 3.com) Copyright © 2004 The McGraw-Hill Companies. This all may sound disappointing. (2. from the carrier frequency f0. and consequently the overall mean square phase jitter becomes twice as large. noise power Pn. But when we succeed in quantifying the sources of trouble.44a the power spectral density (PSD) of noise power Pn was shown. 2.15) and spurs.2)]. we saw that this gives rise to two sidebands in the power spectrum Pn (Fig. The input phase jitter has been shown to modulate the phase of the carrier frequency f0 (center frequency of the PLL). Fig. This spectrum also has the one-sided bandwidth Bi/2 and is symmetrical around f = 0. let us recall the noise theory presented in Sec.15. we are in a position to minimize the undesired disturbances. this was described by u1 (t) = U10 sin(w 1t + q n1 (t)) (3.4.digitalengineeringlibrary.44b. 3. ±2fref. As we see from Fig. Therefore the spectra of input phase jitter and noise power are offset from each other by the carrier frequency f0.

the unit is rad2/Hz. To obtain the PSD of phase jitter. we started from the premise that the noise spectrum would be “white”. but the variable q2 can be n1 considered as power as well. but the power spectral density of phase jitter qn1(t) must also be known.out noiseless Figure 3.in Ps PM +1 Ps Pn qn.6).com) Copyright © 2004 The McGraw-Hill Companies. we will apply the PSD transform onto both sides of Eq. we will recognize that the corresponding noise spectra are not white at all. The phase jitter creates phase modulation of the carrier (PM = phase modulator). 3. Finally. All variables in Eq. When dealing with phase jitter in oscillators.6) represent power quantities. Next we are examining the impact of phase jitter onto a carrier with power Ps = 1 mW and frequency f0. however.. because it is the mean square value of input phase jitter qn1(t). When analyzing noise performance in Sec. This is very clear for the variables Pn and Ps.8. the unit of signal power Ps is W. Any use is subject to the Terms of Use as given at the website.digitalengineeringlibrary. Equation (3. which yields Sqq ( fm ) = Snn ( fm ) Ps rad 2 Hz (3. The noise source is assumed to be thermal noise.16 Model demonstrating the effect of phase jitter onto a carrier signal having power Ps. (3. a phase modulator is shown at the left of the circuit.7) where Sqq(fm) is the power spectral density of phase perturbation (jitter) qn1 at (modulating) frequency fm. All rights reserved. Because the phase jitter modulates the phase of the carrier. (3. qn.4. that each frequency interval of width 1 Hz (within the input noise bandwidth Bi/2) would contain the same power (in W/Hz). the unit is W/Hz.e. For this analysis the model in Fig. i. Snn(fm) is the power spectral density of the noise signal at a frequency that is displaced by the offset fm from the carrier frequency.16 is used.6) tells us how large the phase jitter will be when signal power Ps and noise power Pn are given.PLL Frequency Synthesizers PLL Frequency Synthesizers 137 From now on we specify with q2 n1 the mean square phase jitter resulting from the two-sided power density spectrum of input phase jitter. . It is not sufﬁcient therefore to know the mean square phase jitter q2 n1 alone. Downloaded from Digital Engineering Library @ McGraw-Hill (www. but will be highly nonlinear functions of frequency. 2.

e. the result is Sqq.out(fm)dB is dBc/Hz. however. The phase modulator is followed by an ampliﬁer.41 ◊ 10 -17 Ps rad 2 Hz Because this is an extremely small quantity. The PSD of thermal noise is deﬁned by Snn ( fm ) = kT W Hz (3. If total noise power is Pn and carrier power is Ps. in decibels. All rights reserved. the square root of Sqq. we compute its rms value.out(fm)dB = -174 dBc/Hz. We therefore introduce a new variable Sqq.rms = Sqq.in(fm). and for the current example.out(fm) we then get Sqq. the other input is thermal noise. Sqq. since thermal noise is always present and real ampliﬁers create additional noise. out ( fm ) = kT = 0.e. and application notes on PLL frequency synthesizers.PLL Frequency Synthesizers 138 Chapter Three One of its input signals is the carrier (Ps).8) with k = Boltzmann constant = 1.02 ◊ 10 -9 rad Hz Note The unit dBc/Hz is widely used in textbooks. Sqq(fm) as deﬁned in Eq. Usually one deﬁnes another noise to carrier ratio NCRdB expressed in decibels: NCR dB = 10 log 10 (NCR ) = 10 log 10 Pn Ps Downloaded from Digital Engineering Library @ McGraw-Hill (www. i.9) The unit of Sqq. From a mathematical point of view.out ( fm ) dBc Hz (3. This yields q n.) The power gain of the ampliﬁer is assumed to be 1.4 · 10-23 W · s/K and T = absolute temperature in kelvins (K). To get an idea of phase jitter to expect in this example. W/W.7) represents a ratio of noise power to carrier power.digitalengineeringlibrary. As we know. For Sqq.out ( fm ) = 0.com) Copyright © 2004 The McGraw-Hill Companies.out(fm) is mostly expressed on a logarithmic scale.out(fm)dB stands for noise power referred to carrier power.41 · 10-20 W/Hz. which is assumed to be noise free. the PSD of phase jitter at the output of the ampliﬁer Sqq. and the noise spectral density becomes Snn(fm) = 0.out ( fm )dB = 10 log 10 Sqq. At room temperature we have T = 293 K.. a noise to carrier ratio (NCR) could be deﬁned by NCR = Pn Ps W W Note that the unit of NCR. .out(fm)dB: Sqq.out(fm)dB = -174 dBc/Hz is the absolutely best result we could get from an ampliﬁer.out(fm) is identical with the PSD of phase jitter at the input Sqq.out(fm).. is dimensionless. The value Sqq. The letter c in the unit dBc signiﬁes that Sqq. This tells us that the noise power contained within a bandwidth of 1 Hz (located at a frequency that is offset by fm from the carrier frequency) is 174 dB below the power of the carrier. Any use is subject to the Terms of Use as given at the website. Because the ampliﬁer does not add further noise.41 ◊ 10 -17 = 2. (Later we will release this premise. i. data sheets. this unit is not entirely correct for the following reasons. (3.

] We can circumvent that dilemma by introducing new variables Pnn*(fm) and Sqq*(fm) as follows: Snn* ( fm ) = Snn ( fm ) ◊ B Sqq* ( fm ) = Sqq ( fm ) ◊ B W rad 2 B stands for bandwidth and is set B = 1 Hz. 000)dB = 10 -15 W ◊ 1 Hz = 10 -15 W Hz This is the noise power within the frequency interval from 10. Next Sqq*(fm) is to be computed. however. The new variable Snn*(fm) now signiﬁes noise power (not power density) within a bandwidth B = 1 Hz. the unit of Snn*(fm) becomes W (and not W/Hz). [Try to ﬁnd out what log(Hz-1) is. The new variable Sqq*(fm) is deﬁned by Sqq* ( fm ) = Snn* ( fm ) Ps and is now the ratio of two power quantities. Mathematically it is not correct to build the logarithm of a ratio that is not dimensionless.digitalengineeringlibrary. It is now mathematically correct to build a logarithmic quantity from Sqq*(fm) by setting Sqq* ( fm )dB = 10 log 10 Sqq* ( fm ) dBc The unit of Sqq*(fm)dB now becomes dBc and not dBc/Hz. and that the noise power density Snn(fm) is 10-15 W/Hz at an offset fm = 10 kHz from the carrier frequency. we recognize that the ratio Snn(fm)/Ps is not dimensionless.7) once again. (3.001 Hz relative to the carrier frequency. but for power density. Any use is subject to the Terms of Use as given at the website.PLL Frequency Synthesizers PLL Frequency Synthesizers 139 Checking Eq. Let us make a numerical example. Sqq*(fm) therefore represents no longer the power density of phase perturbations. since Snn(fm) does not stand for power. whose unit is W/Hz.000 to 10. but rather the mean square value of phase perturbation q 2 n1 whose spectrum ranges from fm < f < fm + 1. The noise power Snn*(fm) within a bandwidth of 1 Hz at fm = 10 kHz is then given by Snn* (10. hence the ratio Snn(fm)/Ps has the unit Hz-1. located at an offset fm from the carrier frequency. For the rms value of phase perturbation in that frequency interval we get Downloaded from Digital Engineering Library @ McGraw-Hill (www. Assume that the carrier power is Ps = 1 mW. Furthermore we see that the mean square value of phase perturbation within a bandwidth of 1 Hz at modulating frequency fm = 10 kHz is 10-12 rad2. has the unit W. Its unit is therefore rad2 and not rad2/Hz. All rights reserved.com) Copyright © 2004 The McGraw-Hill Companies. As a result of multiplication with B. The variable Ps. . We get Sqq* ( fm ) = Hence Sqq*(fm)dB becomes Snn* ( fm ) 10 -15 W = = 10 -12 10 -3 W Ps Sqq* ( fm )dB = 10 log 10 10 -12 = 120 dBc We conclude that the noise power within a bandwidth of 1 Hz at offset frequency fm = 10 kHz is 120 dB below carrier power.

i. the equivalent input noise power increases with fm-1 at frequencies below a corner frequency denoted fc (see Fig. . As mentioned.in Pn. In oscillators fc can easily extend into the MHz region. however.10) that is. 3. we will use nevertheless the familiar unit dBc/Hz for power density of phase jitter.in (3. is ﬂicker noise.12) Still assuming F = 6 dB. For a noiseless ampliﬁer the only source of input noise has been thermal noise (kT).e. 3. we get for the PSD of the noise signal fc Snn ( fm ) = kTF Ê 1 + ˆ Ë fm ¯ W Hz (3.out(fm)dB increases by 6 dB: Sqq.out Ps. we get for a modulating frequency fm = fc/10 the value Sqq. which is deﬁned by F= Ps.out ( fm ) = kTF Ê fc 1+ ˆ Ë Ps fm ¯ rad 2 Hz (3.17).rms = J 2 Sqq* ( fm ) = 10 -12 = 10 -6 n1 = rad To avoid confusion with the standards used in practically all books and papers on frequency synthesizers.digitalengineeringlibrary. we now have Sqq. fc can be in the order of 10 Hz to some kHz.out f (m) = F ◊ Sqq. A resonator is placed Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies.PLL Frequency Synthesizers 140 Chapter Three q n1.18. For a real ampliﬁer Sqq. real ampliﬁers add further noise.out(fm) by factor F. however. All rights reserved. When ﬂicker noise is present. Any use is subject to the Terms of Use as given at the website. Sqq. For each real ampliﬁer. For operational ampliﬁers.in ( fm ) = kTF Ps When we assume F = 6 dB.out Pn. The corresponding model is shown in Fig. In the forward path we have an ampliﬁer with power gain G = 1.out ( fm ) = -174 + 6 = -168 dBc Hz A much more disturbing effect in oscillators.out ( fm )dB = -174 + 6 + 10 = -158 dBc Hz At a modulating frequency fm = fc/100 this would increase to -148 dBc/Hz. for example.. We are ready now to compute the phase jitter at the output of an oscillator.out(fm) becomes larger than Sqq. F is the ratio of signal-to-noise at the output to signal-to-noise at the input. The oscillator is represented by a closed loop having positive feedback.11) Now we get for the PSD of phase jitter the expression Sqq. Noise performance of ampliﬁers is speciﬁed by noise ﬁgure F. although this unit has been shown to be somewhat incorrect.

out Ps Resonator Figure 3. All rights reserved. Noise above fc is thermal noise. . PM = phase Downloaded from Digital Engineering Library @ McGraw-Hill (www. qn. Noise below corner frequency fc is called ﬂicker noise.digitalengineeringlibrary.in.in PM G=1 Ps qn. Any use is subject to the Terms of Use as given at the website.com) Copyright © 2004 The McGraw-Hill Companies.PLL Frequency Synthesizers PLL Frequency Synthesizers 141 Snn –1 ~fm kT fc Figure 3. Model for the analysis of phase jitter in an oscillator.17 fm Power spectral density of input phase jitter qn.18 modulator.

Any use is subject to the Terms of Use as given at the website.16. As a result of the feedback path.out is constant above f0/2Q2. In addition to thermal noise kT..13) Here Gn(fm) is the closed-loop gain of the oscillator. . The spectral density of oscillator phase jitter is greatest near the resonance frequency. The term f0/2Q is the one-sided bandwidth of the resonator.out(fm) no longer is identical with Sqq. fm = f .com) Copyright © 2004 The McGraw-Hill Companies.PLL Frequency Synthesizers 142 Chapter Three in the feedback path. and below corner frequency f0/2Q1. What we see dramatically from Fig. Under ideal conditions. The higher the Q.15) Downloaded from Digital Engineering Library @ McGraw-Hill (www.out(fm)dB approaches -174 dB for a signal power of 1 mW (0 dBm). This is shown in Fig.19a and b. Sqq. 3. the closed-loop gain is unity. Going back to the synthesizer noise model in Fig. To compute the output phase signal q2¢(t) we found H (s) = Q¢ 2 ( s) Q1 (s) (3. The result is plotted in Fig.19a sketches once more the power density spectrum of the equivalent input noise. the closed-loop gain increases with fm-2.14) where f0 = resonant frequency of the oscillator fm = frequency offset from resonant frequency (i. 3. 3.in ( fm ) ◊ Gn ( fm ) 2 rad 2 Hz (3. Sqq.4. it increases with fm-3.15. 3. Sqq. As shown by Rohde. In the low-Q case. 3. Let us discuss ﬁrst the high-Q case.out? We know from Sec. 3. this could be expected because the noise gain of the oscillator is maximum at resonance frequency f0. For high Q.48 the squared closed-loop gain is given by 1 f0 ˆ Gn ( f ) = 1 + 2 Ê f m Ë 2Q ¯ 2 2 (3.ref could be. a low Q (Q = Q2) and a high Q (Q = Q1). The two values for Q have been chosen such that the corner frequency f0/2Q1 is below fc.2 how the PLL reacts onto phase signals q1(t) applied to the reference input. In the range between fc and f0/2Q1. 2.19 is that the resonator Q has a tremendous effect on the oscillator phase jitter. we now know how large the phase jitter qn. Below fc. the lower the phase jitter.19c. All rights reserved. but is given by Sqq. and the corner frequency f0/2Q2 is above.e. Sqq. and below fc it increases with fm-3.in(fm) as in the model of Fig.out(fm) increases with fm-1. there is ﬂicker noise below corner frequency fc.19b for two cases.out(fm) is constant versus frequency for f > fc.out ( fm ) = Sqq. Below the corner frequency f0/2Q. Figure 3.digitalengineeringlibrary. The power density spectrum of the ouput phase jitter is obtained by multiplying the appropriate curves in Fig. Sqq. But what is the impact of that phase jitter on the synthesizer output qn. it increases with fm-2.f0) Q = quality factor of the resonator At frequencies far away from the carrier frequency f0.

Downloaded from Digital Engineering Library @ McGraw-Hill (www.out –3 ~fm low Q –3 ~fm high Q –1 ~fm –2 ~fm f0 2Q1 (c) fc f0 2Q2 fm Figure 3.com) Copyright © 2004 The McGraw-Hill Companies.PLL Frequency Synthesizers Snn –1 ~fm kT fc (a) fm ΩGnΩ 2 –2 ~fm high Q low Q f0 2Q1 (b) f0 2Q2 fm Sqq.19 Power density spectra of phase jitter in an oscillator.digitalengineeringlibrary. dashed line represents an oscillator with a low-Q resonator (Q1 > Q2).out(fm). (c) Power density spectrum of the oscillator’s output phase jitter Sqq. All rights reserved. Any use is subject to the Terms of Use as given at the website. (b) Squared closed-loop gain |Gn(fm)|2 of the oscillator. (a) Power density spectrum of the noise applied to the oscillator input. Solid line represents an oscillator having a resonator with high Q. .

the loop bandwidth (BL) must be made as small as possible.23. phase noise qn. If there were no feedback. H(fm) ഠ 1. thus the synthesizer multiplies the reference phase jitter by N2. When the reference divider scales down the frequency by R. The PSD of phase noise contributed by the VCO is given by Downloaded from Digital Engineering Library @ McGraw-Hill (www.4. As is easlily seen from the block diagram in Fig. He(w) is a high-pass function. To mimimize VCO output jitter. 3. All rights reserved.VCO would simply add to the ouput phase noise qn.VCO of the VCO In Sec. it also attenuates the oscillator phase jitter by R. For Gn we obtain the very simple result Gn ( f ) = H e ( f ) (3. phase jitter is attenuated.com) Copyright © 2004 The McGraw-Hill Companies.. But this bandwidth cannot be chosen arbitrarily low. 3. In most cases the reference oscillator is not directly connected to the phase detector input. which decreases the PSD of phase jitter by R2.e. This phase noise (denoted qn.. which will be treated in greater detail in Chap. As can be seen from the Bode diagram for He(w) in Fig. but rather in the phase jitter q2(t) at the output of the VCO. Checking the phase jitter model of Fig. Because we have a feedback path. 4. (2.out.29)].VCO to the output terminal qn.ref ( fm ) 2 rad 2 Hz (3. because a low BL also means a low natural frequency wn.1. In the stopband. is identical with the error frequency response as deﬁned in Eq.e.digitalengineeringlibrary. we recognize that the VCO is nothing more than an oscillator. as shown in Fig. (2. the attenuation depends on the gain roll-off of H( f ) at higher frequencies.2 Phase jitter qn.36). When both ∏R and ∏N dividers are used. If fm lies within the passband of the PLL (given by BL or f3dB). Any use is subject to the Terms of Use as given at the website. 3.4.out ( fm ) = H ( fm ) ◊ 2 N2 ◊ Sqq. 2. however. a large lock-in time.17) We note that the phase frequency response H(f) acts as a low-pass ﬁlter onto the phase jitter caused by the reference oscillator. but rather the frequency created by the reference oscillator is scaled down by a reference divider.PLL Frequency Synthesizers 144 Chapter Three [see Eq. . For the power spectral density of the phase jitter at the output of the VCO we consequently have Sqq. fm is the frequency offset from the carrier frequency f0.1 we investigated the phase jitter introduced by the reference oscillator.out ( fm ) = H ( fm ) ◊ N 2 ◊ Sqq. we must compute the closed-loop gain Gn from the insertion point of the VCO phase noise qn. too.out.16) Here again. q2 and q2¢ are related by q2 = q2¢N.18) i. 3. 2.15 once again. however. hence it will introduce additional phase jitter into the loop.ref ( fm ) R2 rad 2 Hz (3. for example.VCO in the block diagram) enters the loop at the input of summator labeled S.1. the PSD of the VCO output becomes Sqq. we are not interested in phase jitter q2¢(t) (which appears at the output of the divide-by-N counter). i. In case of the frequency synthesizer.

Although a VCO is an oscillator. Little is known about phase jitter created by VCOs. Obviously this cannot have an impact on the Downloaded from Digital Engineering Library @ McGraw-Hill (www. As we will see.e. In the ideal case the VCO would operate at its center frequency. this is not valid for VCOs because the frequency created by a VCO is not determined by a resonant circuit but by the time interval required to charge a capacitor to some threshold level. (2.19) with Sqq. what we know is that most of the noise power is concentrated near the oscillating frequency and hence can be considered as a kind of ﬂicker noise.37). most of its power is concentrated around the center frequency f0. Fig. 3. This is in clear contradiction to the conclusion in Sec. 3. The bandwidth of high-pass function He( f ) is the same as the bandwidth of the low-pass function H(f). 3. the instantaneous phase of the VCO output signal would be modulated by a signal whose frequency is twice that frequency. 2. because He(s) = 1 .6.4. Let us look ﬁrst at what can happen when the EXOR phase detector is used.H( f ). Sqq. its output phase jitter cannot be analyzed by the model used for the reference oscillator. 3. The spectrum of this signal would consist of a line at f = f0 and—as is normal for a rectangular signal—a number of harmonics.18.1) with divider ratio N = 1. Whereas the reference oscillator could be modeled by an ampliﬁer in the forward path and a resonator in the feedback. as shown in Fig.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved.out(fm) = PSD of output phase jitter due to VCO phase jitter.VCO ( fm ) 2 rad 2 Hz (3. however. from Eq. The theory on VCO phase jitter has another weak point.PLL Frequency Synthesizers PLL Frequency Synthesizers 145 Sqq. Under normal PLL operation. its output signal is a squarewave signal whose frequency is twice the reference frequency.VCO(fm) = PSD of phase jitter introduced by the VCO. Because the gain of every loop ﬁlter is nonzero at that frequency. a signal without any phase jitter. the phase detector delivers correction signals as soon as the phase of the VCO output signal deviates from the ideal phase.1 generates an output signal whose frequency is exactly N times the reference frequency. of course. this can lead to spurious sidebands in the VCO output signal.. The ripple signal modulates the output signal of the VCO. Under these conditions the output signal of the VCO would be a “pure” square wave.4. Any use is subject to the Terms of Use as given at the website. In a PLL frequency synthesizer (Fig. If an EXOR gate is used as phase detector.3 Reference feedthrough created by the phase detector The frequency synthesizer shown in Fig.1 where we stated that the loop bandwidth should be made small in order to reduce reference phase jitter. a ripple signal appears at the input of the VCO.digitalengineeringlibrary. 3. i. To minimize output phase jitter it would be optimum to make the PLL bandwidth as large as possible. which affects its spectral purity. The output signal of the loop ﬁlter would then be exactly zero. . If we assume that most of the VCO phase noise is ﬂicker noise. The effects of the ripple are different for the various types of phase detectors and must therefore be treated separately. and fm = frequency offset from center frequency f0.out ( fm ) = H e ( fm ) ◊ Sqq.

because now the instantaneous phase of the VCO output signal is modulated by a signal whose frequency is identical with the VCO frequency. Then the spectrum of the output signal contains lines at frequencies Nfref ± fref. it is sufﬁcient for practical purposes to have an approximation for the ﬁrst sideband. the frequency of the VCO output signal is Nfref.21) If the EXOR or the JK-ﬂipﬂop is used. etc. of course. Nfref ± 4fref. It is of vital interest. Fortunately the duration of the correction pulses is short when the PLL is locked. fr is identical with the reference frequency. when N becomes 2 and greater. . as shown in Fig. however.22) Here fr denotes ripple frequency. a logarithmic quantity S1(dB) is speciﬁed: S1(dB ) = 10 log S1 (3. When the JK-ﬂipﬂop is used.9). nothing happens again. 2. however. the ripple on the VCO input signal only alters the duty cycle of the VCO output signal but does not generate spurious sidebands. so positive and negative correction pulses will appear in succession.13b and c. Nfref ± 2fref. In analogy to noise signals. For the PFD another approximation has been found15: Downloaded from Digital Engineering Library @ McGraw-Hill (www. Under normal PLL operation. In the case of the EXOR gate. so the ripple on the VCO input signal will be much smaller than in the two former cases. For N = 3. and UB is the supply voltage of the phase detector. In the locked state the JK-ﬂipﬂop generates an output signal whose frequency is identical with the reference frequency (Fig. If the divider ratio of the frequency synthesizer is 1. The polarity of the correction pulses will change periodically. spurs will be created at the same frequencies.13a. For general N. fr equals twice the reference frequency. as shown in Fig.com) Copyright © 2004 The McGraw-Hill Companies. its output signal is theoretically in the 0 state. When N = 2. F(2pfr) is the gain of the loop ﬁlter at the ripple frequency.20) where Ps is the power of the synthesized signal and Psb1 is the power of the ﬁrst spurious sideband. however. etc. Spurious signals appear. 2. Because the amplitude of the ﬁrst pair of sidebands is always much greater than the amplitude of the higher ones. Any use is subject to the Terms of Use as given at the website. an approximation for S1(dB) is given by15 S1(dB ) = 20 log K 0U B F (2 pfr ) 2 p 2 fr (3. Mostly. All rights reserved. and the ripple signal has a fundamental frequency of 2fref. When the PFD is used as phase detector. when the VCO operates exactly on its center frequency.PLL Frequency Synthesizers 146 Chapter Three VCO frequency. If the multiplier phase detector is used instead of the EXOR.digitalengineeringlibrary. spurious sidebands appear at the VCO output whose frequencies are Nfref ± 2fref. to know the power of such sidebands. The situation is similar when the JK-ﬂipﬂop is used as phase detector. the PFD will output correction pulses. 2. sideband suppression S1 has been deﬁned as the quotient of signal power to the ﬁrst sideband power: S1 = Ps Psb1 (3. But adverse effects start as soon as N becomes 3 or larger.

3. The loop ﬁlter is also shown. the frequency of the VCO output signal will slowly drift away. (a) Schematic of the PFD including parasitic capacitor Cp. which causes a time lag between these two signals. t is the width of the correction pulses. The following consideration yields an approximation for the quantity t.digitalengineeringlibrary.PLL Frequency Synthesizers PLL Frequency Synthesizers 147 S1(dB ) = 20 log ( K 0U B t) F (2 pfr ) (3. Any use is subject to the Terms of Use as given at the website.20 The ﬁgure explains the backlash effect of the PFD and the effect of parasitic capacitance at the phase detector output. Because the logical circuits inside the PFD have nonzero propagation delays and rise times. the output signal of the PFD is theoretically in the 0 state all the time. The duration t1 of the output pulse cannot be less than the backlash interval. The reference signal u1 and the (scaled-down) output signal u2¢ (refer to Fig. the backlash is typically in the range of 2 to 3 ns. The PFD never generates an output pulse shorter than the backlash interval. All rights reserved.20a) would then be exactly in phase. It will produce a correction pulse only when the delay between the u1 and u2¢ signals has become greater than a time interval called backlash. Figure 3. In reality. (b) Waveform of the ud signal. which is denoted t1 here. as will be discussed in the following. for example. .com) Copyright © 2004 The McGraw-Hill Companies. The width of the u1 PFD u2' OUT ud R3 Cp R1 to VCO input R2 C (a) ud t1 ª 2 º 3ns +1 t2 ª Cp R1 0 t –1 (b) Figure 3. When this time lag is 10 ps. For high-speed CMOS circuits. When a PLL using the PFD as phase detector operates exactly on its center frequency. the PFD is never capable of generating such short pulses.23) Here the ripple frequency fr is not necessarily identical with the reference frequency but can be considerably lower. Downloaded from Digital Engineering Library @ McGraw-Hill (www. the PFD will theoretically generate a correction pulse whose duration is 10 ps as well.20b shows the PFD output signal ud that has been generated just at the instant where the positive edge of the u1 signal led the positive edge of u2¢ by an amount equal to the backlash.

The frequency of the ripple signal is therefore a subharmonic of the reference signal. the pulse as depicted in Fig.) In Chap. for a second-order ﬁlter. 3. 15. Thus t2 will also be in the order of 5 ns or more. One way would be to use a higher-order loop ﬁlter. the PFD is forced to generate positive correction pulses in every cycle of the reference signal. of course. 3.17) but stays constant.PLL Frequency Synthesizers 148 Chapter Three correction pulse is nearly equal to t1 in this case. that slope is reduced to -20 dB/decade. because we need a zero for reasons of stability. 3. however. There is still another way to eliminate subharmonic frequency modulation. Unfortunately. For a ﬁrst-order loop ﬁlter the gain at higher frequencies does not decay towards zero (see the magnitude response in Fig. parasitic capacitance Cp (Fig. each real device contains parasitic capacitances. using the formulas given in Ref. In the example of Fig. so the decay of that pulse will slow down. the ripple is not attenuated by the loop ﬁlter. The PFD will produce a correction pulse (of negative polarity).26) is approximately given by the sum t1 + t2 and is typically around 10 ns. Because the cutoff frequency of the loop ﬁlter is lower than the reference frequency in most cases.) This undesired subharmonic frequency modulation can be reduced in different ways. R1 must be higher than about 500 W. 4 we will deal with higher-order ﬁlters in more detail. With a higher-order ﬁlter. stays in the zero state during a number of succeeding cycles (perhaps 10). R3 is a high-value resistor that slowly but steadily discharges ﬁlter capacitor C toward ground. etc. . Because the correction pulses cannot be arbitrarily narrow. Choosing the cutoff frequency of the ﬁlter very much lower than the reference frequency does not bring any beneﬁt because the ﬁlter gain does not roll off toward zero. so that u2¢ leads u1 now.3. The time constant of the decay is approximately t2 = R1Cp. 2. the ripple signal will be Downloaded from Digital Engineering Library @ McGraw-Hill (www. and so forth.20b alters the instantaneous frequency of the VCO more than would normally be required. This is sketched in Fig. (It is possible to calculate approximately the subharmonic frequency.20a by the dashed resistor R3. Any use is subject to the Terms of Use as given at the website. Therefore. Usually the subharmonic frequency is about 1/20 the reference frequency. the time delay between the edges of the u1 and u2¢ becomes shorter in succeeding cycles of the reference signal. All rights reserved. The ripple frequency is now identical with the reference frequency. (3. In our example. which is undesirable.1 to 0. This means that the value of t in Eq.digitalengineeringlibrary. Normally. If the discharging current is higher than the charging current produced by the parasitic capacitance. This leads to the unhappy situation that the PFD generates a positive correction pulse at some instant. with a third-order ﬁlter the slope will be -40 dB/decade. Cp is in the order of 5 to 10 pF. only when the time lag exceeds the backlash again.20a) will charge to the supply voltage by the correction pulse. After some cycles the delay crosses zero and becomes negative. Typically. typically in the range 0. the slope of the magnitude response will be -20 dB/decade. because this would overload the PFD output.20b the frequency of the VCO is increased. It can be made small by selecting a low value for resistor R1. 3. produces a negative correction pulse then. (Note that the slope of a second-order ﬁlter without a zero would be -40 dB/decade. however. and if the frequency of this subharmonic is very low.com) Copyright © 2004 The McGraw-Hill Companies. but R1 cannot be chosen arbitrarily low. Typically. the gain will roll off toward zero.

The latter has a charge pump output as explained in Sec.21 for three cases: 1. hence the DN ﬂipﬂop would be set during an extremely short interval only.com) Copyright © 2004 The McGraw-Hill Companies. both current sources are turned on during at least 15 ns in every reference cycle. Any use is subject to the Terms of Use as given at the website. 3.. the timing of both current sources is modiﬁed such that the outputs of the upper and of the lower current source overlap during an interval of approximately 15 ns. The signal u1 leads the signal u2¢. which decreases the level of the spurious sidebands. 2.digitalengineeringlibrary. an EXOR and a PFD. Now assume that both positive transients of u1 and u2¢ occur at the 1 u1 u2¢ UP Tov DN 2 3 Figure 3. where Tov Ϸ 15 ns. All rights reserved. the DN ﬂipﬂop is also set unconditionally. i. . The shaded areas characterize the overlapping interval (Tov). 2. in the ﬁgure. In case 2. that both ﬂipﬂops remain in their high state for 15 ns after the leading edge of u2¢. The timing of the current outputs is demonstrated by Fig.21 Pulse timing of the PFD in the 74HCT9046A circuit. When resistor R3 is used. the leading edge of u2¢ ﬁrst sets the DN ﬂipﬂop. where u2¢ leads u1. Another way to force the PFD to output correction pulses in every reference cycle has been realized in the PFD that is incorporated in the integrated circuit type 74HCT9046A manufactured by Philips (see Sec. In a conventional PFD both ﬂipﬂops would be reset immediately by the AND gate that drives the CD (clear direct) inputs of the D ﬂipﬂops.7. Nfref ± 2fref. respectively. The signal u2¢ leads the signal u1. These cases are labeled 1.40c. etc. however.51 This IC contains two phase detectors.PLL Frequency Synthesizers PLL Frequency Synthesizers 149 attenuated by the loop ﬁlter. Delaying the reset action by about 15 ns makes sure. Now a similar thing happens: delaying the reset of both ﬂipﬂops by 15 ns lets both ﬂipﬂops set for about 15 ns after the leading edge of u1. com/products/plls/9046/. 2. 3.philipslogic.1). the leading edge of u1 unconditionally sets the UP ﬂipﬂop. Downloaded from Digital Engineering Library @ McGraw-Hill (www. On arrival of the leading edge of u2¢. The data sheet of the 74HCT9046A can be downloaded from http://www. Both positive edges of u1 and u2¢ occur at the same time.e. Both ﬂipﬂops are set now. With reference to Fig.7 and Table 10. the spurious sidebands occur at frequencies Nfref ± fref. and the UP ﬂipﬂop is set later on the leading edge of u1. 2. and 3. 2. In case 1.

which results in a net negative charge delivered to the loop ﬁlter.PLL Frequency Synthesizers 150 Chapter Three same time. assume that the positive edge of u2¢ is delayed by 1 ns against the positive edge of u1.com) Copyright © 2004 The McGraw-Hill Companies. hence the lower would conduct current for 16 ns. This demonstrates that even for the smallest time delay between the leading edges of u1 and u2¢ the PFD always feeds some charge into the loop ﬁlter. If the u2¢ signal would perform a positive transition 1 ns before the u1 signal. 2.digitalengineeringlibrary. In case of the 74HCT9046A. 1 ns later. The pulse widening due to parasitic capacitances (as shown in Fig.20) does not play any role for this type of PFD. From now on. the positive edge of u2¢ turns on the lower current source as well. This results in a net positive charge supplied to the loop ﬁlter. In a conventional PFD this time delay would fall below the backlash interval. 3. the upper current source in Fig.40c turns on on the positive edge of u1. Both ﬂipﬂops are set immediately. Consequently. the upper current source is on for 16 ns. both current sources would remain on during 15 ns. however. because both current sources are turned on in every reference cycle. . Any use is subject to the Terms of Use as given at the website. the upper for 15 ns. thus canceling the widening effect. and the lower for 15 ns. From this instant on. To demonstrate this. Downloaded from Digital Engineering Library @ McGraw-Hill (www. both current sources will be on for 15 ns. The upper current source would then turn on 1 ns later. hence the PFD would not perform any reaction. With this kind of PFD there is a guaranteed overlap of both current outputs in every reference cycle. and they remain set for about 15 ns. All rights reserved. This virtually inhibits the backlash effect as described for voltage output PFDs. the lower current source would be turned on ﬁrst.

Source: Phase-Locked Loops Chapter 4 Higher-Order Loops 4. All rights reserved. loop ﬁlters of order 2 or higher.e.17 the gain rolls off at -20 dB/dec at higher frequencies but asymptotically approaches a nonzero value for radian frequencies higher than 1/t2. but there is also a simple one.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. the phase shift can become larger than 180°. We will deal with stability of loops in the following section. the Bode plot. If the loop ﬁlter has two or more poles. A pole creates a phase shift of -90° at higher frequencies. i. and a zero creates a phase shift of +90°. 2 and 3 we considered mainly second-order PLLs. loop stability becomes an issue. 4.1 Motivation for Higher-Order Loops In Chaps.16. When the poles and the zeros are properly located the overall phase shift never comes close to -180°. Getting stable operation with a second-order PLL was easy because the open-loop transfer function had two poles and one zero. . 2. With higher-order loop ﬁlters. we recognized that reference frequency feedthrough becomes a problem. This goal was easily met by choosing time constant t2 of the loop ﬁlter such that a reasonable damping factor z was obtained.digitalengineeringlibrary. As can be seen from the Bode diagrams of the loop ﬁlter transfer functions in Fig. These loops used ﬁrst-order loop ﬁlters as shown in Fig. i.2 Analyzing Stability of Higher-Order Loops Control theory offers many mathematical methods for analyzing stability of feedback systems. 2. To reduce reference frequency feedthrough we must use higher-order loop ﬁlters.. In the discussion of spectral purity of PLL frequency synthesizers. where t2 is the time constant in the numerator of the ﬁlter transfer function (see Eqs. Some are sophisticated and mathematically demanding. hence the loop stays stable. 2. Spurious sidebands can be intolerable if the loop ﬁlter does not sufﬁciently attenuate ac components at the reference frequency (plus harmonics) that are created by the phase detector.28). hence the poles and zeros of the loop ﬁlter must be placed such that stability is maintained. Drawing a Bode plot is very easy 151 Downloaded from Digital Engineering Library @ McGraw-Hill (www.26 to 2.e..

All rights reserved.Higher-Order Loops 152 Chapter Four for systems like the PLL. the Bode diagram for G(s) is plotted. This is done by replacing s by jw and plotting magnitude and phase of G(w) versus radian frequency w.1 103 w1 104 w2 wT 105 w3 106 Radian frequency phase margin 103 104 Radian frequency 105 106 Analyzing loop stability by the Bode diagram. but linear on the phase axis. 2. Any use is subject to the Terms of Use as given at the website. the phase plot is logarithmic on the frequency axis. The asymptotic curve consists of line segments and is an approximation to the exact magnitude function. the exact (dashed curve) and the asympotitic diagram (solid curve) are shown. . we will demonstrate that by the example of a thirdorder PLL. 4.1. and it is assumed that T1 > T2 > T3. The corresponding loop ﬁlter has order two. T2. and T3 are time constants. The Bode plot is shown in Fig.1) where T1. Downloaded from Digital Engineering Library @ McGraw-Hill (www. The magnitude plot is logarithmic on both axes. the ﬁlter transfer function becomes F (s) = 1 + sT2 (1 + sT1 ) (1 + sT3 ) (4. The open-loop transfer function of a PLL built with this ﬁlter is given by G(s) = (1 + sT2 ) K0 K d N s(1 + sT1 ) (1 + sT3 ) (4.21). Assuming a passive lead-lag.com) Copyright © 2004 The McGraw-Hill Companies.digitalengineeringlibrary. The 100 Magnitude (dB) –20 dB/dec 50 Exact and Asymptotic Bode Diagrams –40 dB/dec –20 dB/dec 0 –40 dB/dec –50 102 –80 –100 Phase –120 –140 –160 –180 102 Figure 4. To analyze stability. In the magnitude plot.2) (also refer to the PLL model in Fig.

The system is stable if the phase of G(wT) is more positive than -180°. A simple computation shows that the phase function is maximum at a frequency wopt.digitalengineeringlibrary. this is the case for all practical PLLs. . would span some decades of frequency. Above w = w3.Higher-Order Loops Higher-Order Loops 153 magnitude plot has three corners at radian frequencies w1 = 1/T1. (A system is minimum phase if all the poles and zeros of its transfer function are in the left half of the s plane. the asymptotic value of phase becomes -90° because of the onset of the ﬁlters’ zero.48 w opt = w 2w 3 (4. In control engineering. At low frequencies the magnitude is dominated by the term 1/s. The closer the two frequencies w2 and w3 are to each other. It is clear that the phase in the range w2 < w < w3 would closely approach -90° when this region would be chosen larger. At the transition frequency the open-loop gain is exactly 1. Above w = w2. above w = w3 the asymptotic value of the phase becomes -180° again. the smaller the “peak” in the phase curve becomes. now the asymtpotic value of slope is increased to -40 dB/dec. etc.) Under this condition the phase approaches an asymptotic value of -90° when the slope of the magnitude plot is -20 dB/dec. and w3 = 1/T3. Finally. For minimum phase networks. Because the magnitude (gain) rolls off with 1/w.. which is the geometric mean of w2 and w3. 4.e. When the phase margin is very low (a few degrees only) the system is stable but heavily underdamped.1 the phase margin is about 55°. w2 = 1/T2. We note that the phase curve exhibits a “peak” between frequencies w2 and w3 and therefore has a local maximum at some distinct frequency within this range.2) causes the slope of the magnitude curve to bend up toward -20 dB/dec again. We see from the phase plot that the curve starts at -90° at low frequencies. The phase plot asymptotically approaches -180° if the magnitude slope is -40 dB/dec. the slope becomes -40 dB/dec because of the second pole of the loop ﬁlter. (4. The quantity 180° + j(wT) is called phase margin jm. it is therefore optimum to choose the transition frequency such that it is identical Downloaded from Digital Engineering Library @ McGraw-Hill (www. the corner at w2 by its zero. hence its transient response is oscillatory and dies out slowly. however. phase plot and magnitude plot are closely related. The term in the numerator of Eq. Let us denote that phase value by j(wT). In the example of Fig. Any use is subject to the Terms of Use as given at the website. For a proper PLL design it is important to know where the local maximum of the phase curve in the frequency range w2 < w < w3 really is. i. the dynamic response becomes aperiodic and can get sluggish. Above w = w1 the phase bends down towards -180°. The magnitude curve crosses the 0 dB line at a radian frequency named transition frequency wT.com) Copyright © 2004 The McGraw-Hill Companies. Now let us look at the phase plot. When the phase margin is too large. At w = w2 the zero of the ﬁlter becomes active.3) We wanted to have sufﬁcient phase margin at the transition frequency. one attempts to get phase margins between about 30 to 60°. The corners at w1 and w3 are created by the poles of the transfer function. All rights reserved. Above w = w1 the ﬁrst pole of the loop ﬁlter comes into play. however. the slope of the magnitude curve is -20 dB/dec (dec = decade of frequency).

The example in Fig. All these parameters. have about the same order. it can be shown that w3 dB Ϸ 2. i.33 (4.5 we will develop procedures for the design of loop ﬁlters for PLLs having order 3 to 5. This zero is placed exactly as demonstrated in the example of Fig. In our example we have chosen w2 = 31. hence wT is at 100.e.707. when doing so. The gain roll-off at higher frequencies has a slope which is given by S = 20(nz . we get sufﬁcient phase margin to provide stable operation. . Any use is subject to the Terms of Use as given at the website.g. the number of zeros should be chosen as small as possible. for example. This is a consequence of the fact that we always try to shape the magnitude plot so that its magnitude curve crosses the 0-dB line with a slope of about -20 dB/dec. e. Consequently the loop design should start with an initial value for wT. only one zero is chosen.3 to 1. the poles and the zero of the system have been placed with reference to the transition frequency wT.5. the open-loop transfer function G(s) has 5 poles and may also have up to 5 zeros. When building PLL with order higher than 3.55 wn. 4. including wT. As we have seen. Because the natural frequency is deﬁned only for second-order systems (in a strict sense). In Sections 4.5) Experience has shown that this ratio stays nearly unchanged for higher-order PLLs. 5 a computer program will be presented that allows design of mixed-signal PLLs up to order 5 (and all-digital PLLs) automatically.600 s-1 and w3 = 316.1. 4. w3 dB [the 3-dB closed-loop bandwidth of H(w)]. In case of a ﬁfth-order PLL. What we need now is a mathematical relation between w3 dB and wT.1..000 s-1. hence the ratio w3 dB/wT is mostly in the range 1. BL (the noise bandwidth of the loop). Because we want the gain to roll off with maximum slope.4) where nz = number of zeros and np = number of poles of G(s). In most higher-order PLL designs. This will be described in the following sections.3 to 4. additional poles have to be placed at frequencies above w3 in Fig. and wn (the natural frequency).com) Copyright © 2004 The McGraw-Hill Companies. Often w3 dB is chosen to be around 1/20 the (scaled-down) center frequency w0¢. There are a number of parameters related to bandwidth. All rights reserved. All of these methods can be automated.n p ) dB (4. are close together. in Chap. Hence we have w T ª w 3dB 1. Usually the designer of a PLL has an idea about the desired loop bandwidth. The poles at higher frequencies than wT then have little inﬂuence on the Bode plot in the vicinity of wT. This is a software tool developed by the author and is distributed with the book.1 was related to a third-order PLL.digitalengineeringlibrary..Higher-Order Loops 154 Chapter Four with wopt.06 wn and wT Ϸ 1.000 s-1. it seems more practical to start by setting w3 dB. Downloaded from Digital Engineering Library @ McGraw-Hill (www. 4. additional poles (and eventually zeros) must be placed. If the system has higher order than 3. In real higher-order PLL designs it has proved useful to set the ratio w3/w2 approximately to 10. For a second-order high-gain loop with z = 0.

an active lead-lag. it is more convenient to write this function in factorized form: F (s) = 1 + sT2 (1 + sT1 ) (1 + sT3 ) (4.com) Copyright © 2004 The McGraw-Hill Companies. Downloaded from Digital Engineering Library @ McGraw-Hill (www. a passive lead-lag.6) with t1 = R1C1. It has proved most convenient to proceed as described in the following steps: Step 1.3. and w3. To place the poles and zeros of the PLL’s open-loop transfer function G(s).digitalengineeringlibrary. Its transfer function is F (s) = 1 + s(t 2 + t 3 ) 1 + s(t 1 + t 2 + t 3 ) + s2 t 1 t 3 (4.Higher-Order Loops Higher-Order Loops 155 4.1 Passive lead-lag loop ﬁlter The schematic of this ﬁlter is shown in Fig.8) To get the Bode diagram we set s = jw and plot the magnitude |G(w)| versus radian frequency w. and an active PI ﬁlter. t3 = R2C2.2 Second-order passive lead-lag loop ﬁlter. w2. In this section we describe three variants of a second-order loop ﬁlter. the transition frequency wT must be known ﬁrst.3 Designing Third-Order PLLs In a third-order PLL. 4. Normally the designer knows what should be the bandwidth of the PLL. All rights reserved.3. We start the discussion with the passive lead-lag. a second-order loop ﬁlter must be chosen.2. hence it is reasonable to start by choosing a value for w3 dB. Any use is subject to the Terms of Use as given at the website. 4. To determine the corner frequencies w1. This is shown by Fig. t2 = R2C1. 4.7) The open-loop transfer function of the third-order PLL then becomes G(s) = 1 + sT2 K0 K d Ns (1 + sT1 ) (1 + sT3 ) (4. A default value R1 R2 C2 C1 Figure 4. .

Any use is subject to the Terms of Use as given at the website. max = K0 K d N (4. however. Now the corner frequency w1 must be chosen such that the open-loop gain at transition frequency wT bcomes 1. Using the approximation in Eq.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. To get sufﬁcient phase margin. it is recommended to set w 3 = w T 10 w2 = w T 10 Step 4. Step 2. (4. Step 3. With the passive lead-lag ﬁlter there is an upper limit for wT.5) we compute wT = w3 dB/1.33. could by w3 dB = 0.05 · w0¢. . This leads to w1 = K0 K d Nw T (4. (4. where w0¢ is the down-scaled center (radian) frequency of the PLL. this later results in a negative value for t1 [see Eq.Higher-Order Loops 156 Chapter Four G (dB) –20 –40 –20 w1 w2 wT w3 w (log) –40 Figure 4.digitalengineeringlibrary. hence that ﬁlter would be unrealizable.10) Downloaded from Digital Engineering Library @ McGraw-Hill (www. Next the corner frequencies w2 and w3 are chosen.9) When a larger value of wT is speciﬁed.3 Bode diagram (magnitude plot) of a third-order PLL using the passive lead-lag loop ﬁlter. which is given by w T.6)].

12) Step 8. we certainly want to know what is the effect on the quantities T1.t 2 (4. (4. t3 = R2C3. T3. When solving the Eqs.digitalengineeringlibrary. t2. It should be set such that “reasonable” values for the resistors are obtained. in the region of about 1 to 100 kW.11) Step 7. i. T2. T3 = 1/w3. t2 = R2C2.4.Higher-Order Loops Higher-Order Loops 157 Step 5. Given T1.13) with t1 = R1C1. T3.. w2. i. t3 now. Because we must determine the corner frequencies of the Bode plot. T2.6) and (4.T2 t 3 = T2 .com) Copyright © 2004 The McGraw-Hill Companies. t3. t2. and Ka = C1/C2. . C) are computed from the values for t1. Step 6. 4. T3 are computed from T1 = 1/w1. Any use is subject to the Terms of Use as given at the website.7) we get t 1 = T1 + T3 .2 Active lead-lag loop ﬁlter The schematic of a second-order active lead-lag ﬁlter is shown in Fig. T2 = 1/w2. t2. on the corner frequencies w1. w3 in the magnitude plot. (Optional) There are cases where the designer modiﬁes the values for t1. By comparison of coefﬁcients in Eqs. The transfer function for this ﬁlter is given by F (s) = K a 1 + s(t 2 + t 3 ) (1 + st 1 ) (1 + st 3 ) (4.. t3 from an earlier design.4 t 1 t 3 T1 = 2 T2 = t 2 + t 3 t1 t 3 T3 = T1 2 (4. (4. t3 or adopts the values for t1.e.e. it is more convenient to write F(s) in the standardized form as F (s) = K a 1 + sT2 (1 + sT1 ) (1 + sT3 ) (4. (4. T2. The value of C1 can be chosen arbitrarily.3. All rights reserved.6)].T2 T1T3 t 2 = T2 T1 + T3 . The time constants T1. T3 we can calculate the ﬁlter time constants t1.14) The open-loop gain of the third-order PLL then reads Downloaded from Digital Engineering Library @ McGraw-Hill (www. 4. we get t 1 + t 2 + t 3 + (t 1 + t 2 + t 3 ) . When these parameters have been directly set or altered.11) for T1. [see Eq. Finally the ﬁlter components (R. t2. T2.

15) For this design the procedure is very similar to that for the passive lead-lag ﬁlter. it is recommended to set w 3 = w T 10 w2 = w T 10 Step 2. there is no mathematical restriction on the size of wT here. To get sufﬁcient phase margin. In contrast to the passive lead-lag ﬁlter.5) we compute wT = w3 dB/1.05w0¢. Using the approximation in Eq. . The design steps are as follows: Step 1. It is recommended to set w1 = w2/10. For Ka we get Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.33. Next the corner frequencies w2 and w3 are chosen. Step 3. The Bode plot in Fig. thus the open-loop gain rolls off with -40 dB/dec over one full decade of frequency.com) Copyright © 2004 The McGraw-Hill Companies. 4.4 Schematic of the second-order active lead-lag ﬁlter. which always can be speciﬁed such that the open-loop gain becomes 1 at the transition frequency wT. All rights reserved. hence it is reasonable to start by choosing a value for w3 dB. Step 4. because we have an additional parameter Ka. Normally the designer knows what should be the bandwidth of the PLL. Ka must be chosen such that the open-loop gain just becomes 1 at wT. G(s) = 1 + sT2 K0 K d K a (1 + sT1 ) (1 + sT3 ) Ns (4.Higher-Order Loops 158 Chapter Four C3 R1 C1 C2 R2 Figure 4. (4. A default value could be w3 dB = 0. where w0¢ is the down-scaled center (radian) frequency of the PLL.3 remains valid for this type of loop ﬁlter. Any use is subject to the Terms of Use as given at the website.

t3 or adopts the values for t1. t2.3. It should be set such that “reasonable” values for the resistors are obtained. By comparison of coefﬁcients in Eqs. . Any use is subject to the Terms of Use as given at the website. t3 from an earlier design. (Optional) There are cases where the designer modiﬁes the values for t1.13) and (4. t2 = R2C1.17) for T1. The transfer function of this ﬁlter is given by F (s) = 1 + s(t 2 + t 3 ) st 1 (1 + st 3 ) (4. All rights reserved. 4.16) The time constants T1.T3 t 3 = T3 (4. T3 we get T1 = t 1 T2 = t 2 + t 3 T3 = t 3 (4. the corner frequencies w1. T3 we can calculate the ﬁlter time constants t1. T2. t3 now. and t3 = R2C2. i. (4. T3.. T2. When solving the Eqs. Finally the ﬁlter components (R.18) Step 8.20) The open-loop gain of the third-order PLL then reads Downloaded from Digital Engineering Library @ McGraw-Hill (www.19) with t1 = R1C1. 10 Nw T K0 K d (4. w3 in the magnitude plot. The value of C1 can be chosen arbitrarily. T3 are computed from T1 = 1/w1.e. Given T1. it is more convenient to write F(s) in the standardized form as F (s) = 1 + sT2 sT1 (1 + sT3 ) (4. t2. Because we must determine the corner frequencies of the Bode plot. w2. T2 = 1/w2. T3 = 1/w3. 4. When these parameters have been directly set or altered. (4. i. T2. t2. t2.e.Higher-Order Loops Higher-Order Loops 159 Ka = Step 5.com) Copyright © 2004 The McGraw-Hill Companies. it may be desirable to know also the values for T1. T2.5.3 Active PI loop ﬁlter The schematic of a second-order active PI ﬁlter is shown in Fig.digitalengineeringlibrary. C) are computed from the values for t1. Step 6. t3. in the region of about 1 to 100 kW..14) we get t 1 = T1 t 2 = T2 .17) Step 7.

All rights reserved. A default value Downloaded from Digital Engineering Library @ McGraw-Hill (www. G (dB) –40 0 w2 –20 wT w3 w (log) –40 Bode plot of third-order PLL using the active PI loop ﬁlter.6 G(s) = K 0 K d 1 + sT2 Ns sT1 (1 + sT3 ) (4. Any use is subject to the Terms of Use as given at the website. 4. Figure 4.Higher-Order Loops 160 Chapter Four C2 R1 C1 R2 Figure 4.6. Step 1.com) Copyright © 2004 The McGraw-Hill Companies.5 Schematic of second-order active PI loop ﬁlter.21) The Bode plot (magnitude) for this system is shown in Fig. hence it is reasonable to start by choosing a value for w3 dB. .digitalengineeringlibrary. Normally the designer knows what should be the bandwidth of the PLL.

T2.24) Step 8. (4. it becomes desirable to know the effect on the values for T1. Finally the ﬁlter components (R. t3. t2..digitalengineeringlibrary. Downloaded from Digital Engineering Library @ McGraw-Hill (www. in the region of about 1 to 100 kW. T3 we get T1 = t 1 T2 = t 2 + t 3 T3 = t 3 (4.5). It should be set such that “reasonable” values for the resistors are obtained.23) for T1. Step 4. T3.e. where w0¢ is the down-scaled center (radian) frequency of the PLL. t3 or adopts the values for t1. (4.23) Step 7. Parameter T1 is chosen such that the open-loop gain is 1 at w = wT. t3 from an earlier design. i. T2. . The value of C1 can be chosen arbitrarily. This leads to T1 = K0 K d Nw 2 2 10 (4. By comparison of coefﬁcients in Eqs. T2. There is no mathematical restriction on the size of wT. Any use is subject to the Terms of Use as given at the website.e. Step 6. Given T1. C) are computed from the values for t1. i. t2.05w0¢. it is recommended to set w 3 = w T 10 w2 = w T 10 Step 3.T3 t 3 = T3 (4.20) we get t 1 = T1 t 2 = T2 .22) Step 5. t2. (4. because the parameter T1 can be chosen such that the open-loop gain becomes 1 at w = wT. When these parameters have been directly set or altered. Using the approximation in Eq. t2. All rights reserved. To get sufﬁcient phase margin. T3 are computed from T2 = 1/w2 and T3 = 1/w3. T3 we can calculate the ﬁlter time constants t1. (Optional) There are cases where the designer modiﬁes the values for t1.33. When solving the Eqs. Step 2. we compute wT = w3 dB/1. t3 now.19) and (4. Next the corner frequencies w2 and w3 are chosen.com) Copyright © 2004 The McGraw-Hill Companies.Higher-Order Loops Higher-Order Loops 161 could be w3 dB = 0. The time constants T2. on the corner frequencies w2 and w3 in the magnitude plot..

an active lead-lag. When the poles of the second ﬁlter section are real.7 Third-order active lead-lag ﬁlter. 4.com) Copyright © 2004 The McGraw-Hill Companies. Section 2 is a second-order low-pass ﬁlter. For the open-loop transfer function G(s) of R4 R1 C1 C2 R2 R4 C5 R5 C4 Figure 4. To get complex poles with this kind of ﬁlter. 2). Section 1 is a ﬁrst-order lead-lag ﬁlter and is identical with the ﬁlter used to build secondorder PLLs (see Chap. but all the poles are located on the negative real axis in the s plane. and Ka = C1/C2. Any use is subject to the Terms of Use as given at the website. All these ﬁlters will have three poles. Most designers try to avoid inductors in ﬁlter design and resort to active RC ﬁlters. All rights reserved. t2 = R2C2. It can be realized with two real poles or with a complex-conjugate pole pair.1 Active lead-lag loop ﬁlter Third-order ﬁlters can be realized in many ways. The ﬁlter consists of two sections. it is more practical to use a different notation for F(s): F (s) = K a 1 + st 2 ◊ 1 + st 1 1 2 sz s s2 1+ + 2 ws ws (4.4. A passive lead-lag ﬁlter built from resistors and capacitors cannot realize complex poles. For this reason we will drop the passive lead-lag ﬁlter and use active ﬁlters exclusively. .digitalengineeringlibrary.4 Designing Fourth-Order PLLs To obtain a fourth-order PLL we must use a third-order loop ﬁlter.Higher-Order Loops 162 Chapter Four 4. it is most convenient to write the ﬁlter’s transfer function F(s) in the form F (s) = K a 1 + st 2 1 ◊ 1 + st 1 (1 + st 3 ) (1 + st 4 ) (4. It is common practice to build third-order ﬁlters that have a complex-conjugate pole pair.25a) with t1 = R1C1. we would have to use inductors. Downloaded from Digital Engineering Library @ McGraw-Hill (www. or an active PI ﬁlter.25b) In the second case ws is the natural frequency and zs the damping factor of the second-order frequency response. When the poles of the second ﬁlter section form a complex pair. One version of a third-order lead-lag ﬁlter is shown in Fig. 4.7. Of course such a ﬁlter can be realized as a passive lead-lag.

It includes the following steps: G (dB) –20 –40 –20 w1 w2 wT w3 w4 ws w (log) –40 –60 –60 Figure 4.8. All rights reserved.26a) For complex poles.Higher-Order Loops Higher-Order Loops 163 the fourth-order PLL we get two versions.digitalengineeringlibrary. Downloaded from Digital Engineering Library @ McGraw-Hill (www. G(s) reads G(s) = 1 K 0 K d K a 1 + st 2 ◊ ◊ 1 + st 1 (1 + st 3 )(1 + st 4 ) Ns K 0 K d K a 1 + st 2 ◊ ◊ 1 + st 1 Ns (4. At w3 and at w4 the slope of the magnitude curve increases by -20 dB/dec.8 shows. however. We now have to provide a procedure for placing the poles and the zero of the third-order ﬁlter. For real poles.com) Copyright © 2004 The McGraw-Hill Companies. 4. At this point the slope increases by -40 dB/dec. The dashed curve shows the case where these poles form a complex pair. G(s) reads G(s) = 1 2 sz s s2 1+ + 2 ws ws (4. . one for real poles and one for complex poles. The solid curve represents the case where the poles of the second-order ﬁlter are real. 4. When the poles of the second ﬁlter section are complex.26b) Let us look at the magnitude plot now. Fig. there is only one additional break point at ws. as Fig. Any use is subject to the Terms of Use as given at the website. Suppose for the moment that the poles of the second ﬁlter section are real and located at s = -w3 and s = -w4. Then that ﬁlter section creates the two corners at w3 and w4.8 Bode plot for the fourth-order PLL. The ﬁrst ﬁlter section has a pole at s = -w1 and a zero at s = -w2 and therefore provides the break points of the asymptotic magnitude plot at w1 and w2.

A default value could be w3 dB = 0.707.28) Downloaded from Digital Engineering Library @ McGraw-Hill (www. (Complex poles) We must choose a suitable value for natural frequency ws and damping factor zs. It should be set such that we obtain “reasonable” values for the resistors. Using the approximation in Eq. For Ka we get Ka = 10 Nw T K0 K d (4. because we have an additional parameter Ka.33. it is recommended to set w2 = w T 10 Step 2. It is recommended to set w1 = w2/10. hence it is reasonable to start by choosing a value for w3 dB. Step 6. t2 = 1/w2. Step 3. Given ws and zs we can determine the elements (R. Next we must calculate the parameters of the second section.05w0¢. hence we set ws = 5wT.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. in the range 1 to 100 kW.27) Step 5. For zs it is optimum to set zs = 0. The remaining components are computed from C5 = R4 = 2C4 z2 s 2 2 s w C4 C5 R4 R5 = 2 (4. Step 4. To get sufﬁcient phase margin. C4 can be chosen arbitarily. C) of the second ﬁlter section. When complex poles are desired. . The procedure depends on the type of poles.Higher-Order Loops 164 Chapter Four Step 1. The parameters of ﬁlter section 1 are determined now. where w0¢ is the down-scaled center (radian) frequency of the PLL. Step 7. Because there are more unknown elements than equations.digitalengineeringlibrary. thus the open-loop gain rolls off with -40 dB/dec over one full decade of frequency. Normally the designer knows what should be the bandwidth of the PLL. it continues with step 6. The time constants t1 and t2 are computed from t1 = 1/w1. (4. Ka must be chosen such that the open-loop gain just becomes 1 at wT. Experience shows that sufﬁcient phase margin is obtained if ws is placed at 5wT. There is no mathematical restriction on the size of wT here. i. which always can be speciﬁed such that the open-loop gain becomes 1 at the transition frequency wT. All rights reserved. Next the corner frequency w2 is chosen.5) we compute wT = w3 dB/1. otherwise with step 8..e.

To determine the elements of section 2. it is most practical to convert the ﬁlter function in Eq. we now can compute the R and C values using Eqs. . one for real poles and one for complex poles. When the poles of the second ﬁlter section form a complex pair. (Real poles) We must choose values for the break frequencies w3 and w4 now.25a) and (4.8. Step 9. Section 1 is a ﬁrstorder PI ﬁlter that has one pole at s = 0 and one zero at s = -w2. This ﬁlter also consists of two sections.29) Given ws and zs.com) Copyright © 2004 The McGraw-Hill Companies. One version is shown in Fig. 4. or they can form a complex pair.25a) into the ﬁlter function given in Eq. Downloaded from Digital Engineering Library @ McGraw-Hill (www. (4.e. Comparing coefﬁcients in Eqs. we will also use two forms for the ﬁlter transfer function F(s). It is recommended to set w3 = wT 10 and w4 = 5w3. (4.digitalengineeringlibrary. it is more practical to use a different notation for F(s): F (s) = 1 + st 2 ◊ st 1 1 2 sz s s2 1+ + 2 ws ws (4.2 Active PI loop ﬁlter Third-order active PI ﬁlters can be implemented in many ways. see Fig.4. They can be either on the negative real axis in the s plane..Higher-Order Loops Higher-Order Loops 165 Step 8. (4. We now can determine t3 = 1/w3 and t4 = 1/w4. 4. Section 2 has two poles. i. Any use is subject to the Terms of Use as given at the website. As was done previously.25b) yields 1 t3t4 t3 + t4 zs = 2 t3t4 ws = (4. For the case of real poles F(s) is given by F (s) = 1 + st 2 1 ◊ (1 + st 3 ) (1 + st 4 ) st 1 (4.9.30a) with t1 = R1C1 and t2 = R2C1.9 Third-order active PI loop ﬁlter.28). 4.30b) R1 C1 R4 R2 R4 R5 C4 C5 Figure 4. (4.25b). we would compute ws and zs from given w3 and w4. All rights reserved.

When the poles of G (dB) –40 0 w2 –20 wT w3 w4 ws w (log) –40 –60 –60 Figure 4. For the open-loop transfer function G(s) of the fourth-order PLL we again get two versions. At w3 and at w4 the slope of the magnitude curve increases by -20 dB/dec.31b) Let us have a look on the magnitude plot now. 4. The dashed curve shows the case where these poles form a complex pair. The solid curve represents the case where the poles of the second-order ﬁlter are real. Fig. For real poles. Any use is subject to the Terms of Use as given at the website. .Higher-Order Loops 166 Chapter Four In the second case ws is the natural frequency and zs the damping factor of the second-order frequency response. G(s) reads G(s) = 1 2 sz s s2 1+ + 2 ws ws (4.digitalengineeringlibrary. one for real poles and one for complex poles. 4.31a) For complex poles. Suppose for the moment that the poles of the second ﬁlter section are real and located at s = -w3 and s = -w4.10. Then that ﬁlter section creates the two corners at w3 and w4.com) Copyright © 2004 The McGraw-Hill Companies. as in Fig. Downloaded from Digital Engineering Library @ McGraw-Hill (www. All rights reserved.10 Bode plot (magnitude) of fourth-order PLL. G(s) reads G(s) = 1 K 0 K d 1 + st 2 ◊ ◊ (1 + st 3 )(1 + st 4 ) Ns st 1 K 0 K d 1 + st 2 ◊ ◊ Ns st 1 (4. The ﬁrst ﬁlter section has a pole at s = 0 and a zero at s = -w2 and therefore provides the breakpoint of the asymptotic magnitude plot at w2.10.

Higher-Order Loops Higher-Order Loops 167 the second ﬁlter section are complex. in the range 1 to 100 kW.digitalengineeringlibrary. The parameters of ﬁlter section 1 are determined now. A default value could be w3 dB = 0. hence we set ws = 5wT. It should be set such that we obtain “reasonable” values for the resistors. where w0¢ is the down-scaled center (radian) frequency of the PLL. This t1 = K0 K d Nw 2 2 10 leads to (4. When complex poles are desired. (Complex poles) We must choose a suitable value for natural frequency ws and damping factor zs. The remaining components are computed from Step 7. It includes the following steps: Step 1. we compute wT = w3 dB/1.e. All rights reserved.33. Step 3. At this point the slope increases by -40 dB/dec.. there is only one additional break point at ws. There is no mathematical restriction on the size of wT here. i. Using the approximation in Eq. For zs it is optimum to set zs = 0. C4 can be chosen arbitarily.707. it continues with step 6. Experience shows that sufﬁcient phase margin is obtained if ws is placed at 5wT. .32) Time constant t2 is computed from t2 = 1/w2. The procedure depends on the type of poles. hence it is reasonable to start by choosing a value for w3 dB. We now have to provide a procedure for placing the poles and the zero of the third-order ﬁlter. Downloaded from Digital Engineering Library @ McGraw-Hill (www. it is recommended to set w2 = w T 10 Step 4. however. Given ws and zs we can determine the elements (R. Step 6. C) of the second ﬁlter section. To get sufﬁcient phase margin.com) Copyright © 2004 The McGraw-Hill Companies. otherwise with step 8. Any use is subject to the Terms of Use as given at the website. Step 2. Parameter t1 is chosen such that the open-loop gain is 1 at w = wT. Step 5. Normally the designer knows what should be the bandwidth of the PLL.5). Because there are more unknown elements than equations.05w0¢. Next the corner frequency w2 is chosen. because time constant t1 can be set such that the open-loop gain becomes 1 at the transition frequency wT. Next we must calculate the parameters of the second section. (4.

we must select a fourth-order loop ﬁlter.digitalengineeringlibrary. t3 = R2C3.30b).30a) and (4. it is more practical to use a different notation for F(s). All rights reserved. and Ka = C1/C2. see Fig. 4. The ﬁlter consists of two sections.10.34) Given ws and zs.11. (4.5 Designing Fifth-Order PLLs When designing a ﬁfth-order PLL. One version of a fourth-order lead-lag ﬁlter is shown in Fig.33) (Real poles) We must choose values for the break frequencies w3 and w4 now. it is most practical to convert the ﬁlter function in Eq. 4. Section 2 is a second-order low-pass ﬁlter.30a) into to ﬁlter function given in Eq. 4. such as Downloaded from Digital Engineering Library @ McGraw-Hill (www. The procedure is simular to that applied for the fourth-order PLL. we use active ﬁlters exclusively. The poles are located at s = -w1 and s = -w3. we would compute ws and zs from given w3 and w4. (4.35a) with t1 = R1C1. When the poles of the second ﬁlter section are real. It has two poles on the real axis in the s plane and one zero. .. We now can determine t3 = 1/w3 and t4 = 1/w4. 4. (4.Higher-Order Loops 168 Chapter Four C5 = R4 = 2C4 z2 s 2 2 s w C4 C5 R4 R5 = 2 Step 8. Any use is subject to the Terms of Use as given at the website. As in case of the fourth-order PLL. t2 = R2C2. (4.1 Active lead-lag loop ﬁlter Fourth-order ﬁlters can be realized in many ways. i. It is recommended to set w3 = wT 10 and w4 = 5w3. it is most convenient to write the ﬁlter’s transfer function F(s) in the form F (s) = K a 1 + s(t 2 + t 3 ) 1 ◊ (1 + st 1 ) (1 + st 3 ) (1 + st 4 ) (1 + st 5 ) (4. Section 1 is a second-order lead-lag ﬁlter. the zero is at s = -w2.com) Copyright © 2004 The McGraw-Hill Companies.5. To determine the elements of section 2.e. Step 9. Comparing coefﬁcients in Eqs. It can be realized with two real poles or with a complex-conjugate pole pair.33). (4. we now can compute the R and C values using Eqs.30b) yields 1 t3t4 t3 + t4 zs = 2 t3t4 ws = (4. When the poles of the second ﬁlter section form a complex pair.

it is more convenient to write Eqs.12. we get two versions. one for real poles and one for complex poles. 4. F (s) = K a 1 + s(t 2 + t 3 ) ◊ (1 + st 1 ) (1 + st 3 ) 1 2 sz s s2 1+ + 2 ws ws (4.35a) and (4. For real poles.com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. It therefore provides the Downloaded from Digital Engineering Library @ McGraw-Hill (www.36d) Let us look at the magnitude plot now.digitalengineeringlibrary.Higher-Order Loops Higher-Order Loops 169 C3 R4 R1 C1 C2 R2 R4 R5 C5 C4 Figure 4. G(s) reads G(s) = 1 1+ 2 sz s s2 + 2 ws ws (4. G(s) reads G(s) = 1 + sT2 1 K0 K d K a ◊ ◊ (1 + sT1 )(1 + sT3 ) (1 + st 4 )(1 + st 54 ) Ns 1 + sT2 K0 K d K a ◊ ◊ (1 + sT1 )(1 + sT3 ) Ns (4.36c) For complex poles. Any use is subject to the Terms of Use as given at the website. . Fig. For the real poles we get F (s) = K a 1 + sT2 1 ◊ (1 + sT1 )(1 + sT3 ) (1 + st 4 )(1 + st 5 ) 1 + sT2 ◊ (1 + sT1 )(1 + sT3 ) (4.36b) For the open-loop transfer function G(s) of the fourth-order PLL.35b) In the second case ws is the natural frequency and zs the damping factor of the second-order frequency response.11 Fourth-order active lead-lag ﬁlter.35b) in standardized form. Because we want to determine break frequencies (corners) in the asymptotic magnitude plot.36a) and for the complex poles we have F (s) = K a 1 1+ 2 sz s s2 + 2 ws ws (4. (4. The ﬁrst ﬁlter section has poles at s = -w1 and s = -w3 and a zero at s = -w2.

breakpoints of the asymptotic magnitude plot at w1. Step 2. Normally the designer knows what should be the bandwidth of the PLL. The solid curve represents the case where the poles of the second ﬁlter section are real. When the poles of the second ﬁlter section are complex. and w3. At w4 and at w5 the slope of the magnitude curve increases by -20 dB/dec. there is only one additional breakpoint. w2. Using the approximation in Eq. We now have to provide a procedure for placing the poles and the zero of the fourth-order ﬁlter.33. as in Fig.digitalengineeringlibrary. A default value could be w3 dB = 0. It includes the following steps: Step 1. because we have an additional parameter Ka. Downloaded from Digital Engineering Library @ McGraw-Hill (www. The dashed curve shows the case where these poles form a complex pair. where w0¢ is the down-scaled center (radian) frequency of the PLL. (4.12 Bode plot for the ﬁfth-order PLL. Suppose for the moment that the poles of the second ﬁlter section are real and located at s = -w4 and s = -w5. Then that ﬁlter section creates the two corners at w4 and w5. Any use is subject to the Terms of Use as given at the website. There is no mathematical restriction on the size of wT. All rights reserved. At this point the slope increases by -40 dB/dec.5) we compute wT = w3 dB/1. which always can be speciﬁed such that the open-loop gain becomes 1 at the transition frequency wT.12. hence it is reasonable to start by choosing a value for w3 dB. however. . 4. at ws.05w0¢.Higher-Order Loops 170 Chapter Four G (dB) –20 –40 –20 0 w1 w2 wT w3 w4 w5 w (log) ws –40 –40 –60 –80 –80 Figure 4.com) Copyright © 2004 The McGraw-Hill Companies.

T3 t 3 = T3 Step 7. To realize section 1 of the ﬁlter we must also know the time constants t1. otherwise with step 10. t3 and wants to know what is the effect on the quantities T1.com) Copyright © 2004 The McGraw-Hill Companies. It is recommended to set w1 = w2/10. T2. C4 can be chosen arbitarily. Step 8. Step 9. it is recommended to set w2 = w T 10 w 3 = w T 10 Step 4. T2. The procedure depends on the type of poles.Higher-Order Loops Higher-Order Loops 171 Step 3. It should be set such that we obtain “reasonable” values for the resistors. T3 are then computed from t1. All rights reserved. t2. Step 6. t3 as follows: T1 = t 1 T2 = t 2 + t 3 T3 = t 3 The parameters of ﬁlter section 1 are determined now. Any use is subject to the Terms of Use as given at the website. The time constants T1. T3. and T3 are computed from T1 = 1/w1. in the range 1 to 100 kW. C) of the second ﬁlter section.38) (Optional) Sometimes the designer alters the values t1. (4. For Ka we get Ka = 10 Nw T K0 K d (4. and t3. Given ws and zs we can determine the elements (R..707. T2 = 1/w2. t2. The variables T1.digitalengineeringlibrary.e. Downloaded from Digital Engineering Library @ McGraw-Hill (www.37) Step 5. thus the open-loop gain rolls off with -40 dB/dec over one full decade of frequency. T2. and T3 = 1/w3. Next the corner frequencies w2 and w3 are chosen. To get sufﬁcient phase margin. Because there are more unknown elements than equations. When complex poles are desired. t2. i. Ka must be chosen such that the open-loop gain just becomes 1 at wT. Experience shows that sufﬁcient phase margin is obtained if ws is placed at 5wT. .39) (Complex poles) We must choose a suitable value for natural frequency ws and damping factor zs. Next we must calculate the parameters of the second section. For zs it is optimum to set zs = 0. it continues with step 8. (4. They are computed from t 1 = T1 t 2 = T2 . hence we set ws = 5wT.

digitalengineeringlibrary. (4. It has two poles. Any use is subject to the Terms of Use as given at the website. we would compute ws and zs from given w4 and w5.13. 4.41) Given ws and zs. It is recommended to set w4 = 5w3 and w5 = 5w4.35a) and (4. we now can compute the R and C values using Eqs. We now can determine t4 = 1/w4 and t5 = 1/w5.40). 4.35b). i. One version is shown in Fig.12. All rights reserved.5. Comparing coefﬁcients in Eqs.35b) yields 1 t4 t5 t4 + t5 zs = 2 t4 t5 ws = (4. . To determine the elements of section 2.40) 2 (Real poles) We must choose values for the break frequencies w4 and w5 now. Step 11.35a) into the ﬁlter function given in Eq.. (4. (4.2 Active PI loop ﬁlter Fourth-order active PI ﬁlters can be implemented in many ways.13 Fourth-order active PI loop ﬁlter. it is most practical to convert the ﬁlter function in Eq. Section 1 is a secondorder PI ﬁlter. see Fig.com) Copyright © 2004 The McGraw-Hill Companies. (4.e.Higher-Order Loops 172 Chapter Four The remaining components are computed from C5 = R4 = R5 = Step 10. Section 2 is a C2 R4 R1 C1 R2 R4 C5 R5 C4 Figure 4. The ﬁlter consists of two sections. Downloaded from Digital Engineering Library @ McGraw-Hill (www. 2C4 z2 s 2 w C4 C5 R4 2 s (4. one the real axis in the s plane. The poles are located at s = 0 and s = -w3. 4. and one zero. the zero is at s = -w2.

Suppose for the moment that the poles of the second ﬁlter section are real and located at s = -w4 and s = -w5. (4.43b) For the open-loop transfer function G(s) of the fourth-order PLL. Downloaded from Digital Engineering Library @ McGraw-Hill (www. we get two versions. G(s) reads G(s) = 1 2 sz s s2 1+ + 2 ws ws (4. it is more practical to use a different notation for F(s) F (s) = 1 + s(t 2 + t 3 ) ◊ st 1 (1 + st 3 ) 1 2 sz s s2 1+ + 2 ws ws (4. It can be realized with two real poles or with a complex-conjugate pole pair. For the real poles we get F (s) = 1 + sT2 1 ◊ sT1 (1 + sT3 ) (1 + st 4 ) (1 + st 5 ) 1 + sT2 ◊ sT1 (1 + sT3 ) (4. 4. It provides the breakpoints of the asymptotic magnitude plot at w2 and w3.44a) For complex poles.42a) and (4.14. it is more convenient to write Eqs. Because we want to determine break frequencies (corners) in the asymptotic magnitude plot.digitalengineeringlibrary.42b) In the second case ws is the natural frequency and zs the damping factor of the second-order frequency response. it is most convenient to write the ﬁlter’s transfer function F(s) in the form F (s) = 1 + s(t 2 + t 3 ) 1 ◊ st 1 (1 + st 3 ) (1 + st 4 ) (1 + st 5 ) (4. Fig.Higher-Order Loops Higher-Order Loops 173 second-order low-pass ﬁlter. Then that ﬁlter section creates the two corners at w4 and w5.42b) in standardized form. The ﬁrst ﬁlter section has poles at s = 0 and s = -w3 and a zero at s = -w2. as shown in Fig. When the poles of the second ﬁlter section form a complex pair.14. and t3 = R2C3. 4.44b) Let us look at the magnitude plot now. At w4 and at w5 the slope of the magnitude curve increases by -20 dB/dec. . Any use is subject to the Terms of Use as given at the website. t2 = R2C2.43a) and for the complex poles we have F (s) = 1 1+ 2 sz s s2 + 2 ws ws (4. All rights reserved.com) Copyright © 2004 The McGraw-Hill Companies. one for the real poles and one for the complex poles. G(s) reads G(s) = 1 + sT2 1 K0 K d ◊ ◊ Ns sT1 (1 + sT3 ) (1 + st 4 )(1 + st 54 ) 1 + sT2 K0 K d ◊ ◊ Ns sT1 (1 + sT3 ) (4.42a) with t1 = R1C1. For real poles. When the poles of the second ﬁlter section are real.

To get sufﬁcient phase margin.Higher-Order Loops 174 Chapter Four G (dB) –40 0 w2 –20 wT w3 w4 w5 w (log) ws –40 –40 –60 –80 –80 Figure 4. The dashed curve shows the case where these poles form a complex pair.14 Bode plot (magnitude) of ﬁfth-order PLL. (4. There is no mathematical restriction on the size of wT here. We now have to provide a procedure for placing the poles and the zero of the third-order ﬁlter.com) Copyright © 2004 The McGraw-Hill Companies. Normally the designer knows what should be the bandwidth of the PLL. the corner frequencies w2 are chosen. It includes the following steps: Step 1. At this point the slope increases by -40 dB/dec. The solid curve represents the case where the poles of the second ﬁlter section are real. Any use is subject to the Terms of Use as given at the website. there is only one additional breakpoint at ws. however. . When the poles of the second ﬁlter section are complex. Next. because time constant T1 can be set such that the open-loop gain becomes 1 at the transition frequency wT.digitalengineeringlibrary.33.05w0¢. Using the approximation in Eq. Step 3. All rights reserved. where w0¢ is the down-scaled center (radian) frequency of the PLL. it is recommended to set w2 = w T 10 w 3 = w T 10 Downloaded from Digital Engineering Library @ McGraw-Hill (www. Step 2. hence it is reasonable to start by choosing a value for w3 dB. A default value could be w3 dB = 0.5) we compute wT = w3 dB/1.

C4 can be chosen arbitarily. T2. Experience shows that sufﬁcient phase margin is obtained if ws is placed at 5wT. otherwise with step 10. hence we set ws = 5wT. it continues with step 8. (Complex poles) We must choose a suitable value for natural frequency ws and damping factor zs. t2. This leads to T1 = K0 K d Nw 2 2 10 (4.707.e.T3 t 3 = T3 (4. The remaining components are computed from C5 = R4 = 2C4 z2 s 2 2 s w C4 C5 R4 R5 = 2 (4. To realize section 1 of the loop ﬁlter.45) Step 5. t3. These are computed from T1. T3 are altered. It should be set such that we obtain “reasonable” values for the resistors. All rights reserved. t2. Given ws and zs. we can determine the elements (R.47) The parameters of ﬁlter section 1 are determined now. Step 6.digitalengineeringlibrary. T2. T3 = 1/w3. C) of the second ﬁlter section. Because there are more unknown elements than equations. t3 and wants to know how the values T1. Then T1. T3 by t 1 = T1 t 2 = T2 . we must determine the values t1. t3 from T1 = t 1 T2 = t 2 + t 3 T3 = t 3 (4. When complex poles are desired. T3 can be computed from t1.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. Parameter T1 is chosen such that the open-loop gain is 1 at w = wT. For zs it is optimum to set zs = 0.46) Step 7.. i. The procedure depends on the type of poles. (Optional) Sometimes the designer changes the values t1. we must calculate the parameters of the second section. Step 9.48) Downloaded from Digital Engineering Library @ McGraw-Hill (www. Time constants T2 and T3 are computed from T2 = 1/w2. in the range 1 to 100 kW. T2. Next.Higher-Order Loops Higher-Order Loops 175 Step 4. . Step 8. t2.

Comparing coefﬁcients in Eqs. Doing so. as an example that applies to the corner frequencies w1 and w2 in Fig. damping factor.43b). we purposely discard the poles at those frequencies where the open-loop gain has dropped below 1. 4. and gain factors such as Kd and K0.43a) into the ﬁlter function given in Eq. As we have seen the key parameters depend on quantities such as natural frequency. (Real poles) We must choose values for the break frequencies w3 and w4 now.Higher-Order Loops 176 Chapter Four Step 10.6 The Key Parameters of Higher-Order PLLs In Chap. 2 we derived a number of equations for computing parameters such as lock-in range and pull-out range for second-order PLLs. These higher-frequency poles have therefore little impact onto the transient behavior of the loop.and higher-order PLLs we note that there are poles and zeros located at frequencies where the open-loop gain is greater than 1.3 (third-order loop).1 to 2. we would compute ws and zs from given w4 and w5.e. Consequently we still can use the formulas listed in Tables 2. The question arises now how these parameters change with higher-order loops.43b) yields 1 t4 t5 t4 + t5 zs = 2 t4 t5 ws = (4. it has become customary to use such terms for higher-order PLLs as well. (4. It is recommended to set w4 = 5w3 and w5 = 5w4. hence can be discarded for the calculation of lock-in and lock-out processes. 4. We now can determine t4 = 1/w4 and t5 = 1/w5. Although terms such as natural frequency wn and damping factor z are deﬁned for second-order systems only.43a) and (4. Step 11. (4. .4 to compute key parameters such as lock-in range and lock-in time.. Without these higher-frequency poles the open-loop transfer function G(s) looks very much the same as the corresponding transfer function of a second-order loop. i. it is most practical to convert the ﬁlter function in Eq.3). 4. 4. Because this is not fully correct mathematically we should perhaps use the terms pseudo natural frequency and pseudo damping factor for those quantities.14. To determine the elements of section 2. The additional poles are placed at frequencies where the open-loop gain is markedly less than 1 (as in the corner at w3 in Fig.com) Copyright © 2004 The McGraw-Hill Companies. (4.49) Given ws and zs. see Fig.48). we now can compute the R and C values using Eqs. (4. When checking the magnitude plots for third. Any use is subject to the Terms of Use as given at the website. All rights reserved.digitalengineeringlibrary. Downloaded from Digital Engineering Library @ McGraw-Hill (www.

rather than as a function of the current signal iout.50) where the phase detector gain Kd is computed as usual from Eq. check the circuit in Fig. as explained in Sec. This represents a passive ﬁrst-order loop ﬁlter used in a second-order PLL. for example. (2. All rights reserved.7 Loop Filters for Phase Detectors with Charge Pump Output 4. of course.25). In this section we will consider examples of higher-order loop ﬁlters suitable for cascading with charge pump PFDs.15.7. As noted there. 2.Higher-Order Loops Higher-Order Loops 177 4.digitalengineeringlibrary.15 Model for a charge pump output PFD cascaded with a passive ﬁrst-order lead-lag ﬁlter. 4.7.40c. For the output current iout we have iout = ud Rb where Rb is the transimpedance of the voltage-to-current converter. In this block diagram the charge pump PFD has been split into two blocks: A conventional (voltage output) PFD A voltage-to-current converter The output signal of the PFD is given by the current iout.7 we discussed phase-frequency detectors having a charge pump (current) output. Downloaded from Digital Engineering Library @ McGraw-Hill (www.40c by the model in Fig. Rb is usually set by an external resistor. 2. We recognized that the loop ﬁlter cascaded with a charge pump PFD looks somewhat different from a loop ﬁlter that is used for voltage output PFDs. .24) or (2. and obtain ud qe PFD U I iout uf R C Figure 4. To start. 2. 2. Any use is subject to the Terms of Use as given at the website. The signal ud is ﬁctive only and will be used for the following computations. The voltage signal ud would be given by ud = K dq e (4. We now express the loop ﬁlter output signal uf as a function of the (ﬁctive) ud signal. let us review brieﬂy the conﬁguration used in Fig.1 Loop ﬁlters for second-order PLLs In Sec.com) Copyright © 2004 The McGraw-Hill Companies.

16 Passive second-order loop ﬁlter to be used with charge pump PFD. In a computation similar to that for the ﬁrst-order loop ﬁlter. 4. F(s) becomes F (s) = 1 + st 2 st 1 This is identical with the transfer function of the active PI loop ﬁlter [Eq.3. the transfer function F(s) becomes dimensionless.2 Loop ﬁlters for third-order PLLs A passive loop ﬁlter of order 2 is shown in Fig. the expressions in Eq. All rights reserved. the time constant t3 is usally much smaller than t2. (2.16.52) can be simpliﬁed to read qe ud PFD U I iout uf R C2 C1 Figure 4.51) If uf were computed as a function of iout. Under this condition.com) Copyright © 2004 The McGraw-Hill Companies. 4. typically by a factor of 10. which is not very practical for numerical computations. By computing uf from the ﬁctive signal ud. which can be used in combination with charge pump outputs. The model shown in Fig. the ﬁlter transfer function F(s) becomes F (s) = with t 1 = Rb (C1 + C2 ) t 2 = RC1 C1C2 t3 = R C1 + C 2 (4. 4.7. 4. however.28)]. hence C2 is much smaller than C1.15 will be used for all computations.digitalengineeringlibrary. Downloaded from Digital Engineering Library @ McGraw-Hill (www. Setting t1 = RbC and t2 = RC. Any use is subject to the Terms of Use as given at the website.Higher-Order Loops 178 Chapter Four F (s) = U f (s) 1 + sRC = U d (s) sRbC (4. . (4.52) 1 + st 2 st 1 (1 + st 3 ) As we have seen in Sec. In the following we will discuss loop ﬁlters of order 2 to 4. the ﬁlter transfer function would have the dimension ohm.

4. 4. If complex poles are desired. .4. With this kind of ﬁlter. Any use is subject to the Terms of Use as given at the website.20). this loop ﬁlter can be designed by using the design procedure given in Sec. R2 uf 1 + st 2 st 1 (1 + st 3 ) (1 + st 4 ) (4. Eq. only real poles of F(s) can be created. Because the ﬁlter transfer function is identical with that of the fourth-order PLL using a third-order active PI ﬁlter [Eq.30a)]. All rights reserved. Downloaded from Digital Engineering Library @ McGraw-Hill (www.15 could be cascaded with an active second-order ﬁlter as shown in the second section of the third-order ﬁlter in Fig.17.Higher-Order Loops Higher-Order Loops 179 t 1 ª RbC1 t 2 ª RC1 t 3 ª RC2 The loop ﬁlter transfer function F(s) is identical with that of the third-order PLL using the active PI loop ﬁlter.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies.53a) qe PFD ud U I iout R1 C3 C2 C1 Figure 4. 4. Its transfer function F(s) is approximately given by F (s) = with t2 > t3 > t4 t 1 ª RbC1 t 2 ª R1C1 t 3 ª R1C3 t 4 ª R2C2 The approximation is valid under the assumptions t 2 >> t 3 t 3 >> t 4 which are fulﬁlled in most applications.17 Third-order passive loop ﬁlter to be used with charge pump PFD. The loop ﬁlter considered here can therefore be designed exactly like the second-order active PI ﬁlter. 4. 4.3 Loop ﬁlters for fourth-order PLLs A third-order passive loop ﬁlter is shown in Fig. (4. for example.7. the ﬁrst-order passive loop ﬁlter shown in Fig. (4.9.

4.42a)]. this loop ﬁlter can be designed using the design procedure given in Sec.50 1 + st 2 st 1 (1 + st 3 ) (1 + st 4 ) (1 + st 5 ) (4. 4.9. 4.53b) qe ud PFD U I iout R2 R4 uf R1 C1 Figure 4. With this kind of ﬁlter. the second-order passive loop ﬁlter shown in Fig. A large number of passive and active loop ﬁlters that can be cascaded with charge pump PFDs are listed in the EasyPLL design program. Because the ﬁlter transfer function is identical with that of the ﬁfth-order PLL using a fourth-order active PI ﬁlter [Eq.16 could be cascaded with an active second-order ﬁlter.18 C3 C2 C4 Fourth-order passive loop ﬁlter to be used with charge pump PFD.4 Loop ﬁlters for ﬁfth-order PLLs A third-order passive loop ﬁlter is shown in Fig.Higher-Order Loops 180 Chapter Four 4. only real poles of F(s) can be created. 4. If complex poles are desired. Downloaded from Digital Engineering Library @ McGraw-Hill (www. for example.5. a Web application created by National Semiconductor. Any use is subject to the Terms of Use as given at the website. as shown in the second section of the third-order ﬁlter in Fig. Its transfer function F(s) is approximately given by F (s) = with t2 > t3 > t4 > t5 t 1 ª RbC1 t 2 ª R1C1 t 3 ª R1C3 t 4 ª R2C2 t 5 ª R4 C4 The approximation is valid under the assumptions t 2 >> t 3 t 3 >> t 4 t 4 >> t 5 which are fulﬁlled in most applications. (4. All rights reserved.7.18.com) Copyright © 2004 The McGraw-Hill Companies.digitalengineeringlibrary. .

5. start Windows Explorer. .g.2). loop ﬁlters. Hitting the DESIGN speed button starts another dialog.. On start-up it displays a PLL block diagram which deﬁnes the symbols used throughout this application. t2). All rights reserved. Moreover the user will have to tell the program which types of phase detectors. The program can be started now. Clicking the CONFIG button opens a conﬁguration dialog (Fig.Source: Phase-Locked Loops Chapter 5 Computer-Aided Design and Simulation of Mixed-Signal PLLs 5. It is very easy to install the program. Just plug it into the CD player and installation will start automatically.EXE ﬁle in the right pane of Windows Explorer. Here the user will have to enter key parameters such as 3-dB bandwidth (f3dB) and the like.5).digitalengineeringlibrary. DPLL. In the toolbar (on top of the screen) there are a number of speedbuttons that look like this: These buttons are used to call a number of options. Here the response of the loop to phase and frequency steps applied to the reference input can be simulated. will be used in a particular conﬁguration. time constants t1. the ﬁlter design dialog box (Fig.1). If the install program does not start up. With the SIM (simulation) speedbutton the user enters simulation mode (Fig. This dialog box will be used to specify which category of PLL will be designed (LPLL. Any use is subject to the Terms of Use as given at the website. 5. During installation follow the instructions on screen. By the OPT (options) speed181 Downloaded from Digital Engineering Library @ McGraw-Hill (www. The dialog box also allows you to add noise to the reference signal. etc. click on the D:\ drive (it is assumed that the CD uses drive D) and double click on the SETUP ..com) Copyright © 2004 The McGraw-Hill Companies. 5.1 Overview A CD is distributed with this book containing a program developed by the author that enables the user to design and simulate PLLs of different kinds. or ADPLL). This dialog box is used to compute the parameters of the loop ﬁlter (e.

digitalengineeringlibrary. it is recommended that you start the program and perform a quick tour. you start an options dialog where you can shape the appearance of the graphical output frames and printouts individually.2. The speedbutton with the interrogation mark starts a HELP ﬁle. a DPLL (digital Figure 5. Hit the CONFIG button to start system conﬁguration. grid.1 Conﬁguring the PLL system The dialog box for the CONFIG dialog is shown in Fig. The user can. All rights reserved.1.Computer-Aided Design and Simulation of Mixed-Signal PLLs 182 Chapter Five button. 5. Any use is subject to the Terms of Use as given at the website. which provides plenty of information on this program and in addition an overview on PLL fundamentals and much more. Downloaded from Digital Engineering Library @ McGraw-Hill (www. and ADPLL. The last speedbutton (EXIT) closes the program. font size. 5. This will bring up the block diagram of the PLL. On top of the screen there is a toolbar with six speedbuttons labeled CONFIG. DESIGN. etc. top. bold). . (See next page. font style (italic. DPLL.) Click one of these radiobuttons to select either an LPLL (linear PLL). axis tick labels. To see what the program can do. for example. 5. etc. etc. choose colors for curves.1 Dialog box for PLL conﬁguration. On it there are three radiobuttons. labeled LPLL.2 Quick Tour Start the program.com) Copyright © 2004 The McGraw-Hill Companies. and fonts. background..

For details. All rights reserved.com) Copyright © 2004 The McGraw-Hill Companies. If you checked the DPLL radiobutton. there are another ﬁve radiobuttons specifying the order of the PLL system under test. or an ADPLL (all-digital PLL). When the program is started again. Having selected the center frequency.TXT). for example. . a ﬁrst-order PLL doesn’t use a loop ﬁlter at all. etc. it loads the last valid conﬁguration from that ﬁle. you would now tell the program which type of phase detector to use: Downloaded from Digital Engineering Library @ McGraw-Hill (www. all settings will be saved to a ﬁle (PARAMS. Below the ﬁve radiobuttons there is an edit control specifying the center frequency f0 of the PLL. The order number is identical with the number of poles of the system under test. Hence. PLL theory says that the order of the PLL is given by the order of the loop ﬁlter + 1. When you close the program. As you see. proceed with entering the parameters of the PLL’s building blocks. A second-order PLL uses a ﬁrst-order loop ﬁlter. Below these three radiobuttons.Computer-Aided Design and Simulation of Mixed-Signal PLLs Computer-Aided Design and Simulation of Mixed-Signal PLLs 183 PLL).digitalengineeringlibrary. click the Help button in the CONFIG dialog box. Any use is subject to the Terms of Use as given at the website. the program starts with a default conﬁguration when it runs the ﬁrst time.

“1. The upper is named Frequency params. Moreover. Alternatively you can set the ﬁlter params (t 1 and t 2) directly. The last parameters to enter would be the supply voltages.0 and 0. To close the box.e. On top there is a groupbox labeled Conﬁguration showing the setup that has been performed in the CONFIG dialog. the program computes the frequency params (here f3db. Second.Computer-Aided Design and Simulation of Mixed-Signal PLLs 184 Chapter Five To do so. hit the Done button. numbers are tested for correct format. Note: The CONFIG dialog box is a modal one.2). . the positive saturation limit for the phase detector cannot be greater than the positive supply voltage.com) Copyright © 2004 The McGraw-Hill Companies.2. For a DPLL system you can specify one of three phase detector types: the EXOR gate. To complete the CONFIG speciﬁcation. a function is started that checks every entry for validity. the output of the phase detector cannot reach up to the supply rails for most detector circuits. All rights reserved. f3db is the 3-dB corner frequency of the closed-loop gain of the PLL (i. you can exit only by clicking the Done button. For details. In the example shown.5 V . e.6.g.e. the lower Filter params. If a user erroneously entered. For example.. or from the default values when the program runs the ﬁrst time. Below the three corresponding radiobuttons there are two edit controls where you can enter the saturation limits of the phase detector circuit under test. This makes sure that only valid parameters can be entered into the edit controls: when the Done button is hit. which are defaulted here by 5. then hit the Calc ﬁlter params button. The program Downloaded from Digital Engineering Library @ McGraw-Hill (www.b” instead of “1. the upper limit is 4. we now start the DESIGN dialog. (See next page.2. i. 5.) When the DESIGN dialog box starts. for instance. 5. the ﬁlter params (here t 1 and t 2) are taken from the values that have previously been entered. 5. the lower limit 0. enter appropriate values into the other controls of the CONFIG dialog box.” this is an illegal ﬂoating format and is therefore rejected. see the Help ﬁle in the DESIGN dialog box. and damp factor) on the basis of the given ﬁlter params t 1 and t 2. You now can modify the ﬁlter in two ways: Enter an appropriate f3db value into the frequency params box. but stays clamped at same limiting voltage. hit the Calc frequency params button.digitalengineeringlibrary. phase margin. Any use is subject to the Terms of Use as given at the website. First.0 V . 5. or the phase-frequency detector (PFD). Below there are another two groupboxes. etc. Assuming that the PLL is powered from a unipolar 5-V supply. In addition it also computes the values for damping factor and phase margin (see Fig.. click the appropriate radiobutton in the groupbox labeled PD Type.2 Designing the loop ﬁlter Having closed the CONFIG dialog box. the JK-ﬂipﬂop. Having entered these values.1). 5000 Hz. This displays the DESIGN dialog box as shown in Fig. Hit the DESIGN speedbutton.. the ranges of all entries are checked. The program then calculates the values for t 1 and t 2 required to reach that goal. top. the frequency where the gain is 3 dB below the dc gain). respectively (see Fig.5 V .

All rights reserved.com) Copyright © 2004 The McGraw-Hill Companies. . Any use is subject to the Terms of Use as given at the website.2 Dialog box for loop ﬁlter design. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.Computer-Aided Design and Simulation of Mixed-Signal PLLs Computer-Aided Design and Simulation of Mixed-Signal PLLs 185 Figure 5.

The transit frequency fT is obtained from the crossover of the open-loop magnitude curve with the 0-dB line. top.digitalengineeringlibrary. fmax. Fig. 5. . To the right of the curves. this is rounded downward Figure 5.3. and Pts/Dec. Because the system has 4 poles and 1 zero. They are labeled fmin.3 Bode plot for open-loop and closed-loop gain of the PLL. remember that the closed-loop magnitude curve starts with about 0 dB. To avoid confusion of open-loop with closed-loop. which is located at the bottom of the DESIGN dialog box. hence we have a phase margin of roughly 45°. the phase approaches -270° at high frequencies. 5. This is an example of a fourth-order loop. The Bode plot is always formatted such that the low and high ends of the frequency scale are integer powers of 10. The red curve is the open-loop gain. This brings up Bode plots for both open-loop and closed-loop phase transfer functions. hit the button labeled Plot Bode. 5. Any use is subject to the Terms of Use as given at the website. (See next page. Downloaded from Digital Engineering Library @ McGraw-Hill (www. fmax is the high end. however. In this text. phase margin. At that frequency the phase (open-loop) is approximately -135°. Fig.com) Copyright © 2004 The McGraw-Hill Companies. If you don’t like that result. On screen the curves are displayed in colors. All rights reserved.2. for example.3 Analyzing stability of the loop To analyze stability of the loop. modify the ﬁlter params (t 1 and t 2 in this example) until the design is acceptable. and the green curve the closedloop gain.) fmin is the low end of the frequency scale.Computer-Aided Design and Simulation of Mixed-Signal PLLs 186 Chapter Five then calculates the resulting values for f3db.2. the curves are printed in gray scale. Here the closed-loop phase curve starts with about 0°. three edit windows are displayed. In the lower half the phases are plotted. fT is approximately 5000 Hz. and damp factor. Thus if you enter fmin = 4567 Hz.

and if you specify fmax = 300 kHz.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. Pts/Dec indicates how many points of the Bode curves are computed per decade of frequency.digitalengineeringlibrary. All rights reserved. this is rounded upward to 1 MHz. Below the three edit controls there are four pushbuttons in the Bode diagram dialog box: Downloaded from Digital Engineering Library @ McGraw-Hill (www. Default is 50 points per decade.Computer-Aided Design and Simulation of Mixed-Signal PLLs Computer-Aided Design and Simulation of Mixed-Signal PLLs 187 to 1000. .

Hitting the Done button closes the Bode diagram dialog box.Computer-Aided Design and Simulation of Mixed-Signal PLLs 188 Chapter Five If you have entered different values for fmin.4 Getting the loop ﬁlter schematic On bottom of the DESIGN dialog box there is a push button labeled Schematic. The schematic of the loop ﬁlter is shown on the left side in Fig. 5.com) Copyright © 2004 The McGraw-Hill Companies. Hitting that button opens the Schematic dialog box. All rights reserved. hit the Redraw button to recalculate and replot the new Bode diagram. Any use is subject to the Terms of Use as given at the website.2.digitalengineeringlibrary. To the right of the schematic. there are some edit windows and some “static text” windows. or Pts/Dec. which are initially blanked: Downloaded from Digital Engineering Library @ McGraw-Hill (www. .4. You can print the Bode plots by hitting the Print button. This schematic shows a third-order active lead-lag ﬁlter. 5. fmax.

8. so for resistors there are standard values of 1.2. mF. (Note: the R24 series deﬁnes 24 standard values within one decade. 1. etc.2. .5.3. the user can select appropriate values for capacitors C1 and C4.2.1.6. Any use is subject to the Terms of Use as given at the website. 5. . 1. 2. 1. These values are rounded to the closest value in the standard R24 series.Computer-Aided Design and Simulation of Mixed-Signal PLLs Computer-Aided Design and Simulation of Mixed-Signal PLLs 189 Figure 5. 8. . nF. 1. There are two items to enter: a value and the unit (F.0.digitalengineeringlibrary. pF). All rights reserved. 2. 9.4) starts the computation of all other elements (R and C).com) Copyright © 2004 The McGraw-Hill Companies. Hitting the Calculate button (Fig. mF. .4 Schematic of the loop ﬁlter with component values. 1. In this example. 1.) After the Calculate button is clicked the display will look something like this: Downloaded from Digital Engineering Library @ McGraw-Hill (www.1 W. .

Downloaded from Digital Engineering Library @ McGraw-Hill (www. in the range of 1 to 100 kW.digitalengineeringlibrary. can be printed out by using the Print button (Fig.4). 1 nF). including element values. Having completed our design.Computer-Aided Design and Simulation of Mixed-Signal PLLs 190 Chapter Five The values of C1 and C4 should be set such that the resulting resistor values have “reasonable values..2.5. To do so.” i. All rights reserved. 5. Clicking the SIM speedbutton enters the simulation dialog box. 5.g. we can proceed to simulations. the user may wish to get larger values for R4 and R5 and would probably enter a lower C4 (e. The schematic. . In the example above.5 Running simulations We are still navigating through the DESIGN dialog box..e. close the design dialog by hitting the Done button. 5. shown in Fig.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website.

5 Simulation of frequency step applied to the reference input. All rights reserved.digitalengineeringlibrary. . Any use is subject to the Terms of Use as given at the website. Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies.Computer-Aided Design and Simulation of Mixed-Signal PLLs Figure 5.

this will be discussed later in this section. The next window speciﬁes the phase step dphi (if used). The signals ud and uf are displayed versus time.6 Response of the second-order PLL to a frequency step. hit the Run button. This is the response of the PLL to a frequency step df = 2 kHz applied to the reference input. for example. Check the appropriate radiobutton. This will be explained at the end of this section. the time axis is zoomed by a factor of 10. Last.com) Copyright © 2004 The McGraw-Hill Companies. On the Figure 5.6. the center frequency of the PLL under test must be entered (100. When ZoomFact = 10. Next. Downloaded from Digital Engineering Library @ McGraw-Hill (www. T is the duration of the simulation. 5. In edit control f0.13). . The result of that simulation is shown in Fig. df = 2 kHz. All rights reserved. First determine whether a frequency step or a phase step should be applied to the input of the PLL.66 ms in the example. To start the simulation.digitalengineeringlibrary.000 Hz in the example). When the checkbox Add noise is checked. noise is added to the input signal of the PLL under test. a zoom factor (ZoomFact) can be speciﬁed to zoom the results of the simulation. Any use is subject to the Terms of Use as given at the website. nSamp speciﬁes the number of samples to be calculated within one cycle of the PLL simulation. 1.Computer-Aided Design and Simulation of Mixed-Signal PLLs 192 Chapter Five Here a number of simulation parameters can be entered. df denotes the frequency step applied to the PLL (2000 Hz in the example). 5. You can browse through the results by moving the thumb of a scrollbar (as in Fig.

This convention will be used in the following simulations. an options window is displayed. To see what happens when you specify different types of phase detectors. To indicate which curve represents ud and which uf. Help can be called from a number of different locations. if the Help button in the Bode window is clicked (Fig. loop ﬁlters. etc.2.7. go back to the CONFIG and/or DESIGN dialog boxes. Downloaded from Digital Engineering Library @ McGraw-Hill (www. The quick tour ends now.7 Shaping the appearance of graphic objects The user can select a number of options for displaying and printing results of simulations. AxisTickLabels is highlighted. 5.3). the content page of the help ﬁle is displayed. When the speedbutton labeled OPT is clicked. in the book they are printed in gray scale. All rights reserved. 5.Computer-Aided Design and Simulation of Mixed-Signal PLLs Computer-Aided Design and Simulation of Mixed-Signal PLLs 193 screen the curves are in color. At top left there is a list box containing six items. For these tick labels the user can select Figure 5. For example. Any use is subject to the Terms of Use as given at the website.7 Options window.digitalengineeringlibrary. 5. Fig. the corresponding help item is immediately shown. . 5.6 Getting help The help text in this program is context sensitive.2. and return to SIM again. In the example. make modiﬁcations.com) Copyright © 2004 The McGraw-Hill Companies.. When the speedbutton with the interrogation mark in the toolbar is clicked. the ud signal is plotted with a larger line width.

Now we may prefer a lower damping factor. with t2 changed to 90 ms the damping factor becomes 0. enter the following parameters: PLL Category PLL Order Center frequency f0 PD Type Usat+ UsatLF Type: Oscillator Type: Usat+ UsatSupply Voltages U+ U5. If you like. 5. We are now in the DESIGN dialog box. we perform a full-ﬂedged PLL design and evaluate its key parameters (lock-in time. This can be achieved by entering a smaller t2 value.3 Case Study: Design and Simulation of a Second-Order PLL To see what the program is able to do..e. All rights reserved. Let us assume that we want to have a 3-dB bandwidth of 5000 Hz. 5. This is OK. etc. 5. The program computes the ﬁlter parameters t 1 and t 2 required to achieve this goal.5 (V) 0. and you may print out your ﬁlter design.digitalengineeringlibrary. Fig. just to see how the parameters obtained from the simulations agree with the predicted ones.com) Copyright © 2004 The McGraw-Hill Companies. we get the following results: Downloaded from Digital Engineering Library @ McGraw-Hill (www. We can exit the DESIGN dialog now.755. it is 4415 Hz now. line width. Let us start the program and click the CONFIG button (Fig.Computer-Aided Design and Simulation of Mixed-Signal PLLs 194 Chapter Five the color and the font (with all its attributes such as font size.2.000 (Hz) EXOR 4. we get z = 0.) by simulation.5 (V) Click the Done button to close the CONFIG dialog and hit the DESIGN speedbutton. Here the operator can select line color. You also may let the program calculate the R and C values in the schematic. have a look on the Plot Bode or on the Schematic.g. Option Curve1 refers to the display of ud versus time. we ﬁrst compute the relevant key parameters.692. After reducing t1 to 580 ms we ﬁnally get f3dB = 4977 Hz and z = 0. we can make t1 smaller. Any use is subject to the Terms of Use as given at the website. In the CONFIG dialog box. Thus we enter 5000 in the f3db edit window and hit the Calc ﬁlter params button. e. font style. To get the planned value of 5000 Hz. i.1). the resulting damping factor is computed. z = 0.0 (V) 0 DPLL 2 100.5 (V) 0. They remain valid when the program is started next. We get t1 = 707 ms and t2 = 126 ms. .5 (V) Passive LL VCO (N = 1) 4. Using Table 2. At the same time. which is almost perfect. etc. too.2.932. All selected parameters are stored in the conﬁguration ﬁle when you exit the program.7.).. but we realize that the 3-dB bandwidth has also decreased. lock-out range. Knowing all the parameters of the second-order loop. etc.

697 s-1 0. we see a dip in the ud waveform.27 V/rad 15. Fig.8 kHz and starting another simulation. 2.27) made Figure 5.8 Response to frequency step df = 2 kHz. Let us start with a step df = 2 kHz. Any use is subject to the Terms of Use as given at the website. 5.6 kHz.com) Copyright © 2004 The McGraw-Hill Companies.214 s-1 8632 Hz We start simulations by clicking the SIM speed button (Fig.628 Hz 54. The result looks like the transient response of a linear second-order system.163 s-1 5917 Hz 400 ms 98. we suppose that nothing dramatic happens when we apply frequency steps smaller than about 8 kHz. the thinner uf.5). This represents the situation where the pendulum in the mechanical analogy (Fig.148 s-1 15. 5. Knowing that the lock-out range is in the order of 8. 5. .digitalengineeringlibrary.754 37.Computer-Aided Design and Simulation of Mixed-Signal PLLs Computer-Aided Design and Simulation of Mixed-Signal PLLs 195 Detector gain Kd (from Eq. Downloaded from Digital Engineering Library @ McGraw-Hill (www. 2.19) Natural (radian) frequency wn Damping factor z Lock-in range DwL DfL Lock-in time TL Pull-in range DwP DfP Pull-out range DwPO fPO 1. All rights reserved.8. Again the thicker curve represents ud.9. After increasing the frequency step df to 8. Fig.

8 kHz (no lock-out). All rights reserved. but became locked again after a short time. the output signal ud of the phase detector decreases but remains positive..com) Copyright © 2004 The McGraw-Hill Companies. the pendulum tips over for a number of revolutions. as seen from the thinner curve. Downloaded from Digital Engineering Library @ McGraw-Hill (www. i.10. The pumping of the uf signal is very characteristic.6 kHz. After a number of trials we ﬁnd that the loop no longer pulls in when the frequency step is increased to df = 17 kHz. a peak deﬂection greater than 90° but less than 180°. We did not speak about lock-in range and lock-in time hitherto. . which is quite close to the result of the simulation (8900 Hz). for example.11. Because the gain of the phase detector becomes smaller for phase errors greater than 90°. To get the lock-in range we ﬁrst must force the PLL to unlock by making the difference Df between (scaled-down) center frequency f0¢ and reference frequency f1 larger than the pull-in range. 5. Fig.9 Response to frequency step df = 8.9 kHz causes the pendulum to tip over now.e. df = 14 kHz. The computed value was 15.Computer-Aided Design and Simulation of Mixed-Signal PLLs 196 Chapter Five Figure 5. Any use is subject to the Terms of Use as given at the website. It is not easy to measure or simulate the lock-in range. the prediction error is about 9 percent. In this simulation the PLL temporarily locked out (the pendulum performed exactly one rotation). Increasing the frequency step to 8.digitalengineeringlibrary. The pendulum performed about 11 revolutions before coming to rest. 5. When the frequency step is made even larger (but less than the pull-in range). The computed value for DfPO was 8632 Hz. Fig.

2 V . Fig. it is not possible to simulate this process.9 to 3. This frequency step was slightly less than the pull-in range but larger than the pullout range. With this program. the acquisition process is a fast lock-in process: the pendulum makes one revolution at most.com) Copyright © 2004 The McGraw-Hill Companies.digitalengineeringlibrary.3 to 1. that this method is rather crude and cannot yield precise results. Look again at the transient response on the 14-kHz step. At the end of this process (t Ϸ 1. .9 kHz (lock-out).. however.3 V corresponds to a frequency variation of about 6 kHz. This can be used as a prediction of the lock-in range.8 ms).3 ms) the ﬁlter output signal uf reached a value of about 2. Any use is subject to the Terms of Use as given at the website. The loop now reacquires lock. When Df is larger than the lock-in range. When Df becomes less than the pullin range. The lock-in time TL can be estimated quite easily from this kind Downloaded from Digital Engineering Library @ McGraw-Hill (www.9 V . During that interval of time (about 1. It pulled in with a slow transient (observe the pumping from 0 to 1. however.3 ms the loop locked rapidly.e. A variation in uf of 1 V corresponds to a frequency variation of K0/2p Ϸ 20 kHz. performed a lock-in process. The best we can do is a very crude estimation of lock-in range.10 Response to step df = 8. Consequently the loop locked out initially. 5.3 ms). the acquisition process is a slow pull-in process: the pendulum performs a number of revolutions. i. uf was pulled from 2.Computer-Aided Design and Simulation of Mixed-Signal PLLs Computer-Aided Design and Simulation of Mixed-Signal PLLs 197 Figure 5. The computed value was 5917 Hz. It must be stated. Beginning at t = 1.11. The variation of 0. All rights reserved. Then we would suddenly reduce the frequency offset Df to a value between pullin range and lock-in range.

From the response of the PLL for df = 2 kHz. Because the designer of a PLL is mainly interested in the average ud and uf signals. we see that the loop settles in about 400 ms. The simulation program also discards those ac components: under normal operation it ﬁlters out the higher-frequency terms. Theory says that TL corresponds to roughly one period of the transient response (for z < 1). whose default value is 4. This means that the program computes four values for ud and uf in each reference period.com) Copyright © 2004 The McGraw-Hill Companies. Checking again the SIM dialog box (Fig. Any use is subject to the Terms of Use as given at the website. . the output signal of that phase detector Downloaded from Digital Engineering Library @ McGraw-Hill (www. of simulation.11 Response to step df = 14 kHz. You probably became aware that the curves obtained from the simulations look “nicer” than those you would get when measuring transients of a real PLL system with an oscilloscope.digitalengineeringlibrary. TL can be estimated from the settling time of the PLL in the case when the frequency step df is less than the pull-out range. nSamp denotes number of samples computed in one reference period. The value 4 is dictated by Nyquist’s sampling theorem. which agrees well with the predicted lock-in time. All rights reserved. 5.5) we recognize a button labeled nSamp.Computer-Aided Design and Simulation of Mixed-Signal PLLs 198 Chapter Five Figure 5. Assuming that the frequency of the reference signal is f1 and the multiplier type phase detector is used. Because the transient response is a damped oscillation whose frequency is the natural frequency. the higher-frequency components are discarded in most cases.

Any use is subject to the Terms of Use as given at the website. We repeat the simulation with df = 14 kHz with nSamp = 32 and get the result shown in Fig. Fig. it suppresses the ac signals. however. To get better signals we would increase the number of samples.Computer-Aided Design and Simulation of Mixed-Signal PLLs Computer-Aided Design and Simulation of Mixed-Signal PLLs 199 contains an ac component at 2f1. All rights reserved. Now we clearly see what the waveforms really are. This is done by unchecking the Filter checkbox. 5.14.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies.5) is checked (which is the default) and nSamp = 4.12. That looks pretty bad indeed! The curves are smeared over the full window. this gives a very crude approximation of the real waveform. no ﬁltering. the time scale is expanded by a factor of 16. 5. however. . nSamp = 32. To satisfy the sampling theorem we must sample that signal at 4f1 at least. as shown in Fig. To do so check the Add noise checkbox. To see what really happens we will zoom the display. This opens two Figure 5. setting nSamp in the range 4 to 64. When only four samples are computed in each reference period. Below the frame window. When the checkbox labeled Filter (Fig. where the user wants to see how the waveforms look in reality.13. 5. Downloaded from Digital Engineering Library @ McGraw-Hill (www. the program computes the average of the four values ud and uf in every reference period.12 Response to df = 14 kHz. With a zoom factor of 16. There are cases. 5. there is a scrollbar that allows you to scroll through the time window. The simulation program also allows you to add noise to the reference signal. Doing so.

and NoiseBW (rel) is the (one-sided) noise bandwidth related to the (scaled-down) center frequency f0¢.Computer-Aided Design and Simulation of Mixed-Signal PLLs 200 Chapter Five Figure 5. but it is clearly seen that the PLL perfectly locks nevertheless.13 factor = 16. The Help ﬁle contains a lot of additional information on noise. . Any use is subject to the Terms of Use as given at the website.digitalengineeringlibrary. because the ﬁlter bandwidth is much less than the bandwidth of the noise spectrum. which means that there is broadband noise whose power density spectrum reaches from 50 to 150 kHz. The curves have become jittery now. SNR (dB) is the signal-to noise ratio at the reference input. In the example shown. Response to df = 14 kHz. the one-sided noise bandwidth is 50 kHz now. NoiseBW (rel) is set at 0. Downloaded from Digital Engineering Library @ McGraw-Hill (www. The noise on the ud waveform is much larger than the noise on the ﬁltered signal uf. All rights reserved. nSamp = 32.com) Copyright © 2004 The McGraw-Hill Companies. no ﬁltering. the result of the simulation is shown in Fig. SNR is chosen as 20 dB. Because the scaled-down center frequency is 100 kHz.15. zoom additional edit controls labeled SNR (dB) and NoiseBW (rel). For the parameters entered in this window.5. 5.

Use the active lead-lag instead of the passive. Any use is subject to the Terms of Use as given at the website. Use the active PI ﬁlter then. specify a dc gain Ka greater than 1.digitalengineeringlibrary. with added noise. . 5.14 Dialog box for PLL simulation.com) Copyright © 2004 The McGraw-Hill Companies. What is the major difference compared with other ﬁlter types? What happens to the pull-in range? Downloaded from Digital Engineering Library @ McGraw-Hill (www. and see how the key parameters such as pull-out range and pull-in range are inﬂuenced.Computer-Aided Design and Simulation of Mixed-Signal PLLs Computer-Aided Design and Simulation of Mixed-Signal PLLs 201 Figure 5.4 Suggestions for Other Case Studies Now that you are familiar with the simulation program. All rights reserved. try to simulate other kinds of PLLs. Here are some suggestions: Case study 1: Inﬂuence of loop ﬁlter type.

Kd. All rights reserved. measure the pull-in time of the PLL under various conditions (different values for z. different size of frequency step Df1). Ka. Using different types of loop ﬁlters. . Logical high and low levels can easily be displayed. K0. Vary the size of the phase step.digitalengineeringlibrary. Check how the damping factor z depends on the scaling factor N. Simulate a PLL whose output frequency is N times larger than the reference frequency.com) Copyright © 2004 The McGraw-Hill Companies. the output signal of the PFD is a tristate signal. Apply a phase step to the reference input. but what about the high-Z state? In the sim- Downloaded from Digital Engineering Library @ McGraw-Hill (www.15 Response to df = 10 kHz. use the formulas in Tables 2. Case study 3: VCO with divide-by-N counter. with superimposed noise.5 Displaying Waveforms of Tristate Signals As we know.Computer-Aided Design and Simulation of Mixed-Signal PLLs 202 Chapter Five Figure 5. Any use is subject to the Terms of Use as given at the website.4 to compute pull-in time TP.1 to 2. or it can be in the high-impedance state (high Z). Where can you ﬁnd the largest deviations between theory and practice? 5. Case study 2: Phase step. Compare the results of the simulation with the values predicted by theory. Case study 4: Pull-in processes. It can be either high or low.

At the left of the time scale. ulation program.16 Simulation of an acquisition process using the PFD. Downloaded from Digital Engineering Library @ McGraw-Hill (www.16 shows an example. All rights reserved.5 V . the high-Z state is represented by 2. the high-Z state is represented by a signal level that is the mean of positive and negative supply voltages. . Any use is subject to the Terms of Use as given at the website.Computer-Aided Design and Simulation of Mixed-Signal PLLs Computer-Aided Design and Simulation of Mixed-Signal PLLs 203 Figure 5. The time axis is zoomed by a factor 16 here.com) Copyright © 2004 The McGraw-Hill Companies. Figure 5. it temporarily switches to the high state. at the right it switches to the low state. The signal ud is in the high-Z state most of the time.digitalengineeringlibrary. When a circuit is powered from a unipolar 5-V supply. for example.

All rights reserved.com) Copyright © 2004 The McGraw-Hill Companies.digitalengineeringlibrary.Computer-Aided Design and Simulation of Mixed-Signal PLLs Downloaded from Digital Engineering Library @ McGraw-Hill (www. . Any use is subject to the Terms of Use as given at the website.

the center frequency of a DPLL is inﬂuenced by parasitic capacitors on the DPLL chip. In contrast to the older DPLL. i. as was the case with the classical DPLL. too. its key parameters will vary because of parts spread. it is an entirely digital system. 6.e. To realize an ADPLL. to save space. Digital versions of the phase detector are already known. the digital counterpart of the VCO is the digital-controlled oscillator (DCO).1 All-digital phase detectors The three most important digital phase detectors have already been discussed in Sec. But digital also signiﬁes that the signals within the system are digital. .1. 2.3. 6. from the parallel outputs of a counter.1.com) Copyright © 2004 The McGraw-Hill Companies. Many parameters are also subject to temperature drift and aging. Any use is subject to the Terms of Use as given at the website. 2. digital means that the system consists exclusively of logical devices. Its variations can be so large that trimming can become necessary in critical applications. Let us note ﬁrst that the term digital is used here for a number of different things. we concentrate on the most frequently used. When discussing the various types of ADPLL. a number of additional phase-detector circuits become available. Even worse. As we will see in Sec. There are an almost unlimited number of purely digital function blocks for the ADPLL.3. 205 Downloaded from Digital Engineering Library @ McGraw-Hill (www.. All rights reserved. Hence a signal within an ADPLL can be a binary signal (or “bit” signal). the classical “digital PLL ” (DPLL) is a semianalog circuit. Because it always needs a couple of external components.1 ADPLL Components As we have seen in Chap.digitalengineeringlibrary. and the like. but we now have to ﬁnd digital circuits for the loop ﬁlter and for the VCO. all function blocks of the system must be implemented by purely digital circuits.1. but it can as well be a “word” signal. a digital code word coming from a data register. we ﬁnd the whole palette of such digital signals. When digital word signals instead of bit signals are used. too. The all-digital PLL does away with these analog-circuitry headaches. First of all.Source: Phase-Locked Loops Chapter 6 All-Digital PLLs (ADPLLs) 6.

com) Copyright © 2004 The McGraw-Hill Companies. Downloaded from Digital Engineering Library @ McGraw-Hill (www.1 t (b) t Flipﬂop-counter PD. The time period in which the Q output of the ﬂipﬂop is a logic 1 is proportional to the phase error qe.1b. Note that the counter is reset on every positive edge of the u1 signal. They are used to set or reset an edge-triggered RS ﬂipﬂop. 6. Any use is subject to the Terms of Use as given at the website. (b) Corresponding waveforms. The reference (input) signal u1 and the output (or scaled-down output) signal u2 of the DCO (or VCO) are binary-valued signals. The content N of the counter is also proportional to the phase error qe.digitalengineeringlibrary. where N is the n-bit output of this type of phase detector. (a) Block diagram.All-Digital PLLs (ADPLLs) 206 Chapter Six A logical evolution of the simple JK-ﬂipﬂop PD is the FF-counter phase detector illustrated in Fig. All rights reserved. The frequency of the N = content~qe u1 u2 S Flipflop R Q Enable Counter Clock Reset High frequency Clock (a) u1 t u2 t Q ~qe N content Figure 6. 6. .1a. The corresponding waveforms are shown in Fig. The Q signal is used to gate the high-frequency clock signal into the (upward) counter.

Any use is subject to the Terms of Use as given at the website. 6. 6. . and the corresponding waveforms are seen in Fig. Another all-digital phase-detector circuit has become known by the name Nyquist-rate phase detector (NRPD). The block diagram of the NRPD is shown in Fig. which states that a continuous signal can be reconstructed from a sampled version only if the sampling rate is at least twice the highestfrequency component of the signal. All rights reserved.8 The name stems from the well-known Nyquist theorem.2 t Nyquist-rate PD.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 207 high-frequency clock is usually Mf0. (b) Corresponding waveforms.com) Copyright © 2004 The McGraw-Hill Companies. Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary. u1 (analog) ADC u1 (digital) sampled Digital multiplier qe Clock u2 (a) u1 t u2 t qe qe t Clock (b) Figure 6. where f0 is the frequency of the reference signal and M is a large positive integer.2b. (a) Block diagram.2a.

(Refer also to Sec. 6.3b. 2.8 The simplest zero-crossing phase detector is illustrated in Fig. or the multiplication can be done by software. The key element of this PD is a Hilbert transformer. 6. The reference signal u1 is supposed to be analog. In the block diagram of Fig.3a.3b. in a microcontroller. as shown by the dashed line in Fig. which are shown in the following.) Furthermore. Figure 6. so u1 is sampled once during every reference period. It is periodically sampled and digitized at the clock rate. Assuming the input of the device is a digital word signal of the form u1 (t) = cos(w 0 t + q e ) the output signal of the Hilbert transformer is given by p ˆ1 (t) = cosÊ w 0 t + q e . an in-phase signal I = cos(w0t) and a quadrature signal Q = sin(w0t). The digitized signal u1 and the signal u2 are multiplied together by a digital multiplier. This is a special digital ﬁlter that shifts the phase of a sinusoidal input signal by exactly -90° irrespective of its frequency.3. The digital output signal of the ADC is then proportional to the phase error. Still another method of measuring the phase error is the zero-crossing technique.2b. for example. its waveforms are shown in Fig.3. as will be demonstrated in Sec. 6.1. generated by a DCO. Usually this signal is held in a buffer register until the next conversion is completed. In the example shown. Any use is subject to the Terms of Use as given at the website.1. u2 is a binary signal.13 Moreover. the gain of the Hilbert transformer is 1 at all frequencies. the signal u2 has been drawn as a sine wave in Fig. The DCO used in this type of phase detector is supposed to generate two output signals.Qu1 sin q e = Iu (6. the so-called Hilberttransform PD. 6.ˆ = sin(w 0 t + q e ) u Ë 2¯ (6.All-Digital PLLs (ADPLLs) 208 Chapter Six The input signal is supposed to be an analog signal. The signal u2 is an N-bit digital word.4a.2. which is 8 times more than required by the sampling theorem.com) Copyright © 2004 The McGraw-Hill Companies.1. the Hilbert transformer is shown in the top left corner and is marked by the symbol -p/2. All rights reserved. another waveform (such as a square wave) could be used as well. 6. 6.2b.2) (6. By the trigonometric operations ˆ1 cos q e = Iu1 + Qu ˆ1 . The resulting phase error signal qe is also shown in Fig. Its average value will have to be ﬁltered out by a succeeding digital loop ﬁlter.digitalengineeringlibrary. as discussed in Sec.1) The Hilbert-transform PD extracts the phase error qe by trigonometric computations. This multiplier can be a hardware device. 6. . 6.3) Downloaded from Digital Engineering Library @ McGraw-Hill (www. Thus the NRPD operates similarly to the multiplier PD (type 1). The positive transitions of u2 are used to clock the analog-to-digital converter (ADC). thus the phase-error signal qe is a quasi-continuous signal.4 shows another variant of digital PD. the clock rate chosen is 16 times the signal frequency.

6. (b) Corresponding waveforms.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 209 u1 (analog) ADC qe Clock PED u2 (a) u1 sampled sampled t u2 t Clock t qe t (b) Figure 6. The variety of mathematical operations required by the Hilbert transform strongly suggests implementation of this method by software. All rights reserved. 6. by using a digital algorithm for the inverse tangent (tan-1). Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary. Dividing the sine by the cosine term yields the tangent of phase error. As in the NRPD. The double lines in Fig. the sine and cosine of the phase error qe are computed. Any use is subject to the Terms of Use as given at the website. The signals of the Hilbert-transform PD are shown in Fig.4a signify that all signals within this device are digital word signals. .4b. (a) Block diagram (PED = positive-edge detector).3 Zero-crossing PD sampling the phase error at the positive transitions of the reference signal. all mathematical computations are performed under the control of a clock signal whose frequency is usually M times the signal frequency f0 = w0/2p. the phase error is obtained.com) Copyright © 2004 The McGraw-Hill Companies.

5). (a) Block diagram.digitalengineeringlibrary.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. All rights reserved. A similar but simpler way to calculate the phase error is given by the digitalaveraging phase detector (Fig.All-Digital PLLs (ADPLLs) 210 Chapter Six u1(t) – p 2 ˆ 1(t) u MUL Adder MUL cos qe MUL Adder MUL sin qe Y tg qe Divider X/Y X tan–1 qe Q I MUL = Digital multiplier (a) sinwot coswot DCO Q t I t u1(t) t ˆ 1(t) u t Clock (b) Figure 6. respectively. the DCO is also required to generate in-phase and quadrature signals I and Q. These are again multiplied by the digital reference signal u1(t).4 t Hilbert-transform PD. (b) Corresponding waveforms. 6. but the signals cos qe and sin qe are obtained by simply averaging (or integrating) Downloaded from Digital Engineering Library @ McGraw-Hill (www. As in the method discussed previously. .

-1) this ﬁlter can roughly be considered an integrator having the transfer function H (s) = 1 sTi (6. however. the DN pulses. Any use is subject to the Terms of Use as given at the website. 6. 6. It is easily adapted. The up/down counter loop ﬁlter preferably operates in combination with a phase detector delivering UP or DN (DOWN) pulses.digitalengineeringlibrary. different all-digital PDs generate different types of output signals. We have to consider which types of loop ﬁlters can be matched to the various PDs discussed previously. too. The PDs discussed at the end of Sec. It becomes evident that not every all-digital loop ﬁlter is compatible with all types of all-digital PDs.6a.29 Note that this arrangement already includes a ﬁltering function.com) Copyright © 2004 The McGraw-Hill Companies. lends itself particularly to implementation by software. whereas simpler types.4) Downloaded from Digital Engineering Library @ McGraw-Hill (www.1.2 All-digital loop ﬁlters As seen in the preceding section. Because the content N is the weighted sum of the UP and DN pulses (the UP pulses have an assigned weight of +1. such as the PFD.5 Digital-averaging PD.6a). The content N is given by the n-bit parallel output signal uf of the loop ﬁlter. As shown in Fig. the output signals of the multipliers over an appropriate period of time.6b). A DN pulse will decrement N in the same manner. On each UP pulse generated by the phase detector. Probably the simplest loop ﬁlter is built from an ordinary up/down counter (Fig. a pulse-forming network is ﬁrst needed to convert the incoming UP and DN pulses into a count— — ing clock and a direction (UP/DN) signal (as explained by the waveforms in Fig. such as the EXOR or the phase/frequency detector deliver one or two binary-valued output signals (or a tristate signal). All rights reserved. 6.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 211 cos qe u1(t) MUL Averager Y Divider X/Y sin qe tg qe tan–1 qe MUL Averager X Q sinw0t I cosw0t DCO Figure 6.1. 6. deﬁned by the impulse transfer function of the averaging ﬁlter used.1 produce N-bit digital output signals. 6. to operate in conjunction with the EXOR or JKﬂipﬂop phase detectors and others. .14 This method. the content N of the up/down counter is incremented by 1.

a very crude approximation.7a shows.1.com) Copyright © 2004 The McGraw-Hill Companies. the contents of both counters are in a range from 0 to K . The frequency of the clock signal (K clock) is by deﬁnition M times the center frequency f0 of the ADPLL.digitalengineeringlibrary. 6. . This loop ﬁlter always works together with the EXOR or the JK-ﬂipﬂop phase detector. (a) Block diagram. 32. 6.” In reality. If this signal is high. where M is typically 8. however. Up/down counter loop ﬁlter. All rights reserved. they only tell whether the phase of u1 is leading or lagging u2. . One of the most important digital loop ﬁlters is the K counter (Fig. . The oper— — ation of the K counter is controlled by the DN/UP signal. . the K counter consists of two independent counters.All-Digital PLLs (ADPLLs) 212 Chapter Six content N~uf UP from Phase detector DN Pulse forming circuit Clock Clock UP/DOWN counter UP/DN (a) UP/DN UP DN Clock UP/DN (b) Figure 6. since the UP and DN pulses do not carry any information (in this application at least) about the actual size of the phase error. . which are usually referred to as “up counter” and “down counter. both counters are always counting upward. i. Downloaded from Digital Engineering Library @ McGraw-Hill (www. (b) Corresponding where Ti is the integrator time constant. K can be controlled by the K modulus control input and is always an integer power of 2. 16. however.e. K is the modulus of both counters..7). Any use is subject to the Terms of Use as given at the website. This is.6 waveforms. As Fig.

(a) Block diagram. Downloaded from Digital Engineering Library @ McGraw-Hill (www. (b) Corresponding waveforms.com) Copyright © 2004 The McGraw-Hill Companies. . Any use is subject to the Terms of Use as given at the website.7 K counter loop ﬁlter.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 213 K modulus control K clock DN/UP Up counter Carry Dn counter (a) Borrow 1 cycle of u1 K clock 0 DN/UP 8 8 16 Up counter Dn counter K/2 0 8 K/2 0 Carry Borrow (b) Figure 6.digitalengineeringlibrary. All rights reserved.

the — — UP counter is active all the time.7b.3. 6. the carry is high when the contents of the UP counter are equal to or more than K/2. the DN counter is working continually. it was assumed that a JKﬂipﬂop is used and that the ADPLL operates on its center frequency. 6. Any use is subject to the Terms of Use as given at the website. 6. and the DN counter generates exactly one borrow pulse in the same interval. we see that the UP counter counts on the ﬁrst 8 K clock pulses. Otherwise. Under these conditions. . 2.8 it is suggested that the N-before-M ﬁlter operates in conjunction with a phase detector generating UP and DN pulses. Looking at the waveforms in Fig.All-Digital PLLs (ADPLLs) 214 Chapter Six the DN counter is active.9. When this signal is low during a longer fraction of one u1 cycle than it is high.8). input signal u1 and output signal u2¢ of the PLL are in antiphase then. as shown in Fig. The ∏M counter counts the incoming UP and DN pulses. as was the case with the PFD. the carry and borrow pulses then cancel. Consequently. The DN/ UP input is controlled by the output of a phase detector. which will output borrow pulses only when Downloaded from Digital Engineering Library @ McGraw-Hill (www. The counter modulus K has been arbitrarily set to 8. the UP counter generates exactly one carry pulse within each cycle of the u1 signal. 6. 6. while the contents of the UP counter stays frozen. Hence the DN/UP signal is high in one half-cycle of the u1 signal and low in the other. the upper ∏N counter will produce one carry output when it has received N UP pulses. We assume now that there exists a phase — — error in the loop. The frequency of the K clock is assumed to be 16 times the center frequency (M = 16).8.8.digitalengineeringlibrary.7b shows the signals of the K counter. When the DN/UP signal is permanently low. When the DNUP signal is permanently high. the positive-going edges of the carry and borrow signals are used to control the frequency of a digitally controlled oscillator. As will be seen later. The average number of carries then becomes larger than the average number — — of borrows per unit of time. We can say that the upper ∏N counter will produce a carry pulse whenever more than N pulses of an ensemble of M pulses have been UP pulses. But it will generate this carry only when the ∏M counter does not receive M pulses. — — Figure 6. In Fig. The K counter is part of the popular type 74xx297 ADPLL. which will be treated in Sec. The performance of this ﬁlter is very nonlinear. the borrow output gets high when the contents of the DN counter are equal to or more than K/2. where M > N always. The most significant bit of the UP counter is used as a carry output. the ∏N counter would have been reset. All rights reserved. however. the UP counter gets more clock pulses on average than the DN counter.1. As will be shown in Sec. As also seen in the diagram. In this example. In analogy. the UP counter counts up but the DN counter stays frozen. 6. and the output signal ud of the phase detector is a square wave — — having exactly 50 percent duty cycle. A similar statement can be made for the lower ∏N counter in Fig.com) Copyright © 2004 The McGraw-Hill Companies. 6. The N-before-M ﬁlter uses two frequency counters scaling down the input signal by a factor N and one counter scaling down by M. As explained by Fig. Both counters recycle to 0 when the contents exceed K . In the opposite case. thus the duty cycle of the DN/UP signal becomes asymmetric. Another digital loop ﬁlter is the so-called N-before-M counter (Fig. and the DN counter counts on the next 8 pulses.3. and the most signiﬁcant bit of the DN counter is used as a borrow output.

13. We will now deal with digital loop ﬁlters compatible with an N-bit parallel input signal. With digital loop ﬁlters. 2. When a digital ﬁlter is realized.. i.1). F(z) is the ratio of the z transforms of the signals uf and ud. as indicated for the K counter.8 Reset to all counters Block diagram of the N-before-M loop ﬁlter.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 215 ∏ N counter UP e. An introduction to digital ﬁltering is given in App. any desired transfer function performed by an analog loop ﬁlter (and many additional ones) can be realized. a majority of incoming pulses are DN pulses. which yields a recursion of the form 12. The obvious solution for this case is the digital ﬁlter. phase detector type 4 u1 PD u2 Reset Carry ∏ M counter Reset DN ∏ N counter Reset Borrow Figure 6.6) In implemention of the digital ﬁlter. yielding the so-called z transfer function F(z). C. All rights reserved.com) Copyright © 2004 The McGraw-Hill Companies. this equation is transformed back into the time domain. The outputs of the N-before-M ﬁlter can be used in a similar way to control a DCO.g.5) which is the ratio of the Laplace transforms of the signals uf and ud (for signal deﬁnitions. where z is the z operator.14. F ( z) = U f ( z) U d ( z) (6. .e. the performance of an analog loop ﬁlter is described by its transfer function F(s): F (s) = U f (s) U d (s) (6. Any use is subject to the Terms of Use as given at the website. which operates by itself with N-bit input and N-bit output signals.19 Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary. As we know. the transfer function F(s) of a prototype analog ﬁlter is transformed into the z domain. refer to Fig.

1]T ) + b2ud ([n .13.9). Another DCO type is the so-called increment-decrement (ID) counter shown in Fig.1.2. . uf [(n . (n . (For a ﬁrst-order digital ﬁlter.a1uf ([n . .10a shows. Furthermore. . in a recursive digital ﬁlter. . b0.16 This DCO is intended to operate in conjunction with those loop ﬁlters that generate carry and borrow pulses. We consider the most obvious solutions here. a clock input (ID clock). and b1 do not vanish. an increment (INC). from loop filter N modulus control ∏ N counter OUT Fixed high-frequency oscillator Figure 6.10b. The number of “delayed” samples of uf and ud that have to be taken into account is equal to the order of the digital ﬁlter.3 Digital-controlled oscillators A variety of DCOs can be designed. 6. The N-bit parallel output signal of a digital loop ﬁlter is used to control the scaling factor N of the ∏N counter.1. nT. . for example. The recursion formula calculates the output signal uf(nT) in the nth sampling instant from the value of ud sampled at this instant and from one or more previously sampled values of ud. and a decrement (DEC) input.) 6. which means that they exist only at discrete time instants t = 0. . Any use is subject to the Terms of Use as given at the website. denote the values of the sampled signal uf at sampling instants t = nT.com) Copyright © 2004 The McGraw-Hill Companies. 6. As Fig. Probably the simplest solution is the ∏N counter DCO (Fig. .7) The signals uf and ud are sampled signals now.digitalengineeringlibrary.All-Digital PLLs (ADPLLs) 216 Chapter Six uf (nT ) = b0ud (nT ) + b1ud ([n . . . . Downloaded from Digital Engineering Library @ McGraw-Hill (www. . such as the K counter or the Nbefore-M ﬁlter discussed in Sec.1)T.a2uf ([n .14 The terms uf (nT). 6.9. typically 10 to 20 times the corner frequency.1)T]. the ID counter has three inputs. . The sampling frequency fs = 1/T must be chosen much larger than the 3-dB corner frequency of the ﬁlter.10a. The operation of the ID counter follows from the waveforms shown in Fig.2]T ) . uf(nT) depends on values of uf calculated in previous sampling instants. A ∏N counter is used to scale down the signal generated by a high-frequency oscillator operating at a ﬁxed frequency. 6. 6. where T is the sampling interval.9 Block diagram of a ∏N counter DCO. only the ﬁlter coefﬁcients a1. All rights reserved. T.◊ ◊ ◊ (6.1]T ) .2]T ) + ◊ ◊ ◊ . The ai and bi terms are called ﬁlter coefﬁcients. 2T. they can be implemented by hardware or by software.

Downloaded from Digital Engineering Library @ McGraw-Hill (www. . Any use is subject to the Terms of Use as given at the website. (e) Waveforms for the case where a borrow input is applied to the DEC input. (a) Block diagram.FF ID out (b) ID clock Toggle . (d) Waveforms for the case where a carry input is applied when the toggle ﬂipﬂop is in the 1 state.digitalengineeringlibrary.FF Carry advanced ID out (c) Figure 6.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 217 ID clock CP Carry INC OUT ID out Borrow DEC (a) ID clock Toggle .10 ID counter DCO. (b) Waveforms for the case where no carries and no borrows are applied to the INC and DEC inputs. respectively. All rights reserved. (c) Waveforms for the case where a carry input is applied when the toggle ﬂipﬂop is in the 0 state.com) Copyright © 2004 The McGraw-Hill Companies.

Any use is subject to the Terms of Use as given at the website. In the absence of carry and borrow pulses. The output of the ID counter (IDout) is obtained by the logical function IDout = IDclock ◊ Toggle . the duration of these signals is not of concern here.10b. the ID counter simply divides the ID clock frequency by 2. see the waveforms in Fig.FF Borrow delayed ID out (e) Figure 6.10 (Continued) Carry pulses (as delivered. Fig. for example. The carry signal is processed only in the period where the toggle ﬂipﬂop is set high. .FF.7) are fed to the INC input and borrow pulses to the DEC input. it produces an output pulse (IDout) on every second ID clock. All rights reserved.10a. The ID counter is sensitive on the positive-going edges of the carry and borrow inputs.10b shows. by a K counter. 6. one must know that this circuit contains a toggle ﬂipﬂop.All-Digital PLLs (ADPLLs) 218 Chapter Six ID clock Toggle . the toggle ﬂipﬂop toggles on every positive edge of the ID clock if no carries and borrows are present. which is not shown in the schematic diagram of Fig. To understand the function of the ID counter. As the waveform Toggle-FF in Fig.FF Carry advanced ID out (d) ID clock Toggle .digitalengineeringlibrary. 6. If the carry gets “true” when the toggle ﬂipﬂop Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies. Now we assume that a carry pulse appears at the INC input of the ID counter. 6. 6.

for example. If more carries or borrows are delivered. This type of DCO generates sine and/or cosine waveforms by looking up tables stored in read-only memory (ROM). the maximum frequency of carry or borrow pulses must not be higher than one-third the frequency of the ID clock. as will be shown in Sec. This of course limits the hold range of the ADPLL. this ﬂipﬂop is set low on the next ID clock and remains low during two ID clock periods. Any use is subject to the Terms of Use as given at the website.10e demonstrates what happens when a borrow pulse is generated. Because the carry can be processed only when the toggle ﬂipﬂop is in the high state. . . and not from 16 to 24 Hz. Downloaded from Digital Engineering Library @ McGraw-Hill (www. As we will see in Sec. The next IDout pulse is therefore delayed by one ID clock period.30 The block diagram of a waveformsynthesizer DCO is shown in Fig. . the toggle ﬂipﬂop is set high onto the next positive edge of the ID clock and remains high during two ID clock periods.digitalengineeringlibrary.” When the average frequency of the carries is such that all are processed. . This means that the next IDout pulse is advanced in time by one ID clock period.) Because the ID counter needs three ID clock periods to process one carry or one borrow. some are “overslept. the instantaneous frequency of the IDout signal is increased by n/2 hertz when n carries are detected in 1 second. This is most easily understood if we assume that the frequency of the ID clock is 32 Hz. We will discuss software implementations of the PLL in Chap. As soon as a borrow is sensed. 6. the “next” IDout pulse is advanced eight times in 1 second by 1/32 second. Without any carry. the output frequency would be 16 Hz. If the carry becomes true when the toggle ﬂipﬂop is set high. 6. The waveform-synthesizer DCO—the third and last DCO to be considered here—lends itself almost ideally to implementation by software. .11a. the limited output frequency range of the ID counter restricts the realizable hold range of the ADPLL. . All rights reserved. Generally. . (Note that the explanation of ID counter performance has been slightly simpliﬁed. It stays low. 6.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 219 is in the low state (Fig. the actual ID counter circuit consists not only of the mentioned toggle ﬂipﬂop. 6. The two DCO circuits discussed hitherto are better suited for hardware than for software implementations. the output frequency of the ID counter cannot be as high as the frequency of the ID clock. the toggle goes high onto the next positive edge of the ID clock. 8.10d.10c). during two ID clock intervals thereafter. In analogy. but also contains eight more ﬂipﬂops and a number of gates.com) Copyright © 2004 The McGraw-Hill Companies. the maximum frequency of the IDout signal is reached when the toggle ﬂipﬂop follows the pattern high low low high low low. a borrow is processed only when the toggle ﬂipﬂop is in the low state. but at most only two-thirds of that value. as shown in Fig.3. The exact operation of the ID counter can be deduced from the data sheet of the 74HC/HCT297. however. and one borrow pulse causes 1/2 cycle to be deleted correspondingly.3. If 8 carries are detected within 1 second. Figure 6. The number of output pulses is therefore increased from 16 to 20 Hz during that period. 6. Thus the minimum output frequency of the ID counter is one-third the ID clock frequency. The ID counter delivers the minimum output frequency when the toggle ﬂip-ﬂop shows the pattern low high high low high high. one carry pulse causes 1/2 cycle to be added to the IDout signal. Consequently.

In the case of the 0.11b it has been arbitrarily assumed that the sampling period is 50 ms.5 Hz.11 Waveform-synthesizer DCO. most actual waveform synthesizers operate much faster. of course. . When generating a 1-Hz sine (a) (b) Figure 6. 6. .e. .com) Copyright © 2004 The McGraw-Hill Companies.. 2T. twice as many samples (40) are produced within a full period. . T. It shows that a 1-Hz sine wave is generated with a resolution of 20 samples for a full period. . In the example of Fig.5 Hz in this example).All-Digital PLLs (ADPLLs) 220 Chapter Six The waveforms in Fig. irrespective of the desired frequency). (b) The waveforms show how sine waves with frequencies of 1 Hz and 0. It operates at a ﬁxed clock rate (i.11b demonstrate how the synthesizer generates sine waves of different frequencies (1 Hz and 0. nT. All rights reserved. it calculates a sample of the synthesized signal at the sampling instants t = 0. (a) Block diagram. 6.digitalengineeringlibrary. Downloaded from Digital Engineering Library @ McGraw-Hill (www. are synthesized.5-Hz sine wave. Any use is subject to the Terms of Use as given at the website. respectively. Lower-frequency signals are generated with higher resolution than higherfrequency signals.

. the increment DF is given by DF = 2 pfT (6. 6. which encompasses a large variety of mathematical operations. The last example to be discussed is a typical software-based system. and a review of the most important systems is found in Ref.12a. 6. There is an extended literature on this subject. and the phase angle F is incremented by an amount DF = 2p/20 at every clock period. The ﬁrst two are hardware implementations.12b. It is no problem to generate “simultaneously” a sine and a cosine function. the negativegoing edges of u1* trigger a monoﬂop which generates very short pulses. First. By AND-ing u1 and u1*. 2p/20.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 221 wave. 8. An example of the application of a waveform-synthesizer DCO is presented in Sec. There is no reason why they could not be designed to use software as well. a clock signal CK is generated that is applied to the counting input of an up/down counter. Moreover. All rights reserved. Digital waveform synthesizers are easily implemented by using single-chip microcomputers.2 Examples of Implemented ADPLLs Based on the numerous variants of all-digital PDs. 6. an almost unlimited number of ADPLLs can be built by combining compatible functional blocks. Any use is subject to the Terms of Use as given at the website.30 The speed of trigonometric computations can be greatly enhanced by using table-lookup techniques rather than by calculating a sine function with a Taylor series or Chebyshev polynomials. the input signal u1 is ﬁrst preprocessed by a pulse-forming network (see the dashed box on the left). 3(2p/20). The generated signals are shown in Fig. 6. If an arbitrary frequency f is to be produced. 6. A hardware implementation of this type of PLL is certainly not impossible. 6. The signal u1* is used to set the state of D-ﬂipﬂop FF3.11a. when a Hilbert-transform phase detector is used with an ADPLL system (refer to Fig. These Downloaded from Digital Engineering Library @ McGraw-Hill (www. this signal is labeled control on the left of the ﬁgure. D-ﬂipﬂop FF1 scales down the frequency of the input signal by a factor of 2. A detailed discussion of every possible ADPLL system would go beyond the scope of this book. The downscaled signal is denoted u1*. The duration of CK is one-quarter of the period of u1*. and DCOs. the synthesizer calculates the sine function for the phase angles F = 0 (initial value). 2(2p/20). we therefore consider only three typical ADPLL implementations.39 In this circuit.4a). the loop ﬁlter preceding the waveform synthesizer must deliver the digital signal f.digitalengineeringlibrary.1 ADPLL example 1 The ﬁrst example of an ADPLL is depicted in Fig.com) Copyright © 2004 The McGraw-Hill Companies. . . . as required. As shown in Fig.8) where T is the sampling period.2. which serves as a phase detector. . 6.2. but the hardware would be very complex. loop ﬁlters.

.12 All-digital PLL system. Any use is subject to the Terms of Use as given at the website. Two cases are shown: (1) divider ratio N too small.digitalengineeringlibrary.222 Pulse forming circuit Loop Filter CK D Q FF1 Q Mono Flop FF2 K Phase detector Modulus Control u2 TC ÷M counter CP TC variable ÷ N divider CP fc FF3 CP CP Q N~uf Q J UP/DN Q D ud UP/DN counter u1* CP u1 CP Load Start Reset All-Digital PLLs (ADPLLs) (a) DCO Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies. Figure 6. (2) divider ratio N too large. (a) Block diagram. All rights reserved. example 1. (b) Corresponding waveforms.

which will be discussed in the following paragraph. and the modulo-N Downloaded from Digital Engineering Library @ McGraw-Hill (www. Their duration must be shorter than the period of the high-frequency clock fc. When it reaches the terminal count (TC)— which is 0 in this case—a pulse is delivered at the TC output. The clock signal fc causes the divider to count down.12a represents a DCO (digitalcontrolled oscillator). Any use is subject to the Terms of Use as given at the website. The variable modulo-N divider is a down counter. All rights reserved.digitalengineeringlibrary. a variable modulo-N divider and a ﬁxed modulo-M counter.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 223 u1 u1* CK Start T0 Case 1: "early" Content of ÷ M counter TC T0 0 ud reset reset Case 2: "late" TC Content of ÷ M counter 0 set set ud (b) Figure 6. Its content starts with the number N. which is loaded in parallel by the Load input. . This immediately reloads the content N (see the OR gate at the Load input). The dashed enclosure on bottom right of Fig.com) Copyright © 2004 The McGraw-Hill Companies. It is built from a cascade of two counters.12 (Continued) pulses are labeled Start. 6.

that is. the high-frequency clock delivers exactly NM pulses during one cycle of the input signal u1. and the terminal count is reached in shorter time. When the locking process starts. All rights reserved. As soon as the terminal count is reached. a pulse is delivered at the TC output. f1/2. Consequently. The pulses applied to the CP input ramp up its content until it reaches the terminal count.12b. N is too large initially so that the modulo-M counter requires a period longer than T0 to reach TC. i. the modulus N of the variable modulo-N divider can have an arbitrary value. the terminal count of the modulo-M counter would be reached exactly T0 seconds after reset. 6. The positiveedge-triggered JK-ﬂipﬂop FF2 was initially set to its 1 state by the Start pulse..12a. and the content wraps around to zero again.digitalengineeringlibrary.12b. the clock frequency fc should be fc = NMf1 (6. the LOAD pulse of the modulo-N divider would last during several cycles of the fc clock.12a and 6. we want to check the waveforms in Fig. If N already had its correct value. If its pulse width were chosen larger. thus the clock frequency at the CP of the modulo-M counter is too high. This lowers the instantaneous frequency of the TC output of the modulo-N divider. thus N is either too high or too low. In Case 1: early it is assumed that N is smaller than required.e.com) Copyright © 2004 The McGraw-Hill Companies. Because the UP/DN counter immediately controls the frequency of the DCO. Now the TC output of the modulo-M counter resets FF2 before the low-to-high transition of u1* occurs. Under this condition. whose period is marked T0 in Fig. this counter acts as a loop ﬁlter. If this condition is met.9) where f1 is the frequency of the input signal u1. thus inhibiting the counter to change its content. whose output is labeled ud (phase detector output) in Figs. The ﬁxed modulo-M counter is an up counter. . To see how the loop becomes locked. Note that the state of ud has been indeterminate at the start of the locking process. 6. Because ud is low now. The counter then continues counting up.12b. until N has the correct value. 6. 6. As mentioned above. shown on right top of Fig. and the terminal count of the moduloM counter will be reached later in the next cycle of u1*. In this case the frequency of u2 equals the frequency of u1*. The phase detector must adjust the value of N by increasing or decreasing the content of the UP/DN counter. This process repeats until the modulo-M counter reaches TC after occurrence of the positive edge of u1*. the next positive edge of u1* resets D-ﬂipﬂop FF3. The Start pulse resets the modulo-M counter on each high-to-low transition of signal u1* (see the waveform “Content of ∏M counter”). In Case 2: late. Its content is reset to 0 on application of a Reset signal. 6. the next CK (clock) pulse causes the UP/DN counter to increase its content (N) by 1. hence its waveform is drawn by the shaded area in Fig. D-ﬂipﬂop FF3 will Downloaded from Digital Engineering Library @ McGraw-Hill (www.All-Digital PLLs (ADPLLs) 224 Chapter Six divider continues counting down.12b. Any use is subject to the Terms of Use as given at the website. which is a positive number here. before the next low-to-high transition of u1*. the duration of the Start pulse must be shorter than the period of the fc clock. When the circuit is locked.

the content of the UP/DN counter ramps up or down depending on the sign of the phase error.2 ADPLL example 2 The second ADPLL system described here is shown in Fig. this circuit is highly nonlinear. the content N of the UP/DN counter will usually toggle between two adjacent values N and N + 1 in successive cycles of u1*. a VCO is also modeled as an integrator. and the already known ID counter (Fig.7).com) Copyright © 2004 The McGraw-Hill Companies. 6.. All rights reserved. The overall divider ratio of the cascade of both counters (modulo-M and modulo-N) then should be NM = 990. we become aware that the UP/DN counter. Most happily. When the lock process has been completed. This causes the next CK pulse to decrease the content N of the UP/DN counter. but it turns out that its inherent stability is just a consequence of this nonlinearity. (2. In the schematic of Fig. where xx stands for the family speciﬁcation (HC. 6. This is the most often used ADPLL conﬁguration. that the lock-in process will be become slower then. the “integral” term at the output of the DCO is not allowed to wind up.). We will analyze this ADPLL in greater detail in Sec. In other words. 6. Downloaded from Digital Engineering Library @ McGraw-Hill (www. however. When trying to model the circuit. The loop ﬁlter is formed by the previously discussed K counter (Fig. which implies that its phase transfer function H(s) has two poles at s = 0. which acts as a loop ﬁlter.33a)]. The IC contains two phase detectors: an EXOR gate and a JK-ﬂipﬂop. S. Note. This ADPLL system requires an external divide-by-N counter. also behaves like an integrator. LS. 6. as described above. Basically. the instantaneous output frequency of the modulo-N divider will become higher.digitalengineeringlibrary. Because of the nonlinearities of the circuit. because its output phase q2 is proportional to the integral of applied control signal uf [Eq. The phase jitter can be made arbitrarily small by increasing the frequency fc of the clock signal. it is available as an integrated circuit with the designation 74xx297. Supposing that M = 100 (i. This obviously results in a phase jitter of the ADPLL’s output signal u2. No such model has been developed to the author’s knowledge. Any use is subject to the Terms of Use as given at the website. two cascaded decade counters are used for the modulo-M counter).1. the EXOR is used. 6. it becomes very difﬁcult to establish a mathematical model.10) is used as DCO. Because there are no compensating zeros in this system.e. assume that the high-frequency clock is fc = 10 MHz and the input frequency is f1 = 10. because the contents of the counters within the DCO are reset on every Start pulse. etc. because the UP/DN counter would probably have to change its initial content much more but can increase or decrease it only in increments of 1 in one cycle of u1*. HCT.13.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 225 be set 1 on the next low-to-high transition of u1*. .2.13. it would get unstable. If a phase error persists for an extended period of time. this does not occur. the counter thereby performing like an integrator.1 kHz.3. hence our circuit contains a cascade of two integrators. 6. N will then settle at higher values. As a numerical example. N will toggle between 9 and 10 in alternate cycles. Consequently. As we know from the theory of the PLL. An analogous statement can be made for a DCO.

All-Digital PLLs (ADPLLs) 226 Chapter Six K modulus control Mf0 K clock DN/UP K counter Carry Borrow XOROUT u1 J Q DEC INC ID clock 2Nf0 ID counter K IDOUT u2' ÷ N counter CP u2 N control Figure 6. In this case. Because the average number of carries and borrows precisely matches. Normally both M and 2N are integer powers of 2 and are mostly derived from the same oscillator. Assume for the moment that the EXOR phase detector is used and that the ADPLL operates on its center frequency. Any use is subject to the Terms of Use as given at the website. In many cases. the up counter will count during two quarters of the reference cycle and the down counter will count in the remaining two quarter periods. so both clock inputs can be tied together. The average number of carry and borrow pulses delivered by the K counter must therefore be the same. This is possible only when the phase difference between the signals u1 and u2¢ is 90°.13 All-digital PLL. All rights reserved. the output signal of the EXOR gate is a symmmetrical square wave whose frequency is twice the center frequency. an IC of the type 74HC/HCT4040 can be used. M = 2N. example 2. For the external ∏N counter. no cycles are added to or deleted from Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary. . Then the ID counter is required to scale down the ID clock precisely by 2. Consequently. The EXOR phase detector is used here. The K counter and the ID counter are driven by clock signals having frequencies of M times and 2N times the center frequency f0. too. The system is supposed to operate at a center frequency f0 referred to the input u1.com) Copyright © 2004 The McGraw-Hill Companies. respectively. This circuit is based on the familiar IC of type 74HC/HCT297.

the output signal of the EXOR phase detector must become asymmetrical in order to allow the K counter to produce more carries than borrows on average. A ﬁrst-order digital loop ﬁlter 3. 6. which performs the operation 1st order digital loop filter a ud Mul uf Adder b optional quadrature output u1 COS (w0t+qe) Hilbert transform phase detector Clock u2 Mul Clock Clock z –1 I Q cosw0t Clock sinw0t f control Waveform synthesizer DCO Figure 6. A waveform-synthesizer DCO (Fig. 6. Any use is subject to the Terms of Use as given at the website. 6.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 227 the ID counter. Downloaded from Digital Engineering Library @ McGraw-Hill (www.30 The system of Fig.com) Copyright © 2004 The McGraw-Hill Companies. example 3.2. A similar system has been implemented by software on a TMS320 single-chip microcomputer (Texas Instruments). .14 is built from functional blocks introduced previously: 1. This system is best implemented by software. however. 6. 6. The output signal ud is digitally ﬁltered by the loop ﬁlter. The DCO generates the in-phase and quadrature signals I and Q required by the Hilbert-transform PD to calculate the phase error. the arithmetic and logic operations within the functional blocks are performed under control of a clock.14 All-digital PLL system. A Hilbert-transform phase detector (Fig. ud ~ qe. If the reference frequency is increased. This means that all routines calculating the output variables of the blocks are executed periodically.14.3 ADPLL example 3 The last example of an ADPLL is illustrated in Fig.11) As indicated in the block diagram.digitalengineeringlibrary.4) 2. All rights reserved.

As can be seen from the data sheet of the 74HC/HCT297. Performance of the ADPLL is most conveniently analyzed by the waveforms of the circuit. that the minimum value of K for the 74HC/HCT297 is 8).1 Effects of discrete-time operation It is our aim to investigate the most important key parameters such as hold range.com) Copyright © 2004 The McGraw-Hill Companies. the contents will be arbitrary at a given time. or the like. The divider ratio of the ∏N counter is 8 in this example (N = 8). phase-transfer functions). (Note. the familiar 74xx297. we investigate the dynamic performance of the most popular ADPLL type.digitalengineeringlibrary. With only minor program modiﬁcations. One cycle of the reference signal u1 consists therefore of 16 cycles of the K clock. which are shown in Fig. however. the ﬁrst-order loop ﬁlter could be turned into a second-order one. Bode diagrams. The contents of the up and down counters are denoted Kup and Kdn. respectively. and controlled oscillators. as shown in Fig.10) where a1 and b0 are ﬁlter coefﬁcients as deﬁned in Eq.a1uf [(n . 6. The signals are plotted for the simple case that the reference frequency f1 equals the center frequency f0. 6. because the systems to be analyzed are mostly nonlinear. 6. Others will operate like classical DPLLs. loop ﬁlters.15. Any use is subject to the Terms of Use as given at the website. For this reason it is absolutely impossible to create a generalized theory of the ADPLL.. an enormous number of different ADPLL systems can be built. To demonstrate that analyzing an ADPLL is not an entirely hopeless job.13.7).g. these two counters are reset when power is applied to the circuit. All rights reserved.3. and lock-in time. the user is forced to look for appropriate models of the corresponding function blocks and then try to get a reasonable description in the form of transfer functions (e. Downloaded from Digital Engineering Library @ McGraw-Hill (www. The K counter modulus is assumed to be 4 (K = 4). 6. Among these variants. 6. When it has been operating for an undeﬁned period of time. We assume for the moment that the EXOR is used as phase detector. One of the major beneﬁts of the software implementation is the simplicity of changing the structure of the ADPLL system.All-Digital PLLs (ADPLLs) 228 Chapter Six uf (nT ) = b0ud (nT ) .14.3 Theory of a Selected Type of ADPLL Because there are so many variants of purely digital phase detectors.30 This would yield a third-order PLL. The frequency of the K clock has been chosen 16 times the clock frequency (M = 16). The mathematical operations performed by the digital ﬁlter are represented by the dashed block in Fig. To investigate the behavior of a particular ADPLL type. some will perform like LPLLs. In many cases. but the functioning of many ADPLLs will have almost nothing in common with LPLLs and DPLLs. (6. so the K clock and the ID clock can be taken from the same generator.1)T ] (6. 6. lock range. application of standard tools (like linear control theory) will fail.13. which was already shown in Fig. .

com) Copyright © 2004 The McGraw-Hill Companies. For the polarities of the clock pulses the following conventions are made: Both counters of the K counter count onto the negative edges of the K clock. Any use is subject to the Terms of Use as given at the website. 6. The EXOR PD is used. and the parameters of the circuit are M = 16. .All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 229 K clock (Mf0) 0 u1 u2' (ID out ÷ 8) XOROUT=DN/UP 8 16 4 Kup K/2 0 4 Kdn K/2 0 Carry Borrow delayed ID clock (2Nf0) Toggle–FF delayed advanced advanced ID out ID out ÷ 2 ID out ÷ 4 Waveforms of an ADPLL system using the IC type 74HC/HCT297. Figure 6. Note that K has been chosen small to simplify the drawing. K = 4. Kup and Kdn can therefore be assigned arbitrary numbers. The toggle ﬂipﬂop within the ID counter toggles onto the positive edge of the ID clock. and N = 8. K cannot be less than 8. Downloaded from Digital Engineering Library @ McGraw-Hill (www.15).digitalengineeringlibrary. The ADPLL operates at its center frequency. in a real application.15 At the instant where the ﬁrst (0th) K clock occurs (Fig. however. All rights reserved.

Carries are produced onto K clocks 1 and 18. and there is exactly one carry and one borrow in the period where u2¢ is low. note the half-cycle of u2¢. Because advancing and delaying of the IDout pulses no longer cancel in a particular half-cycle of u2¢. 6. Because of the carry and borrow pulses. Any use is subject to the Terms of Use as given at the website. In succeeding reference periods (not shown in this ﬁgure) there must be half-cycles of u2¢ that have a duration of 9 K clock pulses.e.digitalengineeringlibrary. the IDout signal does not have constant frequency but rather exhibits phase jitter. The reason for this is that there is exactly one carry and one borrow in the period where u2¢ is high.All-Digital PLLs (ADPLLs) 230 Chapter Six All ﬂipﬂops of the ∏N counter count onto the negative edge of the corresponding clock signal. The bottom-most two signals represent the scaled-down IDout signal. where the scaling factors are 2 and 4.g. Choosing K=M 4 Downloaded from Digital Engineering Library @ McGraw-Hill (www.11) . The output signals IDout ∏ 2 and IDout ∏ 4 are also asymmetrical. Hence the carry becomes high when the content of the up counter has reached K/2. the second stage (denoted IDout ∏ 4) counts onto the negative edge of the IDout ∏ 2 output signal. and borrows are produced onto K clocks 11 and 23.15 are simply the outputs of the most signiﬁcant bit of the corresponding counter. Carries and borrows are now generated only in each second up-counting or downcounting interval. Its duration is 7 K clock pulses instead of 8. Let us choose a larger value for K in the next example. It would be premature. which goes from K clock 4 to 11. K = 8. but the output signal u2¢ (which corresponds to IDout ∏ 8) is symmetrical again. As we see from the Kup and Kdn waveforms.. the up counter is active during the ﬁrst and third quarters of the reference cycle. Hence carries appear on ID clocks 2 and 10. the ﬁrst stage of the ∏N counter (denoted IDout ∏ 2 in Fig. for example.com) Copyright © 2004 The McGraw-Hill Companies. The ripple introduced by delaying and advancing the IDout pulses is therefore canceled at the output of the ∏N counter. whereas the down counter is active during the second and fourth. which correspond to 32 K clock cycles. respectively. the up counter counts up by 4 in one quarter-period of the reference signal u1 on average. its pulses are periodically advanced and delayed by one cycle of the ID clock.16 shows two periods of the reference signal. the output of the toggle ﬂipﬂop becomes asymmetric. (6. Therefore. Figure 6. etc. (Remember that the carry and borrow signals depicted in Fig. however. We conclude that there is no ripple on the output signal if the K modulus is chosen such that it produces exactly one carry (or one borrow) in a quarter-period of the reference signal. Figure 6. All rights reserved. When the ADPLL operates at its center frequency again.) As the IDout waveform shows. and the down counter counts up by 4 in one quarter-period of u1 on average. e.15) counts onto the negative edge of IDout. while borrows are detected on ID clocks 6 and 14. i. this signal shows ripple.16 shows what happens now.. All other parameters remain unchanged. to conclude that there is never ripple in the output signal u2¢ of this type of ADPLL. 6.

ripple is produced.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. If K > M/4.5.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 231 Figure 6. K = 8. the duty factor d of the output signal u2¢ is d = d0 = 0.15. As we will see later. every ADPLL exhibits some ripple if it operates at other frequencies. It is easy to calculate the amount of ripple to be expected under this condition. The ADPLL operates at its center frequency. the edges of the signal u2¢ can be advanced or delayed by Downloaded from Digital Engineering Library @ McGraw-Hill (www.16 Conditions are like those is Fig. An ADPLL having K = M/4 is therefore called a minimum ripple conﬁguration. provides zero ripple when the EXOR phase detector is used. . 6.and down-counting periods do not cancel. but the parameters of the ADPLL are M = 16. and N = 8. Note that the up counter and down counter of the K counter recycle only on every second upcounting or down-counting period.digitalengineeringlibrary. respectively. If carries and borrows in succeeding up. All rights reserved. Ideally.

Now M.12). 6. the frequency of the carries and borrows would clearly be too high.3 (see also Fig. as shown in Sec. we can conclude that for an ADPLL using the EXOR phase detector we have minimum ripple when M is chosen to produce at least one carry in a quarter-cycle of u1 (K £ M/4) and when N is chosen such that all carries and borrows can be processed (N ≥ 2M/K).5 Ê 1 + ˆ Ë Ë N¯ N¯ (6. This is true. K. and that the Q output Downloaded from Digital Engineering Library @ McGraw-Hill (www. All rights reserved. Because the duration of one ID clock cycle is 1/(2Nf0) seconds.5Ê 1 . It will be demonstrated later that ripple can be suppressed by the addition of only a few components. there should theoretically be no ripple in the u2¢ waveform. so the ADPLL would not work properly. and the down counter would generate 2 borrows in one downcounting period. . i. it produces a carry every K/(Mf0) seconds. If a number of carries have to be processed in succession by the ID counter. Because we have chosen N = 8.14) where Npract is also an integer power of 2. we have Npract = 2 · 16/2 = 16.15 again and assume K = 2 now (which is not possible.10). Generally..com) Copyright © 2004 The McGraw-Hill Companies. When the up counter is counting up for an extended period of time. (6.All-Digital PLLs (ADPLLs) 232 Chapter Six at most one ID clock cycle. Consequently. and N are mostly integer powers of 2.1. we have no overslept carries (or borrows) when the condition N > N min = 3M 2K (6. only when the ID clock frequency is chosen large enough so that the ID counter is able to process all carries and borrows. 6. In this example. Because 2 carries and 2 borrows would cancel in succeeding up-counting and down-counting periods. however.. less than one carry (or borrow) is generated within one quarter-period of u1 on average.13. Let us check what happens if K is chosen smaller than M/4. however.e.digitalengineeringlibrary. If we consider Fig. The amount of ripple is given by Eq. 6. the up counter would generate 2 carries in one upcounting period. the relative duty factor deviation is 1/N at worst. We suppose that the signals u1 and u2¢ are connected to the J and K inputs of the ﬂipﬂop in Fig.13) is met. by a time interval of 1/(2Nf0). Now we have to investigate how the ADPLL performs when the JK-ﬂipﬂop phase detector is used. with the 74HC/HCT297 IC). When K is chosen greater than M/4.ˆ < d < 0. the delay between any two carries should be larger than 3 ID clock periods. so ripple will be created. the actual duty factor can vary in the range 1 1 0. so in practical applications the minimum N will be chosen N > N pract = 2M K (6.e. Any use is subject to the Terms of Use as given at the website. 6.12) i. respectively.

and N = 8. The parameters of the circuit are M = 16. If both signals u1 and K clock (Mf0) 0 u1 u2'(ID out ÷ 8) JK–flipflopOUT =DN/UP 8 Kup k/2 0 8 Kdn k/2 0 Carry advanced Borrow ID clock Toggle–FF ID out ID out ÷ 2 ID out ÷ 4 Figure 6. All rights reserved.17 8 16 ripple delayed Conditions are like those in Fig. Downloaded from Digital Engineering Library @ McGraw-Hill (www. . K = 8. Any use is subject to the Terms of Use as given at the website. 6.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 233 — — of this ﬂipﬂop is tied with the DN/UP input of the K counter.digitalengineeringlibrary. The waveforms for this example are shown in Fig.com) Copyright © 2004 The McGraw-Hill Companies. As we know from theory of the DPLL. 6. K = 8.17 for the parameters M = 16. the signals u1 and u2¢ should be in antiphase when the PLL operates at its center frequency.15. and N = 8. The ADPLL operates at its center frequency. but the JK-ﬂipﬂop phase detector is used.

the down counter would be active in the ﬁrst half of the reference cycle. Furthermore. K = 4.2 The hold range of the ADPLL (6. In contrast to the EXOR phase detector. and N = 8. and hence produces M/(2K) carries.17) It is time now to see what happens if the frequency f1 of the reference signal deviates from the center frequency f0. and the down counter would be active in the second half.5Ê 1 + Ë Ë 2 KN ¯ 2 KN ¯ (6. A simple consideration yields the range of frequencies the ADPLL can work with. let the reference frequency be f1 = 1. It follows that the duty cycle of u2¢ can vary in the range M ˆ M ˆ 0. In many cases.25 f0.5Ê 1 + Ë Ë 2K ¯ 2K ¯ Selecting a large value for K reduces the ripple accordingly. 6. the up counter must operate during longer time intervals than the down counter. where one ID clock cycle lasts for 1/(2Nf0) seconds. Any use is subject to the Terms of Use as given at the website. The asymmetry is easily calculated in this case. Figure 6. To get minimum ripple. i. the K clock and the ID clock are taken from the same generator. both up and down counters would overﬂow once in a counting period. We assume ﬁrst that an EXOR is used as phase detector. M = 2N.All-Digital PLLs (ADPLLs) 234 Chapter Six u2¢ were precisely symmetrical. the up counter overﬂows M/(2K) times.digitalengineeringlibrary. All rights reserved. which corresponds to a phase error near 90°. On average. the up counter produces more than one carry in one up-counting period.5Ê 1 < d < 0.3. As the waveforms show. The phase error must therefore become positive. In one upward-counting period. .. the waveform of u2¢ is unsymmetrical even if K is speciﬁed for minimum ripple.e. the down counter is active in the ﬁrst half of the cycle. which of course increases the ripple on the output signal. 6. we should choose K= M 2 (6. This forces the ID counter to increase its output frequency. The up counter is active most of the time.16) for the JK-ﬂipﬂop PD. Then the duty cycle is in the range 1 ˆ 1 ˆ 0.18 shows.18 shows the waveforms for the case M = 16. the signals u1 and u2¢ are nearly in phase now. As Fig. It is clear that the ADPLL generates the maximum output frequency Downloaded from Digital Engineering Library @ McGraw-Hill (www. Because the borrow causes one of the IDout pulses to be delayed by one ID clock.com) Copyright © 2004 The McGraw-Hill Companies. For the ADPLL to generate a higher frequency. the waveform for u2¢ becomes asymmetric. and many more carries than borrows are produced. The same number of borrows are generated by the down counter as well. too.15) When K is chosen smaller than M/2. The M/(2K) carries cause the next positive edge of the u2¢ signal to be advanced by M/(2K) ID clock cycles.5Ê 1 < d < 0.

All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 235 K clock (Mf0) 0 u1 6.8 19.3 and Fig. the up-counting section of the K counter is active most of the time.digitalengineeringlibrary.4 12.8 phase error! 19. and more carries than borrows are generated on average. 6.com) Copyright © 2004 The McGraw-Hill Companies. Consequently. . The reference frequency is 1. The frequency of carry pulses then is given by fmax = f0 M K (6. when the K counter is continually counting up.19) Because the ∏N counter scales down that frequency by N.25 times the center frequency here.15.10). 6.4 u2' (ID out ÷ 8) XOROUT = DN/UP Kup 4 k/2 0 4 k/2 0 12.18) Because each carry applied to the increment input of the ID counter causes 1/2 cycle to be added to the IDout signal (refer to Sec. the frequency at the output of the ID counter is increased by DfIDout = f0 M 2K (6.2 Kdn Carry advanced Borrow ID clock (2Nf0) Toggle–FF ID out ID out ÷ 2 ID out ÷ 4 Figure 6.1. All rights reserved.2 8 16 24 6. Any use is subject to the Terms of Use as given at the website.18 advanced advanced advanced advanced delayed Conditions are like those in Fig. the maximum frequency deviation from the center frequency the ADPLL can handle is Downloaded from Digital Engineering Library @ McGraw-Hill (www. 6.

. . As a consequence. .com) Copyright © 2004 The McGraw-Hill Companies.21) A simple consideration shows that the hold range given by Eq. Simulations show that even for very large frequency steps applied to the reference input.20) is realizable. Borrow pulses occur from time to time. (6. however. The question arises here. however. and hence is a very fast system. that the duration of one cycle of the reference signal is now 4/5 of the duration of the reference period 1/f0. . It can be observed that the output signal u2¢ exhibits ripple or phase jitter whenever the reference frequency f1 deviates from the center frequency f0. From the LPLLs and DPLLs it is well known.digitalengineeringlibrary. 19. Thus the edges of u1 generally do not coincide with the edges of the output signal u2¢.20) or (6. Any use is subject to the Terms of Use as given at the website. .2.8. but there are short intervals where the down counter becomes active. say to about 90 percent of it.20) This is nothing else than the hold range of the ADPLL.13). If N is smaller than Nmin. This is exactly the situation depicted in Fig. K clocks. this type of ADPLL is a ﬁrst-order loop whose time constant is in the order of the period of the reference signal. the author cannot give an answer that is theoretically justiﬁed. some of the carries and borrows are overslept. or in other words. (6. All rights reserved.6 cycles of the K clock. K = 4. the K counter is not continually counting up.25 f0. Hence the ADPLL is not able to operate at the limit of the hold range.All-Digital PLLs (ADPLLs) 236 Chapter Six Df H = f0 M 2 KN (6. but computer simulations have shown that the maximum frequency deviation comes close to the hold range. 7. which is not realized in practice. the ADPLL does not lock out. that the useful frequency range is not given by the hold range but rather by the lock-in or pullin ranges. Assuming that the reference signal performs a positive edge on the 0th K clock. the next edges occur after 6. For the parameters M = 16. and hold range are all about the same for this circuit. pull-in range. We perform some ADPLL simulations in Chap. Also here. 6. only if N is chosen larger than Nmin deﬁned in Eq. The hold range given by Eq. If the quotient f1/f0 is a rational fraction Downloaded from Digital Engineering Library @ McGraw-Hill (www. so for the practitioner it seems affordable to state that lock-in range. we obtain a theoretical hold range of DfH = 1. the duration of one reference cycle is 12. whether such parameters can also be deﬁned for the ADPLL under concern.18. and the hold range is limited to Df H = f0 3 (6. (6. as seen from Fig. We should note.18. As the following analysis of phasetransfer function indicates. The author does not know an exact method to calculate the usable frequency range of an ADPLL.21) is a theoretical limit.4. 6. pullout range. however. 12. and N = 8 and for an EXOR phase detector. We see very clearly from the waveform of u2¢ that the phase error increases from cycle to cycle.

that is. This duty factor is deﬁned by the average fraction of time the up counter is active. whereas for dK = -1 the down counter is permanently active. In this case the ripple pattern of the u2¢ signal becomes periodic. the phase detector gain is Kd = 1 p (6. 6. dK will be 1 for a phase error of qe = p/2 and -1 for qe = -p/2. The phase detector represents a zero-order block with gain Kd.digitalengineeringlibrary. 6. To get the phase transfer function. Thus for dK = 1 the up counter is permanently active.22a) For the JK-ﬂipﬂop. Deﬁnitions of symbols in text. a mathematical model of the ADPLL (Fig.19. Any use is subject to the Terms of Use as given at the website.22b) Phase detector dK DN/UP K counter 2pf0M Ks wcarry qcarry q1 + – q2 Kd ÷ N counter 1 N Figure 6. Downloaded from Digital Engineering Library @ McGraw-Hill (www.19 ID counter 1 2 Mathematical model of the ADPLL. For the EXOR we then have Kd = 2 p (6. n = integer. If f1/f0 is not rational. it is possible to derive the phase transfer function and the error transfer function for the ADPLL.3. n cycles of the reference signal have exactly the same duration as m cycles of a signal whose frequency equals the center frequency. The phase detector output signal controls the duty factor dK of the K counter. however. then we have mT0 = nT1.com) Copyright © 2004 The McGraw-Hill Companies.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 237 f1 m = f0 n where m. the ripple pattern does not repeat itself. .13) must be found.3 Frequency-domain analysis of the ADPLL As with the LPLL and the DPLL. All rights reserved. where T0 = 1/f0 and T1 = 1/f1. If the EXOR phase detector is used. The model is shown in Fig. 6.

com) Copyright © 2004 The McGraw-Hill Companies. We prefer.24) Because we are looking for the phase-transfer function. Any use is subject to the Terms of Use as given at the website. the phase detector gains become 4 for the EXOR and 2 for the JK-ﬂipﬂop. All rights reserved. Having the model. the ∏N counter is a block with gain 1/N.All-Digital PLLs (ADPLLs) 238 Chapter Six In a number of other texts.27) w0 s + w0 (6. to specify all phase signals in radians in order to get the required phase-transfer function. the phase-transfer function of the K counter becomes K K (s) = Q carry (s) 2 pMf0 = D K (s) Ks (6. however.digitalengineeringlibrary. Here. the error-transfer function He(s) is H e (s) = w0 s + w0 (6. the phase error is alternatively speciﬁed in cycles (of the reference period 1/f1) and not in radians. Clearly.29) Downloaded from Digital Engineering Library @ McGraw-Hill (www.3. 6. respectively. Because the phase is simply the integral of angular frequency over time. Now the mathematical model of the K counter must be found.2. the ID counter can be modeled simply by a zero-order block having the gain 1/2. As explained in Sec. the number of carry pulses generated per second is given by fcarry = d K Mf0 K (6.23) The corresponding angular frequency wcarry is therefore w carry = d K 2 p Mf0 K (6.25) where DK(s) and Qcarry(s) are the Laplace transforms of the signals dK and qcarry. we now ﬁnd the phasetransfer function H(s) to be H (s) = where w0 is given by w0 = K d pMf0 KN (6.26) Moreover. Because each carry pulse applied to the incremental input of the ID counter causes 1/2 cycle to be added to the IDout signal.28) Clearly. Its time constant is given by t= 1 KN = w 0 K d pMf0 (6. this ADPLL is a ﬁrst-order system. . we must know the phase qcarry of the K counter output signal.

so the K counter generates the maximum number of carries. to the DN/UP input of the K counter.31) Downloaded from Digital Engineering Library @ McGraw-Hill (www. the ADPLL settles extremely fast.e. the average number of carries produced is only about half that number for a normal ADPLL circuit (Fig. Consequently.20c shows the case for maximum phase error qe. we obtain t = (N/8)T0 for the EXOR and t = (N/2)T0 for the JK-ﬂipﬂop PD.. its response onto phase or frequency steps becomes slower.30a) If the K modulus is chosen for minimum ripple.4 Ripple reduction techniques We saw in Sec. 6.1 that ripple in ADPLLs can be minimized by choosing an optimum value for the K counter modulus.3. K = M/4 when the EXOR PD is used or K = M/2 when the JK-ﬂipﬂop PD is used. All rights reserved. the time constant of the ADPLL becomes t(EXOR ) = and for the JK-ﬂipﬂop phase detector t(JK ) = KN Mf0 (6.20a shows a ripple cancellation scheme which uses a feature of the K counter that has not yet been mentioned: the enable (EN) input of the K counter. There are other simple ways to reduce ripple. the up counter becomes active. Some numerical examples will be presented in Chap. i. Now. In this circuit. As we easily recognize from the waveforms. It has been shown16 that the hold range of the circuit becomes Df H = Mf0 2 N (2 K + 1) (6. The K counter is in operation only when EN is high. . This shows that for small divider ratio N. The DN/UP input is driven by the Qn-1 signal now.e. Figure 6.com) Copyright © 2004 The McGraw-Hill Companies.13). the EN signal is high about 50 percent of the time. Its output is not connected. i. Figure 6. where T0 = 1/f0. but rather to its enable input — — EN. 6. the hold range is reduced roughly by a factor of 2. so neither the up counter nor the down counter is active. the second most signiﬁcant bit of the ∏N counter is used in addition (denoted Qn-1). At the same time.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 239 Thus for the EXOR phase detector.3. Only one additional inverter is required in this circuit. If this is the case. Any use is subject to the Terms of Use as given at the website. This forces the signals u1 and u2¢ to be nearly in phase when the ADPLL operates at its center frequency (Fig. 6. the EXOR phase detector is utilized.20b). The frequency at the Qn-1 output is twice the frequency of the output signal u2¢. To suppress ripple.digitalengineeringlibrary. 7. K = M/4 for the EXOR and K = M/2 for the JK-ﬂipﬂop PD.30b) KN 2 Mf0 (6. 6. the EN input is FALSE most of the time.. — — however. Only when the reference frequency deviates from the center frequency is a phase difference between u1 and u2¢ established. Only for large N.

32) Still other ripple cancellation schemes are discussed in Ref. refer to text. All rights reserved. its settling time can be made extremely short. this reduces to Df H ª f0 2K (6.All-Digital PLLs (ADPLLs) 240 Chapter Six K modulus control K clock DN/UP EN K counter Mfo Carry Borrow u1 XOROUT u2¢ J Q ID clock ID counter 2Nfo K (not used) ∏ N counter CP Qn Qn–1 IDOUT (a) Figure 6. Downloaded from Digital Engineering Library @ McGraw-Hill (www. If M = 2N and K is large. 16. where a slower response—combined with better noise-suppression capability—is desired. however.20 Ripple cancellation scheme for an ADPLL. 6. a second-order ADPLL is obtained. This arrangement has been considered by Rosink16 in some more detail.3. there are other cases. .com) Copyright © 2004 The McGraw-Hill Companies. If two ADPLLs are cascaded.30).digitalengineeringlibrary. (c) The reference frequency is higher than the center frequency. For details. (6.5 Higher-order ADPLLs The ADPLL considered in this section is a ﬁrst-order system. (b) The ADPLL operates on its center frequency. Any use is subject to the Terms of Use as given at the website. This can be an advantage in some applications. As we have seen in Eqs. (a) This circuit makes use of the enable (EN) input of the K counter.

The ADPLL is mainly used in the ﬁeld of digital communications. All rights reserved.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. one of which represents a logical 0. serial binary data are transmitted by using two different frequencies.4 Typical ADPLL Applications Because of the availability of low-cost ADPLL ICs. Because the JK-ﬂipﬂop phase detector is Downloaded from Digital Engineering Library @ McGraw-Hill (www. FSK is the abbreviation for frequency shift keying.21. The center frequency f0 of the ADPLL is chosen such that it is between the two frequencies used by the FSK transmitter. this type of PLL can replace the classical DPLL in many applications today. which will be considered in the following.20 (Continued) 6. . In FSK data transmission. 6.digitalengineeringlibrary.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 241 u1 u2 ¢ (Qn) Qn–1 EN (b) u1 u2 ¢ (Qn) qe Qn–1 EN Kup (c) Figure 6. the other a logical 1. A good example is the FSK decoder. An extremely simple FSK decoder circuit is shown in Fig.

the output signal u2¢ must lead the reference signal u1 in order to enable the K counter to produce more carries than borrows on the average. the information transmitted by the FSK signal can be recovered simply by storing the u2¢ signal in a D-ﬂipﬂop every time the reference signal goes high. 6.17).All-Digital PLLs (ADPLLs) 242 Chapter Six K modulus control Mfo K clock DN/UP K counter Carry Borrow u1 u2¢ J Q ID counter ID clock K IDOUT Qn ∏ N counter CP N control D FF CP Figure 6. Because the output signal u2¢ is low for a content less than N/2 and high for a content equal to or more than N/2. If the reference frequency is lower than the center frequency. 6. utilized here. the reverse is true. All rights reserved. the contents of the divided-by-N counter would be just N/2 at the time where the reference signal u1 performs a positive transition. In Sec. however.digitalengineeringlibrary. Any use is subject to the Terms of Use as given at the website. If the reference frequency is greater than the center frequency. An additional D-ﬂipﬂop is used to deliver the demodulated FSK signal. This D-ﬂipﬂop is shown at the bottom of Fig. 6. Consequently.com) Copyright © 2004 The McGraw-Hill Companies. Therefore. . the contents of the divide-by-N counter will be greater than N/2 at the positive transient of u1.21 Q FSK signal FSK decoder using the 74HC/HCT297 ADPLL IC. and the content of the divide-by-N counter is less than N/2 at that instant of time.5 we discuss a design procedure for ADPLLs Downloaded from Digital Engineering Library @ McGraw-Hill (www. the two signals u1 and u2¢ would be exactly in antiphase if the ADPLL were operating at its center frequency (see also Fig.21.

6.20a). it can be used only in applications where no cycles of the reference signal are missing. Consequently all ADPLL parameters are integer powers of 2 in most cases. 6. As indicated by Eq. and N. the only parameter that can be freely selected is N.9.1 Case study: Designing an ADPLL FSK decoder To specify the parameters of this ADPLL system. M should be chosen to be 4K when the EXOR PD is used. respectively.3. .5. this program should not be considered as a universal recipe for every kind of ADPLL but rather as a checklist. As we have seen in Sec. 6.5 Designing an ADPLL Designing an ADPLL is much easier than designing an LPLL or DPLL. the settling time t of the ADPLL also depends on these parameters.digitalengineeringlibrary. We do not specify a settling time t for the moment but will check at the end of the design whether the resulting settling time is appropriate or not. as seen from Eqs. For the divide-by-N counter (refer to Fig. Because the JK-ﬂipﬂop phase detector is edge-sensitive. Given the ratio M/K. K. we can derive the design procedure given in Fig. the output of the JK-ﬂipﬂop would hang up in the 1 or 0 state all the time where the reference signal disappears. which inevitably would lock out the loop. there are a number of interdependencies among the quantities M. 6. which is given by Eq. To demonstrate the design procedure.22. (6. we now implement the FSK decoder described in Sec. we choose a center frequency of f0 = 2400 Hz. If minimum ripple is a goal. and N. (6. the resulting hold range is a function of M. To ensure that both frequencies of the FSK transmitter are within the hold range of the ADPLL. to use the same signal generator for the K clock and for the ID clock. because we have to specify only the three parameters: M. Any use is subject to the Terms of Use as given at the website. K.13). K. Many other ADPLL applications are discussed on the data sheets of the 74HC/HCT29731 and in various application notes delivered by the IC suppliers. For the 74HC/HCT297. refer also to Fig.16 6. On the basis of these general considerations. we must deﬁne ﬁrst its center frequency and hold range. Otherwise. Like the procedures worked out for the LPLL and the DPLL. Furthermore.21. All rights reserved. N should be greater than a minimum value Nmin.4. so N will usually be an integer power of 2. or 2K when the JK-ﬂipﬂop is used. Following the description in Sec.4. Moreover.com) Copyright © 2004 The McGraw-Hill Companies.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 243 and use it to specify the parameters of this application. a straight-binary counter is used in most cases. K must always be an integer power of 2 and can be selected in the range 23 to 217.13. we set M = 2N whenever possible.30a and b). 6. too. 6. The selection of the phase detector represents a further degree of freedom. we specify a hold range of DfH = 600 Hz. 6. and N. for example). Step 1. (6. To avoid “oversleeping” of carries and borrows. Let us assume that the FSK transmitter uses the frequencies f11 = 2100 Hz and f12 = 2700 Hz to encode the binary information 0 and 1. Downloaded from Digital Engineering Library @ McGraw-Hill (www.

Any use is subject to the Terms of Use as given at the website. K.22 Design procedure for the ADPLL. All rights reserved. . Downloaded from Digital Engineering Library @ McGraw-Hill (www. N Calculate DfH M DfH = fo 2KN Step 10 Hold range ok ? n y Step 11 Check N > 3M ? 2K y n END Figure 6.All-Digital PLLs (ADPLLs) START Step 1 Specify ADPLL key parameters : Center frequency fo Hold range DfH (Settling time t) y Step 2 Missing pulses in reference signal? n Step 3a Select EXOR PD Step 3b Select JK. b) n Step 9 Changes values for M.digitalengineeringlibrary.flipflop PD Step 4a For minimum ripple: Set M = 4K Step 4b For minimum ripple : Set M = 2K Step 5 For simplicity of circuit : Try M = 2N Step 6 Select K to get desired hold range : Set K = fo /DfH Step 7 K≥8? y Step 8 Final specification of K Calcalate M (see step 4a.com) Copyright © 2004 The McGraw-Hill Companies.

we choose M = 2N. Hence we must insert an additional JK-ﬂipﬂop between the K clock and the ID clock which scales down the K clock frequency by a factor of 2. Using Eq. Step 6. because K should be chosen as 4 to get the desired hold range of 600 Hz. Step 10. Step 3b. . which is certainly acceptable in this application. Because Nmin = 3 in our case. Let us keep in mind. however. The hold range is OK now (600 Hz). Downloaded from Digital Engineering Library @ McGraw-Hill (www. . All rights reserved. (6. the assumption M = 2N cannot be made. Step 5. The clocks for the K counter and for the ID counter are identical then and can be taken from the same signal source. N must be larger than the minimum value Nmin = 3M/2K. The JK-ﬂipﬂop is used as phase detector. To get the simplest circuit. we look at this circuit and see how it performs. Finally. we check the settling time t of this circuit. K = 8.33) Step 9.digitalengineeringlibrary. The 74HC/HCT297 circuit does not allow K = 4. When simulating the ADPLL on the PC (see Chap. This step reveals the ﬁrst ﬂop in our design. For minimum ripple. but only K = 8. where T0 is the duration of one reference cycle. To avoid overslept carries and borrows. Any use is subject to the Terms of Use as given at the website. we get M = 16. that this ADPLL relies on an input signal which does not show up with missing pulses. . The design proceeds with step 9. Step 4b. we choose M = 2K.All-Digital PLLs (ADPLLs) All-Digital PLLs (ADPLLs) 245 Step 2.com) Copyright © 2004 The McGraw-Hill Companies. The hold range becomes 600 Hz if we specify N = 4. 16. This indicates that the ADPLL settles within two cycles of the reference signal. If we will keep M = 2K (the condition for minimum ripple). The design is completed now. the hold range can be expressed as Df H = f0 1 M = f0 2 KN N (6.30b). Step 11. Choosing the minimum value for K. To get a hold range of 600 Hz. we get t = 2/f0 = 2T0. . The decision of whether the EXOR or the JK-ﬂipﬂop will be used as phase detector has been made in advance. 7). . N = 4 is a valid choice.

digitalengineeringlibrary.All-Digital PLLs (ADPLLs) Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies. . All rights reserved. Any use is subject to the Terms of Use as given at the website.

7. To reduce the ripple. the user would probably increase N. Fig. and N required to meet that goal. In the top-most panel (Conﬁguration) the actual ADPLL conﬁguration is displayed. and N into the corresponding edit windows and hit the Calc frequency params button.2. The ADPLL params are represented by the parameters K. two of them can be chosen arbitrarily. for example. To conﬁgure an ADPLL. 5 and are best explained by a quick tour. The program then computes the resulting hold range fH and 3-dB corner frequency f3dB. labeled Frequency params and ADPLL params. The program then computes the parameters K.1 Setting up the Design Parameters The program distributed with the book can also be used to design and simulate ADPLLs. 7. Hit the Done button to complete the dialog. Start the program and hit the CONFIG speedbutton in the taskbar.Source: Phase-Locked Loops Chapter 7 Computer-Aided Design and Simulation of ADPLLs 7. When the user chooses the ﬁrst of these options and enters the desired hold range. and N as described in Sec. by setting 247 Downloaded from Digital Engineering Library @ McGraw-Hill (www. Below there are two panels. M.3. Any use is subject to the Terms of Use as given at the website. This activates the design dialog box. the program computes the corresponding ADPLL hold range DfH and 3-dB corner frequency f3dB. This brings up the conﬁguration dialog box. As in case of the mixed-signal PLL. M. (2) Alternatively. .20). the user can proceed in two ways: (1) Enter the desired hold range into the edit window labeled fH and then hit the Calc ADPLL params button. M. it is required only to specify the center frequency f0 and the type of phase detector. (6.1.com) Copyright © 2004 The McGraw-Hill Companies. The program therefore sets K = 8 and N = 16 and ﬁnally computes the appropriate value of M. click the ADPLL radiobutton. M. and N. M. 6. Eventually the ripple of the ADPLL could be too large. All rights reserved. Exor or JK-FF. In the panel PLL Category. the program calculates the appropriate values for K. Because we have only one equation for three unknown parameters.digitalengineeringlibrary. and N using Eq. immediately enter values for K. The procedures are similar to those described in Chap. This is not necessarily the optimum choice. For the last-speciﬁed values for K. Fig. Next click the DESIGN speedbutton in the taskbar.

Any use is subject to the Terms of Use as given at the website.com) Copyright © 2004 The McGraw-Hill Companies.2 Dialog box for ADPLL parameter speciﬁcation. 7.Computer-Aided Design and Simulation of ADPLLs 248 Chapter Seven Figure.digitalengineeringlibrary. Figure. 7. Downloaded from Digital Engineering Library @ McGraw-Hill (www. .1 Dialog box for conﬁguring an ADPLL. All rights reserved.

f0¢. 7. The DESIGN dialog exits when the Done button is hit. Because the hold range is proportional to M/KN. hit the SIM speedbutton in the taskbar.Computer-Aided Design and Simulation of ADPLLs Computer-Aided Design and Simulation of ADPLLs 249 N = 32..13). 6. .com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. that is. only a discrete set of output frequencies can be created. As we see from the plot in Fig.3. We are ready now to perform simulations. This opens the simulation dialog box. 7. the program computes in every reference cycle the instantaneous frequency f2 of the output signal u2¢ (see Fig. They are almost identical with those of LPLL and DPLL simulations with the exception that there is no ﬁlter function here. where Df2 is the variation of output frequency. The frame window on the left of the simulation dialog box displays qe (thicker curve) and Df2 (thinner curve). Downloaded from Digital Engineering Library @ McGraw-Hill (www. 7. 7. The parameters of the simulation are entered in the panel on the right side.2 Simulating ADPLL Performance To start ADPLL simulation. M would have to be increased by the same factor. The Bode diagram is obtained by clicking the Plot Bode button. Figure. 6. and f0¢ is the scaleddown center frequency of the ADPLL.digitalengineeringlibrary. In contrast to the mixed-signal PLL there are no voltage signals to calculate.13) and the instantaneous phase error qe. Df2 = f2 . Instead of the signals ud and uf.3.e.3 Simulation of ADPLL performance. Because the output signal u2¢ can change state only on the edges of the clock signal (ID clock in Fig. Fig. i. All rights reserved. The DESIGN dialog box also includes an option to display the Bode diagram of the open-loop and closed-loop gain. by the factor 2.

5. In the ADPLL params panel. no ﬁltering of these variables is performed. Hit the Done button to close the design dialog. According to the theory of this type of ADPLL. Click the SIM speedbutton. .3). You are ready now for simulation.000 into the f0 window.4 kHz. Because we want to apply frequency steps to the reference inputs. 7.com) Copyright © 2004 The McGraw-Hill Companies. 7. 7.14). Any use is subject to the Terms of Use as given at the website. check the Exor radiobutton. and click the CONFIG speed button. In the Center frequency panel. Case study 1: Dynamic performance of the ADPLL using the EXOR PD.digitalengineeringlibrary.3 Case Studies of ADPLL Behavior In this section we will investigate ADPLL performance in some typical applications. This is done by checking the Add noise checkbox and entering appropriate values for SNR(dB) and Noise BW(rel). In the PLL Category panel.3 (see also Fig. In the edit window enter the following parameters f 0 = 100. Close the CONFIG dialog by hitting the Done button. 000 (Hz) df = 6000 (Hz) T = 0. Downloaded from Digital Engineering Library @ McGraw-Hill (www. check the f-step radiobutton (see Fig. where T0 = 1/f0. Because one single value for qe and Df2 is calculated in each reference period. Start the simulation program. check the ADPLL radiobutton. noise can be added to the reference signal. Click the DESIGN speedbutton. In the PD Type panel. We get fH = 12.Computer-Aided Design and Simulation of ADPLLs 250 Chapter Seven the output frequency varies in steps of approximately 3. The result of the simulation is shown in Fig. In the next section we will perform a number of case studies that will reveal the substantial differences in the behavior of ADPLLs compared with the classical LPLLs and DPLLs. as explained in Sec. All rights reserved. enter the values K =8 M = 32 N = 16 Hit the Calc frequency params button.4. As in the case of the mixed-signal PLL. 5.00040 (s) ZoomFact = 1 Add noise: unchecked Hit the RUN button. The program computes the resulting hold range and 3-dB corner frequency.5 kHz and f3dB = 7957 Hz. the time constant of the loop is t = 2T0 = 20 ms. enter 100. The frequency step chosen in this simulation is about half the lock range. This opens the design dialog box.

◊ ◊ ◊ˆ f2 = f0 Ë 2N ± 1 2N ± 2 ¯ (7. Unlike a classical DPLL. . the ADPLL is ﬁrmly locked. Hence the instantaneous frequency f2 of the output signal can take only a number of discrete values. in 60 ms.com) Copyright © 2004 The McGraw-Hill Companies. the frequency of the output signal does not asymptotically approach the reference frequency but oscillates around that value.2. i. This is the most typical property of the ADPLL. All rights reserved. The difference frequency curve looks very noisy indeed. . By the nature of the ID counter.1) For positive deviations. The curve for Df2 indicates that the output frequency equals the reference frequency on average. Downloaded from Digital Engineering Library @ McGraw-Hill (www. . 103.7. Any use is subject to the Terms of Use as given at the website. The curve for the phase error is quite jittery. but the settling time is seen to be well within that range. however.. f2 can have the values 100. 106.4 ADPLL simulation. its output signal can perform state changes only on the edges of the ID clock signal. A linear system would settle to within 5 percent of its ﬁnal state in about three time constants. 7. Response to frequency step df = 6 kHz. It is easily shown that f2 can take values of Ê 2 N . Because the phase-error curve is relatively smooth at about 45°.e. .Computer-Aided Design and Simulation of ADPLLs Computer-Aided Design and Simulation of ADPLLs 251 Figure. 2 N . thinner line = frequency deviation. kHz. Thicker line = phase error.digitalengineeringlibrary.

7. If the frequency step is made larger (13 kHz). Let us look now at how the ADPLL reacts to phase steps. the system can no longer maintain lock. In the CONFIG dialog box we check the JK-FF radiobutton.digitalengineeringlibrary. All rights reserved. the phase detector gain changes polarity.5 ADPLL simulation.e. Enter a Center frequency of f0 = 100 kHz Figure. Any use is subject to the Terms of Use as given at the website. and from the relatively quiet phase-error curve we see that the system is still locked. The loop pulls the output frequency to about 114 kHz after some reference cycles. but the loop settles to zero phase error very quickly.6.. After the phase step occurs. Fig. This experiment shows that the realizable hold range is only slightly less than the predicted one. 12 kHz. but because the phase error exceeds 180°. which causes the PLL to unlock. Now we start another simulation and hit the CONFIG speedbutton ﬁrst. 7. Hit the RUN button. 7. Downloaded from Digital Engineering Library @ McGraw-Hill (www. Fig. This simulation is shown in Fig. slightly less than 90° on average.5. The instantaneous output frequency now oscillates between 110 and 114 kHz approximately. say. The phase error is near its limit of stability.Computer-Aided Design and Simulation of ADPLLs 252 Chapter Seven Let us increase now the frequency step to.com) Copyright © 2004 The McGraw-Hill Companies. the output frequency is temporarily increased during a few reference cycles.7. . Check the phi-Step radiobutton in the SIM dialog and enter dphi = 90°. i. Response to frequency step df = 12 kHz. 7. Case study 2: Dynamic performance of the ADPLL using the JK-ﬂipﬂop PD.

Any use is subject to the Terms of Use as given at the website.com) Copyright © 2004 The McGraw-Hill Companies. . 7. 7. Fig.7 ADPLL simulation. Response to frequency step df = 13 kHz. Downloaded from Digital Engineering Library @ McGraw-Hill (www. All rights reserved.digitalengineeringlibrary.6 ADPLL simulation.Computer-Aided Design and Simulation of ADPLLs Figure. Response to phase step DF = 90°.

enter f0 = 2400 Hz.000 (kHz) and click the RUN button. If the frequency step is increased to 12 kHz.8 ADPLL simulation. and hit the Calc frequency params button.5. the time constant of the loop becomes t = 40 ms. According to ADPLL theory. Response to frequency step df = 11 kHz. In the PD type panel. 6. It is not easy to read out the settling time accurately. Let us investigate now the behavior of the FSK decoder we designed in Sec. that is. The loop locks. Any use is subject to the Terms of Use as given at the website. Hit the Done button to exit the DESIGN dialog and click the SIM speed button.5 kHz.digitalengineeringlibrary. 7. All rights reserved. the loop is no longer able to maintain lock. which is roughly 3t. The results of the simulation are shown in Fig. and N = 8. but the phase error nearly approaches the stability limit of 180°. check the JK-ﬂipﬂop radiobutton. In the SIM dialog. enter a frequency step df = 11.com) Copyright © 2004 The McGraw-Hill Companies.8. Hit the Done button to ﬁnish the CONFIG dialog and click the DESIGN speedbutton. .Computer-Aided Design and Simulation of ADPLLs 254 Chapter Seven again. In the Center frequency panel. Phase detector = JK-ﬂipﬂop. Downloaded from Digital Engineering Library @ McGraw-Hill (www. but we recognize that the loop acquires lock after about 120 ms. The program predicts a hold range of fH = 12. K = 8. Start the simulation by clicking the CONFIG speed button. Hit the DESIGN speed button to start the Case study 3: Figure. M = 16. In the ADPLL params panel. Hit the Done button to close the CONFIG dialog. enter the parameters for minimum ripple. Dynamic performance of the FSK decoder. 7.

Response of the FSK decoder onto a frequency step df = DESIGN dialog. As Eq. Downloaded from Digital Engineering Library @ McGraw-Hill (www. however. The results are shown in Fig. (6. In the SIM dialog. which is not acceptable in this application. enter the parameters M = 16.digitalengineeringlibrary. M would have to be doubled. the frequency ripple could be reduced by increasing N.Computer-Aided Design and Simulation of ADPLLs Computer-Aided Design and Simulation of ADPLLs 255 Figure. for example. would reduce the hold range. 7. The reader is encouraged to make his or her own trials on improving the frequency ripple of this ADPLL ability to maintain lock. All rights reserved. 7. Click the Calc frequency params button.com) Copyright © 2004 The McGraw-Hill Companies. by a factor of 2. too.9. check the f-Step radiobutton and specify a frequency step df = 300 Hz.15) indicates. The program calculates the expected hold range fH = 600 Hz. Any use is subject to the Terms of Use as given at the website. Enter simulation mode by hitting the SIM speed button. To maintain the hold range of 600 Hz. and N = 4. Doubling N. the ADPLL locks within a few reference cycles. The phase error is around 900. In the DESIGN dialog. Hit the RUN button to start the simulation. There is quite a bit of ripple on the output frequency. which is not critical in this application. Close the DESIGN dialog by clicking the Done button. . K = 8.9 300 Hz. Clearly.

All rights reserved.Computer-Aided Design and Simulation of ADPLLs Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies. . Any use is subject to the Terms of Use as given at the website.digitalengineeringlibrary.

especially when computing power is already available. The designer realizing a software PLL (SPLL) trades electronic components for microseconds of computation time.digitalengineeringlibrary. All rights reserved. the algorithm of the SPLL must be executed two or even four times in each cycle of the reference signal. When that is done. Nevertheless. the algorithm must execute 200. 257 Downloaded from Digital Engineering Library @ McGraw-Hill (www.1 The Hardware-Software Tradeoff In the age of microcontrollers and digital signal processors (DSPs) it is an obvious idea to implement a PLL system by software.g. the number of computer instructions rises with the complexity of the required PLL algorithms. As the parts count for a hardware PLL increases with the level of sophistication. for example) and the designer is forced to resort to more powerful hardware (e. which can be equal to its reference frequency f1 or twice that value.000 times per second in the most favorable case. . If the reference frequency is a modest 100 kHz. it must replace these continuous operations by a discrete-time process. which leaves not more than 5 ms for one pass-through. for example. When a computer algorithm has to take over that job. we should recognize ﬁrst that an LPLL or a DPLL actually is an analog computer that continuously performs some arithmetic operations. According to the sampling theorem. a price tradeoff also comes into play. SPLLs can offer particular advantages.Source: Phase-Locked Loops Chapter 8 The Software PLL (SPLL) 8.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. When comparing SPLLs with hardware PLLs. If a given algorithm performs too slowly on a relatively cheap microcontroller (one of the popular 8051 family. From our previous discussion of hardware PLLs we know that every signal of such a system contains a fundamental frequency. a DSP).. the functions of the PLL are performed by a computer program. The high speed and low cost of available PLL ICs makes it difﬁcult for the SPLL to compete with its hardware counterpart. Of course the SPLL can compete with a hardware solution only if the required algorithms are executing fast enough on the hardware platform that is used to run the program.

one or more instruction decodings. therefore. Using DSPs instead brings us a big step forward. i.3. To check whether a software implementation can economically be justiﬁed. The programming effort is minimized when a high-level language such as C/C++ or (object) PASCAL is used. Manufacturers of microcontrollers or software houses mostly provide compilers for C/C++ and PASCAL. When the compiled assembly-language program Downloaded from Digital Engineering Library @ McGraw-Hill (www. one instruction needs more— often much more—than one machine cycle to execute. In even more sophisticated DSPs. Examples of structograms are also given in Sec. and the like. and hence can fetch instructions and data within the same machine cycle. Step 1—Deﬁnition of the SPLL algorithm. one or more ﬂoating-point multiplications. at least tentatively. one or more register-to-register operations. for example. If the program is required to ﬁnally run on a microcontroller. so that the DSP chip is able. that the microcontrollers on the lower end of the price scale fail to deliver the required computational throughput.3. to describe conditional or unconditional program branchings.2 Feasibility of an SPLL Design An SPLL design offers the most degrees of freedom available in any one PLL design.digitalengineeringlibrary. 8. 8. because they not only are fast with respect to clock frequency.18 Harvard architecture means that the DSP has physically separated data and program memories. . Examples of such algorithms will be given in Sec. In the next section we discuss the steps required to check the feasibility and economy of an SPLL realization. The term pipeline implies that the arithmetic and logic units of the machine are fully decoupled. There is a risk. a language must be chosen for which a compiler is available. to describe loops that are repeatedly run through. and perhaps even more in one single machine cycle.e.. because it can be tailored to perform similarly to an LPLL or a DPLL or to execute a function that neither of these hardware variants is able to do. some operand fetches (data fetches). For the moment it is sufﬁcient to write down these algorithms in symbolic form. by algebraic and/or logic equations. however. The SPLL design procedure should start with the formal presentation of the algorithm(s) to be performed by the SPLL. we should deﬁne the language that will be used to encode them. of course.The Software PLL (SPLL) 258 Chapter Eight Today’s microcontrollers easily work with clock frequencies up to the gigahertz region. This greatly enhances computational throughput but results in higher cost. For most microcontrollers.com) Copyright © 2004 The McGraw-Hill Companies. but also offer Harvard-Plus and pipeline architecture. Any use is subject to the Terms of Use as given at the website. to perform one instruction fetch. 8. Step 2—Deﬁnition of the language. Having deﬁned the algorithms. the machine can fetch one instruction and several data words at the same time. we recommend going through the steps described in the following. one or more ﬂoating-point additions. Structograms are ideally suited to deﬁne the sequence of the operations. All rights reserved.

. Some manufacturers of DSP chips offer signal-processing libraries written in assembly code. the number of variants becomes virtually unlimited. In cases where efﬁcient compiler programs are not available.com) Copyright © 2004 The McGraw-Hill Companies. DPLL. If the execution time of the full SPLL algorithm is 50 ms.3 SPLL Examples Because every known LPLL. The required algorithms for the SPLL will be described in great detail. If it is necessary to use a DSP . or ADPLL system can be implemented by software. Step 4—Real-time testing. The PLL simulation program on the disk is a good example for SPLLs. it uses many of the algorithms described in the following sections. the time required to execute it can be estimated. All rights reserved. the software designer could even be forced to write the program immediately in assembly code. We should be aware. With parallel-computing DSPs this is not a simple task..18. When the DSP makes use of pipeline techniques. 8.g. To check if the system performs as planned.digitalengineeringlibrary. Any use is subject to the Terms of Use as given at the website. for example. because it demonstrates the ability of software to implement a great number of different linear and digital PLL conﬁgurations. at least 100 ms of computation time is needed in one reference period. e. the designer must calculate the real-time bandwidth of the SPLL system. Whatever language is used. digital ﬁltering and the like. and two passes are required in one cycle of the reference signal.The Software PLL (SPLL) The Software PLL (SPLL) 259 is available. so the reader should be able to adapt the methods to other SPLL realizations. however. Not every compiler is able to generate a time-efﬁcient assembly code. the assembly code must be available to get an estimate of the approximate execution time of the algorithm(s). which can be used to perform most elementary signal-processing tasks. Only such a test can make sure that the real system is not even slower than the designer imagines. an assembler program where a number of different instructions are executed in any one instruction. Step 3—Estimation of real-time bandwidth. however. that the simulation program does not represent a real-time system. Downloaded from Digital Engineering Library @ McGraw-Hill (www. Having estimated the program execution time.. i. Nevertheless. the designer will have to implement a breadboard and test its system in real time. We therefore restrict ourselves to a few examples. since it does not work with real signals or execute the algorithms in real time. the real-time bandwidth is likely to fall well below 10 kHz in this example. Probably the microcontroller or whatever hardware is used will need some more time for timekeeping.e. this point is even more important.19 the compiler must generate parallel assembly code. input/output operations. and the like. It should be noted that different assembler instructions may require different execution times.

. . a sine wave. Consequently. 8. To derive the required SPLL algorithm.1 Block diagram showing the arithmetic operations to be performed by an SPLL whose performance is similar to the LPLL. 2T. The sampled DCO output signal is denoted u2(n). The digital ﬁlter serves as loop ﬁlter. 6. Any use is subject to the Terms of Use as given at the website. . and a DCO. . . The output signal of the DCO. all function blocks of the signal ﬂow diagram are working synchronously with the ADC clock.The Software PLL (SPLL) 260 Chapter Eight 8.e.1 the signals shown by double lines are word signals.digitalengineeringlibrary. All other signals of the SPLL are sampled signals.g. too. . 2T. u1(n) = u1(nT). Downloaded from Digital Engineering Library @ McGraw-Hill (www. (No down-scaler is used in this conﬁguration. however. The input signal u1 is supposed to be an arbitrary analog signal. . Finally. i. nT. As we will see. 8. we plot a signal ﬂow diagram that shows the arithmetic operations within the loop (Fig. and must be calculated at the sampling instants t = 0. Its output signal is denoted ud(n).com) Copyright © 2004 The McGraw-Hill Companies. the Clock fs u1 (n) ud (n) uf (n) u1 ADC MUL Digital Filter u2 (n) j2 (n) DCO Figure 8.1. the DCO is supposed to generate a square wave output signal u2(t).. In Fig. T.) The multiplier is used as phase detector and corresponds exactly with the already known Nyquist rate PD discussed in Sec.1. There are three function blocks in the signal ﬂow diagram: a digital multiplier. 6.e. Thus samples are taken at times t = 0.3.1). . where T is the sampling interval. its output signal is uf(n). T. is a bit signal and is therefore represented by a single line. .2. refer also to Fig. N = 1. . u1(n) is the simpliﬁed notation for the input signal sampled at time t = nT. which is of course known only at the sampling instants.1 An LPLL-like SPLL We are going to develop an SPLL algorithm that performs similarly to a hardware LPLL. All rights reserved. It is periodically sampled with the frequency fs = 1/T by an analog-to-digital converter (ADC).. a digital ﬁlter. i. nT. e.

we would be able to extrapolate the total phase j2(n + 1) at sampling instant t = (n + 1)T from j 2 (n + 1) = j 2 (n) + [w 0 + K 0uf (n)]T (8. We are going now to adapt this computation scheme to the time-discrete case we are dealing with.The Software PLL (SPLL) The Software PLL (SPLL) 261 DCO is not able to compute u2(t) directly. we can also extrapolate the value of u2 (n + 1) at t = (n + 1)T. If we assign the values +1 and -1 to the square wave signal. this signal must be calculated indirectly from the phase j2(t) of the DCO.4a) in that interval. The sampled signals are plotted as dots. refer to Eq. . it follows from the deﬁnition of the square wave function that u2(t) is +1 when the phase j2(t) is either in the interval 0 < j2 < p or in the interval 2p < j2 < 3p. Any use is subject to the Terms of Use as given at the website. 8. j2(2) at t = 1 · T. When we know the digital ﬁlter output signal uf(n) at sampling instant t = nT and assume furthermore that it stays constant during the time interval nT < t < (n + 1)T. If a VCO were used instead of the DCO. u2(t) = -1. The total phase j2(t) of the VCO output signal then would be j 2 (t) = Ú w 2 (t) dt = w 0 t + K 0 Ú uf (t) dt (8. Only the continu- Downloaded from Digital Engineering Library @ McGraw-Hill (www.1)p £ j 2 (n + 1) < 2 kp with k = integer.digitalengineeringlibrary. its instantaneous output angular frequency would be given by w 2 (t) = w 0 + K 0uf (t) The continuous output signal u2(t) then would be given by u2 (t) = rect(w 2 (t) ◊ t) (8.10b). the total phase of the DCO output signal will change by an amount Dj 2 = [w 0 + K 0uf (n)]T (8. u2 (n + 1) = 1 or u2 (n + 1) = -1 if if 2 kp £ j 2 (n + 1) < (2 k + 1)p (2 k .2) (8. The dashed lines represent continuous signals. etc.2. All rights reserved. (8. If the phase j2(n) at sampling instant t = nT were known. The signals of our SPLL are depicted in Fig. In all other cases.1) where rect denotes the square wave function. Given j2 (n + 1). rather.3) Note that we dealt only with the differential phase q2(t) hitherto.4b) This computation is possible because we can initialize the total phase with j2(0) = 0 before the SPLL algorithm is started.3).com) Copyright © 2004 The McGraw-Hill Companies. (2. Here the total phase j2(t) is used to compute the instantaneous value of the DCO output signal u2(t). etc. which corresponds to the second term on the right side of Eq. Hence we can extrapolate j2(1) at time t = 0 · T.

At a given sampling instant t = nT. The required algorithm is easily derived from these waveforms. Downloaded from Digital Engineering Library @ McGraw-Hill (www. all others are only ﬁctive.2 n t Plot of the signals that have to be calculated by the SPLL algorithm.com) Copyright © 2004 The McGraw-Hill Companies.The Software PLL (SPLL) 262 Chapter Eight ous signal u1(t) really exists.digitalengineeringlibrary. . the output signal ud(n) of the multiplier has to be computed by ud (n) = K du1 (n)u2 (n) u1 (n) n–1 T j2 (n) p 0 -p u2 (n) n n+1 t t n–1 ud (n) n t n–1 n t uf (n) n–1 Figure 8. All rights reserved. Any use is subject to the Terms of Use as given at the website.

ud (n – 1) Estimate phase j2 (n+1) and u2(n+1) from j2 (n). because we need u2(n) in the following sampling instant to compute the next value of ud(n).3 Structogram deﬁning the operations of the SPLL according to Fig. All rights reserved. ud (n – 1). This value must be known. When the algorithm is started.The Software PLL (SPLL) The Software PLL (SPLL) 263 where Kd is the gain of the phase detector. This enables us to extrapolate u2(n + 1) also. a new sample of uf (n) must be computed. j2 (n). uf (n – 1) REPEAT Timer interrupt? n y Sample input u1(n) Calculate ud (n) from u1(n). the corresponding ﬁlter algorithm will be given below.com) Copyright © 2004 The McGraw-Hill Companies. The program enters an endless cycle thereafter. Any use is subject to the Terms of Use as given at the website. u2 (n) Calculate uf (n) from uf (n –1). . the value of j2(n + 1) at the next sampling instant is extrapolated.3.. the algorithm within the box is repeatedly executed until the system is halted Initialize variables u2 (n). Given uf(n). 8. ud(n). i.1. The SPLL algorithm is now represented symbolically in the structogram of Fig.digitalengineeringlibrary. initial values are assigned to all relevant variables. Given ud(n). Downloaded from Digital Engineering Library @ McGraw-Hill (www. uf (n) Shift variables ud (n – 1) =ud (n) uf (n – 1) = uf (n) j2 (n) = j2 (n+1) u2 (n) = u2 (n+1) UNTIL abort Figure 8.e. 8.

It starts with the acquisition of a sample of the input signal u1(t). when all variables of the SPLL have been updated.The Software PLL (SPLL) 264 Chapter Eight or switched off. they must be delayed (or shifted in time). Depending on the particular application.8) where the ﬁlter coefﬁcients are given by Downloaded from Digital Engineering Library @ McGraw-Hill (www. 8. we assume that F(s) is the transfer function of the active PI ﬁlter. 8. As soon as the interrupt is recognized by the hardware. .4. There are a number of transforms12. which means that the “new” value of ud(n) computed in this cycle will be the “old” value ud(n . refer also to Eq.1) in the next cycle.7) where z now is the z operator.28). The next statement is the digital ﬁlter algorithm: uf (n) = . 2T.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website.13. First all relevant variables are initialized with 0.digitalengineeringlibrary. Before the digital ﬁlter is designed. The next three statements of the structogram correspond with the computation scheme already described. respectively.1) (8.5) This is the recursion of a ﬁrst-order digital ﬁlter.1) + b0ud (n) + b1ud (n . an analog ﬁlter is described by its transfer function F (s) = U f (s) U d (s) (8. other values can be appropriate. Thus interrupt requests show up at time instants t = T. . we start with the deﬁnition of the (ﬁctive) analog ﬁlter. the SPLL algorithm is executed. we usually transform F(s) into the z domain: F ( z) = U f ( z) U d ( z) (8. The operation of the multiplier is trivial. nT.14. The same holds true for all other variables. All rights reserved.1) periodically generates interrupts in the microcontroller or whatever hardware is used. (2.2. It will be covered in some more detail in Appendix C. 6.6) where s is the Laplace operator and Uf(s) and Ud(s) are the Laplace transforms of the continuous signals uf(t) and ud(t). The variable ud(n . Finally. we can develop the algorithm in mathematical terms. To get a digital ﬁlter performing nearly the same function. Because we know that the active PI ﬁlter offers best PLL performance. .a1uf (n . Using the bilinear z transform. . Knowing what has to be calculated in every step.19 that can be used to convert F(s) into F(z).1) is overwritten by the value ud(n).1. we get F ( z) = b0 + b1 z -1 1 + a1 z -1 (8. The full procedure is listed in Fig. As pointed out in Sec. . The most often used is called bilinear z transform. It is assumed that the clock signal (refer to Fig.

Any use is subject to the Terms of Use as given at the website.digitalengineeringlibrary. . All rights reserved.4 Structogram showing the algorithm to be performed by the SPLL in each sampling interval.The Software PLL (SPLL) The Software PLL (SPLL) 265 Initialize variables u2 (n) = 0 j2 (n) = 0 ud (n – 1) = 0 uf (n – 1) = 0 REPEAT Timer interrupt? n y Get next sample u1 (n) from ADC ud (n) = K d u1 (n) · u2 (n) uf(n) = – a1·uf (n – 1)+b0·ud(n)+b1·ud(n – 1) j2 (n+1) = j2 (n) + [w0+K 0·uf (n)]T y j2 (n+1) = j2 (n+1) – 2p j2 (n+1) > 0 j2 (n+1) > p n y u2 (n+1) = 1 n u2 (n+1) = –1 ud (n – 1) = ud (n) uf (n – 1) = uf (n) j2 (n) = j2 (n+1) u2 (n) = u2 (n+1) UNTIL abort Figure 8. Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies.

2. a digital ﬁlter. Any use is subject to the Terms of Use as given at the website..8) back into time domain. Transforming Eq. which is once more shown in Fig. (8. From Eq.1) ¨ ud (n) etc. The only signal that physically exists—at least at the beginning—is the input signal u1(t). 5. it is more appropriate to implement an SPLL that performs like a DPLL. 8.. Let us again represent the required functions by a signal ﬂow diagram (Fig.1) + b0ud (n) + b1ud (n . 8.7). All rights reserved.5). the values of j2(n + 1) will become very large and could soon exceed the allowable range of a ﬂoating number in the processor used. and a DCO. are delayed by one sampling interval. the sampling rate fs for this SPLL algorithm must be chosen at least 4 times the reference frequency in order to avoid aliasing of signal spectra. Finally.4. that is.The Software PLL (SPLL) 266 Chapter Eight a1 = -1 T È 1 ˘ b0 = 1+ Í ˚ 2 t 1 Î tan(T 2 t 2 ) ˙ T È 1 ˘ b1 = 1Í ˙ Î ( ) 2t1 tan T 2 t 2 ˚ and T is the sampling interval.1) (8. Though the mathematical and logical operations within such a DPLL seem simpler compared with an LPLL. Before going into details of the last two ﬁgures.a1uf (n . 8. Whenever the computed value of j2(n + 1) exceeds p. it turns out that the algorithm for the corresponding SPLL becomes much more complicated.5 when simulating the PLL on the PC.digitalengineeringlibrary.3. i.4b) the total phase of the DCO output signal at the next sampling instant will be j 2 (n + 1) = j 2 (n) + [w 0 + K 0uf (n)]T When the algorithm is executed over an extended period of time. N = 1. To avoid arithmetic overﬂow. It essentially consists of three functional blocks: a PFD algorithm. 8. (8.com) Copyright © 2004 The McGraw-Hill Companies. As we stated in Sec.9) which is also listed in the structogram of Fig. We develop an algorithm now performing like the DPLL using the phase-frequency detector and a passive lead-lag ﬁlter.) The digital ﬁlter is required to operate like the passive lead-lag ﬁlter in a DPLL. (No down-scaler is used in this conﬁguration.2 A DPLL-like SPLL When the input signal u1 of a PLL is a binary signal. the calculated values of ud(n). a square Downloaded from Digital Engineering Library @ McGraw-Hill (www. j2 is limited to the range -p < j2 < p.6. u2(n + 1) = 1. If j2(n + 1) ≥ 0. 2p is subtracted to conﬁne it to that range. 8. etc. we get the recursion uf (n) = . we consider the signals of this SPLL (Fig. . ud (n . otherwise u2(n + 1) = -1.e. Now the value of u2(n + 1) is easily computed by checking the sign of the range-limited total phase.

1. 2. Should the output frequency of the DCO drift away.3. This drawing is used to deﬁne the variables of the loop ﬁlter. R1 ud (n) C R2 uc (n) uf (n) Figure 8. . the PFD Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.6 Schematic of the passive lag loop ﬁlter.The Software PLL (SPLL) The Software PLL (SPLL) 267 u1 Edge Detector INT_REQ fs PFD algorithm t+1(n) t–1(n) Digital Filter uf (n) u2 j2 DCO Figure 8. the logic state Q of the PFD depends on the positive edges of these two signals (or from the negative edges. When the PLL has settled to a steady state.com) Copyright © 2004 The McGraw-Hill Companies. whichever deﬁnition is made).5 Block diagram showing the arithmetic and logic operations to be performed by an SPLL whose performance is similar to the DPLL. The output Q of the PFD is then in the 0 state most of the time. too. wave whose frequency can vary within the frequency range of the DCO. The (ﬁctive) output signal u2(t) of the PLL would be a square wave. As we know from Sec. All rights reserved. Any use is subject to the Terms of Use as given at the website. the signals u1(t) and u2(t) are nearly in phase.

the sampling frequency would have to be at least 1000 times the reference frequency. which is highly unrealistic.digitalengineeringlibrary. Any use is subject to the Terms of Use as given at the website. refer to the signal Downloaded from Digital Engineering Library @ McGraw-Hill (www. Another scheme must be used.The Software PLL (SPLL) 268 Chapter Eight INT_REQ 1 u1(t) 0 t(n–1) 1 u1(n) 0 2p j2 (t) j2 (n) 0 -p u2(t) tcross(n) t(n) p t(n) t(n+1) T(n) Q(t) +1 0 –1 +1 0 –1 t+1 t–1 Q(n) t+1(n) t–1(n) uc(n) uf (n) Figure 8. that is. The width of the correction pulses is mostly less than 1/1000 of one period of the reference signal. would generate correction pulses.com) Copyright © 2004 The McGraw-Hill Companies. to detect the instants where the state of u1 and u2 is changing. .7 Plot of the signals that have to be calculated by the SPLL algorithm. Because we need to know the times where u1 and u2 are switching from low to high. Q would become +1 or -1 for a very short time. All rights reserved. we use the (positive and negative) edges of u1(t) to generate interrupt requests to the computer. therefore. If we tried to detect the edges of u1(t) and u2(t) by sampling these signals.

Before the SPLL algorithm can be discussed. 0.33 As soon as the interrupt is recognized. .digitalengineeringlibrary.t(n .7. this is indicated by another arrow on Fig.7. All rights reserved. u1(n . 8. the time lapsed since the last interrupt is taken. t(1). 8. Next. T(n) = t(n) . 8. the corresponding duration is stored in the variable t+1(n). and at time t(n). where it ﬁrst waits for the next interrupt.6. The computer is supposed to have a timer/counter chip such as the Intel 825332 or the AMD 9513. 8. Any use is subject to the Terms of Use as given at the website. . For example. When Q(t) is in the -1 state in a fraction of the T(n) interval.com) Copyright © 2004 The McGraw-Hill Companies. Three of them are marked on top of Fig. Q(t) is the (ﬁctive) continuous output signal (or state) of the PFD.t(n .1) has the value 0. or 1. we have to deﬁne a number of signals (refer to Fig.7. The signals appearing in the algorithm are shown in Fig. the program then enters an endless loop. . 8.1). as in the example of Sec. u1(n) = u1(t). because Q(t) was in the 0 state before the interrupt at t = t(n . 8.3. . It can have the values -1. Q(n . the time where the interrupt occurred is stored. This is Downloaded from Digital Engineering Library @ McGraw-Hill (www. for example.5. The enumeration of that large set of variables has been quite cumbersome.7. u1(n) = 0. Of course. i. thus T(n) = t(n) . T(n) is deﬁned to be the time interval between the time of the most recent interrupt t(n) and the time of the preceding interrupt at t = t(n . however. uf(n) is used to denote the sampled output signal of the digital ﬁlter in Fig. When the interrupt has been detected.1. t(n). When Q(t) is in the +1 state in a fraction of the T(n) interval. The uppermost portion of the SPLL algorithm is trivial and lists the initialization of some variables. the corresponding duration is stored in the variable t-1(n).5 and 8. j2(t) is the (ﬁctive) continuous phase of the DCO output signal..8 shows what has to be done on every interrupt request. .7): u1(n) is the sampled version of the continuous reference signal u1(t) immediately after occurrence of the interrupt request. uf(n) is nearly identical with uc(n) but can slightly differ when “current” ﬂows in the (ﬁctive) resistor R2.1) = 1. With reference to Fig. a “time stamp” is taken. . 8. as shown by the arrow in Fig. j2(n) is the sampled version of j2(t). u2(t) is the (ﬁctive) continuous output signal of the DCO.The Software PLL (SPLL) The Software PLL (SPLL) 269 INT_REQ in Figs.e. The instants where interrupts have been detected are called t(0). 8. It will be calculated from the phase j2(t).1). 8. At time t(n .1).7.1) was issued. . the current value of the reference signal u1(t) is sampled. .1). 8. uc(n) is used to denote the signal on the (ﬁctive) capacitor C in the schematic of Fig. The structogram of Fig. the samples are also taken at the instants where an interrupt occurred. Q(n) is a sampled version of Q(t) and is deﬁned to be the state of the PFD just prior to occurrence of the interrupt at time t(n). As in the previous example. but the elaboration of the algorithms will be even more fatiguing. 8. .6.

uc(n–1) calculate uc(n) From uc(n). uf (n–1). Downloaded from Digital Engineering Library @ McGraw-Hill (www. 8. Q (n–1). t+1(n). u1 (n – 1). uc (n – 1). . Any use is subject to the Terms of Use as given at the website. tcross (n) compute intervals where Q(t) was in +1 or –1 state t+1(n) interval Q(t) was +1 t–1(n) interval Q(t) was – 1 From t+1(n). u1(n–1).5.com) Copyright © 2004 The McGraw-Hill Companies.8 Fig.The Software PLL (SPLL) 270 Chapter Eight Initialize variables t (n–1). T(n) Check if j2 (t) crossed 0 or 2p boundary yes: tcross (n) = time of crossing – t(n–1) no: tcross (n) = 0 From previous states Q(n–1). t–1(n). t–1(n) calculate uf (n) Shift variables uf (n – 1) = uf (n) Q (n – 1) = Q (n) j2 (n–1) = j2 (n) u1 (n–1) = u1 (n) uc (n – 1) = uc (n) t (n – 1) = t(n) UNTIL abort Structogram deﬁning the arithmetic and logic operations within the SPLL of Figure 8. uf (n – 1) REPEAT WAIT FOR INT_REQ Measure current interval T(n) = t(n)–t(n–1) Sample input signal u1(n) Calculate phase j2 (n) from j2 (n–1).digitalengineeringlibrary. All rights reserved. j2 (n–1).

9 Detailed structograms of the algorithms to be performed by the SPLL of Fig. The algorithm for the computation of tcross(n) is indicated in the structogram of Fig. But since we did not yet know at time t = t(n . (b) algorithm for the PFD. (The attentive reader will have noted that positive edges also would occur at phase crossing with 4p.digitalengineeringlibrary. and consequently we also knew the instantaneous (angular) frequency w2(n . When no crossing is detected. (c) algorithm for the digital ﬁlter. at t = t(n). (a) algorithm to determine the variable tcross(n) [time when output phase j2(t) crosses boundary of 0 or 2p]. we do not know the value of the phase j2(t) at that time! The reason for this is simple: At time t = t(n . etc.com) Copyright © 2004 The McGraw-Hill Companies. Next we must determine whether or not the (ﬁctive) signal u2(t) showed up a positive edge in the interval T(n)..10) Note that the phase j2(n .7. this is sketched in the waveforms of Fig. 8. . as noted above. We assume that the current time t is t(n) right now.1) of the DCO. because the phase signal is computed recursively and was initialized with j2(0) = 0 at t = 0. 8. the time interval from t(n .1) how long the duration of the following half-cycle of u1(t) would be. we periodically reduce the total phase by 2p whenever it becomes larger than 2p. It starts with the “normalization” of the phase signal j2(t).The Software PLL (SPLL) The Software PLL (SPLL) 271 necessary because we need to know whether we are in the positive or negative half-cycle of the square wave u1(t). .5. we could not extrapolate j2(n) but had to postpone that until t = t(n). 6p. In contrast to the previous SPLL example.1) to the crossing] is stored in the variable tcross(n). Downloaded from Digital Engineering Library @ McGraw-Hill (www. are we able to compute j2(n) from j 2 (n) = f 2 (n . 8. As will be shown later.9a. Any use is subject to the Terms of Use as given at the website.1) could be calculated.7. This is the case when the continuous phase signal j2(t) “crossed” the value 0 or 2p during interval T(n). . .e.1) was known.1) at time t = t(n .1) the value of the digital ﬁlter output signal uf(n . .1) + [w 0 + K 0uf (n . 8. All rights reserved.1)]T (n) (8. which corresponds to the second interrupt request shown in the middle of Fig. the corresponding time [i. y j2 (n) = j2 (n) – 2p j2 (n–1) = j2 (n–1) – 2p j2 (n)>2p n y – j2(n–1)·T(n) j2(n)– j2(n–1) j2 (n) > 0 AND j2 (n–1) < 0 n tcross (n) = tcross (n) =0 (a) Figure 8.) When the phase crosses such a boundary. Only now. tcross(n) is set to 0. This is necessary to avoid arithmetic overﬂow in the computer.

digitalengineeringlibrary.9 (Continued) . Any use is subject to the Terms of Use as given at the website.272 +1 n 0 y y n t+1(n) = 0 t–1(n) = T(n) – tcross(n) Q(n) = –1 t+1(n) = 0 t–1(n) = 0 Q(n) = 0 t–1(n) = T(n) – tcross(n) Q(n) = –1 t+1(n) = 0 y tcross(n) = 0 n t+1(n) = 0 t–1(n) = T(n) Q(n) = –1 tcross(n) = 0 y tcross(n) = 0 n y u1(n–1) = 1 u1(n–1) = 1 n –1 n CASE Q(n–1) OF y tcross(n) = 0 t+1(n) = T(n) Q(n) = 0 t–1(n) = 0 Q(n) = 1 Q(n) = 0 Q(n) = 0 t+1(n) = T(n) t+1(n) = tcross(n) t+1(n) = 0 t–1(n) = 0 t–1(n) = 0 t–1(n) = 0 t+1(n) = tcross(n) t–1(n) = 0 Chapter Eight Q(n) = 1 (b) y t+1(n) > 0 n y t –1(n) > 0 n t (n) uc(n) = uc( n–1 ) + +1 [UB – uc (n – 1)] τ1+τ2 t+1(n) T(n) uf(n) = uc(n) 1– The Software PLL (SPLL) uf(n) = uc(n) + τ1+τ2 τ2 τ1+τ2 · · τ2 [uB – uc (n)] uc(n) = uc( n–1 ) 1– t–1(n) τ1+τ2 t–1(n) T(n) uc(n) = uc( n–1 ) uf(n) = uc(n) (c) Downloaded from Digital Engineering Library @ McGraw-Hill (www. All rights reserved. Figure 8.com) Copyright © 2004 The McGraw-Hill Companies.

however. the “capacitor” C would have to be discharged toward ground during the interval t-1(n). 8. depending on the polarity of the current. the state of Q(n . 8.6. When it turns out that t+1(n) is greater than zero. In the intervals where current ﬂows.6. If no current ﬂowed into or out of the capacitor C (Fig. Because most of the computed samples at t = t(n) will be used as starting values in the next interrupt service. Q(n .digitalengineeringlibrary. All computations of one interrupt service are done now. 8. we deﬁne uf(n) to be the average of uf(t) in the interval t(n 1) £ t < t(n). 8. The behavior of the PFD is therefore case-sensitive. All rights reserved. When t-1(n) is nonzero.The Software PLL (SPLL) The Software PLL (SPLL) 273 We are ready now to compute the state Q(t) of the PFD during the interval T(n). the structogram of Fig. 8.7. they must be shifted in time. uf(n) can be higher or lower than uc(n). The digital ﬁlter algorithm in Fig. If. however. In a classical ﬁlter algorithm. This scheme does not apply. to the current example. To avoid overloading the graph. Finally.com) Copyright © 2004 The McGraw-Hill Companies.6). 8. If Q(n . this means that the supply voltage UB must be applied during interval t+1(n) to the RC ﬁlter of Fig.1).9c explains how the voltage uc(n) on capacitor C must be computed from the previous value uc(n . We note that the only signal that physically exists hitherto is the reference signal u1(t). Hence the output signal must be calculated like the output of an analog ﬁlter.8. it could not have changed its state on the positive edge of u1(t). 8.9b demonstrates that as many as nine different cases are possible. This assumption leads to simpler expressions for uc(n) and uf(n). This state will be used as initial condition Q(n . 8. This algorithm determines the values of t+1(n) and t-1(n) and also computes the state of Q at the end of the T(n) interval. Q(t) goes into the +1 state. This yields the expression listed in Fig. and for the digital ﬁlter are shown separately (Fig. A realistic SPLL system should also have one Downloaded from Digital Engineering Library @ McGraw-Hill (www. This is indicated in the bottom of the structogram of Fig. as sketched in Fig. The input is “ﬂoating” in the remaining time. however. Because uf(t) is nonconstant in the interval T(n). for the PFD.1) was 0 and u1(t) made a positive transition at t = t(n . Q(t) goes back to the 0 state.1). When u2(t) also makes a positive transition thereafter. where the input is applied continuously. Under this condition the current ﬂowing into or out from capacitor C remains constant during the charging or discharging intervals. . When deriving the equations in this algorithm. the sample uf(n) of the output signal is calculated from the number of delayed samples of the output signal and from the number of delayed samples of its input signal. The signal Q(t) depends on a number of other variables.9c. The algorithm used to compute the ﬁlter output uf(n) differs considerably from conventional digital ﬁlter algorithms. the algorithms for tcross(n).1) prior to time t = t(n . 8.1) must be known.9a to c).1) in the next interrupt service. Any use is subject to the Terms of Use as given at the website.1) had already been in the +1 state at t = t(n . however.1). 8. the algorithm in Fig.10 lists the full algorithm in mathematical statements. First of all. it was assumed that the duration of a T(n) cycle (half a cycle of the reference signal) is much smaller than the ﬁlter time constant t1 in Fig. the output signal uf(n) would be identical with capacitor voltage uc(n). because the input signal of this circuit is applied only during a fraction of the sampling interval.

. 8. All rights reserved. w0. K0 . 8.5. 8. ) Initialize variables t(n – 1) = 0 uc(n – 1) = 0 j2(n – 1) = 0 Q(n – 1) = 0 u1(n – 1) = 0 uf(n – 1) = 0 REPEAT WAIT FOR INTERRUPT T(n) = t(n) – t(n –1) Sample input signal u1(n) j2(n) = j2(n – 1)+[ w0+K0·uf(n – 1)] T(n) Algorithm for tcross(n) Algorithm for PFD Algorithm for digital filter (Fig.9c) Shift variables Q(n – 1) = Q(n) j2(n – 1) = j2(n) u1(n – 1) = u1(n) uc(n – 1) = uc(n) uf(n – 1) = uf(n) t(n – 1) = t(n) UNTIL abort Figure 8. . 8. t2.10 Structogram showing the complete algorithm of the SPLL of Fig.The Software PLL (SPLL) 274 Chapter Eight Set all filter parameters (t1.com) Copyright © 2004 The McGraw-Hill Companies.9a) (Fig.digitalengineeringlibrary. . Any use is subject to the Terms of Use as given at the website. UB. Downloaded from Digital Engineering Library @ McGraw-Hill (www.9b) (Fig.

including the operations required to service the interrupt request. the upper frequency limit can be extended if the more powerful DSPs are used as hardware platforms. where N is the scale factor of the external ∏N counter. The situation would become more troublesome if the SPLL were requested to deliver the continuous DCO output signal u2(t).digitalengineeringlibrary. The corresponding time delay could then be loaded into a timer. the corresponding interrupt service routine must execute more than 300. On each clock pulse. 8. most hardware ADPLLs use clock signals whose frequency is a multiple of the center frequency.3) by software.. which causes another interrupt request when timed out. hence their realization by software stays restricted to low-frequency applications. Any use is subject to the Terms of Use as given at the website.e. The K modulus of the K counter cannot be smaller than K = 8.3. To output a real-time signal.The Software PLL (SPLL) The Software PLL (SPLL) 275 or more real output signals. The author has built in such an algorithm in the simulation program distributed with the disk. i.3.com) Copyright © 2004 The McGraw-Hill Companies. and the interrupt service routines would have to perform the operations triggered by the clock in the hardware ADPLL. Downloaded from Digital Engineering Library @ McGraw-Hill (www. as pointed out in Sec. Assume that the 74HC/HCT297 circuit is used for clock signal recovery in a modem operating at a rate of 9600 baud. This circuit would then operate with a center frequency of f0 = 9600 Hz. 8. Of course. a number of arithmetic and/or logic operations are performed. To get minimum ripple. If the ADPLL algorithm must be implemented by software. Moreover. it knows only what happened in the past. M (the multiplier of the K clock) would be chosen M = 4K = 32.3 A Note on ADPLL-like SPLLs There is no question that all hardware ADPLLs can easily be implemented by software. Consequently. for example. When the SPLL is used as an FSK decoder. the SPLL algorithm determines at time t = t(n) when this signal made its last transition. It is a relatively simple task to implement the algorithm of the popular 74HC/HCT297 IC (discussed in Sec.000 times in a second. Every hardware ADPLL operates under the control of one or several clock signals. which is directly computed in every interrupt service. This simple example demonstrates that it can become quite cumbersome if only a simple hardware device has to be replaced by software.34 Unfortunately. It would be quite simple to apply uf(n) to an output port of the microcontroller whenever it has been computed. the demodulated signal is represented by uf(n). The corresponding interrupt routine would ﬁnally set a bit of an output port with the current state of the u2 signal. As we see from the waveforms in Fig. this is out of the reach of simpler microcontrollers such as the popular 8051 family. 6. these clock signals would have to be replaced by interrupt requests. . By the present state of the art. 6.7. and one single pass of the routine should take less than 3 ms. the K counter and the ID counter would both operate at a frequency of Mf0 = 307. the assumption M = 2N is made whenever possible. the SPLL algorithm could extrapolate at time t(n) how much time should elapse until the next transient of u2. All rights reserved. In the corresponding SPLL algorithm.200 Hz.

The Software PLL (SPLL) Downloaded from Digital Engineering Library @ McGraw-Hill (www. All rights reserved.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. .digitalengineeringlibrary.

frequency modulation (FM). an analog multiplier can be used. e. For analog signals. hence we will ﬁrst look at the most important variants. on a microcontroller. and measurements of temperature or humidity) onto a carrier. the classical modulation schemes still are amplitude modulation (AM). AM is the oldest modulation scheme. even in the classical analog domains such as telephone. the PLL and related circuits ﬁnd widespread applications. voice. music.1. analog or digital data can be transmitted over a data link. If the multiplication is done 277 Downloaded from Digital Engineering Library @ McGraw-Hill (www.1 Types of Communications In this chapter we will discuss applications of the PLL in the domain of data communications. however. There are many different kinds of communications. PLLs and related circuits come into play. The multiplication can also be performed by a digital multiplier.com) Copyright © 2004 The McGraw-Hill Companies. in the latter case we speak about bandpass modulation. To modulate an analog signal (e. and phase modulation (PM). when analog signals are modulating a highfrequency carrier.Source: Phase-Locked Loops Chapter 9 The PLL in Communications 9.2 9. there is no need for synchronization. All rights reserved. the PLL was developed to be used in the analog domain: the inventor Henri de Bellescize22 designed a vacuum-tube–based synchronous demodulator for an AM receiver.g.. Analog and digital signals can be transmitted either as baseband signals or by modulation of a carrier. . If analog signals are communicated in the baseband. Historically. Historically. however. and television. this operation can also be executed by software on a suitable platform. Any use is subject to the Terms of Use as given at the website. First of all.g.. hence this is not an issue for the PLL.1 From analog to digital In recent years digital communications have become increasingly important.digitalengineeringlibrary. The ﬁrst important application of the PLL was in the recovery of the color subcarrier in television receivers around 1950. radio. Because synchronization is an extremely important task whenever digital data are transmitted.

2. for example). In the same way. PM is therefore realized by inserting a differentiator between the information signal source and the control input (uf) of the VCO. . The integrated uf signal then represents the information signal.47. Moreover. Frequency modulation (FM) is easily realized by PLLs and related circuits. 2.47 delivers an output signal u1¢ which is in phase with the reconstructed carrier u2 and hence can be used to synchronously demodulate the signal by a four-quadrant multiplier. Any use is subject to the Terms of Use as given at the website.5 kHz.digitalengineeringlibrary. there is a phase difference of 90° between the carrier (u1) and the VCO output signal (u2). The phase of the VCO output is the integral of w2 over time: j 2 (t) = w 0 t + K 0 Ú uf (t) dt which can be written as j 2 (t) = w 0 t + J 2 (t) where j2(t) represents the phase that carries the information. (The relationship between phase and radian frequency was explained in Sec. that an integrator is driven into saturation if an offset voltage exists at its input (which is the normal situation). When a linear PLL locks onto an AM carrier whose frequency is identical with the center frequency of the PLL.com) Copyright © 2004 The McGraw-Hill Companies. a VCO acts as an FM modulator. The bandwidth of the low-pass ﬁlter must be matched to the bandwidth of the information signal.47 would have to be removed from this circuit when it is applied as an AM demodulator. The 90° phase shifter in Figure 2. q2(t) is required to be proportional to the information signal uf itself and not to its integral.The PLL in Communications 278 Chapter Nine digitally.e. too. i. If the information signal has a bandwidth of 4. see Fig. for example (as in AM radio). FM modulators and demodulators are easily converted to PM circuits with only a few additional components. the low-pass ﬁlter should have a cutoff frequency of about 4. A low-pass ﬁlter eliminates the unwanted high-frequency component at about twice the carrier frequency. a circuit that integrates higher frequencies only but has ﬁnite gain at dc. A VCO is a frequency modulator by itself. the modulated carrier signal must be converted into analog form by a DAC. The instantaneous radian frequency w2 is w 2 (t) = w 0 + K 0uf (t) and hence is proportional to the information signal uf.1. As we already know. The transfer function F(s) of an ac integrator can be given by Downloaded from Digital Engineering Library @ McGraw-Hill (www..5 kHz. We should be aware. a PLL used as an FM receiver is converted to a PM decoder by integrating the uf signal. The demodulated signal can be taken from the output of the loop ﬁlter (uf. of course.) In PM. however. Demodulation of AM signals can be carried out by an LPLL circuit similar to that shown in Figure 2. Saturation is avoided when an “ac integrator” is used in place of an ordinary integrator. the Schmitt trigger in Figure 2. 2. an ordinary linear or digital PLL is able to demodulate FM signals without additional circuitry. All rights reserved. Of course.

but would have gain 1 for lower frequencies.10. a dash by a long carrier burst.2. digital communications are of much greater interest today. and we will now consider the techniques of bandpass communication in more detail. as is the case with voice signals. the PLL locks. and the pauses by nothing. where we also considered various coding schemes such as NRZ. In its simplest form. around the year 1900. Downloaded from Digital Engineering Library @ McGraw-Hill (www. biphase.1.) On-off keying is very simple. Whenever the carrier is on. which broadens the spectrum of the signal in an undesired way. the PLL unlocks. All rights reserved. Such receiver circuits are commonly referred to as tone decoders. ASK still ﬁnds applications where low bit rates are sufﬁcient and low bandwidth is not of primary concern. a high-frequency carrier is switched by an NRZ-encoded binary data stream. The PLL is equipped with an in-lock detector (as shown in Figure 2. and delay modulation formats. 9. 2. but will be restricted to some lower band edge (maybe 300 Hz).) It is quite clear that the bandwidth of such data transmissions cannot extend down to dc. see Table 10. which can be realized as a passive or active RC network. The receiver is built from an ordinary linear or digital PLL whose center frequency is tuned to the carrier frequency. Though quite primitive. When the carrier is off. Any use is subject to the Terms of Use as given at the website.2 Digital Communications by Bandpass Modulation Let us start with a review of the most important modulation schemes for digital communications. A number of tone decoder ICs are available. We also became aware of the problem of recovering the clock frequency from the information signal and considered a number of circuits that extract clock information from the data.1 Amplitude shift keying Amplitude shift keying (ASK) was one of the earliest methods of digital modulation used in radio telegraphy.com) Copyright © 2004 The McGraw-Hill Companies.The PLL in Communications The PLL in Communications 279 F (s) = 1 1 + sTi where Ti is the integrator time constant. so we will concentrate on digital applications. and the output of the in-lock detector goes to 0. (Note: Such an “ac integrator” is nothing more than a simple ﬁrst-order low-pass ﬁlter. a technique also called on-off keying. . such as the XR2213 (Exar) or the LM567 (National). but has severe drawbacks. As mentioned. 9. such a circuit would integrate signals whose radian frequency is above 1/Ti. Roughly speaking. RZ. and the output of the inlock detector switches into the 1 state.1. the transmission of Morse symbols effectively used a pseudo-ternary code: a dot was represented by a short carrier burst. In broadband communications.47.digitalengineeringlibrary. a high-frequency carrier is turned on and off by a binary data signal. (In the ﬁrst years of communication technology. In a typical ASK setup. Switching the carrier on and off creates steep transients. for example). Baseband transmission of digital signals has already been discussed in Sec. bandpass modulation is applied almost exclusively.

The length of the phasor represents its amplitude. In classical PSK [also referred to as BPSK (binary PSK) or PSK2] the polarity of a carrier is controlled by a binary data signal.2 Phase shift keying Phase shift keying (PSK) is the most widely used digital modulation today. Such a binary signal is shown in Fig.1 Downloaded from Digital Engineering Library @ McGraw-Hill (www. As we will see in Sec.1c.2. (c) Vector plot of the modulated carrier signal. the angle with the horizontal axis its phase.The PLL in Communications 280 Chapter Nine 9. Old analog telephone cables are known for their poor bandwidth. When the data signal is a logical 1. For BPSK the phase can only take two values. QAM) are more bandwidth efﬁcient and will be discussed later. OQPSK. 0 and p. so if we planned to increase the symbol rate of an existing link by (say) a factor of 10. It turns out that for BPSK the (two-sided) bandwidth W becomes approximately equal to R. The deﬁnition can be inverted if desired. 9. Fig. For a data signal of 0. Therefore we must try to increase the channel capacity logical 1 logical 0 (a) (b) 0 1 (c) Binary phase shift keying (BPSK). Any use is subject to the Terms of Use as given at the website. the carrier phase is 0 by deﬁnition.1b.digitalengineeringlibrary. the carrier phase becomes p (180°). As usual in the theory of alternating currents. 9.1a. 9. amplitude and phase of the modulated carrier can be represented as a vector (phasor) in the complex plane. we cannot hope to reach that goal simply by increasing the carrier frequency by a factor of 10 and modulating it with the faster data signal. Figure 9. . (b) Modulated carrier.4.com) Copyright © 2004 The McGraw-Hill Companies. 9. All rights reserved. (a) Binary signal. Some of its descendants (QPSK. there is a distinct relationship between the symbol rate R (number of binary symbols transmitted in 1 second) and the bandwidth W (in hertz) required to transmit the modulated signal. and the modulated carrier in Fig. Digital data are often carried by phone lines.

9. also called quaternary PSK or PSK4) brings us a step further.) We are now going to switch the polarity of the in-phase carrier by one binary signal.3 Quadrature phase shift keying QPSK (quadrature phase shift keying.The PLL in Communications The PLL in Communications 281 (the throughput of binary symbols) without increasing the channel bandwidth. or 315°. Downloaded from Digital Engineering Library @ McGraw-Hill (www. (c) Data stream corresponding to the odd bits in a. Hence. because a signal never can take on complex values—try to think of a complex temperature or humidity! The term complex makes sense only if we consider the in-phase component as the real part of a complex signal and the quadrature component as the imaginary part thereof. and therefore they do not interfere. This sounds a little bit curious. (The ensemble of both carriers is often called a complex signal. but does not require additional bandwidth. as is easily seen from Fig. (b) Data stream corresponding to the even bits in a.2. 135°. the two data signals s1 and s2 can be decoded by synchronous demodulation at the receiver.2 explains the principle of QPSK.2. This seems contradictory at ﬁrst glance.2a. Figure 9. it is assigned a phase of 0° and is mathematically represented by a cosine wave.digitalengineeringlibrary. (a) Binary signal to be transmitted. Moreover we switch the polarity of the quadrature carrier by another binary signal. but the phase of the quadrature carrier can take on the values p/2 (90°) or 3p/2 (270°). .com) Copyright © 2004 The McGraw-Hill Companies. The binary data stream as delivered by the data source is shown in Fig. 2 bits are transmitted in one symbol period. The latter is mathematically represented by a sine wave. 225°. This sequence is partitioned into (a) b0 (b) b0 (c) b1 b3 b5 b2 b4 b1 b2 b3 b4 b5 Figure 9. Adding the two modulated carriers increases the symbol rate by a factor of 2. The symbol rate of the QPSK signal is now half the symbol rate of the original data stream. If we add the two carriers. s1. s2. 9. We note that with QPSK. but we will see shortly that it is possible. All rights reserved. 9. the phase of the in-phase carrier can take on the values 0 or p (1800). How does it work? In BPSK. The other carrier is called quadrature carrier and is assigned a phase of 90°. One of the carriers is called the in-phase component. In QPSK we generate two carriers that are offset in phase by 90°. Any use is subject to the Terms of Use as given at the website. the phase of the resulting signal can have values 45°. we created just one carrier and switched its polarity by a binary data stream.2 The principle of QPSK. Because the two carriers are orthogonal (perpendicular on each other).

Whenever a data signal changes polarity then. 9. 9.4). 9. etc. so we can normalize these amplitudes to 1. When the data streams are low-pass ﬁltered (as will be explained in Sec.com) Copyright © 2004 The McGraw-Hill Companies. In other words.digitalengineeringlibrary. . etc.2. both in-phase and quadrature data streams change their values at half the original symbol rate.2b). but become smoothed. we are going now to expand this principle to even greater beneﬁt. All rights reserved. This drawback becomes less severe if both of the data streams cannot change state at the same time.) form the binary sequence that modulates the in-phase carrier (Fig.2c) is delayed by one symbol period of the source signal. In OQPSK (offset quadrature phase shift keying) the second data stream (Fig.3 (b) Downloaded from Digital Engineering Library @ McGraw-Hill (www. 9. b2.3c shows the corresponding phasor plot. the modulated carrier temporarily fades away. (b) phasor diagram of modulated carrier. 9. Figure 9. on every second symbol delivered by the data source. hence we temporarily loose the signal that the receiver tries to lock onto.The PLL in Communications 282 Chapter Nine two data streams now: the even bits (b0. the two data streams are aligned.. but rather offers some practical beneﬁts. while the odd bits (b1. but are staggered in time.4 QAM (m-ary phase shift keying) Having increased the channel capacity by a factor of 2 without sacriﬁcing bandwidth. and Fig. i. This does not have any impact on channel capacity or bandwidth. Any use is subject to the Terms of Use as given at the website. the data signals are no longer square waves. b3. This is the motivation to use OQPSK.) modulate the quadrature carrier (Fig. Figure 9. the modulated in-phase carrier could take on b0 b1 b2 b3 45 135 (a) 225 315 phase in deg quadrature in-phase Phase relationship of BPSK signals: (a) the modulated carrier can take on four different phases.e.2. As can be seen from Figure 9. The amplitudes of the two carriers for QPSK have always been the same.3a represents the four possible phases of the sum of in-phase and quadrature signals. say 1 or 2? When we do so. 9. In-phase and quadrature data streams no longer change their states simultaneously.2c). What about using more than one amplitude value.

. and hence 4 bits per symbol are transmitted. This modulation scheme is called QAM (quadrature amplitude modulation). the combined carrier can take on 16 states. With the scheme shown in Fig.20 Today QAM is the most widely used technique.6. All rights reserved. however. but noise superimposed on the transmitted signal sets limits. or a phase of 180° with an amplitude of 1.4 is commonly called QAM16. respectively. QAM128. 9. or a phase of 0° with an amplitude of 2. and the marked dots would sit in the center of each square. 9. In other words. 9. In modern modems. if we compare the channel capacity with ordinary BPSK.The PLL in Communications The PLL in Communications 283 a phase of 0° with an amplitude of 1. 9. this would increase the channel throughput by another factor of 2. 9. The code shown in Fig. Of course we must not restrict the amplitudes to only 2 values—more values can be used. To discriminate between different amplitude levels.4 Phasor diagram of QAM. The actual bit error rate of a particular code can be computed by using statistics and Shannon’s information theory. As long as the end point stays within the corresponding decision region. quadrature in-phase Figure 9. all phasors become equidistant on both axes. A phasor diagram of QAM can look like Fig. QAM64. Actually QAM is a combination of PSK with ASK. Note that QAM4 is identical with QPSK. If the receiver is not only able to determine the phases of the two signal components but is also in a position to discriminate different signal amplitudes. the receiver must deﬁne decision limits. because we alter both phase and amplitude. QAM will be used very efﬁciently in digital video broadcasting (DVB). The end points of the phasors have identical distances on the horizontal and vertical axes. the receiver would split the phasor plane into a number of squares of equal size.4. when the noise causes the phasor to migrate into another decision region. Note that the in-phase component can take on relative amplitudes of 0.5 and not 1 and 2. this modulation scheme would transmit 4 bits in one symbol period.com) Copyright © 2004 The McGraw-Hill Companies.4. Errors occur. With reference to Fig.5 and 1. With this choice of amplitudes. no error would result.digitalengineeringlibrary. Here two amplitude values are used. As we will see in Sec. or a phase of 180° with an amplitude of 2. Any use is subject to the Terms of Use as given at the website. and QAM256 come into play.4. Downloaded from Digital Engineering Library @ McGraw-Hill (www. Noise on the signal would cause the phasor to deviate from its nominal position. Theoretically the set of amplitudes can be made as large as desired. The same would hold true for the quadrature signal.

5a.com) Copyright © 2004 The McGraw-Hill Companies. and f2 represents a binary 1 or vice versa.The PLL in Communications 284 Chapter Nine 9. k1 = 4 and k2 = 6. 9. There are a number of simple modems that use FSK2 or FSK4 and work immediately with baseband signals.5b. Let us discuss baseband communication ﬁrst. Of course.1) where i = 1. Any use is subject to the Terms of Use as given at the website. Fig. f2 = 1850 Hz. We considered only binary FSK hitherto. Such a decision is a maximum likelihood decision in the statistical sense. The other choice is orthogonal FSK. Both frequencies then are integer multiples of half the symbol rate 1/(2TS).digitalengineeringlibrary. Here the frequencies f1 and f2 are chosen as to fulﬁll the relationship fi = ki 1 2Ts (9. With added noise. the correlation with the other 0. 2 and ki is a positive integer greater than 0. four different frequencies f1 to f4 would be used. 2 bits per symbol period can be transmitted. for example. it is not required that the symbol interval TS is an integer multiple of one period of the f1 or of the f2 signal.5 Frequency shift keying FSK (frequency shift keying) is another modulation scheme that is frequently used in modems. 9. we have Ts Ú si (t)s j (t) dt = 1 0 i= j (9. of course) can share one single link. Downloaded from Digital Engineering Library @ McGraw-Hill (www. In the example of Fig. Normally a linear or digital PLL serves as an FSK decoder. 9. Fig. A coherent FSK decoder then would store replicas of the symbol waveforms s1(t) and s2(t) and correlate the incoming symbol with both of these. In its simplest form (FSK2). hence the receiver would decide for 0 if the correlation with s1(t) becomes greater than the correlation with s2(t) or for 1 if the reverse is true.2) iπ j =0 which means that the signals s1(t) and s2(t) are orthogonal. An FSK signal can be transmitted in the baseband. the receiver would decide for logical 1. All rights reserved. the baseband signal can be modulated onto a high-frequency carrier. If we denote the signal waveforms for logical 0 and logical 1 by s1(t) and s2(t). f1 = 1650 Hz. For example.5b. The difference between the two frequencies must simply be chosen such that the PLL can safely determine whether it “sees” frequency f1 or f2. two different frequencies f1 and f2 are deﬁned. if m = 4. In doing so. When this is done. respectively. the correlation coefﬁcients depart from their ideal values 0 or 1. This property can be beneﬁcial when the received symbols are buried in noise. The two frequencies can be chosen arbitrarily.2. many FSK-modulated carriers (with different carrier frequencies. Whenever the correlation with s1(t) leads to the result 0. but FSK can be extended to m-ary FSK when more than two frequencies are chosen. the correlation with one of the replicas would yield 1. where f1 represents a binary 0. Without noise. or it can be used to modulate a carrier. This type of FSK is called nonorthogonal FSK. . Moreover.

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f1

f2

TS

(a)

f1

f2

TS

(b)

Deﬁnition of binary FSK: (a) Nonorthogonal FSK: arbitrary values for f1 and f2 are chosen. (b) Orthogonal FSK: there is a tight relationship between frequencies f1 and f2; see text.

Figure 9.5

In the case of nonorthogonal FSK, switching abruptly from one frequency to another can cause sharp transients, which extends the bandwidth of the signal in an undesired manner. This drawback is avoided in a special version of FSK called MSK (minimum shift keying).20,49 With MSK, every symbol waveform starts and ends with a zero crossing of the same direction, e.g., from negative to positive values (as can be seen from Fig. 9.5b). Adjacent symbol waveforms then never execute phase steps. This reduces the bandwidth required to transmit the FSK signal. 9.3 The Role of Synchronization in Digital Communications Before discussing the various modulation techniques applied in digital communications, some notes on the synchronization problem appear appropriate.

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Whenever digital data are transmitted by bandpass modulation, synchronization on different signal levels will be required. Assume for the moment that binary phase shift keying (BPSK) is used to modulate the phase of a highfrequency carrier. At the receiver, the data signal has to be recovered by demodulation. In most cases, the demodulation is performed synchronously; i.e., the receiver generates a replica of the carrier and multiplies the incoming signal with that reconstructed carrier. This shifts the spectrum of the received signal by a frequency offset that is equal to the carrier frequency, and the data signal is obtained by simple low-pass ﬁltering. Because the replica of the carrier must be in phase with the latter, phase synchronization is required. This can be considered the ﬁrst level of synchronization and is usually realized by PLL circuits. For reasons to be explained in the next sections, locking onto a modulated carrier is not always trivial, so extended versions of PLLs are required in many cases (e.g., the Costas loop). After demodulation, the data stream in the receiver is almost always a ﬁltered version of the original data signal. While the original data signal represented a square wave signal, the transients of the ﬁltered data signal become smoothed. In many situations, the receiver performs a correlation of the received data with template functions that are stored in the receiver. This is done to reduce the effects of noise that has been added to the signal on the transmission link. This correlation is usually performed during a time interval that must be identical with the symbol duration; hence the receiver must know when an incoming symbol starts and when it is over. A second level of synchronization must be performed then, referred to as symbol synchronization. The circuits that perform symbol synchronization are still other special versions of PLLs; we will discuss some of them in following sections, including the early-late gate synchronizer. In some communication systems, an even higher level of synchronization is required. This is usually called frame synchronization. This kind of synchronization comes into play when the information is organized in blocks. Such a block may consist of a block header, followed by the actual data and eventually by a trailer that contains check code [e.g., a cyclic redundancy check (CRC)]. Information is organized in blocks when the communication channel is timeshared by a number of transmitters. In this case the receiver must be able to decide when a block starts. Frame synchronization will not be discussed here.20

**9.4 Digital Communications Using BPSK
**

9.4.1 Transmitter considerations Filtering the data: yes or no?

Communicating binary signals by binary phase shift keying looks quite trivial, but imposes serious problems if we consider bandwidth requirements. As shown by Fig. 9.1, the polarity of a high-frequency carrier is switched by the binary information sequence. If the data are not ﬁltered, the carrier is modulated by a square wave. It is not strictly a square wave,

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but rather a binary random sequence that can change its amplitude at the start of each symbol period. What the data signal has in common with a square wave is its very steep transients. Normally the NRZ format is used to modulate the carrier (see Fig. 2.50). If we transmitted an inﬁnite sequence of binary 0s or 1s, the binary random sequence would degenerate to a dc level; hence the bandwidth of the data signal would be zero. Because we actually send an arbitrary sequence of 0s and 1s, the spectrum of the data signal will contain some higher frequencies. It is easy to recognize that the frequency of the data sequence becomes maximum when we transmit a sequence of alternating 1s and 0s. In this case the data signal would be a square wave signal whose frequency is half the symbol rate. As Nyquist realized in 1928,40 a receiver will be able to detect the data signal if only the fundamental component of this square wave signal is transmitted. Consequently we would low-pass-ﬁlter the data signal at the transmitter. The most appropriate ﬁlter would be a “brickwall ﬁlter,” i.e., an ideal low-pass ﬁlter having gain 1 at frequencies below half the symbol rate and gain 0 elsewhere (Fig. 9.6, see curve label r = 0). The impulse response of the brickwall ﬁlter is h(t) = sin(pt T ) pt T (9.3)

which is referred to as a sinc function. T is the symbol period. The duration of the impulse response is inﬁnite, and it starts at t = -•; the ﬁlter delay is also inﬁnite. The impulse response is plotted in Fig. 9.7 by the curve labeled r = 0 (the meaning of r will be explained in the following). Of course such a ﬁlter cannot be realized. An approximation to the brickwall ﬁlter can be implemented by a ﬁnite impulse response (FIR) digital ﬁlter (see App. C) to any desired level of accuracy. However, because the impulse response decays slowly to 0, this leads to excessively long FIR ﬁlters, i.e., to ﬁlters with a large number of taps. Nevertheless we will consider the impulse response in more detail because it exhibits a very useful property. Every FIR ﬁlter causes the signal that is passed to be delayed, where the delay t is given by t= L -1 TF 2 (9.4)

L is the length of the FIR ﬁlter and TF is the sampling interval of the ﬁlter. In Fig. 9.7 the delay of the ﬁlter has been neglected; hence its maximum (+1) occurs at time t = 0. Normally such a ﬁlter would be sampled at a frequency fF that is an integer multiple of the symbol rate R = 1/T, where T is the symbol period. If we used an FIR ﬁlter of length 33, for example, it would have a delay of 16 TF; if we assume furthermore that the ﬁlter sampling frequency fF is 4 times the symbol rate R, the ﬁlter would delay the signal by 4 symbol periods. For this FIR ﬁlter, the impulse response h(t) would no longer be symmetrical about t = 0, but rather about t = 4T. For simplicity the delay has been omitted in Fig.

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1 0.9 0.8 0.7 Magnitude 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.1

RC Frequency Response H(f)

r = 0.5 r=0

r=1

0.6 0.7 0.8 0.2 0.3 0.4 0.5 Frequency normalized to symbol rate

0.9

1

Figure 9.6

(r > 0).

Amplitude response of brickwall ﬁlter (r = 0) and raised cosine ﬁlter

1 0.8 0.6 0.4 h 0.2 0 – 0.2 – 0.4 –4

Impulse response h(t) of raised cosine filter

r=1 r = 0.5 r=0

–3

–2 –1 1 2 3 0 Time t normalized to symbol duration T

4

Figure 9.7

Impulse response of the raised cosine ﬁlter for various values of (relative) excess bandwidth r.

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9.7; i.e., we assume that the ﬁlter is a so-called zero phase ﬁlter, which causes no delay. Note that the impulse response of the brickwall ﬁlter becomes 0 at t = T, 2T, 3T, etc. Now we remember that the impulse response is nothing more than the response of the ﬁlter to a delta function with amplitude 1, applied at t = 0 to its imput. Sending a logical 1 therefore corresponds to applying a positive delta function, and sending a logical 0 corresponds to applying a negative delta function (amplitude -1). Next we consider the case where a number of symbols are passed through the ﬁlter in succession. If two succeding 1s are supplied, the ﬁrst logical 1 will be represented by a delta function with amplitude +1 applied at t = 0, and the second logical 1 by another delta function with amplitude +1 applied at t = T. This situation has been plotted in Fig. 9.8. The upper trace shows the two delta functions (marked by arrows), the lower trace the corresponding impulse responses (solid curves). The zeros of the impulse responses are marked by circles. The superposition of the two impulse responses is shown by the dotted curve (thick). In order to recover the data, the receiver would have to sample the ﬁltered signal exactly at time t = 0, T, 2T, etc. As can be seen from Fig. 9.8, the amplitude of the combined signal at t = 0 (marked by a square) depends uniquely on the impulse applied at t = 0; the impulse response caused by the

Transmitted bit pattern

1 0.8 0.6 0.4 0.2 0 –5 1.5 1 –4

Two logical ones applied to RC filter

–3 –2 –1 0 1 2 3 4 Time t mormalized to symbol period T Filtered bit pattern; dotted curve = superimposed

5

h

0.5 0 – 0.5 –5 –4 –3 –2 –1 0 1 2 3 Time t normalized to symbol rate T 4 5

Response of the raised cosine ﬁlter to a sequence of two binary 1s applied to its input. Upper trace: a sequence of two delta functions corresponding to two binary 1s transmitted in succession. Lower trace: the solid curve (thin) whose maximum is at t/T = -1 is the response of the ﬁlter to the delta function applied at t/T = -1, the solid curve whose maximum is at t/T = 0 is the response to the delta function applied at t/T = 0, and the thick (dotted) curve is the superposition of these two responses.

Figure 9.8

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second delta function is zero at this time. The same holds for the combined signal at t = T. Its amplitude at t = T (marked by a square) uniquely depends on the amplitude of the second delta function and does not contain any contribution from the ﬁrst delta function. In other words, the impulse responses caused by various delta functions do not interfere; when the brickwall ﬁlter is used, there will be no intersymbol interference (ISI). To recover the data signal without error, the applied ﬁlter must be chosen such that no ISI can occur. [It is easy to demonstrate how ISI can be created: assume that we ﬁlter the data signal by a Butterworth low-pass ﬁlter. Its impulse response will be a damped oscillation. It also passes through zero, but these zeros are not at t = 0, T, 2T, etc.; hence the impulse responses coming from delta functions applied to the input will interfere, or in other words, an output sample taken at t = kT (k = positive integer) is the sum of the contributions of many symbols. This cannot be tolerated, of course.]

How to get rid of ISI?

As we have seen, a useful approximation to a brickwall ﬁlter would lead to excessive ﬁlter length. Nyquist has shown a valuable alternative: if the transition region of the ﬁlter is widened, its impulse response decays faster toward zero. Moreover, if the amplitude response H( f ) of the ﬁlter is symmetrical about half the symbol rate (R/2), the locations of the zeros of its impulse response remain unchanged. Filters having this property are commonly referred to as Nyquist ﬁlters. One possible realization of the Nyquist ﬁlter is the raised cosine ﬁlter (RCF). Its transition region (the region between passband and stopband) is shaped by a “raised” cosine function, i.e., by a cosine wave that stands on a “pedestal.” The width of the transition band is determined by the parameter r, which is called excess bandwidth. If the frequency corresponding to half the symbol rate is denoted W0(W0 = 1/2T), the transition band starts at f = (1 - r)W0 and ends at (1 + r)W0. The amplitude response H(s) of the RCF has been plotted in Fig. 9.6 for three values of r: 0, 0.5, and 1. (The case r = 0 applies for the brickwall ﬁlter.) Note that the frequency response is symmetrical about half the symbol rate. Mathematically the frequency response of the RCF is given by Ï1 Ô Ô p 2T f + r - 1 Ô H ( f ) = Ìcos 2 4 r Ô Ô 0 Ô Ó for for for f < 1-r (9.5)

2T 1-r 1+r £ f £ 2T 2T 1+r f > 2T

Figure 9.7 shows the impulse response of the RCF for r = 0, 0.5, and 1. The larger r is chosen, the faster the decay becomes. To economize bandwidth, however, large values of r must be avoided. In practice, values of r in the range 0.15 to 0.35 are customary. For completeness we also give the expression for the impulse response h(t) of the RCF41:

the receiver must know the phase of the carrier exactly. Instead. if we did. and ISI would occur. this is more difﬁcult than it appears at a ﬁrst glance.25 It contains a function called FIRRCOS that calculates the coefﬁcients of the RCF. Because of its higher noise immunity. explicitly for t/T = 1/2r. it takes the phase of the currently detected symbol as a reference for the detection of the next symbol. the receiver must know at the start of a transmission whether the currently received symbol is a 0 or a 1. For the same value of t.. 20. the cosine term also becomes 0. Any use is subject to the Terms of Use as given at the website. 9. for different reasons. When coherent detection has to be applied. the receiver must reconstruct a replica of the carrier. the symbol stream must be demodulated by a convenient procedure.2 Receiver considerations A number of tasks have to be performed in the receiver to reconstruct the symbol stream. As we will see in the following. We will see in the next section that so-called root raised cosine ﬁlter (RRCF) will ﬁx that problem. since there exist values of t where both numerator and denominator become 0. So far the raised cosine ﬁlter seems to offer the optimum solution for lowpass ﬁltering because it completely suppresses ISI. Otherwise it decides that the symbol changed its value from 0 to 1 or from 1 to 0. mathematically this is called L’Hôpital’s rule. If noncoherent detection is to be realized. The most important of these will be discussed here. This singularity is removed by replacing both numerator and denominator by their derivatives. the receiver knows that the next symbol is the same as the previous. All rights reserved. Care must be taken. coherent detec- Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies. the receiver must not know the phase of the carrier. Because the data modulate the carrier. As we will see in Sec. 9. the data signal would have to pass through two cascaded RCFs: one in the transmitter and one in the receiver.. If the phase does not change.4. the receiver also needs a low-pass ﬁlter.The PLL in Communications The PLL in Communications 291 h(t) = sin(pt T ) ◊ cos(prt T ) È 2 rt ˆ ˘ (pt T )Í1 . The computation is made even easier if Matlab’s Signal Processing Toolbox is available. Coherent demodulation is more efﬁcient.2. i. Noncoherent detection has been extensively analyzed in Ref. This happens if the expression in the square brackets of the denominator becomes 0. i.e. however. The overall frequency response then would be the RCF transfer function squared! The resulting frequency response would no longer be symmetrical about half the symbol rate.Ê Ë T ¯ ˙ Î ˚ 2 (9. For correct operation some initial synchronization becomes necessary.6) Designing of an FIR raised cosine ﬁlter is an easy task: Eq.6) can be used to compute the ﬁlter coefﬁcients.e.digitalengineeringlibrary. Basically we can differentiate between coherent (synchronous) and noncoherent demodulation. (9. It turns out that we cannot use another raised cosine ﬁlter at the receiver.4. especially if noise has been added to the signal when it propagates across the data link. .

20 Phase synchronization within the receiver. Consequently the spectrum of the data signal has almost no power at f = 0. When it is not. and the reconstructed Downloaded from Digital Engineering Library @ McGraw-Hill (www. that is.20 It originally was realized as an analog circuit. An example is the digital Costas loop HSP50210 manufactured by Harris. Normally the data signal is an arbitrary sequence of logical 1s and 0s. . A replica of the carrier is obtained by scaling down that signal by a factor of 2. where a 1 is represented by a positive voltage (+1) and a 0 by a negative voltage (-1).com) Copyright © 2004 The McGraw-Hill Companies. and its spectrum consists of just one line at fs. Fig. a term having twice the frequency of the carrier. The radian frequency of the carrier is w1 here.1. Because squaring devices were hard to implement by analog circuitry. the carrier is modulated by a (ﬁltered or unﬁltered) symbol sequence. In the simplest case m(t) is a binary random sequence taking on the values +1 and -1. data signal and carrier are multiplied. One of the earliest circuits is the squaring loop. this consists of a dc term (which can be discarded here) and a high-frequency term of the form cos(2w1t). A conventional PLL is used then to lock onto that frequency. This simply means that we cannot use a simple PLL to reconstruct a replica of the carrier! Quite an arsenal of solutions has been invented to overcome that problem. All rights reserved.The PLL in Communications 292 Chapter Nine tion is the preferred method in most receiver circuits today. the spectrum can be much broader. 9.10. The modulated carrier signal s(t) is therefore represented by s(t) = m(t) sin(w 1t) The output of the (analog) squaring device is then s2 (t) = m2 (t) sin 2 (w 1t) According to the multiplication theorems of trigonometry. but is implemented mostly by digital techniques today. when it is ﬁltered. the power is concentrated at other frequencies. The carrier has the frequency fs. Any use is subject to the Terms of Use as given at the website. hence this signal will have no dc component or only a very small one. there will be approximately the same number of 1s and 0s. The explanation becomes easier if we assume that the circuit has locked.42 so we will concentrate on this technique. A very successful solution is the Costas loop. On a long run.1. ranging approximately from 0 to half the symbol rate. This implies that the modulated carrier does not contain appreciable power at the carrier frequency. but the symbol sequence has a broader spectrum. Assume for the moment that the data signal consists of only one frequency fd. The Costas loop. and the carrier is multiplied by the symbol signal m(t). In BPSK. The input signal can be represented by m(t) sin(w1t + q1).42 The basic Costas loop is shown in Fig. hence their spectrum will contain lines at the sum frequency fs + fd and at the difference frequency fs .fd.9. alternatives have been searched for. With BPSK. The squaring loop. 9.digitalengineeringlibrary.

we are looking for a circuit that does not change polarity when m(t) is inverted.9 Squaring loop. Let us see how the Costas loop manages to lock onto the carrier frequency. which means that the multiplier no longer sees a phase error qe = q1 . This PLL circuit would adjust the frequency of the VCO in such a way that it is phase-locked to the carrier. the I branch is added. This arrangement would work as long as the modulating signal m(t) does not change polarity. connect the output of the loop ﬁlter in the lower branch directly to the input of the center low-pass ﬁlter.The PLL in Communications The PLL in Communications 293 m(t)sinw1t Square Mul Loop filter m2(t)cos(2w1t) uVCO VCO :2 Carrier out Figure 9. the phases q1 and q2 will be nearly the same. however.e. The output of the VCO would have nearly the same phase as the input signal (q1 Ϸ q2). The multiplier at left in the Q branch acts as a phase detector. All rights reserved. When m(t) changes polarity. . In the locked state. together with the additional multiplier at center right. As indicated in Fig. Rather. one in the upper branch (I branch) and one in the lower branch (Q branch). but rather a phase error of qe = q1 . Assume for the moment that only the lower loop does exist. and discard the multiplier at center right. This forms a rather conventional PLL.q2 + p. To overcome the problem.. Any use is subject to the Terms of Use as given at the website. carrier (the output signal of the VCO) by sin(w1t + q2). the output of the multiplier is inverted as well. and the two input signals of the lower multiplier would be out of phase by 90°.10.com) Copyright © 2004 The McGraw-Hill Companies.q2. the output signal of the loop ﬁlter in the I branch is given by m(t) Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary. i. Two closed loops are recognized. 9. Consequently the loop would lock in antiphase with the carrier now. which is not the desired action. as usual with linear PLLs.

Because the polarity of the output signal changes with m(t). Multiplying both loop ﬁlter output signals (I and Q branches) creates a signal of the form m2 (t) sin 2(q1 . When lock is achieved. the receiver must sample the demodulated signal at the right time. But what is the “right Downloaded from Digital Engineering Library @ McGraw-Hill (www. and the reconstructed carrier fed to the Q branch is the quadrature component.q2 ) 2 hence a signal that is proportional to the phase error qe when the loop is locked.10 Costas Loop for BPSK. . If phase is nearly correct for tracking (q1 . All rights reserved.The PLL in Communications 294 Chapter Nine I branch MUL 2sin(w1t + q2) Input VCO m(t) sin(w1t + q1) LP Loop Filter Data output m(t) cos(q1 – q2) MUL 90° 2cos(w1t + q2) MUL m2(t) sin 2(q1 – q2) 2 Loop Filter m(t) sin(q1 – q2) Q branch Figure 9.com) Copyright © 2004 The McGraw-Hill Companies.digitalengineeringlibrary. so the multiplier in the I branch synchronously demodulates the data signal.q2 is small). the cosine term in the I branch is nearly 1. The transients of the data signal are now ﬂattened by the loop ﬁlter within the receiver.q2).10. Any use is subject to the Terms of Use as given at the website. Symbol detection by correlation ﬁlters: the matched ﬁlter. so it originally has a square wave shape. Assume for the moment that the data signal has not been low-pass-ﬁltered at the transmitter. The names of the branches are self-explanatory: the reconstructed carrier fed to the I branch is the in-phase component. thus the output of the upper loop ﬁlter is the demodulated signal m(t). the received data signal passes through the loop ﬁlter in the I branch of the Costas loop. 9. it is used to cancel the change in polarity at the output of the lower loop ﬁlter. cos(q1 . the output of the VCO is in phase with the carrier. To decide whether an incoming symbol is a logical 1 or 0. As we recognize from Fig.

com) Copyright © 2004 The McGraw-Hill Companies.g. but in reversed order. since the ﬁltered symbol must ﬁrst be allowed to settle to its ﬁnal amplitude (for example. It has been shown that the best estimate—in the statistical sense—is obtained from a correlation ﬁlter. the correlation can be performed with the undemodulated or demodulated symbol waveform. hence we start with this topic. The symbol waveform is sampled at the input of the correlation receiver. When the samples are shifted into the FIR ﬁlter. +1 for logical 1 or -1 for logical 0). the result would probably have been correct. It is assumed that the data signal has not been ﬁltered at the transmitter. Any use is subject to the Terms of Use as given at the website. The second sample (b) will be at the second last tap (coefﬁcient b). The samples are digitized by an ADC. which is the cross correlation of the logical 1 waveform with the logical 0 waveform (with time delay t = 0).The PLL in Communications The PLL in Communications 295 time”? Taking a sample at the beginning of the symbol would certainly be wrong. The digitized samples are shifted into an FIR ﬁlter having length 4. The coefﬁcients of the upper FIR ﬁlter have the same values by deﬁnition. A logical 0 is also represented by one cycle of the sine wave. but instead would form some statistic (e. But what if there is noise on the signal? If the current incoming symbol is a 1 and a noise spike appears just at the end of the symbol.20 There are many variants of the correlation ﬁlter. We ﬁrst consider the case where the incoming symbol is a 1 (solid curve).digitalengineeringlibrary. At this instant the upper ﬁlter outputs a sample having the value a2 + b2 + c2 + d2.. In our example. This leads us to the idea that a decision for a symbol could be more meaningful if the receiver would not just check one single sample of the received symbol. First of all. and What type of correlation ﬁlter do we need? Downloaded from Digital Engineering Library @ McGraw-Hill (www. Numerically the upper correlator delivers an output of +2 when a 1 is received. All rights reserved. Figure 9. so one symbol could extend over a number of sine wave cycles. Its coefﬁcients are deﬁned by [-d -c -b -a] and hence correspond to the undistorted values of the symbol waveform for a logical 0. the symbols could have longer duration. this equals the autocorrelation of the symbol sequence (with time delay t = 0). the receiver would falsely decide for a 0. but has initial phase p (dashed curve). To be more general. . an average or a correlation) from all samples of the symbol waveform within the symbol period. the lower correlator outputs the value -a2 -b2 -c2 -d2 at the end of the symbol period. and that a logical 1 is represented by one full cycle of a sine wave (solid curve at top left) having initial phase 0. The receiver then would decide that the symbol is 1 if the ﬁnal amplitude is positive. these values form a vector.11 demonstrates the operating principle. etc. which is also referred to as a matched ﬁlter. or a 0 if it is negative. causing the signal to take on a negative value. If there is no noise on the received symbol. which is not shown in the diagram. assume that the 4 samples of the symbol have the values [a b c d]. after four shifts the ﬁrst sample (a) will be at the last tap of the ﬁlter (coefﬁcient a). here it was assumed that the sampling rate is 4 times the symbol rate. so they take on the values [d c b a]. Of course. We now consider what happens with the lower FIR ﬁlter. Had it taken a sample just prior to that noise spike. Hence it would be more appropriate to sample that signal at the end of the symbol. Correlating the undemodulated waveform is simpler to explain.

The incoming symbol is correlated with the template functions that are stored in the receiver.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website.digitalengineeringlibrary. The ﬁlters shown in the diagram are called matched ﬁlters because their coefﬁcients exactly match the samples of the undistorted symbol waveform(s). the receiver decides that the symbol is a 1 and vice versa. Whenever the upper correlator output is more positive than the lower. An error occurs only if the noise level is so high that it reverses the polarities of the correlator output signals. In such simple cases the receiver does not need two correlators. the lower correlator delivers -2. The upper correlator then would output +1. To decide whether a symbol is 0 or 1. The upper correlator in Fig. the reverse happens: the upper correlator outputs -2. and the lower -1. the receiver compares the two correlator outputs at the end of each symbol. but with inverted polarity. and the lower outputs +2.The PLL in Communications 296 Chapter Nine Received symbol waveform +1 0 0 –1 TS 0 *–1 FIR filter "1" D D D *0 *1 *0 Correlator "1" Out SUM FIR filter "0" D = delay D D D *1 *0 *–1 *0 Correlator "0" Out SUM Figure 9. which means that this error does not lead to a wrong decision. It can be shown that the decision made by a correlation receiver is a maximum likelihood decision in the statistical sense.11 would be sufﬁcient: decisions would be made by looking only at the sign of the correlator output. The beneﬁt of the correlation ﬁlter becomes obvious when we assume that a logical 1 was received.20 since the receiver compares the incoming symbol waveform with all existing Downloaded from Digital Engineering Library @ McGraw-Hill (www. . 9. All rights reserved. but are arranged in reversed order. but the second sample (nominal value 1) was corrupted by noise and has a value of 0. for example. In this example the waveform for logical 0 was chosen identical with the waveform for logical 1. If a logical 0 is received.11 Block diagram of a correlation receiver.

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theoretical symbol waveforms and checks which of the stored templates has the greatest similarity (likelihood) to the received symbol.

What about raised cosine ﬁlters?

As stated, the described correlation method works best with carriers that are modulated with a square wave data signal. To reduce the bandwidth, modern digital communications mostly work with ﬁltered data, as discussed in Sec. 9.4.1. When considering the working principle of the Costas loop (refer again to Fig. 9.10), we became aware that the output of the loop ﬁlter in the I branch provides the recovered data signal. When ﬁltering the symbol stream in the transmitter, we must design the ﬁlter such that no intersymbol interference (ISI) can occur. The raised cosine ﬁlter has been considered an optimum solution for this problem. But now in the Costas loop the data signal passes through an additional low-pass ﬁlter. As was demonstrated by the correlation receiver in the example of Fig. 9.11, the qualitiy of symbol decision in the receiver would be optimum when the same RCF is used in place of the I branch of the Costas loop. Unfortunately this does not work in the desired way, because now the signal goes through two cascaded raised cosine ﬁlters. The frequency response of the combined ﬁlter then would be no longer symmetrical about half the symbol rate, and ISI would be generated. The frequency response of the low-pass ﬁlter in the receiver should be chosen such that the combined ﬁlter represents an RCF in order to realize minimum ISI. Theoretically this goal is achieved only if the loop ﬁlter is an ideal low-pass ﬁlter. In the best case, we could try to approximate a brickwall ﬁlter, but this is suboptimal and results in an FIR ﬁlter with a very great number of taps. Moreover the brickwall ﬁlter would not be matched to the symbol waveform, and hence would have poor noise-suppressing capabilities. There is a more elegant solution: the root raised cosine ﬁlter (RRCF). The frequency response of the root raised cosine ﬁlter is deﬁned to be the square root of the frequency response of the raised cosine ﬁlter. Thus the RRCF has a frequency response of the kind Ï1 Ô Ô p 2T f + r - 1 Ô H ( f ) = Ìcos 4 r Ô Ô 0 Ô Ó for for for f < 2T f > 1-r 2T £ f £ 1+r 2T (9.7)

1-r

1+r 2T

The impulse response h(t) of the RRCF is given by41 pt 4 rt pt (1 - r)˘ + (1 + r)˘ sin È cos È Í ˙ Í ˙ Î ˚ Î ˚ T T T h(t) = 2 pt È Ê 4 rt ˆ ˘ Í1 ˙ TÎ Ë T ¯ ˚

(9.8)

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Like the impulse response of the RCF, the impulse response given by Eq. (9.8) has singularities. For some values of time t, h(t) becomes a division 0/0. In analogy, this problem is mastered by applying L’Hôpital’s rule and replacing numerator and denominator by their derivatives. The frequency response of the RRCF is no longer symmetrical about half the symbol rate; hence it leads to ISI which, of course, is not desired. But if the receiver also contains an identical RRCF, the overall frequency response is identical to that of the RCF; hence after the demodulator, ISI becomes zero again. The second goal—a maximum likelihood demodulator—is achieved simultaneously: the impulse response of the RRCF in the receiver closely matches the symbol waveform, which is nothing else than the impulse response of the RRCF in the transmitter. Consequently, the RRCF in the receiver is a matched ﬁlter. The operating principle of the matched ﬁlter is shown in Fig. 9.12. This schematic can be considered part of the block diagram of the Costas loop in Fig. 9.10. The modulated carrier is ﬁrst fed to the input of a multiplier, which serves as a demodulator. The multiplier can be an analog circuit, though in many cases a digital multiplier is used today. The matched ﬁlter is given by the RRCF. This ﬁlter is usually clocked with a frequency fC that is an integer multiple of the symbol rate fS. (In Fig. 9.12, fC = 1/TC and fS = 1/TS.) The output of the matched ﬁlter (correlator) is read out at the symbol rate fS. It must be emphasized that the data signal at the output of the matched ﬁlter is no longer given by pulses or square waves, but by the superposition of oscillating waveforms as was shown by Fig. 9.8. To reconstruct the data correctly, it is very important that the receiver sample the matched ﬁlter ouput at the correct times, i.e., precisely at t = 0, T, 2T. . . . This implies that the receiver must know when a symbol starts and when it is over. This must be accomplished by appropriate symbol synchronization circuits; these will be discussed at the end of this section.

The “integrate and dump” circuit.

When the data signal is not low-pass-ﬁltered at the transmitter, the demodulated symbol stream represents nearly a square wave signal. The input to the matched ﬁlter then would be almost constant

Modulated carrier MUL TC

Matched Filter TS

Symbol out

**Reconstructed carrier cos(w1t)
**

Figure 9.12

Principle of a matched ﬁlter that correlates the demodulated symbol waveform with a template stored in the receiver.

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299

during the symbol period (+1 or -1). Under this condition, the correlator can be built from an integrator, as shown in Figure 9.13a. At the end of a symbol, the integrator is reset (dumped) to zero. When the next symbol is a logical 1 and is shifted into the integrator, its output builds up a staircase (Fig. 9.13b). The staircase function reaches its maximum at the end of the symbol. If the incoming symbol were a logical 0, the staircase would run negative. The symbol is determined at the end of the symbol period. Because the integrator is dumped after every symbol period, this conﬁguration is also called an integrate and dump circuit. Integrated digital Costas loops such as the Harris HAS5021042 provide both RRCF and integrate and dump circuits. They can be conﬁgured individually according to the given application and symbol format.

Symbol synchronization.

To conclude we will deal with the problems related to symbol synchronization. When performing phase synchronization, the receiver reconstructs a replica of the carrier that is locked in frequency and phase to the

Modulated carrier MUL TC

Integrate and dump

UID Symbol out TS

Reconstructed carrier cos(w1t)

Dump

(a)

UID Dump

TS

(b)

**Integrate and dump circuit: (a) block diagram; (b) output of the integrator for a square wave input.
**

Figure 9.13

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incoming carrier. When synchronizing with symbol timing, the receiver must recreate the symbol clock in order to know exactly when the end of a symbol period has been reached. We remember that the receiver has to sample the output of the correlation ﬁlter at the instant where the incoming symbol is terminated and the next symbol period is starting. There are many methods to achieve symbol synchronization; we discuss only the most often used.

“Midsymbol” sampling. We ﬁrst discuss a method called midsymbol synchronization. It is mainly used when the data are low-pass ﬁltered, e.g., by the root raised cosine ﬁlter. The correlator output is then sampled at the end of each symbol period (which corresponds to the instants t = -2T, -T, 0, T, 2T, etc., in Fig. 9.8). If a sequence of 1s is received, the end-symbol amplitudes will all be around +1. If a sequence of 0s is transmitted, all succeding end-symbol amplitudes will be around -1. Whenever a 1 is following a 0 or vice versa, however, the data signal crosses zero; this is shown in Fig. 9.14. When the symbol clock is properly adjusted, the zero crossing will be in the center between two succeding decision points (labeled End symbol “1” and End symbol “0” in the ﬁgure). The expected midsymbol time is now calculated by taking the average of the two end-symbol times. The theoretical location of the zero crossing is labeled Mid symbol (expected). If the actual zero crossing of the symbol signal deviates from this precalculated value [the point labeled Mid symbol (actual)], the symbol timing is erroneous and must be corrected. The timing error (the difference between actual and expected location of midsymbol) is used to adjust the frequency of a local symbol clock generator. The midsymbol synchronization makes use of zero crossings. No timing information is available when a logical 1 is following by another logical 1. The same holds true for a sequence of 0s. The early-late gate. Another symbol synchronization technique that is widely used is the early-late gate, Fig. 9.15. This method works best when the data are square wave signals. In this case the symbol signal s(t) is constant and

End symbol "1" Data signal

+1

TS/2

**0 Mid symbol (actual) Mid symbol (expected) –1 End symbol "0" TS
**

Figure 9.14

Symbol synchronization using midsymbol values.

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Early gate

Integrator

y1

ABS

Ôy1Ô

Symbol out s(t)

Gate 0...TS /2 e VCO LF

– Add +

Figure 9.15

Gate TS /2...TS

Integrator

y2

ABS

Ôy2Ô

Symbol synchronization using the early-late gate technique.

Late gate

e =Ôy2Ô–Ôy1Ô

positive during a symbol period if the incoming symbol is a 1, or constant and negative if the symbol is a 0. The “early gate” is a gated integrator summing up the symbol during the ﬁrst half of the symbol period. The “late gate” is another integrator that is gated on during the second half of the symbol period. When symbol timing is correct, the outputs of both integrators are identical, as shown in Fig. 9.16a (the shaded areas). The output signals y1 and y2 are equal then, and the error signal e in Fig. 9.15 is zero. When there is an offset in symbol timing, the outputs of the integrators become unequal (Fig. 9.16b), and the error signal becomes positive or negative. Its polarity depends on the sign of the timing error. The waveforms in Fig. 9.16 are shown for an incoming symbol representing logical 1. If the symbol is a 0, the polarities of the integrator outputs get inverted. Because the sign of the error signal must not change when the symbol switches from 1 to 0, absolute value circuits follow the integrators (Fig. 9.15). Additional symbol synchronization circuits have been discussed in references.1,20 9.5 Digital Communications Using QPSK

9.5.1 Transmitter considerations

QPSK has been deﬁned in Sec. 9.2; refer also to Fig. 9.3. To implement QPSK, two carriers have to be generated in the transmitter that are offset in phase by 90°. As explained by Fig. 9.2, the symbol stream is partitioned into two data streams; one of those is used to modulate the in-phase carrier, while the other modulates the quadrature carrier. An example of a QPSK modulator is shown in Fig. 9.17. This is a block diagram of the Harris HSP50307 burst QPSK modulator.43 Data are fed at a rate of 256 kbit/s to the TX_DATA input. The partitioning into I and Q streams is made by the demultiplixer. The bit rate after partitioning is reduced to 128 kbit/s. I and Q data are ﬁltered by an RRCF. This

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Chapter Nine

(a)

(b)

Data symbol +1 0 –1

TS

Early gate

Late gate

Correct timing

Timing error DT

Figure 9.16 Gate timing of the early-late gate circuit. (a) Waveforms for correct timing. (b) Waveforms for timing error DT.

RCLK VCO_IN

VCO_SET PD_OUT

RESET CCLK C_EN CDATA TX_EN I TX_DATA DEMUX CONTROL INTERFACE SYNTHESIZER † QUAD GEN † D/A LPF LPF Q 9 8RRC D/A LPF PGA QUADRATURE MODULATOR

†

I/Q GENERATOR 9 8RRC

MOD OUT-

MOD OUT+ TX_EN

TXCLK MCLK /100

IBBIN

QBBOUT

DAC_REF † Indicates analog circuitry. MCLK MUST ALWAYS BE PRESENT FOR PROPER OPERATION

IBBOUT

QBBIN

VCM_REF

Figure 9.17

Block diagram of burst QPSK modulator Harris HSP50307. (Used with the permission of the Harris Corporation.)

m2 (t) sin(w 1t + q1 ) where w1 is the radian frequency of the carrier and q1 is the phase.20 This circuit is shown in Fig.10). but receive a signal that is the addition of two carriers modulated by two different data signals. so the circuit can also be used to demodulate QAM signals (see Sec. Oversampling is accomplished by zero padding: 7 zeros are inserted between any two succeding samples of the I and Q data stream. 9. Any use is subject to the Terms of Use as given at the website. These ﬁlter outputs (IBBOUT and QBBOUT) modulate the two carriers. 9. 9.The PLL in Communications The PLL in Communications 303 ﬁlter has order 64 (length 65) and is clocked at a frequency of 1. All operations that can be done digitally are performed by digital circuits.024 MHz.1 the output vd of the adder (at center right in Fig. we no longer have to deal with one single carrier. 9. With QPSK. m1(t) and m2(t).5. It is quite similar to the original arrangement (Fig.1.m2 (t) sin q e ] . This integrated circuit is a mix of analog and digital circuitry. the combined output signal uQPSK of the transmitter can be written as uQPSK (t) = m1 (t) cos(w 1t + q1 ) . The excess bandwidth of the RRCF is chosen r = 0. If we assume that m1(t) modulates the in-phase carrier and m2(t) the quadrature carrier. the ﬁlter input signal is oversampled by a factor of 8. that is.com) Copyright © 2004 The McGraw-Hill Companies.digitalengineeringlibrary. When the loop has locked.2 Receiver considerations The receiver for BPSK had to regenerate a carrier that was in phase with the carrier. For rectangular data signals the average dc output vd of the adder becomes Downloaded from Digital Engineering Library @ McGraw-Hill (www. .m2 (t) sin q e ] sgn[m1 (t) sin q e + m2 (t) cos q e ] where sgn (signum) speciﬁes the action of the limiter and qe = q1 .q2 is the phase error. The two low-pass ﬁlters (loop ﬁlters) in the I and Q branches are now followed by limiters.10.5. The unwanted high-frequency signals caused by digital-to-analog conversion are removed by two analog low-pass ﬁlters.6). the VCO will generate a signal of the form uVCO (t) = sin(w 1 + q2 ) where q2 is the phase of the output signal. 9. 9.18) is given by vd (t) = [m1 (t) sin q e + m2 (t) cos q e ] sgn[m1 (t) cos q e .18. All rights reserved. The Costas loop was extended to lock onto a modulated QPSK signal. as shown in the right half of the block diagram. respectively. The ﬁltered data are applied to the inputs of two DACs. The carrier frequency can be programmed within a range of 8 to 15 MHz in steps of 32 kHz. By virtue of the limiters the output signals become independent of the levels of the modulating signals.[m1 (t) cos q e . Following the analysis of Gardner. this was done by the Costas loop in Fig.

the HSP50110 (digital quadrature tuner) and the HSP50210 to be described here.18 LPF Costas loop extended for the demodulation of QPSK. These are fed to two root raised cosine ﬁlters. .com) Copyright © 2004 The McGraw-Hill Companies. When the phase error deviates only slightly from 90°. Any use is subject to the Terms of Use as given at the website.The PLL in Communications 304 Chapter Nine Q branch MUL LPF Limiter MUL + Input Q out 90∞ ADD I out – vd I branch MUL LPF Limiter MUL VCO Figure 9.digitalengineeringlibrary. All rights reserved. Downloaded from Digital Engineering Library @ McGraw-Hill (www. If it locks at qe = 00. 180°. The complex multiplier output delivers the unﬁltered baseband data. Analog operations can be performed with the remaining values of phase error where the Costas loop can lock. vd(t) is proportional to that deviation. Complex multiplication simply means that the incoming signal is multiplied with a cosine wave in one arm and with a sine wave in the other arm of the demodulator. 90°. which is near zero. Ïsin q e Ô. vd(t) = sin qe.19 shows a block diagram of this device. and 270°.sin q e Ô Ócos q e if if -45∞ < q e < 45∞ 45∞ < q e < 135∞ if 135∞ < q e < 225∞ if 225∞ < q e < 315∞ There are four values for qe where the loop can lock: qe = 0°. If the loop locks at qe = 90°. which can be approached by qe for small phase error. Demodulation of the I and Q signals takes place at the complex multiply circuit at the left. respectively. vd(t) becomes –cos qe.cos q e Ô ( ) vd t = Ì Ô Ô. Actually the full receiver is made up from cascading two integrated circuits. A realization of the Costas loop for QPSK reception is found in the circuit HSP50210 manufactured by Harris. and the circuit again operates like a simple PLL. The Costas loop then operates like a conventional PLL.42 Figure 9.

com) Copyright © 2004 The McGraw-Hill Companies.TO SYMBOL TRACKING MID AND END SYMBOL SAMPLES Q Q I I MID END MID END REGISTER ENABLE RATE @ = SYNC RATE * = TWICE SYMBOL RATE ! = SYMBOL RATE BLANK = CLK RATE FALSE LOCK REG MATCHED FILTERING DATA DE-SKEW OQPSK COMPARE BYPASS RRC R E G M U R X E G R E G + * M U X * “0” TWO SAMPLE SUMMER S H I F T BYPASS I&D D E M U X R E G SOFT DECISION SLICER REG REG NCO MIXER R E G AOUT9-0 TEST M U X R R E E G G R R E E G G CARTESIAN TO POLAR 8 BYPASS MIXER ! OR * ! OR * O U T P U T HI/LO D E M U X SIN COS LEVEL DETECT DUMP M U X + @ ROOT RAISED COSINE (RRC) AGC LOOP FILTER * R E G R E G + S H I F T @ M U 15 TAP RRC R R X E E @ G G R E G R E G 15 TAP RRC R R E E G G @ R L E I G M I R T E G M U X INTEGRATE AND DUMP HOLD AGC “0” + R E G S H I F T R E G M U X GAIN ERROR R E G @ OR ! L I M I T UPPER LOWER GAIN GAIN LIMIT LIMIT LOOP GAIN EXPONENT LOOP GAIN MANTISSA DUMP “0” M U X R E + G R E G R E G BOUT9-0 ÷ I +Q 2 2 S E L E C T 5 DELAY REG 5 –1 Q TAN ( ) DELAY I REG PHASE OUT AT @ OR * MAG OUT AT @ OR ! AGC ERROR DETECT AGC THRESHOLD – POWER THRESHOLD + 8 The PLL in Communications QIN9-0 R E G M U R R X COMPLEX E E MULTIPLY G G R R E E G G IIN9-0 REG REG REG REG SIN/COS ROM TO CARRIER TRACKING AND DISCRIMINATOR REG + COMPARE R THRESH E G Downloaded from Digital Engineering Library @ McGraw-Hill (www. Any use is subject to the Terms of Use as given at the website.) 305 .digitalengineeringlibrary. All rights reserved. REG CF REGISTER FROM CARRIER TRACKING LOOP FILTER Figure 9.19 Block diagram of the digital Costas loop Harris HSP50210. (Used with permission of the Harris Corporation.

2. the symbol rate becomes (41. With QAM64.20 RS(188.4). we therefore would have to sample it at 10 MHz. 9. the redundancy of the compressed signal is slightly increased by making use of Reed-Solomon codes. we transmit 188 + 16 = 204. the bit rate goes up to 41.9 Mbaud. While all symbols have the same amplitude with QPSK. With this amount of added redundancy. Consequently. To transmit the signal using BPSK the bandwidth would become around 50 MHz.15) for ﬁltering the data.97 MHz. Any use is subject to the Terms of Use as given at the website.6 Digital Communications Using QAM As was demonstrated in Sec. 6 bits per symbol can be transmitted (refer to Fig. A nice application of QAM is found in digital video broadcasting (DVB). All rights reserved. the bandwidth is slightly increased to (1 + r)3. In Europe.9/2 = 3.The PLL in Communications 306 Chapter Nine The sine and cosine waveforms that are required for demodulation are taken from a table lookup ROM. QAM can be considered an extension to QPSK. When transmitting the signal digitally.digitalengineeringlibrary. shown at bottom left.4 Mbit/s)/6 = 6. which is below the required value of 8 MHz.45 MHz would be required.45. The circuits for transmission and reception of QAM signals are similar to those used with QPSK. its two-sided bandwidth becomes 2(3.97) = 7. a one-sided bandwidth of 6. which is far from realistic. Because the proposal recommends the RRCF (with r = 0. . channel spacing is standardized to 8 MHz. 9. Downloaded from Digital Engineering Library @ McGraw-Hill (www. The major beneﬁt of QAM is increased symbol throughput without increased bandwidth. This represents a Reed-Solomon code that adds 16 check bytes for each block of 188 bytes: instead of transmitting 188 bytes. 204). When the color signal is added. which can be used when the data signals are rectangular. By source coding. These signals are generated digitally by interpolating values of sine and cosine functions stored in a ROM.4 Mbit/s. It was one of the goals of this standard to use the same bandwidth with digital TV broadcasting.47 In analog video broadcasting.45 = 3. some redundancy is removed from the signal. we easily end up with 100 Mbit/s.20 Source coding is a means to reduce the symbol rate at the data source. Because MPEG-2 adds little error protection. Using 8 bits per pixel. hence the code RS(188. the amplitude of both in-phase and quadrature components now can take on a number of different values with QAM.46 9. but the receiver must be equipped with additional level discriminators. When transmitting the signal in the baseband. Also shown are two integrate and dump circuits. This can only be realized by extensive use of source and channel coding. a proposal for digital video broadcasting was presented under the name DVB-C.com) Copyright © 2004 The McGraw-Hill Companies. More detailed information is available from application notes. An analog TV signal has a bandwidth of approximately 5 MHz. 204) is recommended in the proposal.94 MHz. the luminance signal alone needs a channel capacity of around 80 Mbit/s. Application of the MPEG-2 standards reduces the bit rate to about 38 Mbit/s. When a highfrequency carrier is modulated with that signal.

there are two basic types of FSK decoding—coherent and noncoherent. Before discussing alternatives. If a binary coherent FSK system with a symbol rate of 2400 bit/s is envisaged. To accomplish the required symbol rate. Such circuits are very easily implemented. and a binary 1 would be given by one full cycle at 2400 Hz. The decoder circuit shown in Fig. 6.7 Digital Communications Using FSK 9. The difference between any two frequencies used in FSK must therefore be at least half the symbol rate. 9. All rights reserved. Any use is subject to the Terms of Use as given at the website. but have the disadvantage that the maximum symbol rate stays far below the limits predicted by theory. for example).digitalengineeringlibrary. As will be demonstrated later a coherent detector for FSK must know the phase of the FSK signal. respectively. let us recall what should be achieved theoretically.2.7. but not effective FSK is still one of the most widely used techniques in the communication of digital signals. This can be explained by looking at the spectrum of the tones. In such applications a linear digital. For noncoherent detection. Tone 1 is called s1(t) and is represented by a burst of a cosine wave of frequency f1 and duration TS.21 sets the D ﬂipﬂop on every positive edge of the input signal u1 and hence needs at least one cycle to react onto a frequency step. . 6. Equation (9. it would have to lock onto a new frequency whenever an imcoming symbol differs from the preceding. This requirement is dropped if the receiver uses noncoherent detection. DPLL. If an LPLL.com) Copyright © 2004 The McGraw-Hill Companies. we could use the frequencies f1 = 1200 Hz and f2 = 2400 Hz to represent the binary values 0 and 1.1) says that for coherent FSK.21. the frequencies f1 and f2 would have to be chosen much higher. and hence can be written as s1 (t) = (cos 2 pf1t) rect(t TS ) (9. and why the simpler circuits cannot reach these goals. Although the ADPLL is the fastest circuit of those mentioned. respectively.The PLL in Communications The PLL in Communications 307 9. We assume that FSK2 is applied and two tones having frequencies f1 and f2 are used to represent binary 0 and 1. the minimum frequency spacing is larger by a factor of 2. the minimum spacing becomes equal to the symbol rate 1/TS. or ADPLL were used as FSK decoder (as in Fig. it would certainly not be able to settle to another input frequency within one half-cycle only. or all-digital PLL can immediately serve as an FSK demodulator. As stated in Sec. Binary FSK has been extensively used in modems for moderate speeds. each frequency representing a symbol value must be an integer multiple of half the symbol rate. that is. where the symbol rate is given by 1/TS. This would result in much larger bandwidth.1 Simple FSK decoders: Easy to implement. A binary 0 would then be given by just one half-cycle of a 1200-Hz oscillation.9) where rect(t/TS) denotes a rectangular pulse of duration TS and is deﬁned by 1 for -TS 2 £ t £ TS 2 rect(t TS ) = Ï Ì Ó0 for t > TS 2 The spectrum of tone 1 is a sinc function Downloaded from Digital Engineering Library @ McGraw-Hill (www. of course.

7. where k is an integer >0.The PLL in Communications 308 Chapter Nine S1 ( f ) = Ts sin(pTS ( f . This requirement is fulﬁlled if the frequency of tone 2 is displaced by exactly 1/TS.f1 ) (9.8 0.20.20 (solid curve). In order that two tones in binary FSK not interfere with each other during detection.4 –4 –3 –2 –1 0 1 2 Frequency f normalized to symbol rate R 3 4 Figure 9.2 0 –0. The incoming symbol is correlated by two correlators.4 0.21. 9.6 Amplitude 0. 9. 9.com) Copyright © 2004 The McGraw-Hill Companies. Any use is subject to the Terms of Use as given at the website. . Hence the two tones can be detected without interference. 9. This proves that the frequency spacing must be equal to the symbol rate 1/TS and is therefore larger by a factor 2 than the spacing required for coherent detection.digitalengineeringlibrary. It has zeros at frequencies f = f1 ± k/Ts. Its peak is at a location where the spectrum of tone 1 is exactly 0.10) The spectrum is symmmetrical about the frequency f = f1. Downloaded from Digital Engineering Library @ McGraw-Hill (www.2 –0. This demodulator is not shown in the block diagram. The spectrum of tone 2 is shown by the dotted curve in Fig.2 Coherent FSK detection A coherent binary FSK decoder is shown in Fig.20 Spectra of tone 1 and tone 2 in noncoherent FSK detection. All rights reserved. These are usually imple- Spectra of tone 1 and tone 2 1 0. as shown in Fig. We are going now to discuss some of the most familiar coherent and noncoherent FSK decoder schemes. The input is given by the demodulated FSK signal.f1 )) pTS ( f . the peak of the spectrum of tone 1 must coincide with one of the zero crossings of the spectrum of tone 2.

22 Noncoherent (quadrature) FSK decoder. The lower correlator will then output a signal that is close to 0. the upper correlator delivers a large positive output at the end of the symbol. which is mostly an integer multiple of the symbol rate. the result is actually the autocorrelation of the signal s1(t) at a delay of 0.The PLL in Communications The PLL in Communications 309 TC Correlator s1 FSK in TC Correlator s2 Figure 9. If s1(t) is the waveform for a logical 0 and the incoming symbol is a logical 0. If the output of the upper correlator is larger than the output of the lower. Any use is subject to the Terms of Use as given at the website. All rights reserved. Downloaded from Digital Engineering Library @ McGraw-Hill (www. mented by FIR ﬁlters. more than two frequencies are used to represent m-ary TC Correlator cosw1t TS Square Add TC FSK input TC Correlator sinw1t TS Square Max selector Square Add Symbol out Correlator cosw2t TS TC Correlator sinw2t TS Square Figure 9. the decoder decides that the symbol was a 0. see Fig. To decide whether an incoming symbol is a 0 or a 1. The FIR ﬁlters operate at the clock frequency fC = 1/TC. their coefﬁcients are identical to those of the samples of the corresponding symbol waveforms. In m-ary FSK. the detector compares the outputs of both correlators. 9.21 TS Symbol out Max selector TS Coherent FSK decoder.5b. . The correlator outputs are sampled at the symbol rate fS = 1/TS at the end of each symbol. actually it is the cross correlation between s1(t) and s2(t) which is 0 by deﬁnition.com) Copyright © 2004 The McGraw-Hill Companies. and vice versa.digitalengineeringlibrary.

If the incoming symbol is a 0. It is still assumed that radian frequency w1 represents a logical 0.e. By squaring and adding the outputs of the upper two correlators. If j were close to 0. the reverse would happen: the uppermost correlator output would be near 0.digitalengineeringlibrary.. but the second correlator would deliver a large correlation. With noncoherent detection. It then must provide a pair of correlators (cosine and sine waves) for each state the symbol can take on. because there is almost no correlation with the sine wave sin w1t. so the uppermost correlator would deliver a large positive output at symbol end. e. Any use is subject to the Terms of Use as given at the website. sin w1t. and sin w2t. cos w1t. four.3 Noncoherent FSK detection and quadrature FSK decoders A noncoherent binary FSK decoder is shown in Fig. there would be a correlation with both cosine and sine waves. its waveform can be written as s1 (t) = cos(w 1t + j) where j is an arbitrary phase. cos w2t. i. The lower two correlators provide correlation of the incoming symbol with the stored replicas for a logical 1. 9. but the second correlator output would be near 0. the decoder decides that the received symbol is a logical 0. Consequently the decoder provides four waveforms. 9.7. the combined correlator output becomes independent of phase j. It therefore generates quadrature signals for every existing symbol waveform. there would be a strong correlation of the FSK signal with cos w1t. If it happens that the upper correlator has a larger output. In fact the output signal of the adder is proportional to the energy of the symbol waveform. m correlation ﬁlters must be provided in the FSK decoder.g. Assume that the FSK signal can have the two radian frequencies w1 and w2. For arbitrary phase j. a maximum selector checks which of the summed correlator outputs is greater at symbol end. Downloaded from Digital Engineering Library @ McGraw-Hill (www.22. This decoder is therefore referred to as a quadrature FSK decoder. Again. the receiver does not know the phase of the symbol waveforms. For arbitrary m.. All rights reserved. This circuit can also be extended for m-ary FSK.com) Copyright © 2004 The McGraw-Hill Companies. . If j were close to p/2.The PLL in Communications 310 Chapter Nine symbols. and radian frequency w2 represents a logical 1.

silicon and SiGe devices came on the market that outperformed even the GaAs types in speed. or just an analog multiplier. or parts of a PLL 311 Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies. production of GaAs devices has been discontinued. Because the frequency range of many such circuits exceeds the capabilities of standard CMOS devices. an additional in-lock detector. Any use is subject to the Terms of Use as given at the website. All rights reserved. however. In addition.or variable-ratio down-scalers for the reference input and one or more programmable down-scalers for the VCO output signal. i. and the like.digitalengineeringlibrary.Source: Phase-Locked Loops Chapter 10 State of the Art of Commercial PLL Integrated Circuits The designer of a PLL system has a broad choice of ICs built from different semiconductor technologies. in recent years. some gallium arsenide (GaAs) PLLs were added to the already big family of silicon devices. There are a great number of ICs that contain a complete PLL system. The ﬁrst of these down-scalers is used to scale down the frequency of a quartz oscillator that typically operates at 5 or 10 MHz. a single VCO. Table 10. a full frequency synthesizer. In the last few years. they used a process known from bipolar operational ampliﬁers. many PLL frequency synthesizer systems are available in one single package. the number of high-speed prescalers is increasing very fast.1 lists the presently available ICs containing a full PLL. In the last few years.. . transistor-transistor logic (TTL) circuits appeared. Faster circuits were produced in emitter-coupled logic (ECL) technology. there exist ICs that include only one or more phase comparators. the synthesizer ICs mostly include ﬁxed. Many of the offered ICs contain some extras such as an additional op-amp. and somewhat later complementary metal-oxide-semiconductor (CMOS) devices became available.e. The ﬁrst available ICs were mainly manufactured in “bipolar” technology. In the late 1980s. a great number of PLL-based semiconductor devices have been introduced that contain the full circuitry for radio and television receivers or for mobile phones. The GaAs technology could not realize the expected breakthrough. The GaAs devices extended the frequency range to the gigahertz region. Besides the usual PLL components. Shortly after. Most of these synthesizer ICs include the circuitry of the reference oscillator. Furthermore.

for example. the general-purpose DPLL chips are all based on the old 4046 chip. There are links to all PLL IC manufacturers. the 74xx297. The choice is largest among the LPLL chips.7). a bandgap reference has been added which controls the frequency generated by the VCO. but the 74HC/HCT4046 is different.com/appinfo/wireless). The second column describes the function of the IC. the market offers a wide selection of related circuits such as phase detectors. There is also a link to a Web site created by National Semiconductor that performs frequency synthesizer designs based on the company’s synthesizer ICs (http://www/national. the 74HC/HCT4046. we recognize that only one type is on the market. which is listed in the ﬁrst column. The 4046 contains two phase detectors: an EXOR and a PFD. Any use is subject to the Terms of Use as given at the website. VCOs.com) Copyright © 2004 The McGraw-Hill Companies. however: in CMOS and in LS-TTL. Many of the newer frequency synthesizer PLLs include phase detectors with charge pump output. When looking for an ADPLL circuit.com free of charge. It is available in two device technologies. and the 74HCT9046. and frequency synthesizers. Garden City. The 74HC/ HCT7046 is functionally equivalent to the former 4046. New York. This library is also available on CD-ROM and can be accessed from http://www. a JK-ﬂipﬂop. . which enables the user to download almost every data sheet and a great number of application notes. All rights reserved. The PLL circuits are listed in the category of linear circuits. prescalers.digitalengineeringlibrary.50 This design feature can be accessed by calling the EasyPLL option on this Web site. In addition. and a PFD. Furthermore. Besides the PLL systems. Three descendants have been derived from this circuit: the 74HC/HCT7046. but the PFD integrated in this chip provides charge pump outputs (see Sec. because it contains three different phase detectors instead of two: an EXOR.icmaster. Downloaded from Digital Engineering Library @ McGraw-Hill (www.State of the Art of Commercial PLL Integrated Circuits 312 Chapter Ten system. Searching for PLL devices has become simple because most of them are listed in IC Master. Using a stable source improves the stability of the VCO output frequency. 2. The PLL ICs are sorted by device family. The 74HCT9046 is similar to the 74HCT7046. a data book published yearly by Hearst Business Communications. which is a member of the 4000 CMOS family originally introduced by RCA.

Linear Linear Linear Linear PLL prescaler Count extender Count extender Frequency synthesizer 200–400 MHz. Downloaded from Digital Engineering Library @ McGraw-Hill (www. General-purpose ADPLL. As 74HC7046. All rights reserved. for cordless phones. As 74HC297. Phase-locked loop (DPLL) *74HC4046* HCT Phase-locked loop (DPLL) *74HCT4046* As 74HC4046. Any use is subject to the Terms of Use as given at the website. As 74HC297.State of the Art of Commercial PLL Integrated Circuits State of the Art of Commercial PLL Integrated Circuits 313 TABLE 10. HC ADPLL 74HC297 Philips HCT LS-TTL TTL Linear ADPLL ADPLL Phase-frequency detector Clock recovery and data retiming PLL 74HCT297 74LS297 4344 AD802-155 AD802-45 AD802-52 AD805 CLC016 TB2109 TB31201 SP8790* SP8794* RCK604 Philips Intersil TI Lansdale AD AD AD AD National Toshiba Toshiba Mitel Mitel IntCirSys For cordless phones. JK-ﬂipﬂop. Crystal controlled. Has two phase detectors: EXOR and JKﬂipﬂop. ∏4. . ∏8. VCO powered by band gap reference for high stability of center frequency. HC Phase-locked loop (DPLL) *74HC7046* General-purpose DPLL containing two phase detectors: EXOR and PFD. General-purpose DPLL containing two phase detectors: EXOR and PFD.1 Commercially Available PLL ICs and Related Components.digitalengineeringlibrary. 2002 Device technology Function HC Device Source Fairchild Intersil On Semi Philips Rochester TI Intersil Philips TI Philips TI Intersil Philips TI Fairchild Intersil Lansdale On Semi R&E Intl ST Micro TI Philips Features General-purpose DPLL containing three phase detectors: EXOR.com) Copyright © 2004 The McGraw-Hill Companies. ∏N divider is external. ∏10/11 becomes ∏40/41. Frequency range to 19 MHz. ∏10/11 becomes ∏80/81. and PFD. PFD has charge pump output. HCT 4xxx Phase-locked loop (DPLL) *74HCT7046* Phase-locked loop (DPLL) *4046* HCT Phase-locked loop (DPLL) 74HCT9046 General-purpose DPLL containing two phase detectors: EXOR and PFD.

Linear Linear Linear Frequency synthesizer Frequency synthesizer Frequency synthesizer For DTS.digitalengineeringlibrary. All rights reserved. ∏2 reference divider.6 GHz.7 GHz.1 Continued Device technology Function Linear Frequency synthesizer Device MC145106 Source Motorola Features Chip contains reference oscillator. and ∏2 reference output. square. triangular.State of the Art of Commercial PLL Integrated Circuits 314 Chapter Ten TABLE 10. . For AM/FM radio. bidirectional Frequency synthesizer.3 GHz. 1. for satellite TV . 3 V . Programming by parallel data input (9 + 1 bits). another reference divider (scaling factor 29 or 210). Linear Linear Frequency synthesizer and down-converter Frequency synthesizer. and 9-bit programmable divide-by-N counter. bidirectional Frequency synthesizer Frequency synthesizer/ controller Frequency synthesizer. direct Frequency synthesizer Frequency synthesizer Dual. Linear CMOS Linear Linear Linear Linear 2. For tuners. Up to 400 MHz. phase detector. For FM/AM tuner. Downloaded from Digital Engineering Library @ McGraw-Hill (www. Any use is subject to the Terms of Use as given at the website. 2. for TV/VCR tuning systems. SM5133* SM5142A SM5165 SM5166 LV2105V LV2151V LV2153V Linear Frequency synthesizer LV2158V U2781B TH7010 UPB1004GS SP5510* SP5512 SP5611 SP5055 SP5655 TDD1742T LC7185-8750 SP2002 TDA7326 LC72121* LC72131* LC72132* LC72133* LC72134M LC72135M LC72136* LC72137* LC72144M LC72146* LC72191 NJU6104 LC72140 BU2611* BU2614* BU2615* NPC NPC NPC NPC Sanyo Sanyo Sanyo Sanyo TEMIC Thesys NEC Mitel Mitel Mitel Mitel Mitel Philips Sanyo Mitel ST Micro Sanyo Sanyo Sanyo Sanyo Sanyo Sanyo Sanyo Sanyo Sanyo Sanyo Sanyo NJR Sanyo ROHM ROHM ROHM For CB transceiver.com) Copyright © 2004 The McGraw-Hill Companies. for TV tuning systems. or sine wave output. For AM/FM tuners.

125 to 1000 MHz. Linear Linear Linear Frequency synthesizer Frequency synthesizer Frequency synthesizer For TV/VCR tuners. 1. 2. All rights reserved. Fractional N. dual. Programmable reference divider (scaling factor 8/64/128/256/ 640/1000/1024/2048). Fractional N. Linear Linear Linear Linear Linear Linear ECL Linear 4xxx Frequency synthesizer Frequency synthesizer Frequency synthesizer Frequency synthesizer Frequency synthesizer Frequency synthesizer Frequency synthesizer Frequency synthesizer Frequency synthesizer 20 to 200 MHz. For TV/VCR tuners. 1 GHz. Digital programming of A and N by serial input signal (10 + 7 bits). triple channel. 1. Fractional N. Serial input.5 GHz.25 to 510 MHz.digitalengineeringlibrary. 1. with dc-dc converter.1 Continued Device technology Function Device BU2616F BU2618FV Source ROHM ROHM Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi Mitsubishi TI Philips Philips Philips Philips Philips Philips Philips Philips Mitel Mitel Mitel NPC IntCirSys Micrel Micrel Motorola Fujitsu Motorola Features Linear Linear Frequency synthesizer Frequency synthesizer M64895 M54937 M54938 M54939 M56768 M56769 M56770 M56771 M56773 M56776 M64092 M64093 M64892 M64893 M64894 M64897GP M64898GP TRF2040 SA7026 SA8016 SA8026 SA7015 SA7025 SA7016 SA8025* SA8015 NJ88C33 SP5658* SP5659 SM5160* MK1711-01 SY89429V SY89430V MC12181 MB87094 MC145156-2 For TV/VCR tuners. Fractional N. I2C-bus.3 GHz. dual. Any use is subject to the Terms of Use as given at the website. 2. Fractional N. Fractional N.8 GHz. serial input. . Downloaded from Digital Engineering Library @ McGraw-Hill (www.State of the Art of Commercial PLL Integrated Circuits State of the Art of Commercial PLL Integrated Circuits 315 TABLE 10.com) Copyright © 2004 The McGraw-Hill Companies. Low phase noise.3 GHz. 50 to 950 MHz. I2C-bus.7 GHz. 31. Fractional-N/integer-N operation. programmable ∏N counter (3 to 1023) and programmable ∏A counter (0 to 127). Uses external 2-modulus prescaler. 2 GHz.

and 14-bit programmable divide-by-N counter. in-lock detector. For mobile phones. Linear Linear 4xxx Frequency synthesizer Frequency synthesizer Frequency synthesizer With 3-line bus.5 GHz. Linear Linear Frequency synthesizer Frequency synthesizer Dual PLL. Dual. oscillator.4 GHz. programmable ∏A counter.2 GHz. Programming by serial data input. 2. 60 MHz. Dual. 1. up to 2.5 GHz. up to 2. with DACs and voltage multipliers. With power-saving function. uses external 2-modulus prescaler. with analog phase detector. 1. 1. All rights reserved. 2 GHz/280 MHz.1 Continued Device technology Function Device MC145157-2 Source Motorola Features Chip contains reference oscillator.State of the Art of Commercial PLL Integrated Circuits 316 Chapter Ten TABLE 10. for cordless phones. MC145158-2 Motorola Linear PLL0305* PLL2001 SM5158A Frequency synthesizer Frequency synthesizer Frequency synthesizer MC14159-1 UMA1014 SP8861 SP8853* SP8858 SP8855D SP8855E MB87093A MB87095A MB87096A MC145170 MC145170-1 MC145170-2 TBB206 UMA1005T ST7162 MC145162 MC145162-1 MC145165 MC145166 MC145167 MC145168 MC145169 BU2630* UMA1021* UMA1022M UMA1020M MC145225 MC145230 NPC NPC NPC Motorola Philips Mitel Mitel Mitel Mitel Mitel Fujitsu Fujitsu Fujitsu Motorola Motorola Motorola Inﬁneon Philips ST Micro Motorola Motorola Motorola Motorola Motorola Motorola Motorola ROHM Philips Philips Philips Motorola Motorola Serial input. 4xxx Frequency synthesizer Downloaded from Digital Engineering Library @ McGraw-Hill (www.7 GHz. 10-bit programmable ∏N counter.3 GHz.3/1. 14-bit programmable reference divider. Any use is subject to the Terms of Use as given at the website. Programming by serial signal.digitalengineeringlibrary. 1.7 GHz. Dual. Dual. 4xxx Linear Linear Linear Frequency synthesizer 4xxx Frequency synthesizer With serial interface. . Dual.com) Copyright © 2004 The McGraw-Hill Companies. in-lock detector. Programmable reference divider (scaling factor 3 to 16384). 2 phase detectors. PFD.

1. Dual.1 GHz. 2 GHz/510 MHz. 1. 1. ETACS.5 GHz/510 MHz.1 Continued Device technology Function 4xxx Linear Linear Linear ECL Linear Frequency synthesizer Frequency synthesizer Frequency synthesizer Frequency synthesizer Frequency synthesizer Frequency synthesizer Device MC145149 WB1315 M64074 LMX2335* MC12302 PE3282 LMX2332* PE3292 UMA1018M LMX2336* LMX2331* MC12306 MC12310 LMX2330* HFA3524 S4503 UMA1015* NJ88C50 M54958 LMX2337 ICS9502 TH7023 Source Motorola IC Works Mitsubishi National Motorola Peregrine National Peregrine Philips National National Motorola Motorola National Intersil AMCC Philips Mitel Mitsubishi National IntCirSys Thesys Motorola Micrel Mitel Motorola National National Motorola Motorola Philips Philips Philips Philips Mitel Philips Philips Philips Philips Philips Philips Mitel Mitel Features Dual. Dual band with ADC/frequency counter. 2.1 GHz. Dual. Dual. with 5-V phase detector. Any use is subject to the Terms of Use as given at the website. 400 MHz. for TV/VCR tuning systems.State of the Art of Commercial PLL Integrated Circuits State of the Art of Commercial PLL Integrated Circuits 317 TABLE 10. Dual. 1. 125 MHz (AMPS.5 GHz/600 MHz. Dual. Dual 1 GHz. I2C-bus. Dual. 1. . 1 GHz. Dual. 1. 4xxx Linear 4xxx Linear 4xxx Linear Frequency synthesizer Frequency synthesizer Frequency synthesizer Frequency synthesizer Frequency synthesizer Frequency synthesizer MC145173 SY89424V SP5026 MC145192 LMX1501A LMX9301 MC145190 MC145191 TSA5511 TSA5512 TSA5514 TSA5515T SP5024 TSA5520 TSA5521 TSA5526* TSA5527* TSA5522 TSA5523M SP8852D SP8854D Frequency synthesizer 1. Dual.4 GHz.5 GHz/500 MHz.1 GHz. Dual. Dual.0 GHz/500 MHz. Dual. Frequency synthesizer Frequency synthesizer Frequency synthesizer 1.1 GHz.1 GHz.digitalengineeringlibrary.3 GHz. Dual. 1 GHz. for TV tuning systems.2 GHz/510 MHz. All rights reserved. with serial interface. for TV/VCR tuning systems.1 GHz/510 MHz.1 GHz/1. Dual. 900 MHz/500 MHz.4 GHz. 1200 MHz/520 MHz.5-GHz prescalers. Dual. with 2. 550 MHz/550 MHz. 50 to 1100 MHz.7 GHz.25 GHz. 1.com) Copyright © 2004 The McGraw-Hill Companies. DECT). for TV/VCR tuning systems. Dual. 1. Downloaded from Digital Engineering Library @ McGraw-Hill (www.1 GHz.1 GHz/500 MHz. 2. Dual. ECL Linear Frequency synthesizer Frequency synthesizer Dual.3 GHz. Dual. 2. 2 GHz/1. 2. 1. with PFD and prescaler. 1. 1. Dual. with prescaler. 1. Dual.1 GHz. 1. 10 to 300 MHz.2 GHz/550 MHz. 1.

2. for satellite receivers. Any use is subject to the Terms of Use as given at the website.1 Continued Device technology Function Frequency synthesizer 4xxx Linear Frequency synthesizer Frequency synthesizer Device Q3236 CXA1787 MC145200 SP5070 SP5054 SP8852E SP8854E M64896 SP5657 SP5668 SP5654 SP5502 SP5511* MC145145-2 Source Qualcomm Sony Motorola Mitel Mitel Mitel Mitel Mitsubishi Mitel Mitel Mitel Mitel Mitel Motorola Features 2 GHz. 550 MHz. 2 GHz. for RF communications. Programmable reference divider (∏3 to 4096). 4xxx Frequency synthesizer MC145146-2 Linear Frequency synthesizer PCK604 SC11346 AD809 LMX2301 SY89429A M56760 LMX2305 M64080 LC72130 4002Y-A MC12002 IMI4345 12540 MCH12140 MCK12140 MC12040 MB1501H mPC1820 OnChipSys Int.7 GHz. programmable ∏A counter (for external 2-modulus prescaler).7 GHz. 2 phase detectors. for satellite TV . for mobile phones. 2. 410 MHz. All rights reserved.to 9. 155. Downloaded from Digital Engineering Library @ McGraw-Hill (www.52 MHz. 160 MHz. 2. Chip contains reference oscillator.6 GHz. 2. ∏64/65 or ∏128/129.State of the Art of Commercial PLL Integrated Circuits 318 Chapter Ten TABLE 10. .7 GHz. 400 to 800 MHz. oscillator. PFD. programmable ∏N counter.com) Copyright © 2004 The McGraw-Hill Companies.7 GHz.3 GHz. 3-wire bus. Double balanced. analog mixer. and data latches for parameter storage. 500 MHz. 4-bit address. for satellite TV tuning systems. 14-bit programmable divide-by-N counter. 1. for TV/VCR tuning systems.digitalengineeringlibrary. For FM/AM tuner. for TV/VCR tuning systems.4 GHz. 4-bit data bus input. in-lock detector. 50 to 600 MHz. 2. Internal PLL and comparator. for RF communications.5-V phase detector. 12-bit programmable reference divider. 4-bit address.3 GHz. 2 GHz with 8. 4-bit data bus input. Frequency synthesizer Frequency synthesizer 2. 2-modulus. 1. in-lock detector. Semi AD National Micrel Mitsubishi National Mitsubishi Sanyo NCM Motorola IMI Lansdale Motorola Motorola Motorola Fujitsu NEC Linear ECL 4xxx ECL Intercarrier modulator Mixer Phase detector Phase-frequency detector Linear PLL with prescaler PIF processor/PLL 1. 80 MHz.1-GHz prescaler.

FSK. Pentium applications.digitalengineeringlibrary. 155 MHz. etc.1 Continued Device technology Function Linear PLL Device NE565 SE565 XR215* XR2212* SL652 Source Philips Features Frequency range 0 to 500 kHz. PSK modulator/demodulator. Programmable. Any use is subject to the Terms of Use as given at the website. LC7150 LC7152 Linear Linear Linear PLL and prescaler PLL-based zero delay buffer PLL clock driver MB1503 MPC961* MC88LV930 MC88LV950 MC88LV970 CDC2509* CDC2510* CDC2516 CDC509 CDC516 MPC932 MC88PL117 SN54CDC586 AD800 AD800-45 AD800-52 AD800-155 AD803 UC1637 UC2637 UC3637 LMC568 LC7218 LM7001 Sanyo Sanyo Fujitsu Motorola Motorola Motorola Motorola TI TI TI TI TI Motorola Motorola TI AD AD AD AD AD Unitrode Unitrode Unitrode National Sanyo Sanyo FM/FSK demodulator. Exar Exar Mitel LPLL having 4 timing current inputs and 2 binary control inputs for switching of timing currents.State of the Art of Commercial PLL Integrated Circuits State of the Art of Commercial PLL Integrated Circuits 319 TABLE 10. Frequency range to 50 MHz. 52 MHz. Linear PLL clock driver PLL clock recovery and data retiming Linear PLL controller for DC motor drive PLL demodulator PLL for radio receiver PLL for radio receiver Linear CMOS NMOS Downloaded from Digital Engineering Library @ McGraw-Hill (www. 45 MHz. Power PC 601.com) Copyright © 2004 The McGraw-Hill Companies. Frequency range 0–500 kHz. 30 Mbps. MN6152 MN6153 MN6155 NE564 SE564 Panasonic Panasonic Panasonic Philips Philips Postdetection processor and limiting circuit at the input of the PD integrated on chip. . 3 state outputs. 1 GHz. All rights reserved. VCO has parallel square and triangular wave outputs. Main application is FM.

Downloaded from Digital Engineering Library @ McGraw-Hill (www. high speed. clock chip Two independent serial input PLL frequency synthesizers equivalent to two IMI145157’s on one chip. but is intended to drive two-phase brushless motors. UC1634 UC1635 UC2633 UC2634 UC2635 UC3633 UC3634 UC3635 Linear Frequency synthesizer MB1503/13 HPLL8001 PMB2307R TBB200 SM5162 SM5168 SM5170A IMISC434 IMISC464 IMISC465 IMISC466 IMISC468 IMISC470 IMISC471 IMI2XFSUT157 Unitrode Unitrode Unitrode Unitrode Unitrode Unitrode Unitrode Unitrode Fujitsu HP Inﬁneon Inﬁneon NPC NPC NPC IMI IMI IMI IMI IMI IMI IMI IMI Linear Frequency synthesizer. Serial input. Linear Frequency synthesizer MK1574-01* TDA8735* MK2049-01 SM5160 ILC1080 MB15C101 MB15C103 IMI4347 PMB2306 IntCirSys Philips IntCirSys NPC Impala Linear Fujitsu Fujitsu IMI Inﬁneon Motorola Motorola Motorola Motorola Motorola NPC Hyundai Fujitsu ECL Frequency synthesizer MC12179 MC12202 MC12206 MC12210 MC122179 SM5158 GM6530 MB15E03SL Linear Frequency synthesizer Serial input.State of the Art of Commercial PLL Integrated Circuits 320 Chapter Ten TABLE 10. .com) Copyright © 2004 The McGraw-Hill Companies. E3. E1. T3. High speed. All rights reserved. Input frequency >60 MHz (typical).digitalengineeringlibrary.2-GHz prescaler.1 Continued Device technology Function Linear PLL frequency controller Device UC1633 Source Unitrode Features PLL for motor speed control. High speed. Serial interface. Any use is subject to the Terms of Use as given at the website. Contains sense ampliﬁer for speed feedback signal (from Hall sensor or other speed detector). Serial control. For satellite receivers. For frame rate communications. With 1. 40 to 120 MHz. Similar to UC1633. IF band. Generates T1. Phase detector. and OC3 frequencies.

1. ∏64/65 or ∏128/129. 2 GHz. Fixed-ratio frequency dividing.digitalengineeringlibrary.0 GHz. Any use is subject to the Terms of Use as given at the website. 12bit programmable reference divider.1 Continued Device technology Function Device MB15E05SL MB15E07SL MB15F02SL MB15F03SL MB15F07SL MB15F08SL IMI145145 Source Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu IMI Features Single serial input. ∏64/65 or ∏128/129. 1. Dual serial input.5 GHz. Dual. 2 GHz.com) Copyright © 2004 The McGraw-Hill Companies. Dual. Dual serial input. and data latches for parameter storage. 1.State of the Art of Commercial PLL Integrated Circuits State of the Art of Commercial PLL Integrated Circuits 321 TABLE 10.8 GHz. 0. Dual serial input. Linear PLL PLL + prescaler SM5153 SM162LF1S MB15F02* MB15F03L MB15F05L MB15F03 MB15F04 MB1504* MB1505 MB1507 MB1508 MB1509 MB1519 MB15A01 MB15A02 MB15A16 MB15B01 MB15B03 MB15B11 MB15B13 MB1501 MB1502 MB1502H MB1510 MB1511 MB1512 MB1513 MB1516A WB1332 MB15E03* MB15A19 MB1514 MB1506 MB1517* MB15E05* MB15E06 MB1515 MB1518 NPC NPC Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu IC Works Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu 1 GHz. Downloaded from Digital Engineering Library @ McGraw-Hill (www. 2. 2.5 GHz.2 GHz. ∏64/65 or ∏128/129. 1. ∏64/65 or ∏128/129. Chip contains reference oscillator. ∏64/65 or ∏128/129. 4-bit data bus input.5 GHz. 14-bit programmable divide-by-N counter. All rights reserved.2 GHz. . 2 phase detectors.2 GHz. 1. Dual serial input. in-lock detector. 2 GHz. Dual.

Any use is subject to the Terms of Use as given at the website. Scaling factor N digitally controlled by serial input signal (14 bits). adder. 120 MHz. PLL programmable divider NMOS Linear PLL Frequency synthesizer IMI145157 IMI SAA1057 4xxx Frequency synthesizer IMI145106A IMI145151 Philips IMI IMI MC145151-2 Motorola MC145152-2 Motorola Linear HC0320 IMI145152 Hughes IMI Downloaded from Digital Engineering Library @ McGraw-Hill (www. 2 phase detectors. in-lock detector. PFD. ∏64/65. 6-bit programmable ∏A counter for external 2-modulus prescaler. Programming by serial data input. in-lock detector. Ranges to UHF. All rights reserved. Programmable reference divider (∏8/128/256/512/1024/2048/2410/ 8192) and ∏N divider with scaling factor 3 to 16383. Fully parallel programming. Chip contains reference oscillator.com) Copyright © 2004 The McGraw-Hill Companies. Fully parallel programming. Binary 14-bit counter. and 14-bit programmable divide-by-N counter. phase comparator. Programmable reference divider (scaling factors 8/64/128/256/512/1024/1160/2048). . oscillator. Binary 10-bit counter.1 Continued Device technology Function Device MB15E07* MB15C03 MB15S03 MB15S01 MB15S02 MB87086A MB87087 LM7005 IMI145155 Source Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Sanyo IMI Features 2. Programmable reference divider (scaling factors 64/128/256/512/1024/1160/2048). Programmable reference divider (∏8/128/256/512/1024/2048/2410/ 8192) and ∏N divider with scaling factor 3 to 16383.5 GHz. 14-bit programmable reference divider. 10-bit programmable ∏N counter. Programmable divider.State of the Art of Commercial PLL Integrated Circuits 322 Chapter Ten TABLE 10. ∏32/33 or ∏64/65. ∏N counter with scaling factor of 3 to 16383. Programmable reference divider (scaling factor 16/512/1024/2048/ 3668/4096/6144/8192). Parallel input. in-lock detector. oscillator. ∏16/17. Parallel input (14 bits). 10bit programmable ∏N counter. 178 MHz. ∏16/17. 284 MHz. ∏16/17. 259 MHz. 6-bit programmable ∏A counter for external 2-modulus prescaler. to 1021 channels. Parallel input (14 bits). PFD.digitalengineeringlibrary.

2 GHz. programmable ∏N counter.1 GHz. All rights reserved. Uses external 2-modulus prescaler. in-lock detector. 5 V .1 Continued Device technology Function Device IMI145156* Source IMI Features Programmable reference divider (scaling factor 8/64/128/256/640/ 1000/1024/2048).3-GHz prescaler. universal PLL. 2 channel. ∏64/65 or ∏128/129. 1. in-lock detector. Scaling factor N digitally controlled by serial input signal (14 bits). 1. IMI145158* IMI MC145155-2 Motorola MB87001A IMIFSUT157* IMI145146* Fujitsu IMI IMI PLL tuning circuit PLL. Digital programming of A and N by serial input signal (10 + 7 bits). ∏64/65 or ∏32/33. ∏64/65. 60 MHz.State of the Art of Commercial PLL Integrated Circuits State of the Art of Commercial PLL Integrated Circuits 323 TABLE 10. ∏N counter with scaling factor of 3 to 16383. programmable ∏A counter.1 GHz. 1. oscillator. programmable ∏A counter (for external 2-modulus prescaler).digitalengineeringlibrary. dual PLL + prescaler PLL + prescaler PLL + prescaler MC44818 MC44824 MC44825 MC44826 MC44827* MC44828 MC44829 MC44871 MC44802 MC44864 KS8805B CH9073 AV9173 AV9173-01 MC145220 TEA8805 MC145201 MC145202 MB1501L SM1532* SM1534* Motorola Motorola Motorola Motorola Motorola Motorola Motorola Motorola Motorola Motorola Samsung Chrontel IntCirSys IntCirSys Motorola ST Micro Motorola Motorola Fujitsu NPC NPC 1. uses external 2-modulus prescaler. for TV/VCR.3-GHz prescaler. Programmable reference divider (scaling factor 16/512/1024/2048/ 3668/4096/6144/ 8192). Programming by serial data input. 13 MHz. for cordless phones.3 GHz. Programmable reference divider (∏3 to 4096). oscillator. 3 mA. D/A converters. PFD. 1. 1. Serial input. Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies. . Serial input. Any use is subject to the Terms of Use as given at the website. programmable ∏N counter (3 to 1023) and programmable ∏A counter (0 to 127).3 GHz. dual. ∏8. Programmable reference divider (scaling factor 3 to 16384). 4-bit data input. 10-bit programmable ∏N counter. video dot clock generator 4xxx Linear 4xxx Linear PLL. PFD.

2 GHz. Downloaded from Digital Engineering Library @ McGraw-Hill (www. serial input. . 1. with prescalers PLL + prescaler PWM controller Frequency synthesizer PLL system block Subcarrier PLL Frequency synthesizer Tone decoder Operation to 500 kHz. 2-device set.4 GHz. serial input.digitalengineeringlibrary. 3 mA. 2-GHz/1.1 Continued Device technology Function PLL. 400 MHz. dual. 3. 2. 1250 MHz.7-GHz/510-MHz prescalers. dual PLL + prescaler PLL PLL + prescaler PLL. with prescalers Device WB1310 WB1336 WB1331 WB1330 WB1305 WB1333 MB15U20 U2782 SY89420 SY89423 U2783B U2784B MB87014A SY89421V WB1220 WB1215 WB1337 WB1225 MB3785 MB87091 MB87006A MB87076 MB87086 MC44144 NJ8811 NJ8812 SP8901 SP8906 NE567 Source IC Works IC Works IC Works IC Works IC Works IC Works Fujitsu Temic Micrel Micrel Temic Temic Fujitsu Micrel IC Works IC Works IC Works IC Works Fujitsu Fujitsu Fujitsu Fujitsu Fujitsu Motorola Mitel Mitel Mitel Mitel Philips Features 1. PLL. serial input.1 GHz.5 mA.State of the Art of Commercial PLL Integrated Circuits 324 Chapter Ten TABLE 10. For mobile radio. serial input. Serial input. serial input. ∏64/65 or ∏128/129. 2 GHz. serial input.12 GHz. Serial input. 2. VCO KA567C CEM3340 CEM3345 AN8585 AN8586 AN8587 LC7444 SN74LS624 SN74LS628 LM565C KGF1145 KGF1146 RF2501 RF2502 KGF1191 Samsung OnChipSys OnChipSys Panasonic Panasonic Panasonic Sanyo TI TI National OKI OKI RF Micro RF Micro OKI LS-TTL Linear VCO VCO + phase detector VCO buffer ampliﬁer For ISM cellular.5 GHz. Any use is subject to the Terms of Use as given at the website.2-GHz prescalers. All rights reserved. Has additional quadrature phase detector that can be used as in-lock detector. 1. Serial input. dual. 2200 MHz. 300 MHz to 2. 95 MHz. 2-GHz/510-MHz prescalers. power saving function. 1. serial input. serial input. 3 to 5 V . For video applications.1-GHz prescalers. 3 to 5 V . Serial input. 10 mA. 10 MHz.com) Copyright © 2004 The McGraw-Hill Companies. 3 to 5 V . 15 MHz. 1.12 GHz. 550 MHz. 510-MHz prescalers. 400 MHz.

As SL650.com) Copyright © 2004 The McGraw-Hill Companies. . dual CEM3374 LS-TTL SN74LS625 SN74LS629 SN74LS124 Video dot clock generator Video PLL system Voltage-controlled multivibrator Voltage-controlled oscillator buffer 2-modulus prescaler ICS1394 LM1291 LM1292 MC12101 MC12100 MC12147 SP8643 Linear For continuous-sync monitors. MC14046B. XR2207* XR2207* RC2207 Raytheon Exar Fairchild ECL Linear VCO. triangular. Example: *4046* is delivered as CD4046B.1 Continued Device technology Function VCO function generator Device XR2209* LM566* Source Exar National Features Frequency range 0–1 MHz. Downloaded from Digital Engineering Library @ McGraw-Hill (www. CD4046BC. square. Frequency range 0–500 kHz. Simultaneous square and triangular wave output. All rights reserved. low power PLL MC12148 MC12149 SL650 Motorola Motorola Mitel Multiplier phase detector. Frequency range 0–1 MHz. without op amp. VCO waveform generator SL651 XR2206* XR8038A ICL8038 Mitel Exar Exar Intersil OnChipSys OnChipSys TI TI TI IntCirSys National National Motorola Motorola Motorola Mitel Sine. Any use is subject to the Terms of Use as given at the website. etc. sawtooth. ∏10/11. Simultaneous square and triangular wave output. Four timing resistors can be switched in and out by two binary inputs. no sine.digitalengineeringlibrary. and pulse output. VCO waveform generator. CEM3371 dual VCO. ECL Low power. no sine. Linear Note: Asterisks (*) preceding and/or following a part number mean that this device is registered with different preﬁxes and/or sufﬁxes.State of the Art of Commercial PLL Integrated Circuits State of the Art of Commercial PLL Integrated Circuits 325 TABLE 10. Chip contains additional op-amp.

All rights reserved. Any use is subject to the Terms of Use as given at the website.digitalengineeringlibrary. .com) Copyright © 2004 The McGraw-Hill Companies.State of the Art of Commercial PLL Integrated Circuits Downloaded from Digital Engineering Library @ McGraw-Hill (www.

so the phase detector gain Kd is approximately UB/p for the EXOR. for example.. Kd.com) Copyright © 2004 The McGraw-Hill Companies. because all parameters of the circuit are multipliers for clock frequencies and divider ratios of counters. wn. The situation is different in the case of LPLLs. the phase detector gain depends on the level of the reference signal. UB/2p for the JK-ﬂipﬂop. z. For the following measurements a multifunction integrated circuit of type XR-S200 (EXAR) has been arbitrarily selected as the device under test (DUT). Many LPLL ICs have a large supply voltage range. .1). All rights reserved. The center frequency is now easily mea327 Downloaded from Digital Engineering Library @ McGraw-Hill (www. Furthermore.digitalengineeringlibrary. Consequently the VCO will oscillate at the center frequency f0. Moreover.1 Measurement of Center Frequency f0 Only the VCO portion of the DUT is used for this measurement (Fig. nothing has to be measured. depends uniquely on the supply voltage in most cases.Source: Phase-Locked Loops Chapter 11 Measuring PLL Parameters This chapter deals with the measurement of PLL parameters. so there is sufﬁcient information to calculate the values of the external components of the DPLL system. and many others are easily measured with the standard equipment available even in a hobbyist’s lab.e. the parameters are normally well speciﬁed in the data sheets. For a DPLL built from CMOS technology. an oscilloscope and a waveform generator. Any use is subject to the Terms of Use as given at the website. and UB/4p for the PFD. and some of the PLL parameters can vary with it. 11.1). the VCO characteristics are well speciﬁed on the data sheets of the 4046 and the 7046 ICs (refer to Table 10. The phase detector gain. It will be shown in this section that the relevant parameters such as K0. It is therefore advantageous if the users are able to measure these parameters themselves. where some parameters are poorly speciﬁed for some products. When an ADPLL is used. The two pins of the symmetrical VCO input are grounded. i. In the case of the DPLL. 11. the levels of the phase detector output signal come close to the supply rails.

1) can be used to measure the VCO gain K0.54 kHz. Any use is subject to the Terms of Use as given at the website. . All rights reserved.2 kW are chosen for the external components. (b) measurement of K0. One of the VCO inputs (VCO in) stays grounded. the VCO frequency falls to 5. which corresponds to a variation of 0. As shown in Fig.1 Test circuit for the measurement of the center frequency w0 and the VCO gain K0. By deﬁnition the VCO gain K0 is equal to the variation of VCO angular frequency Dw0 related to a variation of the uf signal by Duf = 1 V . If the values Cext = 82 nF and R0 = 2.Measuring PLL Parameters 328 Chapter Eleven sured with an oscilloscope (Fig.78 kHz for Duf = 1 V .digitalengineeringlibrary. This signal corresponds to the loop ﬁlter output signal uf.com) Copyright © 2004 The McGraw-Hill Companies. uf = 0 V. 11. Downloaded from Digital Engineering Library @ McGraw-Hill (www. 11. the VCO oscillates at a center frequency f0 of 6. The sign of the frequency variation is irrelevant here.2a).2 Measurement of VCO Gain K0 The same test circuit (Fig. a variable dc voltage is applied to the other.2 (a) Measurement of w0. For the VCO gain K0 we now obtain Cext 19 23 VCO in 24 17 VCO gain 18 20 VCO out to Oscilloscope (Counter) 10 k Figure 11. it would have been positive if the VCO input pins had been connected with inverted polarity.2 k Ro VCO out uf = 0 uf = 0 Figure 11.76 kHz. 11.2b. VCO out 2. uf = 1 V . 11.

The measurement procedure is explained by the waveforms in Fig. Hence.2 k Ro 10 k ground 6 Figure 11.4a the signal applied to phase detector input 1 (PD in #1) is a sine wave.3 is used for the measurement of Kd. K0 is given by the general equation K 0 = 0.3 Test circuit for the measurement of phase detector gain Kd .73 f0 rad s -1 V -1 (11.gain DC-LEVEL 7 5 10 11 RY = 0 Y. for this device.1) where f0 is in hertz.78 ◊ 103 rad s -1 V -1 Duf 1 The test shows furthermore that K0 would be larger by a factor of 10 if w0 had been chosen larger by a factor of 10.Measuring PLL Parameters Measuring PLL Parameters 329 K0 = Dw 0 2 p ◊ 0.com) Copyright © 2004 The McGraw-Hill Companies.3 Measurement of Phase Detector Gain Kd The test circuit of Fig. 11. All rights reserved. the PD and the VCO are used. we ﬁnd K0 = 730 rad s-1 V-1.2 kW is chosen. For example. and the signal applied to phase detector input 2 (PD in #2) is a square wave (usually the VCO output signal).gain 8 9 3 PD out 4 to Oscilloscope PD in 19 Cext 20 VCO in 23 24 21 VCO out 0. K0 varies in proportion to w0. When R0 = 2. 11.1 m 17 18 VCO gain 2. A variable dc level is applied to the other input. 11. The PD of the XR-S200 is realized in form of an operational multiplier. 11.digitalengineeringlibrary. In the conﬁguration shown. The VCO output signal is coupled capacitively to one of the PD inputs. . In Fig. Any use is subject to the Terms of Use as given at the website. for f0 = 1 kHz.4.76 ◊ 103 = = 4. Downloaded from Digital Engineering Library @ McGraw-Hill (www. It is furthermore assumed that RX = 0 X.

and the signal level is usually given as an rms value. (b) For a dc level. If a dc voltage is applied to PD in #1. this PD has a symmetrical output. Downloaded from Digital Engineering Library @ McGraw-Hill (www. 20. Any use is subject to the Terms of Use as given at the website.5. 11. both signals are in phase. 40. its average value is given by ud = K d sin 90∞= K d i. 11. and the bottom trace multiplier output 2 (MUL OUT 2).] Consequently. we have to apply a dc level of 1/1. As Fig. All rights reserved.4 Waveforms of the phase detector output signal ud for different signals applied to input 1. the rms value is 1 2 .3 was measured at four different levels of the reference signal: at 10.digitalengineeringlibrary. 30.e. a sine signal is usually chosen for the reference signal.4b we see that the rms value of the sine signal is 1. and 100 mV rms. Three signals are displayed in each oscillogram: the top trace shows multiplier output 1 (MUL OUT 1). . Consequently the phase error qe is 90°. the output signal of the phase detector becomes a square wave having a peak amplitude Kd.11 times its average value. 11. (a) For a sine-wave signal. Kd is speciﬁed as a function of the reference signal level. and the average value (linear average) is 2/p.11 Ϸ 0. to measure Kd for a reference signal level of 1 V rms. the measured output signal is identical with Kd.3 demonstrates. 11. respectively. The phase detector gain of the DUT in Fig. In most data sheets. whose level is equal to the average value of the previously applied sine signal. The four oscillograms show the results for u1 = 10. The phase detector output signal (PD out) is a full-wave rectiﬁed sine signal. The measured signals are displayed in Fig.9 V to PD in #1 and then simply measure the peak value of the output signal. [For a sine signal of peak amplitude 1. 30..Measuring PLL Parameters 330 Chapter Eleven a b PD in ն 1 (Pin 7) DC . and 40 mV rms. the center trace the reference signal (dc). In Fig.com) Copyright © 2004 The McGraw-Hill Companies.Level PD in ն 2 (Pin 5) PD out (Pin 3 or 4) Kd +Kd –Kd Figure 11.

11.6. 11. a full PLL circuit must be built. .com) Copyright © 2004 The McGraw-Hill Companies. All rights reserved. (b) 30 mV . (c) 40 mV . as indicated in Fig. the phase detector gain is twice the measured peak amplitude of the square wave.Measuring PLL Parameters Measuring PLL Parameters 331 0V 0V (a) (b) 0V 0V (c) Figure 11. Any use is subject to the Terms of Use as given at the website. Because the output of the PD is a symmetrical signal.4. This is easily done by adding a loop ﬁlter to the test circuit of Fig. This means that the PD output signal (shown in the bottom trace of Fig. 11. 11.5 (d) Waveforms measured with the test circuit of Fig. The phase detector gain is then the amplitude of the square wave measured from the centerline.3 and by closing the Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary. 11.4 Measurement of Hold Range DwH and Pull-in Range DwP To measure these parameters. The measured Kd values are plotted against the reference signal level in Fig. (d) 100 mV .3 for different dc levels applied to input 1. It is clearly observed that the PD becomes saturated at signal levels above 400 mV rms. (a) 10 mV .4) must be measured differentially between pins 3 and 4. 11.

loop.) A signal generator is applied to the reference input (pin 7) of the DUT.6 Plot of Kd against input voltage level in millivolts rms. 11.8). 11. . The PLL is trying to pull in the VCO. and the external capacitor C. All rights reserved. the PLL suddenly locks (Fig.Measuring PLL Parameters 332 Chapter Eleven 1 2 4 6 8 101 2 4 6 8 102 2 4 6 8 103 2 4 6 8 104 2 4 6 8 105 104 8 6 4 2 103 8 6 4 2 102 8 6 4 2 Kd (V/rad) 5 4 3 2 1 0. Downloaded from Digital Engineering Library @ McGraw-Hill (www. The frequency of the signal generator is now varied manually until lock-in is observed (Fig. hence we have N = 1 (N = scaling factor).8a the reference frequency f1 is far away from the center frequency f0 and the system is unlocked. In the case of Fig. Both reference signal u1 and VCO output signal u2 are displayed versus time on an oscilloscope. The oscilloscope is triggered on u2. 11.com) Copyright © 2004 The McGraw-Hill Companies. This PLL does not use a down-scaler. 2.8b shows the situation where f1 has come closer to the center frequency. The new test circuit of Fig.01 1mV 10mV 100mV 1V u1 (mVrms) 1 Figure 11.7 is then obtained.16) is chosen for simplicity.1 101 8 6 4 2 0. Figure 11. it consists of two on-chip resistors. (Note that resistor R2 is set 0 here.8c). 11. If the reference frequency approaches f0 slightly more.digitalengineeringlibrary. Any use is subject to the Terms of Use as given at the website. Frequency modulation of u2 is easily observable. although this is a bad choice for loop stability. A passive loop ﬁlter (Fig. R1 = 6 kW each.

8 Waveforms of signals u1 and u2 in the test circuit of Fig. .1 m 10 k Y1 to Oscilloscope Y2 Figure 11. 11. All rights reserved.7 Test circuit for the measurement of hold range DwH and pull-in range DwP. (a) PLL unlocked. Any use is subject to the Terms of Use as given at the website. Downloaded from Digital Engineering Library @ McGraw-Hill (www.com) Copyright © 2004 The McGraw-Hill Companies. (c) PLL locked. u2 u2 u1 u1 (a) (b) u2 u1 (c) Figure 11.Measuring PLL Parameters Measuring PLL Parameters 333 RX = 0 X-Gain RY = 0 Y-Gain 10 11 Signal Generator u1 f1 u2 PD in 7 5 8 6k 6k 9 R1 3 PD out Loop Filter C 20 n R1 4 19 Cext 8.2 n 20 VCO in 23 24 21 VCO out 0.digitalengineeringlibrary.7. (b) PLL near locking.

The difference between the value of f1 and the center frequency f0 is the pull-in range DfP. we must reduce the reference frequency slowly and monitor the value of f1 where the loop pulls in.com) Copyright © 2004 The McGraw-Hill Companies. Thus the transient response of the PLL can be easily analyzed by recording on an oscilloscope.Measuring PLL Parameters 334 Chapter Eleven Determination of the hold range DfH and the pull-in range DfP is very simple.9 factor z. To measure the natural frequency wn and the damping factor z of a PLL.digitalengineeringlibrary. top trace). which displays the signals u1 (reference signal. Any use is subject to the Terms of Use as given at the website. All rights reserved.5 Measurement of Natural Frequency wn . .7 is used for the following measurements. Because the reference signal has a much higher frequency than the 1-kHz square wave and is by no means synchronized with the latter.10a. u1 square wave generator FM input out u1 PD ud LF uf ª1 kHz signal generator ª70 kHz to oscilloscope VCO uz Figure 11. The hold range is measured by slowly varying the reference frequency f1 and monitoring the upper and lower values of f1 where the system unlocks. This is most easily done by modulating the reference frequency with a square wave signal. The output signal uf of the loop ﬁlter can be considered a measure of the average phase error. we apply a disturbance to the PLL that forces the system to settle at a different stable state. If the frequency of the signal generator is abruptly changed. 11. and the 1-kHz square wave (bottom trace). The pull-in range DfP is determined in a similar way. 1 kHz. a phase error qe results. uf (center trace). The PLL under test operates at a center frequency of approximately 70 kHz. The corresponding test circuit is shown in Fig. Test circuit for the measurement of natural frequency wn and damping Downloaded from Digital Engineering Library @ McGraw-Hill (www. it is displayed as a bar only. The oscilloscope is triggered on the 1-kHz square wave. Of course.9. To get DfP. 11. the modulating frequency must be chosen much smaller than the center frequency. To see where the loop pulls in again. 11. The frequency of the signal generator is modulated by a square wave generator. we ﬁrst set the reference frequency f1 to approximately the center frequency f0 and then increase f1 slowly until the loop locks out. and Lock Range DwL The PLL circuit of Fig. Damping Factor z. 11. for example. This is shown by the waveforms in Fig.

The uf signal performs a damped oscillation on every transient of the 1-kHz square wave and settles at a stable level thereafter. For A1 and A2 we read approximately 1. 11. center trace.0 ◊103 rad s -1 or fn ª 4. Hence wn is w n ª 26. center trace—output signal of the loop ﬁlter. All rights reserved.) The damping factor is given by z= ln( A1 A2 ) [p 2 + {ln( A1 A2 )} 2 ] 12 The natural frequency wn is calculated from the period T of one oscillation in Fig. (b) Enlarged view of the uf waveform shown in (a).Measuring PLL Parameters Measuring PLL Parameters 335 A1 A2 (a) Figure 11.com) Copyright © 2004 The McGraw-Hill Companies.1 kHz Downloaded from Digital Engineering Library @ McGraw-Hill (www. z can be calculated from the ratio of the amplitudes of two subsequent halfwaves A1 and A2.digitalengineeringlibrary.10 T (b) Waveforms of the test circuit shown in Fig. respectively. Now wn and z can be calculated from the waveform of uf. (a) Top trace—input signal u1.08 For T we ﬁnd T Ϸ 240 ms.9 and 1. .5 divisions.10b is an enlarged view of this signal. Figure 11. 1-kHz square wave. 11.z2 Let us now evaluate numerically the waveform of Fig. Consequently we obtain z ª 0. 11.9. (Any pair of subsequent half-waves may be chosen.10b according to wn = 2p T 1 .10b. bottom trace—modulating signal. Any use is subject to the Terms of Use as given at the website.

we obtain for the VCO gain K 0 = 0. 11. t2 should be chosen > 0. i. The higher of the two frequencies (whigh) generated by the signal generator must now be chosen higher than the pull-out frequency.41)] and check whether our measurements agree with the predicted results. though not so easy.1). Using Eq. 11. however.10a the amplitude of the reference signal is about 120 mV peak to peak.) This agrees well with the experimental measurements.10a.Measuring PLL Parameters 336 Chapter Eleven To complete this measurement. Note that this experimental method of measuring wn and z is applicable only for z < 1. An underdamped system is often obtained when a loop ﬁlter without a zero is chosen. (11. This requirement is met. in most cases. 11.41). . but that wlow decreases when the square wave amplitude is made larger. Assume that the radian center frequency of the PLL under test is w0. During the interval where the frequency of the signal generator is high.10a. In this situation the amplitude of the square wave generator will be zero. which corresponds to an rms value of 43 mV .5 ◊10 3 rad s -1 V -1 According to Fig.7: t 1 = 12 kW ◊ 20 nF = 240 ms t2 = 0 Using Eq.digitalengineeringlibrary.6. (2. the transient response would become aperiodic. It can be done using the setup shown in Fig. Measurement of the lock range DwL is possible. All rights reserved. 11. which is visible only as a smeared trace. let us calculate the values of wn and z using the theory of the linear PLL [Eq.9.7 51. In the example of Fig.e. 11. The signal generator is still frequency-modulated by the square wave generator as shown. uf will be a “high-frequency” signal. (2. If z were greater than 1. When Downloaded from Digital Engineering Library @ McGraw-Hill (www. whigh > w0 + DwP. 11.7 V/rad from Fig. The two time constants t1 and t2 can be derived from the test circuit in Fig. 11.com) Copyright © 2004 The McGraw-Hill Companies. To increase z. and it would become impossible to deﬁne the values A1 and A2 in Fig. The test circuit must now be tuned such that whigh stays always the same. we ﬁnally get K0 K d ˆ wn = Ê Ë N (t 1 + t 2 ) ¯ z= 12 =Ê Ë N ˆ wn Ê t2 + = = 0. Any use is subject to the Terms of Use as given at the website. which was built to measure the natural frequency and damping factor.7 ˆ 240 ◊10 -6 ¯ 28 ◊103 12 = 28 ◊103 rad s -1 (Note: N = 1. The square wave amplitude is now continually increased while watching the uf signal with the scope as shown in Fig. For this signal level we read a phase detector gain Kd Ϸ 3.07 Ë 2 K 0 K d ¯ 2 ◊ 51.1 ◊103 ◊ 3.10a the damping factor z has purposely been chosen too small in order to get a marked oscillatory transient. The lower frequency (wlow) has to be chosen initially to be as high as the higher (wlow = whigh).73 ◊70 ◊103 = 51.1 ◊103 ◊ 3..

qe < p/4) so the PD never operates in its nonlinear region. Any use is subject to the Terms of Use as given at the website.w0. 11.4) FM Signal Sine Generator wm FM input out PD LF uf ~ H(jw) Signal Generator to Oscilloscope or Spectrum Analyzer VCO Figure 11.3) The amplitude of the reference phase signal q1(t) is therefore Q1 (w m ) = Dw wm (11.49 The PM technique has the advantage that the maximum phase error qe can be limited to small values (e. most signal generators used in the lab can be frequency-modulated but not phase-modulated. The frequency of the signal generator is tuned to the center frequency of the PLL.6 Measurement of the Phase-Transfer Function H(w) and the 3-dB Bandwidth w3dB There are different methods of measuring H(w). All rights reserved. the PLL will lock quickly.digitalengineeringlibrary. The test setup is shown in Fig. Unfortunately. The size of Dw will be determined later. a pull-in process will be observed: the uf signal also settles to some ﬁnite value.2) where wm is the modulating frequency and Dw is the peak frequency deviation. For larger values of wlow. The lock range DwL is now given by the difference wlow .com) Copyright © 2004 The McGraw-Hill Companies.Measuring PLL Parameters Measuring PLL Parameters 337 the lower frequency reaches a value around wlow Ϸ w0 + DwL.35. Downloaded from Digital Engineering Library @ McGraw-Hill (www.g. we have q1 (t) = Dw cos w m t wm (11.. Because the phase q1(t) of the reference signal is equal to the integral of the frequency deviation Dw sin(wm t) over time. i. the uf signal will settle to a stable value within at most one cycle (oscillation). therefore.e. Consequently. others use frequency modulation. A sine wave is applied now to the FM input..11 Test circuit for the measurement of H(w). the output signal of the generator is given by w 1 = w 0 + Dw sin w m t (11. some of these use PM techniques. we use FM techniques. . but shows up more than one cycle. To enable the measurement of H(w).11. 11.

All rights reserved. 0 to 10 kHz.12a).Measuring PLL Parameters 338 Chapter Eleven From the deﬁnition of the phase-transfer function. as shown in Fig. the peak phase deviation of the reference signal is proportional to Dw. As Eq. If the uf waveform stays undistorted at its peak amplitude. What is still unknown is the peak frequency deviation Dw. the peak frequency deviation Df is adequate (refer to Fig. If such a distorted waveform is observed.digitalengineeringlibrary. 11.34).4) into Eq. If too large a peak frequency deviation has been selected.com) Copyright © 2004 The McGraw-Hill Companies. The phase-transfer function can now be measured by plotting the amplitude of the signal against the modulating frequency wm. say. but can also be automated by means of a spectrum analyzer. . the gain of the VCO at frequency w = wm is Q 2 (w m ) K0 = ( ) Uf wm jw m For the amplitude of the signal uf we obtain therefore U f (w m ) = jw m H (w m )Q1 (w m ) K0 (11. we monitor the uf waveform on an oscilloscope and manually sweep the modulating frequency fm from 0 to. (11. 10 kHz. the uf waveform ˆe has bebecomes distorted.6) (11. (11. To check whether the initially chosen peak frequency deviation Dw is adequate. This measurement can be done manually. a resonance peak is observed on the scope. because H(w) = 1 for small frequencies wm.7) (11. In this case the modulating frequency wm must be generated by a sweep generator.8) This indicates that the phase-transfer function is very easily obtained just by measuring the amplitude of the uf signal at different modulating frequencies wm.5) Inserting Eq. Any use is subject to the Terms of Use as given at the website. the peak frequency deviation simply must be reduced. If the phase-transfer function H(w) has to be recorded within a range of modulating frequencies of. If fm comes close to the natural frequency fn. a sweep range of 10 kHz has to be Downloaded from Digital Engineering Library @ McGraw-Hill (www. (11. 11.4) says. say.12b. As long as the peak phase deviation is small enough.7) we ﬁnally get H (w m ) = U f (w m ) K 0 Dw (11. (2. This indicates that q come so large that the phase detector now operates near saturation. the amplitude Q2(wm) of the phase signal q2(t) is given by Q 2 (w m ) = H (w m )Q1 (w m ) According to Eq. The absolute level of uf is unimportant. the PD operates within its linear range and the signal uf is an undistorted sine wave.

14a is the “correct” measurement.08 was purposely chosen for this measurement. (a) The peak frequency deviation of the FM is chosen low enough to enable linear operation of the PD.14.13. a spectral resolution of 300 Hz has been chosen. In this example. 11. The left half of the spectrum covers the range of negative frequencies from 0 to -10 kHz and can be discarded here. (b) The peak frequency deviation is too large. the chosen sweep rate of the sweep generator should be much slower than the sweep rate of the spectrum analyzer. A large resonance peak is therefore observed at the natural frequency Downloaded from Digital Engineering Library @ McGraw-Hill (www. which indicates the origin of the frequency scale. Figure 11. The phase-transfer function H(w) of the PLL is shown in Fig.Measuring PLL Parameters Measuring PLL Parameters 339 (a) Figure 11. The sweep rate of the spectrum analyzer depends on the speciﬁed spectral resolution. the peak frequency deviation was chosen small enough to avoid nonlinear operation of the PD. 11. 11. Any use is subject to the Terms of Use as given at the website. the modulating frequency fm should stay quasistationary during one sweep period of the spectrum analyzer. the sweep rate has to be chosen differently for each instrument. A low damping factor of z = 0. The phase-transfer function H(w) recorded with this technique is shown in Fig.11. The spectrum analyzer then scans the frequency spectrum from 0 to 10 kHz once every second (Fig. speciﬁed for both the spectrum analyzer and the sweep generator. as shown in Fig.digitalengineeringlibrary. As an alternative. To avoid intermodulation between spectrum analyzer and sweep generator. In our example the sweep generator scans through the frequency range from 0 to 10 kHz within 100 s.13). because the spectrum of 0 to 10 kHz is scanned in a time interval of 100 s. . 11. 11. All rights reserved. The PD is operating in its nonlinear region. Consequently. The frequency scale is symmetrical with respect to the marker.12 (b) Output signal of the loop ﬁlter uf measured by the test circuit of Fig.com) Copyright © 2004 The McGraw-Hill Companies. the shutter of the camera had to remain open for 100 s. However. the spectrum could have been recorded ﬁrst by a storage oscilloscope and photographed afterward with a normal exposure time.14 for two different conditions. The spectrum was recorded by means of a Polaroid camera.

11. All rights reserved.14a we obtain f3dB Ϸ 6. and the curve shows a discontinuity.com) Copyright © 2004 The McGraw-Hill Companies. From Fig. (b) The peak frequency deviation is too high. 11. of fn Ϸ 4. Marker Marker 0 dB 0 dB (a) Figure 11.1 kHz. Any use is subject to the Terms of Use as given at the website. Note that this value was measured by a different method in Sec. but the peak frequency deviation Dw was purposely chosen so high as to cause nonlinear operation of the PD. The waveforms explain the timing of the spectrum analyzer and the sweep generator. The 3-dB frequency f3dB is by deﬁnition the frequency for which ΩH(w)Ω is 3 dB lower than the dc value H(0). the amplitude of the spectrum is heavily compressed.5. .digitalengineeringlibrary. The measurement is dramatically corrupted by this procedure. and the transfer function is distorted. locations of the natural frequency fn and the 3-dB frequency f3dB were not shifted to any considerable extent. (a) The peak frequency deviation was chosen so that the PD operates in its linear region.Measuring PLL Parameters 340 Chapter Eleven f 10 kHz Spectrum Analyzer 0 fm 10 kHz Sweep Generator 0 100 s t 1s 2s 3s 99 s 100 s t Figure 11. Figure 11. Nevertheless.8 kHz.14b shows the same measurement.13 Measurement of phase-transfer function H(w).14 (b) Automatic recording of H(w) by a spectrum analyzer. Downloaded from Digital Engineering Library @ McGraw-Hill (www.

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