DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

P.S.R.ENGINEERING COLLGE

II YEAR

IV SEMESTER

EE 2258 Linear and Digital Integrated Circuits Laboratory

LAB MANUAL
(ACADEMIC YEAR 2012-2013)

P.S.R.ENGINEERING COLLEGE, SIVAKASI-626 140 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EE2258 - Linear and Digital Integrated Circuits Laboratory
CLASS: II YEAR EEE LIST OF EXPERIMENTS ` SEMESTER: IV

1. 2. 3. 4. 5. 6. 7. 8. 9.

APPLICATION OF OP-AMP I APPLICATION OF OP-AMP II APPLICATION OF 555 TIMER I APPLICATION OF 555 TIMER II STUDY OF BASIC GATES IMPLEMENTATION OF BOOLEAN FUNCTIONS IMPLEMENTATION OF ADDER AND SUBTRACTOR CODE CONVERSION PARITY GENERATORS AND CHECKERS

10. MULTIPLEXER AND DEMULTIPLEXER 11. ENCODER AND DECODER 12. REALISATION OF DIFFERENT FLIP-FLOPS USING LOGIC GATES 13. REALISATION OF COUNTERS 14. REALISATION OF SHIFT REGISTERS 15. FREQUENCY MULTIPLICATION USING PHASE LOCKED LOOP 16. VOLTAGE CONTROLLED OSCILLATOR USING 566

STAFF INCHARGE

HOD/EEE

CIRCUIT DIAGRAM: (Inverting Summing Amplifier)

DESIGN: If resistor Ra, Rb, Rc has same value ie; Ra=Rb=Rc=R We know for an inverting Amplifier Vo = - (Rf/R) x (Va + Vb +Vc) If the values of Rf and R are made equal, then the equation becomes, Vo = -(Va + Vb +Vc) Rm =Ra|| Rb|| Rc|| Rf OBSERVATIONS: S.No. Va in Volts Va in Volts Va in Volts Vo in Volts ACL = RF / R

PIN DIAGRAM:

1. APPLICATIONS OF OP-AMP-I
(Inverting Summing Amplifier, Non-Inverting Summing Amplifier and Voltage Follower)
AIM: To design an inverting amplifier, non-inverting amplifier and voltage follower for the given specifications using Op-Amp IC 741 REFERENCE BOOKS: 1. 2. Ramakant A.Gayakward, Op-amps and Linear Integrated Circuits, IV edition, Pearson Education, 2003 / PHI. (2000). D.Roy Choudhary, Sheil B.Jani, Linear Integrated Circuits, II edition, New Age, 2003.

APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. THEORY: INVERTING SUMMING AMPLIFIER Summing amplifier is a type operational amplifier circuit which can be used to sum signals. The sum of the input signal is amplified by a certain factor and made available at the output .Any number of input signal can be summed using an op-amp. The circuit shown is a three input summing amplifier in the inverting mode. In the circuit, the input signals Va,Vb,Vc are applied to the inverting input of the op-amp through input resistors Ra,Rb,Rc. Any number of input signals can be applied to the inverting input in the above manner. Rf is the feedback resistor. Non inverting input of the op-amp is grounded using resistor Rm. RL is the load resistor. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Connecting wires and probes Range 20 MHz 30 MHz 0 30 V IC 741 As required As required Quantity 1 1 1 1 1

CIRCUIT DIAGRAM: (non-Inverting summing Amplifier)

DESIGN: We know for a Non-inverting Summing Amplifier Vo = (1+ (Rf/R1)) (( Va+Vb+Vc)/3) Assume R1=R2=R3=Rf/2=R V0= (V1+V2+V3)

OBSERVATIONS: S.No. Va in Volts Va in Volts Va in Volts Vo in Volts

PIN DIAGRAM:

NON-INVERTING SUMMING AMPLIFIER A non inverting summing amplifier circuit with three inputs is shown above. The voltage inputs Va, Vb and Vc are applied to non inverting input of the op-amp. Rf is the feedback resistor. The output voltage of the circuit is governed by the equation; Vo = (1+ (Rf/R1)) (( Va+Vb+Vc)/3) VOLTAGE FOLLOWER A unity gain buffer amplifier may be constructed by applying a full series negative feedback (Fig. 2) to an op-amp simply by connecting its output to its inverting input, and connecting the signal source to the non-inverting input (Fig. 3). In this configuration, the entire output voltage ( = 1 in Fig. 2) is placed contrary and in series with the input voltage. Thus the two voltages are subtracted according to Kirchhoff's voltage law (KVL) and their difference is applied to the op-amp differential input. This connection forces the op-amp to adjust its output voltage simply equal to the input voltage (Vout follows Vin so the circuit is named op-amp voltage follower). PRECAUTIONS: 1. Output voltage will be saturated if it exceeds 15V.

PROCEDURE: 1. 2. 3. 4. Connections are given as per the circuit diagram. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the non - inverting input terminal of the Op-Amp. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet.

Voltage Follower:

+Vcc + 741 -Vcc Vs V0

Model Graph:

Vs

time Vo at f1 time Vo at f2 time

Slew Rate=2fVm/106 V/s

.
6

DISCUSSION QUESTIONS: 1. 2. 3. 4. 5. 6. 7. 8. What do you mean by linear circuits? Define an IC? What is an inverting amplifier? What is the type of feedback employed in the inverting op-amp What is a voltage follower? Define a non-inverting amplifier? Give the closed loop gain of an inverting amplifier? What is the gain of a non-inverting amplifier?

RESULT: The design and testing of the Inverting, Non-inverting amplifier and Voltage Follower is done and the input and output waveforms were drawn.

CIRCUIT DIAGRAM :( Differentiator)

DESIGN: Given: fa = --------------We know the frequency at which the gain is 0 dB, fa = 1 / (2 Rf C1) Let us assume C1 = 0.1 F; then Rf = Since fb = 10 fa, fb = --------------We know that the gain limiting frequency fb = 1 / (2 R1 C1) Hence R1 = Also since R1C1 = Rf Cf ; Cf =

OBSERVATIONS:

S.No

Waveforms

Amplitude in Volts

Time period in ms

1. 2.

Input Waveform Output Waveform

2. APPLICATIONS OF OP-AMP-II (Differentiator and Integrator)

AIM: To design a Differentiator circuit for the given specifications using Op-Amp IC 741 REFERENCE BOOKS: 1. 2. Ramakant A.Gayakward, Op-amps and Linear Integrated Circuits, IV edition, Pearson Education, 2003 / PHI. (2000). D.Roy Choudhary, Sheil B.Jani, Linear Integrated Circuits, II edition, New Age, 2003.

APPARATUS REQUIRED: S. No 1. 2. 3. 4. 5. 6. 7. 8. THEORY: Differentiator The differentiator circuit performs the mathematical operation of differentiation; that is, the output waveform is the derivative of the input waveform. The differentiator may be constructed from a basic inverting amplifier if an input resistor R1 is replaced by a capacitor C1. The expression for the output voltage is given as, Vo = - Rf C1 (dVi /dt) Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal of the op-amp to compensate for the input bias current. A workable differentiator can be designed by implementing the following steps: 1. 2. 3. Select fa equal to the highest frequency of the input signal to be differentiated. assuming a value of C1 < 1 F, calculate the value of Rf. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf. The differentiator is most commonly used in wave shaping circuits to detect high frequency components in an input signal and also as a rateofchange detector in FM modulators. Then, Name of the Apparatus AFO CRO Dual RPS Timer IC Bread Board Resistors Capacitors Connecting wires and probes Range 20 MHz 30 MHz 0 30 V IC 555 Quantity 1 1 1 1 1

As required

CIRCUIT DIAGRAM :( INTEGRATOR)

DESIGN: We know the frequency at which the gain is 0 dB, fa = 1 / (2 Rf Cf) Therefore Rf = Since fb = 10 fa, and also the gain limiting frequency fb = 1 / (2 R1Cf) We get, R1 = OBSERVATIONS:

S.No

Waveforms

Amplitude in Volts

Time period in ms

1. 2. Pin diagram:

Input Waveform Output Waveform

10

Integrator A circuit in which the output voltage waveform is the integral of the input voltage waveform is the integrator. output voltage is given as, Vo = - (1/Rf C1) Vi dt Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. Normally between fa and fb the circuit acts as an integrator. Generally, the value of fa < fb . The input signal will be integrated properly if the Time period T of the signal is larger than or equal to Rf Cf. That is, T Rf Cf The integrator is most commonly used in analog computers and ADC and signal-wave shaping circuits. Comparator: (Add Theory) PROCEDURE: 1. 2. 3. 4. Connections are given as per the circuit diagram. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the Op-Amp. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet. DISCUSSION QUESTIONS: 1. 2. 3. 4. 5. 6. 7. 8. 9. What is integrator? Write the disadvantages of ideal integrator? Write the application of integrator? Why compensation resistance is needed in integrator and how will you find it values? What is differentiator? Write the disadvantages of ideal differentiator. Write the application of differentiator? Why compensation resistance is needed in differentiator and how will you find it values? Why integrators are preferred over differentiators in analog comparators? Such a circuit is obtained by using a basic inverting amplifier is replaced by a capacitor Cf . The expression for the configuration if the feedback resistor Rf

11

MODEL GRAPH: Input Signal

Amplitude Amplitude

Time Period Output Signal (Differentiator)

Amplitude

Time Period

Output signal (Integrator)

Amplitude

Time Period

COMPARATOR:

R + _ R Vi 741

+Vcc V0 RL

-Vcc

+ -

Vref

12

Model Graph :( Comparator)

Vi Vi

time -V ref +V sat Vo Vo +V sat

time

time -V sat -V sat

time

OBSERVATIONS:

S.No 1. 2.

Waveforms Input Waveform Output Waveform

Amplitude in Volts

Time period in ms

RESULT: The design of the Integrator, Differentiator and Voltage Follower circuit was done and the input and output waveforms were obtained.

13

CIRCUIT DIAGRAM:

DESIGN: Given f= 4 KHz, Therefore, Total time period, T = 1/f = We know, duty cycle = tc / T Therefore, tc =______ and td = _________ We also know for an astable multivibrator td = 0.69 (R2) C Therefore, R2 = tc = 0.69 (R1 + R2) C Therefore, R1 =

14

3. TIMER APPLICATION ASTABLE MULTIVIBRATOR

AIM: To design an astable multivibrator circuit for the given specifications using 555 Timer IC. REFERENCE BOOKS: 1. 2. Ramakant A.Gayakward, Op-amps and Linear Integrated Circuits, IV edition, Pearson Education, 2003 / PHI. (2000). D.Roy Choudhary, Sheil B.Jani, Linear Integrated Circuits, II edition, New Age, 2003.

APPARATUS REQUIRED: S. No 2. 3. 4. 5. 6. 7. 8. THEORY: An astable multivibrator, often called a free-running multivibrator, is a rectangular-wavegenerating circuit. This circuit does not require an external trigger to change the state of the output. The time during which the output is either high or low is determined by two resistors and a capacitor, which are connected externally to the 555 timer. The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given by,
tc = 0.69 (R1 + R2) C

Name of the Apparatus CRO Dual RPS Timer IC Bread Board Resistors Capacitors Connecting wires and probes

Range 30 MHz 0 30 V IC 555

Quantity 1 1 1 1

As required

Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the output is low and is given by,
td = 0.69 (R2) C

Thus the total time period of the output waveform is,

T = tc + td = 0.69 (R1 + 2 R2) C

The term duty cycle is often used in conjunction with the astable multivibrator. The duty cycle is the ratio of the time tc during which the output is high to the total time period T. It is generally expressed in percentage. In equation form,
% duty cycle = [(R1 + R2) / (R1 + 2 R2)] x 100

15

PIN DIAGRAM:

OBSERVATIONS: Time period in ms tc td

S.No

Waveforms

Amplitude in Volts

1. 2.

Output Voltage , Vo Capacitor voltage , Vc

MODEL GRAPH:

16

PROCEDURE: 1. 2. 3. 4. Connections are given as per the circuit diagram. + 5V supply is given to the + Vcc terminal of the timer IC. At pin 3 the output waveform is observed with the help of a CRO At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage waveforms are plotted in a graph sheet. DISCUSSION QUESTIONS: 1. Define Offset voltage. 2. Define duty cycle. 3. Mention the applications of IC555. 4. Give the methods for obtaining symmetrical square wave. 5. What is the other name for monostable multivibrator? 6. Explain the operation of IC555 in astable mode.. 7. Why negative pulse is used as trigger?

RESULT: The design of the Astable multivibrator circuit was done and the output voltage and capacitor voltage waveforms were obtained.

17

CIRCUIT DIAGRAM:

DESIGN: Consider VCC = 5V, for given tp Output pulse width tp = 1.1 RA C Assume C in the order of microfarads & Find RA Typical values: If C=0.1 F , RA = 10k then tp = 1.1 mSec Trigger Voltage =4 V

18

4. TIMER APPLICATION MONOSTABLE MULTIVIBRATOR

AIM: To design a monostable multivibrator circuit for the given specifications using 555 Timer IC. REFERENCE BOOKS: 1. 2. Ramakant A.Gayakward, Op-amps and Linear Integrated Circuits, IV edition, Pearson Education, 2003 / PHI. (2000). D.Roy Choudhary, Sheil B.Jani, Linear Integrated Circuits, II edition, New Age, 2003.

APPARATUS REQUIRED: S. No 1. 2. 3. 4. 5. 6. 7. 8. THEORY: A monostable multivibrator often called a one-shot multivibrator is a pulse generating circuit in which the duration of the pulse is determined by the RC network connected externally to the 555 timer. In a stable or stand-by state the output of the circuit is approximately zero or at logic low level. When an external trigger pulse is applied, the output is forced to go high
tp = 1.1 R1 C

Name of the Apparatus AFO CRO Dual RPS Timer IC Bread Board Resistors Capacitors Connecting wires and probes

Range 20 MHz 30 MHz 0 30 V IC 555

Quantity 1 1 1 1 1

As required

(approx. Vcc). The time during which the output remains high is given by, At the end of the timing interval, the output automatically reverts back to its logic low state. The output stays low until a trigger pulse is applied again. Then the cycle repeats. Thus the monostable state has only one stable state hence the name monostable. PROCEDURE: 1. 2. 3. 4. 5. Connections are given as per the circuit diagram. + 5V supply is given to the + Vcc terminal of the timer IC. A negative trigger pulse of less than (1/3 VCC) i.e Ground to pin 2 of the 555 IC At pin 3 the output time period is observed with the help of a LED or CRO At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage waveforms are plotted in a graph sheet.

19

PIN DIAGRAM:

OBSERVATIONS: Time period S.No Value of R1 Value of C Theoretical 1. 2. Practical

MODEL GRAPH:

20

DISCUSSION QUESTIONS: 1. 2. 3. 4. 5. 6. Explain the operation of IC555 in monostable mode. What is the charging time for capacitor in monostable mode? What are the modes of operation of 555 timers? Give the comparison between combinational circuits and sequential circuits. What do you mean by present state? Give the applications of 555 timers IC.

RESULT: The design of the Monostable multivibrator circuit was done and the input and output waveforms were obtained.

21

AND GATE

OR GATE

LOGIC DIAGRAM:

LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7408 :

PIN DIAGRAM OF IC 7432 :

CIRCUIT DIAGRAM:

CIRCUIT DIAGRAM:

TRUTH TABLE: Sl. No 1. 2. 3. 4. A 0 0 1 1 INPUT B 0 1 0 1 OUTPUT Y=A.B 0 0 0 1

TRUTH TABLE: Sl. No 1. 2. 3. 4. A 0 0 1 1 INPUT B 0 1 0 1 OUTPUT Y=A+B 0 1 1 1

22

5. a. STUDY OF BASIC GATES

AIM: To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates. REFERENCE BOOKS: 1. 2. Raj Kamal, Digital systems-Principles and Design, Pearson education 2nd edition, 2007 M. Morris Mano, Digital Design, Pearson Education, 2006

APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate NAND gate NOR gate EX-OR gate Connecting wires Range IC 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486 As required Quantity 1 1 1 1 1 1 1

THEORY: a. AND gate:

An AND gate is the physical realization of logical multiplication operation. It is an electronic circuit which generates an output signal of 1 only if all the input signals are 1. b. OR gate:

An OR gate is the physical realization of the logical addition operation. It is an electronic circuit which generates an output signal of 1 if any of the input signal is 1. c. NOT gate:

A NOT gate is the physical realization of the complementation operation. It is an electronic circuit which generates an output signal which is the reverse of the input signal. A NOT gate is also known as an inverter because it inverts the input.

23

NOT GATE LOGIC DIAGRAM:

NAND GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7404:

PIN DIAGRAM OF IC 7400 :

CIRCUIT DIAGRAM:

CIRCUIT DIARAM:

TRUTH TABLE: Sl.No 1. 2. INPUT A 0 1 OUTPUT Y = A 1 0

TRUTH TABLE: Sl. No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y = (A . B) 1 1 1 0

24

d. NAND gate: A NAND gate is a complemented AND gate. The output of the NAND gate will be 0 if all the input signals are 1 and will be 1 if any one of the input signal is 0. e. NOR gate:

A NOR gate is a complemented OR gate. The output of the OR gate will be 1 if all the inputs are 0 and will be 0 if any one of the input signal is 1. f. EX-OR gate:

An Ex-OR gate performs the following Boolean function, A B = ( A . B ) + ( A . B )

It is similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive OR is a function that give an output signal 0 when the two input signals are equal either 0 or 1. PROCEDURE: 1. 2. 3. Connections are given as per the circuit diagram For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. Apply the inputs and verify the truth table for all gates.

DISCUSSION QUESTIONS: 1. 2. 3. 4. 5. 6. 7. 8. 9. Why NAND & NOR gates are called universal gates? Realize the EX OR gates using minimum number of NAND gates? Give the truth table for EX-NOR (EX-OR+NOT) and realize using NAND gates? Explain the operation of NAND gate when realized using discrete components? In what a region does the transistor is operated such that it behaves like a Switch? What are the logic low and High levels of TTL ICs and CMOS ICs? Compare TTL logic family with CMOS family? Which logic family is called fastest and which logic family is called low power dissipated? Explain the operation of OR, NOR gates when realized using discrete Components? 10. Why the transistor operates as NOT gate?

25

NOR GATE

EX-OR GATE

LOGIC DIAGRAM:

LOGIC DIAGRAM

PIN DIAGRAM OF IC 7402 :

PIN DIAGRAM OF IC 7486 :

CIRCUIT DIAGRAM:

CIRCUIT DIAGRAM:

TRUTH TABLE: Sl.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y = (A + B) 1 0 0 0

TRUTH TABLE: Sl.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A 0 1 1 0 B

26

RESULT: The truth table of all the basic digital ICs were verified.

27

CIRCUIT DIAGRAM:

28

5. b. IMPLEMENTATION OF BOOLEAN FUNCTIONS

AIM:

To design the logic circuit and verify the truth table of the given Boolean expression, F (A, B, C, D) = (0, 1, 2, 5, 8, 9, 10)

REFERENCE BOOKS:

1. 2.

Raj Kamal, Digital systems-Principles and Design, Pearson education 2nd edition, 2007 M. Morris Mano, Digital Design, Pearson Education, 2006

APPARATUS REQUIRED:

S.No 1. 2. 3. 4. 5. 6. 7. 8.

Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate NAND gate NOR gate EX-OR gate Connecting wires IC 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486

Range

Quantity 1 1 1 1 1 1 1 As required

PROCEDURE:

1. 2. 3.

Connections are given as per the circuit diagram For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. Apply the inputs and verify the truth table for the given Boolean expression.

29

DESIGN: Given , F (A,B,C,D) = (0,1,2,5,8,9,10) TRUTH TABLE: INPUT A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT F=DB+C(B+AD) 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0

S.No 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.

The output function F has four input variables hence a four variable Karnaugh Map is used to obtain a simplified expression for the output as shown,

From the K-Map, F = B C + D B + A C D Since we are using only two input logic gates the above expression can be re-written as, F = C (B + A D) + D B Now the logic circuit for the above equation can be drawn.

30

RESULT: The truth table of the given Boolean expression was verified.

31

HALF ADDER TRUTH TABLE:

Input A B S Output C

Sl.no

1. 2. 3. 4.

0 0 1 1

0 1 0 1

0 1 1 0

0 0 0 1

From the truth table the expression for sum and carry bits of the output can be obtained as, Sum, S = A B Carry, C = A . B

CIRCUIT DIAGRAM:

FULL ADDER TRUTH TABLE:

Sl.no

1. 2. 3. 4. 5. 6. 7. 8.

0 0 0 0 1 1 1 1

Input B

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

Output Sum Carry

0 1 1 0 1 0 0 1

0 0 0 1 0 1 1 1

32

6. IMPLEMENTATION OF ADDER AND SUBTRACTOR a. HALF ADDER AND FULL ADDER

AIM: To design and verify the truth table of the Half Adder & Full Adder circuits. REFERENCE BOOKS: 1. 2. Raj Kamal, Digital systems-Principles and Design, Pearson education 2nd edition, 2007 M. Morris Mano, Digital Design, Pearson Education, 2006

APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. THEORY: The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely, 0+0=0 0+1=1 1+0=1 1 + 1 = 102 The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum. HALF ADDER: A combinational circuit which performs the addition of two bits is called half adder. The input variables designate the augend and the addend bit, whereas the output variables produce the sum and carry bits. FULL ADDER: A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input bits include two significant bits and a previous carry bit. implemented with two half adders and one OR gate. From the truth table the expression for sum and carry bits of the output can be obtained as, SUM = ABC + ABC + ABC + ABC CARRY = ABC + ABC + ABC +ABC A full adder circuit can be Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate EX-OR gate Connecting wires IC 7408 IC 7432 IC 7404 IC 7486 As required Range Quantity 1 1 1 1 1

33

Using Karnaugh maps the reduced expression for the output bits can be obtained as, SUM

SUM = ABC + ABC + ABC + ABC = A CARRY

CARRY = AB + AC + BC

CIRCUIT DIAGRAM:

34

PROCEDURE: 1. 2. 3. Connections are given as per the circuit diagrams. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. Apply the inputs and verify the truth table for the half adder and full adder circuits.

RESULT: The design of the half adder and full adder circuits was done and their truth tables were verified.

35

HALF SUBTRACTOR TRUTH TABLE:

Input A B Diff Output Borr

S.no

1. 2. 3. 4.

0 0 1 1

0 1 0 1

0 1 1 0

0 1 0 0

From the truth table the expression for difference and borrow bits of the output can be obtained as, Difference, DIFF = A Borrow, BORR = A. B CIRCUIT DIAGRAM: B

2. FULL SUBTRACTOR TRUTH TABLE:

S.no 1. 2. 3. 4. 5. 6. 7. 8. Input A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Diff 0 1 1 0 1 0 0 1 Output Borr 0 1 1 1 0 0 0 1

36

b. HALF SUBTRACTOR AND FULL SUBTRACTOR

AIM: To design and verify the truth table of the Half Subtractor & Full Subtractor circuits. REFERENCE BOOKS: 1. 2. Raj Kamal, Digital systems-Principles and Design, Pearson education 2nd edition, 2007 M. Morris Mano, Digital Design, Pearson Education, 2006

APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. THEORY: The arithmetic operation, subtraction of two binary digits has four possible elementary operations, namely, 0-0=0 0 - 1 = 1 with 1 borrow 1-0=1 1-1=0 In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed. HALF SUBTRACTOR: A combinational circuit which performs the subtraction of two bits is called half subtractor. The input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits. FULL SUBTRACTOR: A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two half subtractors and one OR gate. From the truth table the expression for difference and borrow bits of the output can be obtained as, Difference, DIFF= ABC + ABC + ABC + ABC Borrow, BORR = ABC + ABC + ABC +ABC Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate EX-OR gate Connecting wires IC 7408 IC 7432 IC 7404 IC 7486 As required Range Quantity 1 1 1 1 1

37

Using Karnaugh maps the reduced expression for the output bits can be obtained as, DIFFERENCE

DIFF = ABC + ABC + ABC + ABC = A BORROW

BORR = AB + AC + BC CIRCUIT DIAGRAM:

38

PROCEDURE: 1. 2. 3. Connections are given as per the circuit diagrams. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. Apply the inputs and verify the truth table for the half subtractor and full subtractor circuits.

DISCUSSION QUESTIONS: 1. 2. 3. 4. 5. What is combinational circuit? What is different between combinational and sequential circuit? What are the gates involved for binary adder? List the properties of Ex-Nor gate? What is expression for sum and carry?

RESULT: The design of the half subtractor and full subtractor circuits was done and their truth tables were verified.

39

DESIGN: TRUTH TABLE: 4-bit binary B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 4-bit gray code G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

From the truth table the expression for the output gray bits are, G3 (B3, B2, B1, B0) = (8, 9, 10, 11, 12, 13, 14, 15) G2 (B3, B2, B1, B0) = (4, 5, 6, 7, 8, 9, 10, 11) G1 (B3, B2, B1, B0) = (2, 3, 4, 5, 9, 10, 11, 12, 13) G0 (B3, B2, B1, B0) = (1, 2, 5, 6, 9, 10, 13. 14) Hence obtain the reduced SOP expression using Karnaugh maps as follows, K-Map for G3: K-Map for G2:

G3 = B3

40

7. a. CODE CONVERSION

AIM: To design, construct and study the performance of different code converters. REFERENCE BOOKS: 1. 2. Raj Kamal, Digital systems-Principles and Design, Pearson education 2nd edition, 2007. M. Morris Mano, Digital Design, Pearson Education, 2006

APPARATUS REQUIRED: S.No 1. 2. 3. THEORY: The availability of large variety of codes for the same discrete elements of information results in the use of different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different codes for same information. Thus, code converter is a circuit that makes the two systems compatible even though each uses different binary code. The bit combination assigned to binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0 and the output variables are designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code to Excess-3 code, the input lines must supply the bit combination of elements as specified by code and the output lines generate the corresponding bit combination of code. Each one of the four maps represents one of the four outputs of the circuit as a function of the four input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is C+D has been used to implement partially each of three outputs. Name of the Apparatus Digital IC trainer kit EX-OR gate Connecting wires IC 7486 As required Range Quantity 1

41

K-Map for G1:

K-Map for G0:

CIRCUIT DIAGRAM:

4- BIT BINARY TO GRAY CODE CONVERTER

42

PROCEDURE: 1. 2. 3. Connections are given as per the circuit diagrams. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. Apply the inputs and verify the truth table for the three bit binary to gray code converter.

DISCUSSION QUESTIONS: 1. 2. 3. 4. 5. List the procedures to convert gray code into binary? Why weighted code is called as reflective codes? What is a sequential code? What is error deducting code? What is ASCII code?

RESULT: The design of the 4-bit Binary to Gray code converter circuit was done and its truth table was verified.

43

LOGIC DIAGRAMS: Odd parity checker:

A B C D

1 2

3 74LS86A 4 5 6 74LS86A 10 9

8 74LS86A

ODD PARITY

Even parity checker:

A B C D

1 2

3 74LS86A 4 5 6 74LS86A 10 9

8 74LS86A

ODD PARITY 1

EVEN PARITY

74LS04

Odd parity generator:

A B C D

1 2

A B C D
3 74LS86A 4 5 6 74LS86A 10 9 8 74LS86A 1 2

PARITY BIT

74LS04

Even parity generator:

A B C D

A B C D
1 2 3 74LS86A 4 5 6 74LS86A 10 9 8 74LS86A

PARITY BIT

44

7. b. PARITY GENERATORS AND CHECKERS AIM: To implement the odd and even parity checkers using the logic gates and also to generate the odd parity and even parity numbers using the generators. REFERENCE BOOKS: 1. 2. Raj Kamal, Digital systems-Principles and Design, Pearson education 2nd edition, 2007. M. Morris Mano, Digital Design, Pearson Education, 2006.

APPARATUS REQUIRED: Sl.No 1 2 3 4 THEORY: Parity checking is used for error detection in data transmission. Odd parity checkers: It counts the number of 1s in the given input and produces a 1 in the output when the number of 1s is odd. Even parity checker: It counts the number of 1s in the given input and produces a 1 in the output when the number of 1s is even. Odd parity generators: It generates an odd parity number. The odd parity checker circuit is used with the inverted output and also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits which is an odd parity number. Even parity generator: It generates an even parity number. The even parity checker circuit is used with the inverted output and also the input bits. So when the input is a 4-bit number then the output of the generator circuit will have 5 bits which is an even parity number. PROCEDURE: 1. 2. 3. 4. The circuit is implemented using logic gates. The inputs are given as per the truth table. The corresponding outputs are noted. The theoretical and practical values were verified. EX-OR NOT gate Connecting wires Component Trainer Kit Type IC7486 IC 7404 Quantity 1 1 1 Required

45

TRUTH TABLE: Input A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Checker output odd 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 even 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 Generator output odd 00001 00010 00100 00111 01000 01011 01101 01110 10000 10011 10101 10110 11001 11010 11100 11111 even 00000 00011 00101 00110 01001 01010 01100 01111 10001 10010 10100 10111 11000 11011 11101 11110

DISCUSSION QUESTIONS: 1. 2. 3. 4. 5. What is parity bit? Why parity bit is added to message? What is parity checker? What is odd parity and even parity? What are the gates involved for parity generator?

RESULT: The odd and even parity checkers are implemented using the logic gates and the odd parity and even parity numbers are generated using the corresponding generators.

46

4 X 1 MULTIPLEXER LOGIC SYMBOL: TRUTH TABLE:

S.no

1. 2. 3. 4.

Selection input S1 S2

0 0 1 1

0 1 0 1

Output Y

I0 I1 I2 I3

PIN DIAGRAM OF IC 7411:

CIRCUIT DIAGRAM:

47

8. a. MULTIPLEXER AND DEMULTIPLEXER

AIM: To design and verify the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer. REFERENCE BOOKS: 1. 2. Raj Kamal, Digital systems-Principles and Design, Pearson education 2nd edition, 2007 M. Morris Mano, Digital Design, Pearson Education, 2006

APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. THEORY: Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selection lines whose bit combinations determines which input is selected. A multiplexer is called a data selector, since it selects one of many inputs and steers the binary information to the output line. A Strobe is also provided to allow the designer to disable all output data until a specified time. Then, by allowing the STROBE to go low, the proper lead can be selected. This feature is very useful where data might be changing the same time DATA SELECT leads change. It is a very useful Medium Scale Integration (MSI) function and has a multitude of applications. It is used for connecting two or more sources to a single destination among the computer units and it is useful for constructing a common bus system. A decoder with an enable input can function as a demultiplexer. A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. The selection of specific output line is controlled by the bit values of n selection lines. The decoder and demultiplexer operations are obtained from the same circuit; a decoder with an enable input is referred to as a decoder / de-multiplexer. The Strobe lead can be used to active or de-active the entire IC, allowing time for the address lines to change the information is fed to the output. Demultiplexers are useful anytime information from one source must be fed several places. Name of the Apparatus Digital IC trainer kit OR gate NOT gate AND gate ( three input ) Connecting wires IC 7432 IC 7404 IC 7411 Range Quantity 1 1 1 1 As required

48

1X4 DEMULTIPLEXER LOGIC SYMBOL: TRUTH TABLE:

S.no

1. 2. 3. 4. 5. 6. 7. 8.

Input S1 S2 Din

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

Y0

0 1 0 0 0 0 0 0

Output Y1 Y2

0 0 0 1 0 0 0 0

0 0 0 0 0 1 0 0

Y3

0 0 0 0 0 0 0 1

CIRCUIT DIAGRAM:

49

DISCUSSION QUESTIONS: 1. 2. 3. 4. 5. 6. 7. 8. 9. What is multiplexer? What are the applications of multiplexer? What is the difference between multiplexer & demultiplexer? In 2n to 1 multiplexer how many selection lines are there? How to get higher order multiplexers? Impliment full subtractor using demux? Impliment a 8:1 mux using 4:1 muxes? Design full adder using 8:1 Mux Ics? Design a BCD-to- gry code connecter using 8:1 muxes?

10. Draw and explain the design of a32:1 mux using 8:1 MUX and 4:1 MUX?

RESULT: The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables were verified.

50

CIRCUIT DIAGRAM: Binary Decoder:

7 4 0 4

7 4 0 4

7408

Y0

7408

Y1

7408

Y2

7408

Y3

OBSERVATIONS:

Input s

Inputs A 0 0 1 1 B 0 1 0 1 Y3 0 0 0 1

Outputs Y2 0 0 1 0 Y1 0 1 0 0 Yo 1 0 0 0

51

8. b. ENCODER AND DECODER

AIM: To study the operation of Encoder and Decoder circuits using logic gates REFERENCE BOOKS: 1. 2. Ramakant A.Gayakward, Op-amps and Linear Integrated Circuits, IV edition, Pearson Education, 2003 / PHI. (2000) D.Roy Choudhary, Sheil B.Jani, Linear Integrated Circuits, II edition, New Age, 2003.

APPARATUS REQUIRED: S. No 1. 2. 3. 4. 5. 6. 8. Name of the Apparatus Digital IC trainer NOT Gate OR Gate AND Gate Bread Board NOT Gate Connecting wires and probes IC 7404 IC 7432 IC7408 IC7404 Range Quantity 1 1 1 1 1 1 As required

THEORY: DECODER In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different e.g. n-to-2n , binary-coded decimal decoders. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding. The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) only when all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is called as "active low output". A slightly more complex decoder would be the n-to-2n type binary decoders. These types of decoders are combinational circuits that convert binary information from 'n' coded inputs to a maximum of 2n unique outputs. In case the 'n' bit coded information has unused bit combinations, the decoder may have less than 2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder are other examples. The input to a decoder is parallel binary number and it is used to detect the presence of a particular binary number at the input. The output indicates presence or absence of specific number at the decoder input.

52

Octal to Binary Encoder:

D7

D6

D5

D4

D3

D2

D1

D0 7432 7432 7432 A

7432 7432 7432

7432 7432 7432

OBSERVATIONS: Input D7 0 0 0 0 0 0 0 1 D6 0 0 0 0 0 0 1 0 D5 0 0 0 0 0 1 0 0 D4 0 0 0 0 1 0 0 0 D3 0 0 0 1 0 0 0 0 D2 0 0 1 0 0 0 0 0 D1 0 1 0 0 0 0 0 0 D0 1 0 0 0 0 0 0 0 A 0 0 0 0 1 1 1 1 Output B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1

53

ENCODER An encoder is a device, circuit, transducer, software program, algorithm or person that converts information from one format or code to another. The purpose of encoder is standardization, speed, secrecy, security, or saving space by shrinking size. Encoders are combinational logic circuits and they are exactly opposite of decoders. They accept one or more inputs and generate a multibit output code. Encoders perform exactly reverse operation than decoder. An encoder has M input and N output lines. Out of M input lines only one is activated at a time and produces equivalent code on output N lines. If a device output code has fewer bits than the input code has, the device is usually called an encoder PROCEDURE: 1. 2. Make the circuit connections as shown in the figure. Check the corresponding truth table.

RESULT: The design of the Encoder and Decoder circuit was done and the input and output were obtained

54

Circuit Diagram: SR FLIP FLOP:

7400

7400

CLK 7400
JK FLIP FLOP:

7400

J CLK K

7411

7400

7411

7400

D FLIP FLOP:

7400

7400

CLK 7400
T FLIP FLOP:

7400

7408

7400

7400

CLK 7408 7400 7400

55

9. REALISATION OF DIFFERENT FLIP-FLOPS USING LOGIC GATES

AIM: To verify the characteristic table of RS, D, JK, and T Flip flops. REFERENCE BOOKS: 1. 2. Raj Kamal, Digital systems-Principles and Design, Pearson education 2nd edition, 2007 M. Morris Mano, Digital Design, Pearson Education, 2006

APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. THEORY: A Flip Flop is a sequential device that samples its input signals and changes its output states only at times determined by clocking signal. Flip Flops may vary in the number of inputs they possess and the manner in which the inputs affect the binary states. RS FLIP FLOP: The clocked RS flip flop consists of NAND gates and the output changes its state with respect to the input on application of clock pulse. When the clock pulse is high the S and R inputs reach the second level NAND gates in their complementary form. high the output is in an indeterminate state. D FLIP FLOP: To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the same time. This is obtained by making the two inputs complement of each other. The Flip Flop is reset when the R input high and S input is low. The Flip Flop is set when the S input is high and R input is low. When both the inputs are Name of the Apparatus Digital IC trainer kit NOR gate NOT gate AND gate ( three input ) NAND gate Connecting wires IC 7402 IC 7404 IC 7410 IC 7400 As required Range Quantity 1

56

RS Flip -Flop
Clock Pulse S Input R Present State (Q) Next State(Q+1)

1 2 3 4 5 6 7 8

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 0 0 1 1 X X

JK Flip -Flop
Clock Pulse J Input K Present State (Q) Next State(Q+1)

1 2 3 4 5 6 7 8

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 0 0 1 1 1 0

D Flip -Flop
Clock Pulse Input D Present State (Q) Next State(Q+1)

1 2 3 4 T Flip -Flop
Clock Pulse

0 0 1 1

0 1 0 1

0 0 1 1

Input T

Present State (Q)

Next State(Q+1)

1 2 3 4

0 0 1 1

0 1 0 1

0 0 1 T

57

JK FLIP FLOP: The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave like S and R inputs to set and reset the Flip Flop. The output Q is NAND with K input and the clock pulse, similarly the output Q is NAND with J input and the Clock pulse. When the clock pulse is zero both the AND gates are disabled and the Q and Q output retain their previous values. When the clock pulse is high, the J and K inputs reach the NOR gates. When both the inputs are high the output toggles continuously. This is called Race around condition and this must be avoided. T FLIP FLOP: This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs together. T Flip Flop is also called Toggle Flip Flop.

DISCUSSION QUESTIONS: 1. 2. 3. 4. 5. 6. 7. 8. 9. What is the difference between Flip-Flop & latch? Give examples for synchronous & asynchronous i/Ps? What are the applications of different Flip-Flops? What is universal flip-flop? What is the advantage of Edge triggering over level triggering? What is the relation between propagation delay & clock frequency of flip-flop? What is race around in flip-flop & how to over come it? What are not allowed inputs for RS flip flop using NAND & NOR gates? Connect the J K Flip-Flop into D flip-flop and T flip-flop?

10. List the functions of asynchronous inputs?

RESULT: The Characteristic tables of RS, D, JK, T flip flops were verified.

58

CIRCUIT DIAGRAM: Asynchronous 3 bit Binary Counter: QA QB QC

J1 Clock pulse Logic 1 +5V

7 4 cp1 7 K1 3

Q1

J2 cp2 K2

7 4 7 3

Q2

J3 cp3 K3

7 4 7 3

Q3

Synchronous 3 bit Binary Counter:

QA Logic 1 +5V J1
7 4 cp1 7 K1 3

QB 7408

QC

Q1

J2

7 4 cp2 7 K2 3

Q2

J3

7 4 cp3 7 K3 3

Q3

Clock pulse

PIN DIAGRAM OF IC 7473:

TRUTH TABLES:

Binary Counters: clk 1 2 3 4 5 6 7 QC 0 0 0 1 1 1 1 QB 0 1 1 0 0 1 1 QA 1 0 1 0 1 0 1

59

10. a. REALISATION OF COUNTERS

AIM: To implement and verify the truth table of an aSynchronous and synchronous decade counter REFERENCE BOOKS: 1. 2. Raj Kamal, Digital systems-Principles and Design, Pearson education 2nd edition, 2007 M. Morris Mano, Digital Design, Pearson Education, 2006

APPARATUS REQUIRED: S.No 1. 2. 4. 5. THEORY: Asynchronous decade counter is also called as ripple counter. In a ripple counter the flip flop output transition serves as a source for triggering other flip flops. In other words the clock pulse inputs of all the flip flops are triggered not by the incoming pulses but rather by the transition that occurs in other flip flops. The term asynchronous refers to the events that do not occur at the same time. With respect to the counter operation, asynchronous means that the flip flop within the counter are not made to change states at exactly the same time, they do not because the clock pulses are not connected directly to the clock input of each flip flop in the counter. DISCUSSION QUESTIONS: 1. 2. 3. 4. 5. 6. 7. 8. What is the modulus counter? How many numbers of flip-flops are there in decade counter? What is up down counter? What is the difference between Register &counter? What is BCD counter? If the counter has n-flip-flops. What is the maximum count? Which flip- flops are used in counter? Design a divide by-96 counter using 7490Ics? Name of the Apparatus Digital IC trainer kit JK Flip Flop AND gate Connecting wires IC 7473 IC 7408 Range Quantity 1 2 1 As required

RESULT: The truth table of the synchronous and asynchronous decade counter was hence verified.

60

CIRCUIT DIAGRAM: Serial in Serial out Shift Register: D1 Q4 D1 7 Q1 cp1 7

4 4

D2 7 Q2 cp2 7
4 4

D3 7 Q3 cp3 7
4 4

D4 7 Q4 cp4 7
4 4

Clock pulse Parallel in - Serial out Shift Register

D4 Load/ shift 7404

D3

D2

D1

7408

7408

7408

7432

7432

7432

O/P D1
7 4 cp1 7 4

Q1

D2

7 4 cp2 7 4

Q2

D3

7 4 cp3 7 4

Q3

D4

7 4 cp4 7 4

Q4

Clock pulse

61

10. b. REALISATION OF SHIFT REGISTERS

AIM: To implement and verify the truth table of a serial in serial out and parallel in parallel out shift register. REFERENCE BOOKS: 1. 2. Raj Kamal, Digital systems-Principles and Design, Pearson education 2nd edition, 2007 M. Morris Mano, Digital Design, Pearson Education, 2006

APPARATUS REQUIRED: S.No 1. 2. 3. 4. 4. 3. Name of the Apparatus Digital IC trainer kit D Flip Flop AND Gate NOT Gate OR Gate Connecting wires IC 7474 IC 7408 IC7404 IC 7432 Range Quantity 1 2 1 1 1 As required

THEORY: A register capable of shifting its binary information either to the left or to the right is called a shift register. The logical configuration of a shift register consists of a chain of flip flops connected in cascade with the output of one flip flop connected to the input of the next flip flop. All the flip flops receive a common clock pulse which causes the shift from one stage to the next. The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each clock pulse shifts the contents of the register one bit position to the right. The serial input determines, what goes into the right most flip flop during the shift. The serial output is taken from the output of the left most flip flop prior to the application of a pulse. Although this register shifts its contents to its left, if we turn the page upside down we find that the register shifts its contents to the right. Thus a unidirectional shift register can function either as a shift right or a shift left register.

62

PIN DIAGRAM OF IC 7474:

TRUTH TABLE:

For a serial data input of 1101,

S.no Clock Pulse Inputs D1 D2 D3 D4 Q1 Outputs Q2 Q3 Q4

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8

1 1 0 1 X X X X

X 1 1 0 1 X X X

X X 1 1 0 1 X X

X X X 1 1 0 1 X

1 1 0 1 X 1 0 X

X 1 1 0 1 X X X

X X 1 1 0 1 X X

X X X 1 1 0 1 X

For a Parallel data input of 1101,

S.no Clock Pulse D1 D2 Inputs D3 D4 Outputs Q4

1 2 3 4

1 2 3 4

1 1 1 1

1 1 1 1

0 0 0 0

0 0 0 0

1 1 0 1

63

PROCEDURE: 1. 2. Connections are given as per the circuit diagrams. Apply the input and verify the truth table of the counter.

DISCUSSION QUESTIONS: 1. 2. 3. 4. 5. 6. 7. 8. 9. What are the applications of shift registers? Which flip flop is used in shift register? What is universal shift register? What are different types of shift registers? Which shift gives multiplication by 2? Which shift gives division by 2? Can we use shift register as counter? How timing sequences can be generated using shift registers? Explain the working of 4-bit SIPO shift register?

10. What are glitches in digital circuits?

RESULT: The truth table of a serial in serial out left shift register was hence verified.

64

CIRCUIT DIAGRAM:

+10V

2K

10 F

20 K 0.001F

10 2

VCO Output

Fo = 5 Fin

NE565

4.7K 5
3 9 1 5

11

IC 7490
2 3 6 7 10

1 10K TN2222

0.01 F

-10V

OBSERVATIONS: Sl.No Input Frequency Output Frequency

MODEL GRAPH:
Input Vin

Time (ms)

Output Vo Time (ms)

65

11. a. FREQUENCY MULTIPLICATION USING PHASE LOCKED LOOP

AIM To perform the frequency multiplication using phase locked loop (NE 565) and to draw the output wave form REFERENCE BOOKS: 1. 2. Ramakant A.Gayakward, Op-amps and Linear Integrated Circuits, IV edition, Pearson Education, 2003 / PHI. (2000) D.Roy Choudhary, Sheil B.Jani, Linear Integrated Circuits, II edition, New Age, 2003.

APPARATUS REQUIRED: S. No 1. 2. 3. 4. 5. 6. 7. 8. 9. Name of the Apparatus Digital IC trainer PLL Decade Counter Resistor Capacitor Signal Generator POT RPS Connecting wires and probes Range NE565 IC 7490 2K, 4.7K,10K 0.001F, 0.01F, 10F 20K (0-30V) Quantity 1 1 3 3 1 1 1 As required

THERORY To use PLL as a multiplier make connections as shown in fig the circuit uses and bit binary counter 7490 used as a divide by 5 circuit. Set the lip signal at 1 Vpp square wave at 500 HZ vary the VCO frequency by adjusting the by adjusting the 20k potentiometer till the PLL is locked Measure the output frequency it should be 5 times the input frequency repeat steps for input frequency of 1 KHZ Fo=1.2/4R1 C1 PROCEDURE 1. The connections are made as shown in figure 2. we get a output frequency which is in five times of inputs frequency then plot the graph

RESULT Thus the frequency multiplication using phase locked loop was done and the output wave forms were drawn.

66

CIRCUIT DIAGRAM:
+15V

10 K

8
2K

6 4

5
20 K

NE566

PIN DIAGRAM:

0.01 F

The frequency of the output waveforms is approximated by Fo=2(VCC-VC )/ CT RT VCC

INTERNAL DIAGRAM:

67

11. b. VOLTAGE CONTROLLED OSCILLATOR USING NE 566

AIM: To obtain square wave and triangular wave using voltage controlled oscillator REFERENCE BOOKS: 1. 2. Ramakant A.Gayakward, Op-amps and Linear Integrated Circuits, IV edition, Pearson Education, 2003 / PHI. (2000) D.Roy Choudhary, Sheil B.Jani, Linear Integrated Circuits, II edition, New Age, 2003.

APPARATUS REQUIRED: S. No 1. 2. 4. 5. 7. 9. THEORY: In most cases, the frequency of an oscillator is determined by the time constant RC. However, in cases or applications such as FM, tone generators, and frequency-shift keying (FSK), the frequency is to be controlled by means of an input voltage, called the control voltage. This can be achieved in a voltagecontrolled oscillator (VCO). A VCO is a circuit that provides an oscillating output signal (typically of square-wave or triangular waveform) whose frequency can be adjusted over a range by a dc voltage. An example of a VCO is the 566 IC unit, that provides simultaneously the square-wave and triangular-wave outputs as a function of input voltage. The frequency of oscillation is set by an external resistor R1 and a capacitor C1 and the voltage Vc applied to the control terminals. Figure shows that the 566 IC unit contains current sources to charge and discharge an external capacitor C v at a rate set by an external resistor R1 and the modulating dc input voltage. A Schmitt trigger circuit is employed to switch the current sources between charging and discharging the capacitor, and the triangular voltage produced across the capacitor and square-wave from the Schmitt trigger are provided as outputs through buffer amplifiers. Both the output waveforms are buffered so that the output impedance of each is 50 f2. The typical magnitude of the triangular wave and the square wave are 2.4 Vpeak.to-peak and 5.4Vpeak.to.peak. PROCEDURE: 1. 2. 3. Connections are made as shown in diagram. The square and triangular wave is obtained in terminal 3&4 respectively. The Modulating Input at Pin 5 Is Changed by varying rheostat the voltage at pin 5 and corresponding frequency at output are noted and characteristics were drawn RESULT: Thus the voltage controlled oscillator using NE566 was done and the output was verified Name of the Apparatus Digital IC trainer VCO Resistor Capacitor POT Connecting wires and probes NE566 2K, 10K 0.01F 20K Range Quantity 1 1 2 1 1 As required

68