Chapter 4

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FLIP FLOPS
(Sequential Circuits)

EE 202 : DIGITAL ELECTRONICS

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Course Learning Outcomes, CLO

CLO 2: simplify logical expressions by using Boolean algebra and related techniques orderly.

CLO 5: explain the operation of basic sequential circuits correctly.
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Summary
Types Of Flip Flops:  SR Flip-Flop,  Clocked SR Flip-Flop,  T Flip-Flop and  JK Flip-Flop. - Symbols, Truth Tables and Timing.  T Flip-Flops and D Flip-Flops built using JK Flip-Flops.
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4.0 Introduction

Sequential Circuits
  

The output of circuit depends on the previous output and the present inputs. The inputs must follow a specific sequence to produce a required output. In order to follow a sequence of inputs the circuits must contain some form of memory to retain knowledge of those inputs, which have already occurred. This memory are obtained by feedback connections, which are made so that history of the previous inputs is maintained. Most sequential systems are based on a small number of simple sequential circuit elements known as Bistables or Flip Flops.

EE 202 : DIGITAL ELECTRONICS

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4.0

Flip Flop (Sequential Circuits)

What is Flip flop? Answer:  In digital circuits, the flip-flop, is a kind of bistable multivibrator.  It is a Sequential Circuits / an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory , bit 1 or bit 0.
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These stable conditions are usually called the states of the circuit.1 : General Flip flop symbol They are 1 (HIGH) or 0 (LOW).0 Introduction – Flip Flop  Figure 4. 6  Inputs Q Normal output Q Inverted Output  They have two stable conditions and can be switched from one to the other by appropriate inputs. Whenever we refer to the state of flip flop. EE 202 : DIGITAL ELECTRONICS . we refer to the state of its normal output (Q). These clocked flip-flops are used whenever the input and output signals must occur within a particular sequence.4. More complicated Flip flop use a clock as the control input.0.

6.Types Of Flip Flop 1. Clocked SR Flip Flop JK Flip Flop JK Flip Flop With Preset And Clear T Flip Flop D Flip Flop 7 . SR Flip Flop Active Low = NAND gates b. 3. SR Flip Flop Active High = NOR gates 2. SR Flip Flop a. 5. 4.

The Used of Flip Flop For Memory circuits  For Logic Control Devices  For Counter Devices  For Register Devices  8 .

 The basic SR flip flop is an asynchronous device.1  SR Flip Flop The most basic Flip Flop is called SR Flip Flop.  It does not operate in step with a clock or timing.  In asynchronous device.  SR Flip Flop Active Low = NAND gates  SR Flip Flop Active High = NOR gates 9 EE 202 : DIGITAL ELECTRONICS .  These basic Flip Flop circuit can be constructed using two NAND gates latch or two NOR gates latch.4. the outputs is immediately changed anytime one or more of the inputs change just as in combinational logic circuits.

The other output ¯ Q is simply the compliment of output Q. The SR Flip Flop has two outputs. SET (S) and RESET (R).1:  SR Flip Flop logic Symbol The SR Flip Flop has two inputs.1.1  SR Flip Flop  Figure 4.  EE 202 : DIGITAL ELECTRONICS 10 . Q and ¯ Q   The Q output is considered the normal output and is the one most used.4.

1 SR Flip Flop . SET (S) and RESET (R). The circuit outputs depends on the inputs and also on the outputs. Q as normal output and Q ¯ as inverted output and feedback mechanism.2: SR NAND (Active LOW) Logic circuit. The feedback mechanism is required to form a sequential circuit by connecting the output of NAND-1 to the input of NAND-2 and vice versa.1.  1  2   Figure 4.4. EE 202 : DIGITAL ELECTRONICS 11 .NAND GATE LATCH  NAND GATE LATCH  The NAND gate version has two inputs. Two outputs.

1 SR Flip Flop .1.NAND GATE LATCH  Figure 4.3 Feedback Mechanism EE 202 : DIGITAL ELECTRONICS 12 .4.

This is the normal resting state of the circuit and it has no Q output effect of the states.a 1 0 0 0    1 2 1 1 1  Input S=1 .1.4.NAND GATE LATCH  1 Normal Resting State Figure 4.1 SR Flip Flop . 13 EE 202 : DIGITAL ELECTRONICS . R=1 .4. It works in HOLD mode of operation. Output Q and ¯ will remain in whatever state they were in prior to the occurrence of this input condition.

R = 1  This will set Q = 1. S = 0.1.  It works in SET mode operation.b 1  0 0 1 Input.4.4.NAND GATE LATCH  Figure 4. 1 2 1 0 EE 202 : DIGITAL ELECTRONICS 14 .1 SR Flip Flop .

4.c 1  1 1 0 Input S = 1.4.NAND GATE LATCH  Figure 4. 0 2 0 1 EE 202 : DIGITAL ELECTRONICS 15 .1. R = 0  This will reset Q = 0.  It works in RESET mode operation.1 SR Flip Flop .

It is called INVALID/PROHIBITED 16 EE 202 : DIGITAL ELECTRONICS .NAND GATE LATCH  Figure 4.  If the inputs are returned to 1 simultaneously.1. the design should make this condition S = R = 0 never arises.4. the output states are unpredictable.4.  This input condition should not be used and when circuits are constructed.1 SR Flip Flop .d 1  0 0 1 0 2 1 1 This condition tries to set and reset the NAND gate latch at the same time.  It produces Q = Q ¯ =1  This is unexpected condition. since the two outputs should be inverses of each other.

the reset condition means resetting (clearing) the output Q to 0.4. The set condition means setting the output Q to 1.1 SR Flip Flop . condition of the RS flip-flop. The SET input will set Q = 1 when SET is 0 (LOW).RESET input will reset Q = 0 when RESET is 0 (LOW) In the prohibited/INVALID state both outputs are 1. This condition is not used on the RS flip-flop.  Figure 4.5 : SR NAND gate latch Truth Table  S R Q Q ¯ STATUS INVALID  0 0 1 1 0 1 1 1 1 0 0 0 1 1 Q Q ¯ SET RESET HOLD (NoChange)  The flip-flop memorizes the previous condition. or hold. Likewise.1. it shows that the SET and RESET inputs are active LOW. The last row shows the disabled. EE 202 : DIGITAL ELECTRONICS 17 . The outputs remain as they were before the hold condition existed. There is no change in the outputs from the previous states.NAND GATE LATCH  From the description of the NAND gate latch operation.

1.1 SR NAND Flip Flop-Waveforms Exercise 4.1: Determine the output of NAND gate latch which Q initialy 0 for the given input waveform.1: Determine the output of NAND gate latch which Q initially 1 for the given input waveforms. Example 4.4. S R Q ¯Q S R Q ¯ Q EE 202 : DIGITAL ELECTRONICS 18 .1.

The construction is similar to the NAND latch except that the normal output Q and inverted output Q ¯ have reversed positions.6: SR NOR (Active HIGH) Logic circuit EE 202 : DIGITAL ELECTRONICS 19 .NOR GATE LATCH  NOR GATE LATCH  The latch circuit can also be constructed using two NOR gates latch.1 SR Flip Flop .4.1.   Figure 4.

This is the normal resting state of the circuit and it has no effect of the output states. R = 1. R = 0. • S = 0. it works in RESET mode operation.4.1 SR Flip Flop . 20 EE 202 : DIGITAL ELECTRONICS . It works in HOLD (no change) mode operation.NOR GATE LATCH SR FLIP FLOP NOR (Active HIGH) Logic circuit The analysis of a SR FLIP FLOP NOR : * S = 0. This will reset Q to 0. Q and Q ¯ will remain in whatever state they were in prior to the occurrence of this input condition.

and it produces Q = Q ¯ = 0. This input condition should not be used and when circuits are constructed. If the inputs are returned to 1 simultaneously. S = 1.1 SR Flip Flop . Since the two outputs should be inverse of each other. it works in SET mode operation. R = 0.4. R = 1. This condition tries to set and reset the NOR gate latch at the same time. the design should make this condition SET=RESET = 1 never arises. EE 202 : DIGITAL ELECTRONICS 21 . This is an unexpected condition and are not used.NOR GATE LATCH   S = 1. This will set Q to 1. the output states are unpredictable.

NOR GATE LATCH  From the description of the NOR gate latch operation.7 : SR NOR gate latch Truth Table  The SET input will set Q = 1 when SET is 1 (HIGH). RESET input will reset Q when RESET is 1 (HIGH). S R Q Q ¯ _ 0 0 Q Q 0 1 0 1 1 1 0 1 0 1 0 0 STATUS HOLD (NoChange) RESET SET INVALID EE 202 : DIGITAL ELECTRONICS 22 .4.1 SR Flip Flop .1. it shows that the SET and RESET inputs are Active HIGH.  Figure 4.

2 : Determine the output of NOR gate latch which Q initially 1 for the given input waveforms.2: Determine the output of NOR gate latch which Q initially 0 for the given input waveforms. S S R Q ¯ Q R Q ¯ Q EE 202 : DIGITAL ELECTRONICS 23 .1  SR NOR Flip Flop -Waveforms Example 4.4.1.1.  Exercise 4.

and most of the system outputs can change state only when the clock makes a transition.4.  The clock is distributed to all parts of the system.9. EE 202 : DIGITAL ELECTRONICS 24 .2  The CLOCK In synchronous device. the exact times at which any output can change states are controlled by a signal commonly called the clock.  The clock signal is generally a rectangular pulse train or a square wave as shown in figure 4.

it is called negative going transition (NGT) or negative edge triggered. Figure 4. this is called the positive-going transition (PGT) or positive edge triggered.4.  When the clock changes from a HIGH state to a LOW state.2.1: Clock Pulse-Train Enable (a) Positive going transition Disable (b) Negative going transition EE 202 : DIGITAL ELECTRONICS 25 .2  The CLOCK When the clock changes from a LOW state to a HIGH state.

2 Clocked  SR Flip Flop    Additional clock input is added to change the SR flipflop from an element used in asynchronous sequential circuits to one. Figure 4.2. which can be used in synchronous circuits.2.2 Its means that the flip flop can change the output states only when clock signal makes a transition from LOW to HIGH. The clocked SR flip flop logic symbol that is triggered by the PGT is shown in Figure 4.4.2 : PGT Clocked SR Flip flop symbol EE 202 : DIGITAL ELECTRONICS 26 .

3 shows how the flip flop output will respond to the PGT at the clocked input for the various combinations of SR inputs and output.2. Figure 4.3: Truth Table for clocked SR Flip Flop clock S R Q Q ¯ _ 0 0 Q Q 0 1 0 1 1 0 1 0 1 1 0 0 STATUS HOLD (NoChange) RESET SET INVALID EE 202 : DIGITAL ELECTRONICS 27 . • The up arrow symbol indicates PGT.2 Clocked RS Flip Flop •The Truth Table in figure 4.4.2.

Cp S R Q Cp S R Q ¯ Q ¯ Q EE 202 : DIGITAL ELECTRONICS 28 .1: Determine the output of PGT clocked SR flip flop which Q initially 0 for the given input waveforms  Exercise 4.2.4.2.2  Clocked SR Flip Flop Example 4.1: Determine the output of PGT clocked SR flip flop which Q initially 1 for the given input waveforms.

2  Clocked SR Flip Flop Figure 4.2.4 : NGT Clocked SR Flip flop symbol  The clocked SR Flip Flop logic symbol that is triggered by the NGT is shown in Figure 4.2. 29 EE 202 : DIGITAL ELECTRONICS .4  It means that the Flip flop can change the output states only when clocked signal makes a transition from HIGH to LOW.4.

5: CLOCKED SR FLIP FLOP LOGIC CIRCUIT EE 202 : DIGITAL ELECTRONICS 30 .2.2  Clocked SR Flip Flop Figure 4.4.

6: CLOCKED SR FLIP FLOP LOGIC CIRCUIT  If used NOR Gate.2.4.2  Clocked SR Flip Flop Figure 4. must used AND Gate in front. EE 202 : DIGITAL ELECTRONICS 31 .

Cp S R Q R Q ¯ Q ¯ Q EE 202 : DIGITAL ELECTRONICS 32 .2  Clocked SR Flip Flop Example 4.2: Determine the output of NGT clocked SR flip flop which Q initially 1 for the given input waveforms.2.2: Determine the output of NGT clocked SR flip flop which Q initially 0 for the given input waveforms  Cp S Exercise 4.4.2.

3.3. The JK Flip flop has clock input Cp and two control inputs J and K. Operation of Jk Flip Flop is completely described by truth table in Figure 4.1 : PGT JK Flip flop symbol  Figure 4.2 : NGT JK Flip flop symbol EE 202 : DIGITAL ELECTRONICS 33 . Toggle means that Q and ¯ Q will switch to their opposite states.Symbol     Another types of Flip flop is JK flip flop. Figure 4.3. It differs from the RS flip flops when J=K=1 condition is not indeterminate but it is defined to give a very useful changeover (toggle) action.3 JK   Flip Flop .4.3.

3.3: Truth Table for JK Flip Flop clock  Figure 4.3.3 JK Flip Flop – Truth Table And Logic Circuit Figure 4.4.4: JK FLIP FLOP LOGIC CIRCUIT J K Q Q ¯ 0 0 _ Q Q STATUS HOLD (No Change) 0 1 0 1 1 0 1 0 RESET SET Toggle 1 1 _ Q Q EE 202 : DIGITAL ELECTRONICS 34 .

waveforms Example 4.3.1 : Determine the output of PGT clocked JK flip flop for the given input waveforms which the Q initially 0.3 JK Flip Flop .4. Clk J K Q EE 202 : DIGITAL ELECTRONICS 35 .

Cp Cp J K Q ¯ Q J K Q ¯ Q EE 202 : DIGITAL ELECTRONICS 36 .3 JK Flip Flop .3.waveforms Exercise 4.2:Determine the output of PGT clocked JK flip flop for the given input waveforms which the Q initially 0.3.4. Exercise 4.1:Determine the output of NGT clocked JK flip flop for the given input waveforms which the Q initially 0.

These inputs can change the state of the flip flop regardless of synchronous inputs or the clock.4. This flip flop can also have other inputs called Preset (or SET) and clear that can be used for setting the flip flop to 1 or resetting it to 0 by applying the appropriate signal to the Preset and Clear inputs. EE 202 : DIGITAL ELECTRONICS   37 .4 JK  Flip Flop with Asynchronous Input The J and K inputs are called synchronous inputs since they only influence the state of the flip flop when the clocked pulse is present.

4.4.1 : Symbol and Truth Table EE 202 : DIGITAL ELECTRONICS 38 .4 JK Flip Flop with Preset and Clear Figure 4.

4.4 JK Flip Flop with Asynchronous Input  Example 4.4. Cp Preset Clear J K Q Q EE 202 : DIGITAL ELECTRONICS 39 .2 : The output of clocked JK flip flop which output initially 0 for the given input waveforms.

4.4 JK Flip Flop with Asynchronous Input  Exercise 4. Cp Preset Clear K Q EE 202 : DIGITAL ELECTRONICS 40 .3 : The output of clocked JK flip flop which output initially 0 for the given input waveforms.4.

2 :Truth Table for T Flip Flop T clock Q Q status 0 1 EE 202 : DIGITAL ELECTRONICS Q Q Q Q HOLD TOGOL 41 .5. Figure 4. The output will toggle from 1 to 0 or vice versa.Symbol  The T flip flop has only the Toggle and Hold Operation. If Toggle mode operation.4.5 T  Flip Flop .5.1: Symbol for T Flip Flop T CP  Figure 4.

3: Logic circuit for T Flip Flop EE 202 : DIGITAL ELECTRONICS 42 .4.5 T Flip Flop – Logic Circuit Logic circuit T Flip flop using NAND gate Logic circuit T Flip flop using NOR gate T T Cp Figure 4.5.

5 T Flip Flop – Waveforms Example 4.4. Clk T Q Q EE 202 : DIGITAL ELECTRONICS 43 .1 : Determine the output of PGT T flip flop for the given input waveforms which the Q initially 0.5.

5.1 : Determine the output of PGT T flip flop for the given input waveforms which the Q initially 0.5 T Flip Flop – Wave forms Exercise 4. Exercise 4.2 : Determine the output of NGT T flip flop for the given input waveforms which the Q initially 0.4. Cp Cp T Q T Q Q Q EE 202 : DIGITAL ELECTRONICS 44 .5.

 Figure 4.6   D Flip Flop Also Known as Data Flip flop Can be constructed from RS Flip Flop or JK Flip flop by addition of an inverter. The D flip flop will act as a storage element for a single binary digit (Bit).6. Inverter is connected so that the R input is always the inverse of S (or J input is always complementary of K).4.1 :  D Flip flop symbol   EE 202 : DIGITAL ELECTRONICS 45 .

4.Symbol PGT Positive Edge Q D D Flip Flop Clk Q  NGT Negative Edge Q D D Flip Flop Clk Q Figure 4.6  D Flip Flop .6.2 : D Flip flop symbol using JK Flip Flop / SR Flip Flop EE 202 : DIGITAL ELECTRONICS 46 .

3: Logic circuit for D Flip Flop  Figure 4.4.4: Truth Table for D Flip Flop D 0 1 clock Q Q ¯ 0 1 1 0 status RESET SET Cp EE 202 : DIGITAL ELECTRONICS 47 .6.Logic circuit-Truth Table  Figure 4.6 D Flip Flop.6.

Cp Cp D D Q Q Q Q EE 202 : DIGITAL ELECTRONICS 48 .6. Exercise 4. which output Q initially 0.1 Determine the output of NGT D flip flop for the given input waveforms.6.1 : Determine the output of PGT D flip flop for the given input waveforms which the Q initially 0.6 D Flip Flop – Waveforms  Example 4.4.

7. A combination of Jk flip flop and an inverter can construct a D Flip Flop as shown in Figure 4.18 It also can construct T Flip Flop by combine both J and K inputs with HIGH level input as shown in Figure 4.4.2 : T Flip flop symbol using JK Flip Flop / SR Flip Flop T EE 202 : DIGITAL ELECTRONICS 49 .19  Figure 4.1 : D Flip flop symbol using JK Flip Flop / SR Flip Flop  Figure 4.7 T Flip Flops and D Flip Flops can be Built using JK Flip Flop    The JK flip flop is considered as a universal flip flop.7.

The END……. EE 202 : DIGITAL ELECTRONICS 50 .