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S1-Septembei S, 2uu8, pp. 626-629.

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fiom the IEEE.
On the Design of Single-Inductor Double-Output
DC-DC Buck, Boost and Buck-Boost Converters

Massimiliano Belloni, Edoardo Bonizzoni, and Franco Maloberti
Department of Electronics
University of Pavia
Via Ferrata, 1 – 27100 Pavia – ITALY
[massimiliano.belloni, edoardo.bonizzoni, franco.maloberti]@unipv.it

Abstract – Design methodologies for Single-Inductor Dual-
Output (SIDO) DC-DC switching converters are presented.
The suitable control of a double feedback loop enables the
single inductor sharing between two outputs with low output
voltages errors and limited load-regulation. The design
methods to achieve SIDO converters with a wide input
supply voltage range and with an overall driving capability
as large as 1.4 A have been verified with simulations at the
transistor level. The switching frequency can be 3 MHz or
more with a small off-chip inductor.

I. INTRODUCTION

The fast market growth of multiple-voltage battery-
operated portable applications such as digital cameras,
PDAs, cellular phones, MP3 players, etc. demands for
more and more efficient power management systems. In
this area, DC-DC switching converters play a critical role
in keeping long battery life while still providing stable
supply voltage together with the required driving
capability, [1]. Typical features of these devices are high
power efficiency, low cost, and small size, [2], [3].
Often, in portable applications, the power reduction is
obtained by using multiple supply voltages for different
functional blocks, [4]. However, since in a system the use
of one inductor per DC-DC switching converter is
expensive (in terms of area and cost) and not practical,
the strategy is viable only if two or more converters share
the same inductor as proposed in recent implementations
(single-inductor multiple-output buck converter, [5], and
boost or buck converters with double output, [6], [7]).
Since the regulation of each output requires its control
loop, a multiple-output system must foresee a multi-
feedback loop with the request of suitable signals
processing. Moreover, it is necessary to use extra power
switches that must be properly driven.
This paper studies the above mentioned design issues
for Single-Inductor Dual-Output (SIDO) switching
converter topologies and applies the identified solutions
to a study case: a two-output single-inductor buck-boost
converter able to independently regulate the two output
voltages. This converter has been fully implemented at
the transistor level and simulated by using a conventional
0.5-µm CMOS process. Simulation results demonstrate
the effectiveness of the proposed method.
II. SISO DC-DC SWITCHING REGULATORS

The four conventional Single-Inductor Single-Output
(SISO) DC-DC switching regulators topologies are
shown in Fig. 1.

Figure 1. SISO DC-DC switching regulators conventional topologies.
Fig. 1(a) is the conventional buck converter architecture.
During the switch M1 on-time, T
on,M1
, the inductor
current I
L
ramps-up with a positive slope (V
dd
-V
out
)/L. On
the contrary, during the switch M2 on-time, T
on,M2
, I
L

ramps-down with a negative slope -(V
out
/L).
Applying the small-ripple approximation and the volt-
second balance to the inductor, the conversion ratio is
given by M
buck
=(V
out
/V
dd
)=T
on,M1
/T=D, where T is the
switching period and the duty cycle D has been defined.
The boost topology is shown in Fig. 1(b). During the
switch M1 on-time, T
on,M1
, the inductor current I
L
ramps-
up with a positive slope (V
dd
/L). While, during the switch
M2 on-time, T
on,M2
, I
L
ramps-down with a negative slope
(V
dd
-V
out
)/L. By using the small-ripple approximation and
the volt-second balance to the inductor, the conversion
ratio is given by M
boost
=(V
out
/V
dd
)=1/(1-D).
A similar study can be done for the inverting and non-
inverting buck-boost architectures, shown respectively in
Fig. 1(c) and Fig. 1(d).
In order to obtain N independent outputs, a
straightforward approach consists in using N independent
regulators. This solution leads to waste of components
(since N off-chip inductors are required), and, hence, of
area. Furthermore, this method will increase the overall
cost of the system. The Single-Inductor Multiple-Output
(SIMO) approach overcomes these drawbacks by
978-1-4244-2182-4/08/$25.00 ©2008 IEEE. 626
consistently reducing the system area and cost. The
penalty that has to be sustained is the reduction of the
overall system power efficiency due to the additional load
switches.

III. SIDO DC-DC BUCK CONVERTER

A DC-DC switching regulator with multiple outputs
time-shares the inductor current among the different
loads. Fig. 2 shows a buck converter with two outputs
(SIDO buck). While a conventional SISO buck uses just a
PWM control for the switches on the supply side, namely
M1 and M2, the SIDO configuration foresees two
additional power switches, referred to as S
1
and S
2
, for
the inductor current time-sharing.


Figure 2. DC-DC SIDO buck converter.
Fig. 3 shows an example of the load switched
currents, I
1
and I
2
, in the cases in which T
on,M1
<T
on,S1
(Fig. 3(a)) and

T
on,M1
>T
on,S1
(Fig. 3(b)) in the Continuous
Conduction Mode (CCM), being T
on,SW
the on-time of the
switch SW. The inductor current I
L
is the sum of the two
output currents I
1
and I
2
. A main duty cycle D and a
sharing duty cycle D
1
can be defined, respectively, as
follows
D =T
on,M1
T (1)
D
1
=T
on,S1
T (2)
As shown in Fig. 3, even if the buck converter
operates in the CCM from the inductor point of view,
currents I
1
and I
2
, delivered to the output capacitors C
out1

and C
out2
, respectively, are discontinuous. Indeed, during
the discontinuous periods, the two output capacitors
provide the current to the loads.
In the system, two control loops are, hence, foreseen.
The errors of the two outputs, ε
i
= V
set,i
– V
out,i
(i = 1, 2),
are the control loops inputs. Assuming a PWM control,
the regulator provides two control signals. One is used to
obtain the buck converter switching, while the other to
divide the clock period into two slots. The control
strategy for a SIDO buck in the DCM is straightforward,
[8], while, for a SIDO buck in the CCM, it has been
already discussed together with the compensation scheme
in [9]. Its extension to the case of a SIMO buck is
approached in [5].

Figure 3. SIDO buck output branches currents (I1, I2) in the two cases
D < D1 (a) and D > D1 (b).
Starting from the control circuit proposed in [9], in
order to better stabilize the closed loop control system
and to decrease the output voltage errors, two different
processors can be used in the main and into the sharing
path, H
m
(s) and H
s
(s), respectively, as shown in Fig. 4.

Figure 4. SIDO buck control scheme.
H
m
(s) and H
s
(s) are conventional type-III and type-II
filters, respectively:
H
m
s ( )= k
m
1+
ω
z1
s






1+
s
ω
z2






1+
s
ω
p1








1+
s
ω
p2








(3)
H
s
s ( )= k
s
1+
ω
z
s






1+
s
ω
p








(4)
With regard to the compensation strategy:
• the poles in the origin increase the DC loop gain in
order to minimize the output voltages errors;
• ω
z1
and ω
z2
cancel out the output filter double-pole
ω
o
=1/ LC
outi
;
627
• k
m
and k
s
set the bandwidth of the main and
sharing loop affecting the transient settling times.

IV. SIDO DC-DC BOOST CONVERTER

Fig. 5 shows a boost converter with two outputs.
While the SIDO buck topology needs two extra load
switches, the SIDO boost architecture requires only one
extra load switch in order to time-share the inductor
current between the two output branches.


Figure 5. DC-DC SIDO boost converter.
Fig. 6 shows an example of the main switch (M1)
current, I
M1
, and the two load switches (S
1
, S
2
) currents, I
1

and I
2
, in the CCM. The inductor current I
L
is equal to
I
M1
+ I
1
+ I
2
. Also for the boost configuration, (1) and (2)
define the main and the sharing duty cycles D and D
1
,
respectively.

Figure 6. SIDO boost main switch M1 current (IM1) (a) and output
branches currents (I1, I2) (b).
Similar considerations discussed in the above case of
the SIDO buck converter lead to the proposed SIDO
boost control scheme, shown in Fig. 7. Let us consider,
for instance, the waveform related to the main duty D
(Fig. 6(a)). An increment of (ε
1
+ ε
2
) means that the
whole system needs more energy, so that the duty D
should increase. By contrast, a decrement of (ε
1
+ ε
2
)
means that the whole system needs less energy, then the
duty D should decrease. Consider now the waveform
related to the sharing duty D
1
(Fig. 6(b)). An increment of

1
- ε
2
) means that the first output needs more energy, so
that the duty D
1
should increase. While, a decrement of

1
- ε
2
) means that the first output needs less energy, then
the duty D
1
should decrease.
The two filters, H
m
(s) in the main, and H
s
(s) in the
sharing path, have again the same purpose as in the SIDO
buck case, but, with regard to the H
m
(s) filter, the
different transfer function of the boost converter has to be
taken into account.

Figure 7. SIDO boost control scheme.

V. SIDO DC-DC BUCK-BOOST CONVERTER

Fig. 8 shows a buck-boost converter with two outputs.
Again the SIDO buck-boost architecture needs only one
extra load switch with respect to its SISO counterpart in
order to time-share the inductor current between the two
output branches.
Fig. 9 depicts an example of the main switches (M1,
M2, M3) currents, I
M1
, I
M2
, and I
M3
, and the two load
switches (S
1
, S
2
) currents, I
1
and I
2
, in the CCM. The
inductor current I
L
is equal to I
M1
+I
1
+ I
2
. The main and
the sharing duty cycles, D and D
1
, are again expressed by
(1) and (2). Similar considerations discussed in the above
case of the SIDO boost converter lead to the same control
scheme (Fig. 7) also for the SIDO buck-boost converter.
It is worth to point out that the different transfer function
of the buck-boost configuration has to be taken into
account when designing the H
m
(s) filter.

Figure 8. DC-DC SIDO buck-boost converter.
628

Figure 9. SIDO buck-boost main switches currents (IM1, IM2, IM3) (a) and
output branches currents (I1, I2) (b).

VI. DESIGN EXAMPLE

The proposed design methods have been validated on
a two-output buck-boost design, simulated at the
transistor level using a 0.5-µm CMOS technology. The
design example target specifications are a total output
current up to 1.4 A, a supply voltage that can range from
2.5 V to 5.5 V, a switching frequency of 3 MHz with a
single 2.2-µH inductor and two 22-µF output capacitors.
Fig. 10 shows the simulation results of a load-
regulation test with a supply voltage of 3.6 V. The two
output voltages, V
out1
and V
out2
,

are set to 3.3 V. I
out1
and
I
out2
have a simultaneous step-up variation from 100 mA
to 650 mA and vice versa. The output voltages drops are
of about 100 mV and the settling time is about 60 µs for
both voltages.

Figure 10. Load-regulation simulation. Vdd=3.6 V, Vouti=3.3 V.
Iout1 = Iout2 = 100 mA↔650 mA.
Fig. 11 shows the simulation results of a load-
regulation test with a supply voltage of 3.6 V. The two
output voltages V
out1
and V
out2
are set to 3.3 V. I
out2
has a
step-up variation from 100 mA to 650 mA and vice versa,
while I
out1
is fixed at 100 mA. The V
out2
voltage drop is of
about 60 mV and the settling time is about 80 µs.
In order to increase the overall power efficiency,
depending on the supply voltage V
dd
, the converter can
work also in buck mode (M3 always off) and in boost
mode (M1 always on).

Figure 11. Load-regulation simulation. Vdd=3.6 V, Vouti=3.3 V.
Iout1 =100 mA, Iout2 = 100 mA↔650 mA.

CONCLUSIONS

In this paper, the design methodologies for single-
inductor dual-output DC-DC converters have been
presented. Suitable controls of double feedback loops are
discussed. The identified solutions have been applied to a
study case: a two-output single-inductor buck-boost
converter able to independently regulate two output
voltages. This converter has been fully simulated at the
transistor level by using a conventional 0.5-µm CMOS
process. Simulation results demonstrate the effectiveness
of the proposed method, showing excellent performances
in terms of output voltages errors (less than 2% for both
outputs) and load-regulation.

ACKNOWLEDGMENTS

This work is supported by FIRB project, Italian National
Program #RBAP06L4S5.

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