You are on page 1of 4

Gii thiu v RS232: RS232 l mt chun giao tip dng dng truyn thng tin gia cc thit b vi khong

g cch ln n 20 mt. Cng RS232 thng c cc nh sn xut tch hp vo cc sn phm ca h. Board FPGA vi mc ch phc v nhu cu cho cc sinh vin cc trng ai hc khi mun nghin cu v lp trnh nhng (embededd) nn trong thit k c tch hp cng RS232. Thng qua cng RS232 chng ta c th thc hin giao tip (truyn tn hiu) gia board FPGA v my tnh hay cc thit b phn cng khc c chun giao tip ni tip (serial interface). Cu to cng RS232: Cc chn ca cng RS232 c th c 9 chn (pin) hoc 25 chn ty theo mi loi m n c cc c tnh khc nhau, tuy nhin a s cc cc board FPGA hin nay s dng loi 9 chn nh cc c tnh n gin v d s dng ca loi RS232 ny. Cng RS232 chia ra lm 2 loi: loi cng c (male) v loi cng ci (female) V d v cng RS232 loi 9 chn cng c.

M t cc chn tn hiu ca RS232:

DTR: Data Terminal Ready--Used by a DTE to signal that it is plugged in and available to begin communication. DSR: Data Set Ready--Sister signal to DTR, it is used by the DCE to indicate it is ready to begin communication. CTS: Clear to Send--Used by DCE to signal it is available to send data, and used in response to a RTS request for data. RTS: Request to Send--Used by a DTE to indicate that it wants to send data. DCD: Data Carrier Detect--Used by a DCE to indicate to the DTE that it has received a carrier signal from the modem and that real data is being transmitted.

RI: Ring Indicator--Used by DCE modem to tell the DTE that the phone is ringing and that data will be forthcoming. TxD: Transmit Data--This wire is used for sending data. RxD: Receive Data--This line is used for receiving data. GND: Signal Ground--This pin is the same for DTE and DCE devices, and it provides the return path for both data and hand-shake signals. Gii thiu cch lp trnh giao tip gia board FPGA v my tnh thng qua cng RS232:

Cng RS232 c 3 chn quan trng trong lp trnh truyn thng d liu l:

Chn RD: nhn d liu. Chn TD: truyn d liu. Chn GND: Ground.

C ch truyn d liu:

Bn truyn truyn bt 0 (bt start) trc khi truyn mt byte d liu, bn nhn nh vy bit c khi no d liu truyn n. Tin hnh truyn 1 byte d liu.

Sau khi truyn xong mt byte d liu th bn truyn truyn bt 1 (bt stop) bo cho bn nhn bit kt thc vic truyn 1 byte.

Cu hnh cc thng s cn thit cho vic truyn d liu qua RS232:

Nh speed (s bt truyn trong 1 giy), data bits (s bt d liu), parity (bt chn l), stop bits (s bt stop), flow control. Chng trnh v d giao tip gia my tnh vi board FPGA challenge kit.

S khi cu trc chng trnh:

M t chng trnh: Chng trnh thc hin nhn byte k t ASCII v gi li byte k t k tip trong bng m ASCII.

V d t PC gi chui JNAD xung FPGA, FPGA s gi chui KOBE tr li PC. Khi UART s nhn d liu t trn my tnh PC truyn xung qua tn hiu RX. Byte m k t nhn c s c cng vi 1 trong khi Application v c khi UART truyn ngc tr li my tnh qua tn hiu TX.

Test chng trnh: np file .bit chng trnh mu xung con FPGA ca board, sau dng chng trnh terminal ca window cu hnh cc thng s nh sau:

Tin hnh gi nhn d liu.