OMAP-L138 DSP+ARM Processor

Technical Reference Manual

Literature Number: SPRUH77A December 2011

2
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Contents
Preface 1

2

3

4

5

6

...................................................................................................................................... 81 Overview .......................................................................................................................... 83 1.1 Introduction ................................................................................................................. 84 1.2 Block Diagram ............................................................................................................. 84 1.3 DSP Subsystem ........................................................................................................... 84 1.4 ARM Subsystem ........................................................................................................... 84 1.5 DMA Subsystem ........................................................................................................... 85 ARM Subsystem ................................................................................................................ 87 2.1 Introduction ................................................................................................................. 88 2.2 Operating States/Modes .................................................................................................. 89 2.3 Processor Status Registers .............................................................................................. 89 2.4 Exceptions and Exception Vectors ...................................................................................... 90 2.5 The 16-BIS/32-BIS Concept ............................................................................................. 91 2.6 16-BIS/32-BIS Advantages ............................................................................................... 91 2.7 Co-Processor 15 (CP15) ................................................................................................. 92 2.7.1 Addresses in an ARM926EJ-S System ........................................................................ 92 2.7.2 Memory Management Unit (MMU) ............................................................................. 92 2.7.3 Caches and Write Buffer ........................................................................................ 93 DSP Subsystem ................................................................................................................ 95 3.1 Introduction ................................................................................................................. 96 3.2 TMS320C674x Megamodule ............................................................................................. 97 3.2.1 Internal Memory Controllers ..................................................................................... 97 3.2.2 Internal Peripherals ............................................................................................... 97 3.3 Memory Map .............................................................................................................. 102 3.3.1 DSP Internal Memory ........................................................................................... 102 3.3.2 External Memory ................................................................................................ 102 3.4 Advanced Event Triggering (AET) ..................................................................................... 102 System Interconnect ........................................................................................................ 103 4.1 Introduction ............................................................................................................... 104 4.2 System Interconnect Block Diagram .................................................................................. 105 System Memory ............................................................................................................... 107 5.1 Introduction ............................................................................................................... 108 5.2 ARM Memories ........................................................................................................... 108 5.3 DSP Memories ........................................................................................................... 108 5.4 Shared RAM Memory ................................................................................................... 108 5.5 External Memories ....................................................................................................... 108 5.6 Internal Peripherals ...................................................................................................... 109 5.7 Peripherals ................................................................................................................ 109 Memory Protection Unit (MPU) .......................................................................................... 111 6.1 Introduction ............................................................................................................... 112 6.1.1 Purpose of the MPU ............................................................................................ 112 6.1.2 Features .......................................................................................................... 112 6.1.3 Block Diagram ................................................................................................... 112 6.1.4 MPU Default Configuration .................................................................................... 113
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6.2

6.3

Architecture ............................................................................................................... 6.2.1 Privilege Levels .................................................................................................. 6.2.2 Memory Protection Ranges .................................................................................... 6.2.3 Permission Structures .......................................................................................... 6.2.4 Protection Check ................................................................................................ 6.2.5 DSP L1/L2 Cache Controller Accesses ...................................................................... 6.2.6 MPU Register Protection ....................................................................................... 6.2.7 Invalid Accesses and Exceptions ............................................................................. 6.2.8 Reset Considerations ........................................................................................... 6.2.9 Interrupt Support ................................................................................................ 6.2.10 Emulation Considerations ..................................................................................... MPU Registers ........................................................................................................... 6.3.1 Revision Identification Register (REVID) .................................................................... 6.3.2 Configuration Register (CONFIG) ............................................................................ 6.3.3 Interrupt Raw Status/Set Register (IRAWSTAT) ............................................................ 6.3.4 Interrupt Enable Status/Clear Register (IENSTAT) ......................................................... 6.3.5 Interrupt Enable Set Register (IENSET) ..................................................................... 6.3.6 Interrupt Enable Clear Register (IENCLR) ................................................................... 6.3.7 Fixed Range Start Address Register (FXD_MPSAR) ...................................................... 6.3.8 Fixed Range End Address Register (FXD_MPEAR) ....................................................... 6.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) .............................. 6.3.10 Programmable Range n Start Address Registers (PROGn_MPSAR) .................................. 6.3.11 Programmable Range n End Address Registers (PROGn_MPEAR) ................................... 6.3.12 Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA) ............ 6.3.13 Fault Address Register (FLTADDRR) ....................................................................... 6.3.14 Fault Status Register (FLTSTAT) ............................................................................ 6.3.15 Fault Clear Register (FLTCLR) .............................................................................. Overview .................................................................................................................. Frequency Flexibility ..................................................................................................... Peripheral Clocking ...................................................................................................... 7.3.1 USB Clocking .................................................................................................... 7.3.2 DDR2/mDDR Memory Controller Clocking .................................................................. 7.3.3 EMIFA Clocking ................................................................................................. 7.3.4 EMAC Clocking .................................................................................................. 7.3.5 uPP Clocking .................................................................................................... 7.3.6 McASP Clocking ................................................................................................ 7.3.7 I/O Domains ..................................................................................................... Introduction ............................................................................................................... PLL Controllers ........................................................................................................... 8.2.1 Device Clock Generation ....................................................................................... 8.2.2 Steps for Programming the PLLs ............................................................................. PLLC Registers ........................................................................................................... 8.3.1 PLLC0 Revision Identification Register (REVID) ........................................................... 8.3.2 PLLC1 Revision Identification Register (REVID) ........................................................... 8.3.3 Reset Type Status Register (RSTYPE) ...................................................................... 8.3.4 PLLC0 Reset Control Register (RSCTRL) ................................................................... 8.3.5 PLLC0 Control Register (PLLCTL) ........................................................................... 8.3.6 PLLC1 Control Register (PLLCTL) ........................................................................... 8.3.7 PLLC0 OBSCLK Select Register (OCSEL) .................................................................. 8.3.8 PLLC1 OBSCLK Select Register (OCSEL) .................................................................. 8.3.9 PLL Multiplier Control Register (PLLM) ......................................................................

113 113 114 115 116 116 116 117 117 117 117 118 120 120 121 122 123 123 124 124 125 126 127 128 129 130 131 134 136 137 137 139 141 142 144 145 146 148 148 150 151 153 154 155 155 156 157 158 159 160 161

7

Device Clocking
7.1 7.2 7.3

............................................................................................................... 133

8

Phase-Locked Loop Controller (PLLC)
8.1 8.2

............................................................................... 147

8.3

4

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8.3.10 8.3.11 8.3.12 8.3.13 8.3.14 8.3.15 8.3.16 8.3.17 8.3.18 8.3.19 8.3.20 8.3.21 8.3.22 8.3.23 8.3.24 8.3.25 8.3.26 8.3.27 8.3.28 8.3.29 8.3.30 8.3.31 8.3.32 8.3.33 8.3.34 8.3.35 8.3.36 8.3.37

PLLC0 Pre-Divider Control Register (PREDIV) ............................................................ PLLC0 Divider 1 Register (PLLDIV1) ....................................................................... PLLC1 Divider 1 Register (PLLDIV1) ....................................................................... PLLC0 Divider 2 Register (PLLDIV2) ....................................................................... PLLC1 Divider 2 Register (PLLDIV2) ....................................................................... PLLC0 Divider 3 Register (PLLDIV3) ....................................................................... PLLC1 Divider 3 Register (PLLDIV3) ....................................................................... PLLC0 Divider 4 Register (PLLDIV4) ....................................................................... PLLC0 Divider 5 Register (PLLDIV5) ....................................................................... PLLC0 Divider 6 Register (PLLDIV6) ....................................................................... PLLC0 Divider 7 Register (PLLDIV7) ....................................................................... PLLC0 Oscillator Divider 1 Register (OSCDIV) ............................................................ PLLC1 Oscillator Divider 1 Register (OSCDIV) ............................................................ PLL Post-Divider Control Register (POSTDIV) ............................................................ PLL Controller Command Register (PLLCMD) ............................................................ PLL Controller Status Register (PLLSTAT) ................................................................ PLLC0 Clock Align Control Register (ALNCTL) ........................................................... PLLC1 Clock Align Control Register (ALNCTL) ........................................................... PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) ............................................ PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) ............................................ PLLC0 Clock Enable Control Register (CKEN) ............................................................ PLLC1 Clock Enable Control Register (CKEN) ............................................................ PLLC0 Clock Status Register (CKSTAT) ................................................................... PLLC1 Clock Status Register (CKSTAT) ................................................................... PLLC0 SYSCLK Status Register (SYSTAT) ............................................................... PLLC1 SYSCLK Status Register (SYSTAT) ............................................................... Emulation Performance Counter 0 Register (EMUCNT0) ................................................ Emulation Performance Counter 1 Register (EMUCNT1) ................................................

161 162 162 163 163 164 164 165 165 166 166 167 167 168 168 169 170 171 172 173 174 174 175 176 177 178 179 179 182 182 184 185 187 187 187 188 188 188 189 190 191 192 192 193 193 194 194 195 195 196 197 198
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9

Power and Sleep Controller (PSC)
9.1 9.2

..................................................................................... 181

9.3

9.4 9.5

9.6

Introduction ............................................................................................................... Power Domain and Module Topology ................................................................................. 9.2.1 Power Domain States .......................................................................................... 9.2.2 Module States ................................................................................................... Executing State Transitions ............................................................................................ 9.3.1 Power Domain State Transitions .............................................................................. 9.3.2 Module State Transitions ....................................................................................... IcePick Emulation Support in the PSC ................................................................................ PSC Interrupts ............................................................................................................ 9.5.1 Interrupt Events ................................................................................................. 9.5.2 Interrupt Registers .............................................................................................. 9.5.3 Interrupt Handling ............................................................................................... PSC Registers ............................................................................................................ 9.6.1 Revision Identification Register (REVID) .................................................................... 9.6.2 Interrupt Evaluation Register (INTEVAL) .................................................................... 9.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0) .................................. 9.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0) .................................. 9.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) ...................................... 9.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) ...................................... 9.6.7 Power Error Pending Register (PERRPR) ................................................................... 9.6.8 Power Error Clear Register (PERRCR) ...................................................................... 9.6.9 Power Domain Transition Command Register (PTCMD) .................................................. 9.6.10 Power Domain Transition Status Register (PTSTAT) ..................................................... 9.6.11 Power Domain 0 Status Register (PDSTAT0) .............................................................
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9.6.12 9.6.13 9.6.14 9.6.15 9.6.16 9.6.17 9.6.18 9.6.19

Power Domain 1 Status Register (PDSTAT1) ............................................................. Power Domain 0 Control Register (PDCTL0) .............................................................. Power Domain 1 Control Register (PDCTL1) .............................................................. Power Domain 0 Configuration Register (PDCFG0) ...................................................... Power Domain 1 Configuration Register (PDCFG1) ...................................................... Module Status n Register (MDSTATn) ...................................................................... PSC0 Module Control n Register (modules 0-15) (MDCTLn) ............................................ PSC1 Module Control n Register (modules 0-31) (MDCTLn) ............................................

199 200 201 202 203 204 205 206 208 208 208 209 210 210 210 211 211 211 212 213 214 214 214 214 214 216 217 217 218 218 218 219 220 221 222 222 222 223 223 223 226 226 226 227 227 229 229 231 231 232 233

10

Power Management
10.1 10.2 10.3 10.4 10.5

.......................................................................................................... 207

Introduction ............................................................................................................... Power Consumption Overview ......................................................................................... PSC and PLLC Overview ............................................................................................... Features ................................................................................................................... Clock Management ...................................................................................................... 10.5.1 Module Clock ON/OFF ........................................................................................ 10.5.2 Module Clock Frequency Scaling ............................................................................ 10.5.3 PLL Bypass and Power Down ............................................................................... 10.6 ARM Sleep Mode Management ........................................................................................ 10.6.1 ARM Wait-For-Interrupt Sleep Mode ........................................................................ 10.6.2 ARM Clock OFF ................................................................................................ 10.6.3 ARM Subsystem Clock ON ................................................................................... 10.7 DSP Sleep Mode Management ........................................................................................ 10.7.1 DSP Sleep Modes ............................................................................................. 10.7.2 C674x DSP CPU Sleep Mode ............................................................................... 10.7.3 C674x Megamodule Sleep Mode ............................................................................ 10.7.4 C674x Megamodule Clock ON/OFF ......................................................................... 10.8 RTC-Only Mode .......................................................................................................... 10.9 Dynamic Voltage and Frequency Scaling (DVFS) ................................................................... 10.9.1 Frequency Scaling Considerations .......................................................................... 10.9.2 Voltage Scaling Considerations .............................................................................. 10.10 Deep Sleep Mode ....................................................................................................... 10.10.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up ........................... 10.10.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up ................................. 10.10.3 Deep Sleep Sequence ....................................................................................... 10.10.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking ..................................... 10.11 Additional Peripheral Power Management Considerations ........................................................ 10.11.1 USB PHY Power Down Control ............................................................................ 10.11.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode .............................. 10.11.3 SATA PHY Power Down .................................................................................... 10.11.4 LVCMOS I/O Buffer Receiver Disable ..................................................................... 10.11.5 Pull-Up/Pull-Down Disable ..................................................................................

11

System Configuration (SYSCFG) Module
11.1 11.2

............................................................................ 225

11.3 11.4 11.5

Introduction ............................................................................................................... Protection ................................................................................................................. 11.2.1 Privilege Mode Protection ..................................................................................... 11.2.2 Kicker Mechanism Protection ................................................................................ Master Priority Control ................................................................................................... ARM-DSP Communication Interrupts ................................................................................. SYSCFG Registers ...................................................................................................... 11.5.1 Revision Identification Register (REVID) ................................................................... 11.5.2 Device Identification Register 0 (DEVIDR0) ................................................................ 11.5.3 Boot Configuration Register (BOOTCFG) .................................................................. 11.5.4 Kick Registers (KICK0R-KICK1R) ...........................................................................

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11.5.5 11.5.6 11.5.7 11.5.8 11.5.9 11.5.10 11.5.11 11.5.12 11.5.13 11.5.14 11.5.15 11.5.16 11.5.17 11.5.18 11.5.19 11.5.20 11.5.21 11.5.22 11.5.23 11.5.24 11.5.25

Host 0 Configuration Register (HOST0CFG) ............................................................... Host 1 Configuration Register (HOST1CFG) ............................................................... Interrupt Registers ............................................................................................. Fault Registers ................................................................................................. Master Priority Registers (MSTPRI0-MSTPRI2) ........................................................... Pin Multiplexing Control Registers (PINMUX0-PINMUX19) ............................................ Suspend Source Register (SUSPSRC) ................................................................... Chip Signal Register (CHIPSIG) ........................................................................... Chip Signal Clear Register (CHIPSIG_CLR) ............................................................. Chip Configuration 0 Register (CFGCHIP0) .............................................................. Chip Configuration 1 Register (CFGCHIP1) .............................................................. Chip Configuration 2 Register (CFGCHIP2) .............................................................. Chip Configuration 3 Register (CFGCHIP3) .............................................................. Chip Configuration 4 Register (CFGCHIP4) .............................................................. VTP I/O Control Register (VTPIO_CTL) ................................................................... DDR Slew Register (DDR_SLEW) ......................................................................... Deep Sleep Register (DEEPSLEEP) ...................................................................... Pullup/Pulldown Enable Register (PUPD_ENA) ......................................................... Pullup/Pulldown Select Register (PUPD_SEL) ........................................................... RXACTIVE Control Register (RXACTIVE) ................................................................ Power Down Control Register (PWRDN) .................................................................

234 235 236 239 241 244 285 288 289 290 291 294 296 297 298 300 301 302 302 304 304 306 306 309 309 310 310 310 310 311 311 312 313 313 313 314 315 316 316 317 317 318 318 319 319 320 320 321 321 322 322 323
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12

ARM Interrupt Controller (AINTC)
12.1 12.2 12.3

....................................................................................... 305

12.4

Introduction ............................................................................................................... Interrupt Mapping ........................................................................................................ AINTC Methodology ..................................................................................................... 12.3.1 Interrupt Processing ........................................................................................... 12.3.2 Interrupt Enabling .............................................................................................. 12.3.3 Interrupt Status Checking ..................................................................................... 12.3.4 Interrupt Channel Mapping ................................................................................... 12.3.5 Host Interrupt Mapping Interrupts ............................................................................ 12.3.6 Interrupt Prioritization .......................................................................................... 12.3.7 Interrupt Nesting ............................................................................................... 12.3.8 Interrupt Vectorization ......................................................................................... 12.3.9 Interrupt Status Clearing ...................................................................................... 12.3.10 Interrupt Disabling ............................................................................................ AINTC Registers ......................................................................................................... 12.4.1 Revision Identification Register (REVID) ................................................................... 12.4.2 Control Register (CR) ......................................................................................... 12.4.3 Global Enable Register (GER) ............................................................................... 12.4.4 Global Nesting Level Register (GNLR) ..................................................................... 12.4.5 System Interrupt Status Indexed Set Register (SISR) .................................................... 12.4.6 System Interrupt Status Indexed Clear Register (SICR) .................................................. 12.4.7 System Interrupt Enable Indexed Set Register (EISR) ................................................... 12.4.8 System Interrupt Enable Indexed Clear Register (EICR) ................................................. 12.4.9 Host Interrupt Enable Indexed Set Register (HIEISR) .................................................... 12.4.10 Host Interrupt Enable Indexed Clear Register (HIEICR) ................................................ 12.4.11 Vector Base Register (VBR) ................................................................................ 12.4.12 Vector Size Register (VSR) ................................................................................. 12.4.13 Vector Null Register (VNR) ................................................................................. 12.4.14 Global Prioritized Index Register (GPIR) .................................................................. 12.4.15 Global Prioritized Vector Register (GPVR) ................................................................ 12.4.16 System Interrupt Status Raw/Set Register 1 (SRSR1) .................................................. 12.4.17 System Interrupt Status Raw/Set Register 2 (SRSR2) ..................................................
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12.4.18 12.4.19 12.4.20 12.4.21 12.4.22 12.4.23 12.4.24 12.4.25 12.4.26 12.4.27 12.4.28 12.4.29 12.4.30 12.4.31 12.4.32 12.4.33 12.4.34 12.4.35 12.4.36 12.4.37 12.4.38 12.4.39

System Interrupt Status Raw/Set Register 3 (SRSR3) .................................................. System Interrupt Status Raw/Set Register 4 (SRSR4) .................................................. System Interrupt Status Enabled/Clear Register 1 (SECR1) ........................................... System Interrupt Status Enabled/Clear Register 2 (SECR2) ........................................... System Interrupt Status Enabled/Clear Register 3 (SECR3) ........................................... System Interrupt Status Enabled/Clear Register 4 (SECR4) ........................................... System Interrupt Enable Set Register 1 (ESR1) ......................................................... System Interrupt Enable Set Register 2 (ESR2) ......................................................... System Interrupt Enable Set Register 3 (ESR3) ......................................................... System Interrupt Enable Set Register 4 (ESR4) ......................................................... System Interrupt Enable Clear Register 1 (ECR1) ....................................................... System Interrupt Enable Clear Register 2 (ECR2) ....................................................... System Interrupt Enable Clear Register 3 (ECR3) ....................................................... System Interrupt Enable Clear Register 4 (ECR4) ....................................................... Channel Map Registers (CMR0-CMR25) ................................................................. Host Interrupt Prioritized Index Register 1 (HIPIR1) ..................................................... Host Interrupt Prioritized Index Register 2 (HIPIR2) ..................................................... Host Interrupt Nesting Level Register 1 (HINLR1) ....................................................... Host Interrupt Nesting Level Register 2 (HINLR2) ....................................................... Host Interrupt Enable Register (HIER) .................................................................... Host Interrupt Prioritized Vector Register 1 (HIPVR1) ................................................... Host Interrupt Prioritized Vector Register 2 (HIPVR2) ...................................................

323 324 324 325 325 326 326 327 327 328 328 329 329 330 330 331 331 332 332 333 334 334

13

Boot Considerations
13.1 13.2

........................................................................................................ 335

Introduction ............................................................................................................... 336 DSP Wake Up ............................................................................................................ 337

14 15

............................................................. 339 DDR2/mDDR Memory Controller ........................................................................................ 341 15.1 Introduction ............................................................................................................... 342 15.1.1 Purpose of the Peripheral ..................................................................................... 342 15.1.2 Features ......................................................................................................... 342 15.1.3 Functional Block Diagram ..................................................................................... 343 15.1.4 Supported Use Case Statement ............................................................................. 343 15.1.5 Industry Standard(s) Compliance Statement ............................................................... 343 15.2 Architecture ............................................................................................................... 344 15.2.1 Clock Control ................................................................................................... 344 15.2.2 Signal Descriptions ............................................................................................ 345 15.2.3 Protocol Description(s) ........................................................................................ 346 15.2.4 Memory Width and Byte Alignment .......................................................................... 354 15.2.5 Address Mapping .............................................................................................. 355 15.2.6 DDR2/mDDR Memory Controller Interface ................................................................. 360 15.2.7 Refresh Scheduling ............................................................................................ 363 15.2.8 Self-Refresh Mode ............................................................................................. 363 15.2.9 Partial Array Self Refresh for Mobile DDR ................................................................. 364 15.2.10 Power-Down Mode ........................................................................................... 364 15.2.11 Reset Considerations ........................................................................................ 365 15.2.12 VTP IO Buffer Calibration ................................................................................... 366 15.2.13 Auto-Initialization Sequence ................................................................................ 366 15.2.14 Interrupt Support .............................................................................................. 369 15.2.15 DMA Event Support .......................................................................................... 369 15.2.16 Power Management .......................................................................................... 370 15.2.17 Emulation Considerations ................................................................................... 371 15.3 Supported Use Cases ................................................................................................... 372 15.3.1 Connecting the DDR2/mDDR Memory Controller to DDR2/mDDR Memory ........................... 372
Programmable Real-Time Unit Subsystem (PRUSS)
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15.4

15.3.2 Configuring Memory-Mapped Registers to Meet DDR2 Specification .................................. Registers .................................................................................................................. 15.4.1 Revision ID Register (REVID) ................................................................................ 15.4.2 SDRAM Status Register (SDRSTAT) ....................................................................... 15.4.3 SDRAM Configuration Register (SDCR) .................................................................... 15.4.4 SDRAM Refresh Control Register (SDRCR) ............................................................... 15.4.5 SDRAM Timing Register 1 (SDTIMR1) ..................................................................... 15.4.6 SDRAM Timing Register 2 (SDTIMR2) ..................................................................... 15.4.7 SDRAM Configuration Register 2 (SDCR2) ................................................................ 15.4.8 Peripheral Bus Burst Priority Register (PBBPR) ........................................................... 15.4.9 Performance Counter 1 Register (PC1) ..................................................................... 15.4.10 Performance Counter 2 Register (PC2) ................................................................... 15.4.11 Performance Counter Configuration Register (PCC) .................................................... 15.4.12 Performance Counter Master Region Select Register (PCMRS) ...................................... 15.4.13 Performance Counter Time Register (PCT) .............................................................. 15.4.14 DDR PHY Reset Control Register (DRPYRCR) .......................................................... 15.4.15 Interrupt Raw Register (IRR) ................................................................................ 15.4.16 Interrupt Masked Register (IMR) ........................................................................... 15.4.17 Interrupt Mask Set Register (IMSR) ........................................................................ 15.4.18 Interrupt Mask Clear Register (IMCR) ..................................................................... 15.4.19 DDR PHY Control Register (DRPYC1R) .................................................................. Introduction ............................................................................................................... 16.1.1 Purpose of the Peripheral ..................................................................................... 16.1.2 Features ......................................................................................................... Architecture ............................................................................................................... 16.2.1 Capture and APWM Operating Mode ....................................................................... 16.2.2 Capture Mode Description .................................................................................... Applications ............................................................................................................... 16.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example ......................................... 16.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example ........................... 16.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example ....................................... 16.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example ......................... 16.3.5 Application of the APWM Mode ............................................................................. Registers .................................................................................................................. 16.4.1 Time-Stamp Counter Register (TSCTR) .................................................................... 16.4.2 Counter Phase Control Register (CTRPHS) ............................................................... 16.4.3 Capture 1 Register (CAP1) ................................................................................... 16.4.4 Capture 2 Register (CAP2) ................................................................................... 16.4.5 Capture 3 Register (CAP3) ................................................................................... 16.4.6 Capture 4 Register (CAP4) ................................................................................... 16.4.7 ECAP Control Register 1 (ECCTL1) ........................................................................ 16.4.8 ECAP Control Register 2 (ECCTL2) ........................................................................ 16.4.9 ECAP Interrupt Enable Register (ECEINT) ................................................................. 16.4.10 ECAP Interrupt Flag Register (ECFLG) ................................................................... 16.4.11 ECAP Interrupt Clear Register (ECCLR) .................................................................. 16.4.12 ECAP Interrupt Forcing Register (ECFRC) ............................................................... 16.4.13 Revision ID Register (REVID) .............................................................................. Introduction ............................................................................................................... 17.1.1 Introduction ..................................................................................................... 17.1.2 Submodule Overview .......................................................................................... 17.1.3 Register Mapping ..............................................................................................
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373 377 377 378 379 382 383 384 385 386 387 387 388 390 391 391 392 392 393 394 395 398 398 398 399 400 401 408 409 411 413 415 417 424 424 425 425 426 426 427 427 429 430 432 433 434 435 438 438 438 442
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16

Enhanced Capture (eCAP) Module
16.1

..................................................................................... 397

16.2

16.3

16.4

17

Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
17.1

.............................................. 437

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17.2

17.3

17.4

Architecture ............................................................................................................... 17.2.1 Overview ........................................................................................................ 17.2.2 Proper Interrupt Initialization Procedure .................................................................... 17.2.3 Time-Base (TB) Submodule .................................................................................. 17.2.4 Counter-Compare (CC) Submodule ......................................................................... 17.2.5 Action-Qualifier (AQ) Submodule ............................................................................ 17.2.6 Dead-Band Generator (DB) Submodule .................................................................... 17.2.7 PWM-Chopper (PC) Submodule ............................................................................. 17.2.8 Trip-Zone (TZ) Submodule ................................................................................... 17.2.9 Event-Trigger (ET) Submodule ............................................................................... 17.2.10 High-Resolution PWM (HRPWM) Submodule ............................................................ Applications to Power Topologies ..................................................................................... 17.3.1 Overview of Multiple Modules ................................................................................ 17.3.2 Key Configuration Capabilities ............................................................................... 17.3.3 Controlling Multiple Buck Converters With Independent Frequencies .................................. 17.3.4 Controlling Multiple Buck Converters With Same Frequencies .......................................... 17.3.5 Controlling Multiple Half H-Bridge (HHB) Converters ..................................................... 17.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ........................................ 17.3.7 Practical Applications Using Phase Control Between PWM Modules .................................. 17.3.8 Controlling a 3-Phase Interleaved DC/DC Converter ..................................................... 17.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter ..................................... Registers .................................................................................................................. 17.4.1 Time-Base Submodule Registers ............................................................................ 17.4.2 Counter-Compare Submodule Registers ................................................................... 17.4.3 Action-Qualifier Submodule Registers ...................................................................... 17.4.4 Dead-Band Generator Submodule Registers .............................................................. 17.4.5 PWM-Chopper Submodule Register ........................................................................ 17.4.6 Trip-Zone Submodule Registers ............................................................................. 17.4.7 Event-Trigger Submodule Registers ........................................................................ 17.4.8 High-Resolution PWM Submodule Registers .............................................................. Introduction ............................................................................................................... 18.1.1 Overview ........................................................................................................ 18.1.2 Features ......................................................................................................... 18.1.3 Functional Block Diagram ..................................................................................... 18.1.4 Terminology Used in This Document ........................................................................ Architecture ............................................................................................................... 18.2.1 Functional Overview ........................................................................................... 18.2.2 Types of EDMA3 Transfers ................................................................................... 18.2.3 Parameter RAM (PaRAM) .................................................................................... 18.2.4 Initiating a DMA Transfer ..................................................................................... 18.2.5 Completion of a DMA Transfer ............................................................................... 18.2.6 Event, Channel, and PaRAM Mapping ...................................................................... 18.2.7 EDMA3 Channel Controller Regions ........................................................................ 18.2.8 Chaining EDMA3 Channels .................................................................................. 18.2.9 EDMA3 Interrupts .............................................................................................. 18.2.10 Event Queue(s) ............................................................................................... 18.2.11 EDMA3 Transfer Controller (EDMA3TC) .................................................................. 18.2.12 Event Dataflow ................................................................................................ 18.2.13 EDMA3 Prioritization ......................................................................................... 18.2.14 EDMA3CC and EDMA3TC Performance and System Considerations ................................ 18.2.15 EDMA3 Operating Frequency (Clock Control) ............................................................ 18.2.16 Reset Considerations ........................................................................................

443 443 446 446 456 461 479 483 487 491 495 502 502 503 504 507 510 513 517 518 523 526 526 530 533 537 540 541 545 548 552 552 552 555 555 557 557 560 563 573 576 577 580 582 583 590 592 595 596 598 599 599

18

Enhanced Direct Memory Access (EDMA3) Controller
18.1

.......................................................... 551

18.2

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18.3

18.4

18.5

18.6

18.2.17 Power Management .......................................................................................... 18.2.18 Emulation Considerations ................................................................................... Transfer Examples ....................................................................................................... 18.3.1 Block Move Example .......................................................................................... 18.3.2 Subframe Extraction Example ................................................................................ 18.3.3 Data Sorting Example ......................................................................................... 18.3.4 Peripheral Servicing Example ................................................................................ Registers .................................................................................................................. 18.4.1 Parameter RAM (PaRAM) Entries ........................................................................... 18.4.2 EDMA3 Channel Controller (EDMA3CC) Registers ....................................................... 18.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers ....................................................... Tips ........................................................................................................................ 18.5.1 Debug Checklist ................................................................................................ 18.5.2 Miscellaneous Programming/Debug Tips ................................................................... Setting Up a Transfer .................................................................................................... Introduction ............................................................................................................... 19.1.1 Purpose of the Peripheral ..................................................................................... 19.1.2 Features ......................................................................................................... 19.1.3 Functional Block Diagram ..................................................................................... 19.1.4 Industry Standard(s) Compliance Statement ............................................................... 19.1.5 Terminology ..................................................................................................... Architecture ............................................................................................................... 19.2.1 Clock Control ................................................................................................... 19.2.2 Memory Map .................................................................................................... 19.2.3 Signal Descriptions ............................................................................................ 19.2.4 Ethernet Protocol Overview .................................................................................. 19.2.5 Programming Interface ........................................................................................ 19.2.6 EMAC Control Module ........................................................................................ 19.2.7 MDIO Module ................................................................................................... 19.2.8 EMAC Module .................................................................................................. 19.2.9 MAC Interface .................................................................................................. 19.2.10 Packet Receive Operation .................................................................................. 19.2.11 Packet Transmit Operation .................................................................................. 19.2.12 Receive and Transmit Latency ............................................................................. 19.2.13 Transfer Node Priority ....................................................................................... 19.2.14 Reset Considerations ........................................................................................ 19.2.15 Initialization .................................................................................................... 19.2.16 Interrupt Support .............................................................................................. 19.2.17 Power Management .......................................................................................... 19.2.18 Emulation Considerations ................................................................................... Registers .................................................................................................................. 19.3.1 EMAC Control Module Registers ............................................................................ 19.3.2 MDIO Registers ................................................................................................ 19.3.3 EMAC Module Registers ......................................................................................

599 600 600 600 602 603 605 617 617 624 663 684 684 685 686 688 688 688 689 690 690 691 691 692 692 695 696 707 708 713 715 719 724 725 725 726 727 729 733 733 734 734 748 761

19

EMAC/MDIO Module
19.1

......................................................................................................... 687

19.2

19.3

20

External Memory Interface A (EMIFA)
20.1

20.2

................................................................................. 811 Introduction ............................................................................................................... 812 20.1.1 Purpose of the Peripheral ..................................................................................... 812 20.1.2 Features ......................................................................................................... 812 20.1.3 Functional Block Diagram ..................................................................................... 812 Architecture ............................................................................................................... 812 20.2.1 Clock Control ................................................................................................... 813 20.2.2 EMIFA Requests ............................................................................................... 813
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20.3

20.4

20.2.3 Pin Descriptions ................................................................................................ 20.2.4 SDRAM Controller and Interface ............................................................................. 20.2.5 Asynchronous Controller and Interface ..................................................................... 20.2.6 Data Bus Parking .............................................................................................. 20.2.7 Reset and Initialization Considerations ..................................................................... 20.2.8 Interrupt Support ............................................................................................... 20.2.9 EDMA Event Support .......................................................................................... 20.2.10 Pin Multiplexing ............................................................................................... 20.2.11 Memory Map .................................................................................................. 20.2.12 Priority and Arbitration ....................................................................................... 20.2.13 System Considerations ...................................................................................... 20.2.14 Power Management .......................................................................................... 20.2.15 Emulation Considerations ................................................................................... Example Configuration .................................................................................................. 20.3.1 Hardware Interface ............................................................................................ 20.3.2 Software Configuration ........................................................................................ Registers .................................................................................................................. 20.4.1 Module ID Register (MIDR) ................................................................................... 20.4.2 Asynchronous Wait Cycle Configuration Register (AWCC) .............................................. 20.4.3 SDRAM Configuration Register (SDCR) .................................................................... 20.4.4 SDRAM Refresh Control Register (SDRCR) ............................................................... 20.4.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG) .......................................... 20.4.6 SDRAM Timing Register (SDTIMR) ......................................................................... 20.4.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) ................................................. 20.4.8 EMIFA Interrupt Raw Register (INTRAW) .................................................................. 20.4.9 EMIFA Interrupt Masked Register (INTMSK) .............................................................. 20.4.10 EMIFA Interrupt Mask Set Register (INTMSKSET) ...................................................... 20.4.11 EMIFA Interrupt Mask Clear Register (INTMSKCLR) ................................................... 20.4.12 NAND Flash Control Register (NANDFCR) ............................................................... 20.4.13 NAND Flash Status Register (NANDFSR) ................................................................ 20.4.14 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) ......................................... 20.4.15 NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) ...................................... 20.4.16 NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) .................................................. 20.4.17 NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) .................................................. 20.4.18 NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) .................................................. 20.4.19 NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) .................................................. 20.4.20 NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) ................................ 20.4.21 NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) ................................ 20.4.22 NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) .................................... 20.4.23 NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) .................................... Introduction ............................................................................................................... 21.1.1 Purpose of the Peripheral ..................................................................................... 21.1.2 Features ......................................................................................................... 21.1.3 Functional Block Diagram ..................................................................................... 21.1.4 Industry Standard(s) Compliance Statement ............................................................... Architecture ............................................................................................................... 21.2.1 Clock Control ................................................................................................... 21.2.2 Signal Descriptions ............................................................................................ 21.2.3 Pin Multiplexing ................................................................................................ 21.2.4 Endianness Considerations .................................................................................. 21.2.5 GPIO Register Structure ...................................................................................... 21.2.6 Using a GPIO Signal as an Output ..........................................................................

813 815 827 845 845 846 847 847 847 848 849 850 851 852 852 852 874 875 875 877 879 880 881 882 883 884 885 886 887 889 890 891 892 892 893 893 894 894 895 895 898 898 898 898 898 899 899 899 899 899 900 903

21

General-Purpose Input/Output (GPIO)
21.1

................................................................................ 897

21.2

12

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21.3

21.2.7 Using a GPIO Signal as an Input ............................................................................ 21.2.8 Reset Considerations .......................................................................................... 21.2.9 Initialization ..................................................................................................... 21.2.10 Interrupt Support .............................................................................................. 21.2.11 EDMA Event Support ........................................................................................ 21.2.12 Power Management .......................................................................................... 21.2.13 Emulation Considerations ................................................................................... Registers .................................................................................................................. 21.3.1 Revision ID Register (REVID) ................................................................................ 21.3.2 GPIO Interrupt Per-Bank Enable Register (BINTEN) ..................................................... 21.3.3 GPIO Direction Registers (DIRn) ............................................................................ 21.3.4 GPIO Output Data Registers (OUT_DATAn) ............................................................... 21.3.5 GPIO Set Data Registers (SET_DATAn) ................................................................... 21.3.6 GPIO Clear Data Registers (CLR_DATAn) ................................................................ 21.3.7 GPIO Input Data Registers (IN_DATAn) .................................................................... 21.3.8 GPIO Set Rising Edge Interrupt Registers (SET_RIS_TRIGn) .......................................... 21.3.9 GPIO Clear Rising Edge Interrupt Registers (CLR_RIS_TRIGn) ....................................... 21.3.10 GPIO Set Falling Edge Interrupt Registers (SET_FAL_TRIGn) ........................................ 21.3.11 GPIO Clear Falling Edge Interrupt Registers (CLR_FAL_TRIGn) ..................................... 21.3.12 GPIO Interrupt Status Registers (INTSTATn) ............................................................ Introduction ............................................................................................................... 22.1.1 Purpose of the Peripheral ..................................................................................... 22.1.2 Features ......................................................................................................... 22.1.3 Functional Block Diagram ..................................................................................... 22.1.4 Industry Standard(s) Compliance Statement ............................................................... 22.1.5 Terminology Used in This Document ........................................................................ Architecture ............................................................................................................... 22.2.1 Clock Control ................................................................................................... 22.2.2 Memory Map .................................................................................................... 22.2.3 Signal Descriptions ............................................................................................ 22.2.4 Pin Multiplexing and General-Purpose I/O Control Blocks ............................................... 22.2.5 Protocol Description ........................................................................................... 22.2.6 Operation ........................................................................................................ 22.2.7 Reset Considerations .......................................................................................... 22.2.8 Initialization ..................................................................................................... 22.2.9 Interrupt Support ............................................................................................... 22.2.10 EDMA Event Support ........................................................................................ 22.2.11 Power Management .......................................................................................... 22.2.12 Emulation Considerations ................................................................................... Registers .................................................................................................................. 22.3.1 Revision Identification Register (REVID) ................................................................... 22.3.2 Power and Emulation Management Register (PWREMU_MGMT) ...................................... 22.3.3 GPIO Enable Register (GPIO_EN) .......................................................................... 22.3.4 GPIO Direction 1 Register (GPIO_DIR1) ................................................................... 22.3.5 GPIO Data 1 Register (GPIO_DAT1) ....................................................................... 22.3.6 GPIO Direction 2 Register (GPIO_DIR2) ................................................................... 22.3.7 GPIO Data 2 Register (GPIO_DAT2) ....................................................................... 22.3.8 Host Port Interface Control Register (HPIC) ............................................................... 22.3.9 Host Port Interface Write Address Register (HPIAW) ..................................................... 22.3.10 Host Port Interface Read Address Register (HPIAR) .................................................... Introduction

904 904 905 905 906 906 906 907 908 909 910 912 914 916 918 920 922 924 926 928 932 932 932 933 934 934 935 935 935 935 936 937 937 952 952 953 954 954 955 955 956 956 957 958 958 959 960 961 963 963

22

Host Port Interface (HPI)
22.1

................................................................................................... 931

22.2

22.3

23

Inter-Integrated Circuit (I2C) Module
23.1

................................................................................... 965 ............................................................................................................... 966
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23.2

23.3

23.1.1 Purpose of the Peripheral ..................................................................................... 966 23.1.2 Features ......................................................................................................... 966 23.1.3 Functional Block Diagram ..................................................................................... 967 23.1.4 Industry Standard(s) Compliance Statement ............................................................... 967 Architecture ............................................................................................................... 968 23.2.1 Bus Structure ................................................................................................... 968 23.2.2 Clock Generation .............................................................................................. 969 23.2.3 Clock Synchronization ......................................................................................... 970 23.2.4 Signal Descriptions ............................................................................................ 970 23.2.5 START and STOP Conditions ................................................................................ 971 23.2.6 Serial Data Formats ........................................................................................... 972 23.2.7 Operating Modes ............................................................................................... 974 23.2.8 NACK Bit Generation .......................................................................................... 975 23.2.9 Arbitration ....................................................................................................... 976 23.2.10 Reset Considerations ........................................................................................ 977 23.2.11 Initialization .................................................................................................... 977 23.2.12 Interrupt Support .............................................................................................. 978 23.2.13 DMA Events Generated by the I2C Peripheral ........................................................... 979 23.2.14 Power Management .......................................................................................... 979 23.2.15 Emulation Considerations ................................................................................... 979 Registers .................................................................................................................. 980 23.3.1 I2C Own Address Register (ICOAR) ........................................................................ 981 23.3.2 I2C Interrupt Mask Register (ICIMR) ........................................................................ 982 23.3.3 I2C Interrupt Status Register (ICSTR) ...................................................................... 983 23.3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH) ...................................................... 986 23.3.5 I2C Data Count Register (ICCNT) ........................................................................... 987 23.3.6 I2C Data Receive Register (ICDRR) ........................................................................ 988 23.3.7 I2C Slave Address Register (ICSAR) ....................................................................... 989 23.3.8 I2C Data Transmit Register (ICDXR) ........................................................................ 990 23.3.9 I2C Mode Register (ICMDR) ................................................................................. 991 23.3.10 I2C Interrupt Vector Register (ICIVR) ...................................................................... 995 23.3.11 I2C Extended Mode Register (ICEMDR) .................................................................. 996 23.3.12 I2C Prescaler Register (ICPSC) ............................................................................ 997 23.3.13 I2C Revision Identification Register (REVID1) ........................................................... 998 23.3.14 I2C Revision Identification Register (REVID2) ........................................................... 998 23.3.15 I2C DMA Control Register (ICDMAC) ..................................................................... 999 23.3.16 I2C Pin Function Register (ICPFUNC) ................................................................... 1000 23.3.17 I2C Pin Direction Register (ICPDIR) ..................................................................... 1001 23.3.18 I2C Pin Data In Register (ICPDIN) ....................................................................... 1002 23.3.19 I2C Pin Data Out Register (ICPDOUT) .................................................................. 1003 23.3.20 I2C Pin Data Set Register (ICPDSET) ................................................................... 1004 23.3.21 I2C Pin Data Clear Register (ICPDCLR) ................................................................ 1005

24

Liquid Crystal Display Controller (LCDC)
24.1

.......................................................................... 1007
1008 1008 1009 1009 1009 1009 1011 1012 1013 1015

24.2

Introduction .............................................................................................................. 24.1.1 Purpose of the Peripheral ................................................................................... 24.1.2 Features ....................................................................................................... 24.1.3 Terminology ................................................................................................... Architecture .............................................................................................................. 24.2.1 Clocking ........................................................................................................ 24.2.2 LCD External I/O Signals .................................................................................... 24.2.3 DMA Engine ................................................................................................... 24.2.4 LIDD Controller ............................................................................................... 24.2.5 Raster Controller .............................................................................................

14

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24.3

Registers ................................................................................................................. 24.3.1 LCD Revision Identification Register (REVID) ............................................................ 24.3.2 LCD Control Register (LCD_CTRL) ........................................................................ 24.3.3 LCD Status Register (LCD_STAT) ......................................................................... 24.3.4 LCD LIDD Control Register (LIDD_CTRL) ................................................................ 24.3.5 LCD LIDD CSn Configuration Registers (LIDD_CS0_CONF and LIDD_CS1_CONF) .............. 24.3.6 LCD LIDD CSn Address Read/Write Registers (LIDD_CS0_ADDR and LIDD_CS1_ADDR) ..... 24.3.7 LCD LIDD CSn Data Read/Write Registers (LIDD_CS0_DATA and LIDD_CS1_DATA) ........... 24.3.8 LCD Raster Control Register (RASTER_CTRL) ......................................................... 24.3.9 LCD Raster Timing Register 0 (RASTER_TIMING_0) .................................................. 24.3.10 LCD Raster Timing Register 1 (RASTER_TIMING_1) ................................................. 24.3.11 LCD Raster Timing Register 2 (RASTER_TIMING_2) ................................................. 24.3.12 LCD Raster Subpanel Display Register (RASTER_SUBPANEL) .................................... 24.3.13 LCD DMA Control Register (LCDDMA_CTRL) ......................................................... 24.3.14 LCD DMA Frame Buffer n Base Address Registers (LCDDMA_FB0_BASE and LCDDMA_FB1_BASE) ...................................................... 24.3.15 LCD DMA Frame Buffer n Ceiling Address Registers (LCDDMA_FB0_CEILING and LCDDMA_FB1_CEILING) ............................................... Introduction .............................................................................................................. 25.1.1 Purpose of the Peripheral ................................................................................... 25.1.2 Features ....................................................................................................... 25.1.3 Protocols Supported ......................................................................................... 25.1.4 Functional Block Diagram ................................................................................... 25.1.5 Industry Standard Compliance Statement ................................................................ 25.1.6 Definition of Terms ........................................................................................... Architecture .............................................................................................................. 25.2.1 Overview ....................................................................................................... 25.2.2 Clock and Frame Sync Generators ........................................................................ 25.2.3 General Architecture ......................................................................................... 25.2.4 Operation ...................................................................................................... 25.2.5 Reset Considerations ........................................................................................ 25.2.6 EDMA Event Support ........................................................................................ 25.2.7 Power Management .......................................................................................... Registers ................................................................................................................. 25.3.1 Register Bit Restrictions ..................................................................................... 25.3.2 Revision Identification Register (REV) ..................................................................... 25.3.3 Pin Function Register (PFUNC) ............................................................................ 25.3.4 Pin Direction Register (PDIR) ............................................................................... 25.3.5 Pin Data Output Register (PDOUT) ........................................................................ 25.3.6 Pin Data Input Register (PDIN) ............................................................................. 25.3.7 Pin Data Set Register (PDSET) ............................................................................ 25.3.8 Pin Data Clear Register (PDCLR) .......................................................................... 25.3.9 Global Control Register (GBLCTL) ......................................................................... 25.3.10 Audio Mute Control Register (AMUTE) .................................................................. 25.3.11 Digital Loopback Control Register (DLBCTL) ........................................................... 25.3.12 Digital Mode Control Register (DITCTL) ................................................................. 25.3.13 Receiver Global Control Register (RGBLCTL) .......................................................... 25.3.14 Receive Format Unit Bit Mask Register (RMASK) ..................................................... 25.3.15 Receive Bit Stream Format Register (RFMT) ........................................................... 25.3.16 Receive Frame Sync Control Register (AFSRCTL) .................................................... 25.3.17 Receive Clock Control Register (ACLKRCTL) .......................................................... 25.3.18 Receive High-Frequency Clock Control Register (AHCLKRCTL) .................................... 25.3.19 Receive TDM Time Slot Register (RTDM) ..............................................................
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1025 1025 1026 1028 1030 1032 1033 1034 1035 1042 1044 1048 1052 1054 1055 1055 1058 1058 1058 1059 1060 1063 1068 1071 1071 1071 1075 1081 1112 1112 1112 1113 1116 1117 1117 1119 1121 1123 1125 1127 1129 1131 1133 1134 1135 1136 1137 1139 1140 1141 1142
15

25

Multichannel Audio Serial Port (McASP)
25.1

........................................................................... 1057

25.2

25.3

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25.3.20 25.3.21 25.3.22 25.3.23 25.3.24 25.3.25 25.3.26 25.3.27 25.3.28 25.3.29 25.3.30 25.3.31 25.3.32 25.3.33 25.3.34 25.3.35 25.3.36 25.3.37 25.3.38 25.3.39 25.3.40 25.3.41 25.3.42 25.3.43 25.3.44 25.3.45 25.3.46 25.3.47 25.3.48

Receiver Interrupt Control Register (RINTCTL) ......................................................... Receiver Status Register (RSTAT) ....................................................................... Current Receive TDM Time Slot Registers (RSLOT) .................................................. Receive Clock Check Control Register (RCLKCHK) ................................................... Receiver DMA Event Control Register (REVTCTL) .................................................... Transmitter Global Control Register (XGBLCTL) ....................................................... Transmit Format Unit Bit Mask Register (XMASK) ..................................................... Transmit Bit Stream Format Register (XFMT) .......................................................... Transmit Frame Sync Control Register (AFSXCTL) ................................................... Transmit Clock Control Register (ACLKXCTL) ......................................................... Transmit High-Frequency Clock Control Register (AHCLKXCTL) ................................... Transmit TDM Time Slot Register (XTDM) .............................................................. Transmitter Interrupt Control Register (XINTCTL) ...................................................... Transmitter Status Register (XSTAT) .................................................................... Current Transmit TDM Time Slot Register (XSLOT) ................................................... Transmit Clock Check Control Register (XCLKCHK) .................................................. Transmitter DMA Event Control Register (XEVTCTL) ................................................. Serializer Control Registers (SRCTLn) .................................................................. DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) ......................................... DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) ....................................... DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) .................................... DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) .................................. Transmit Buffer Registers (XBUFn) ...................................................................... Receive Buffer Registers (RBUFn) ....................................................................... AFIFO Revision Identification Register (AFIFOREV) .................................................. Write FIFO Control Register (WFIFOCTL) .............................................................. Write FIFO Status Register (WFIFOSTS) ............................................................... Read FIFO Control Register (RFIFOCTL) ............................................................... Read FIFO Status Register (RFIFOSTS) ................................................................

1143 1144 1145 1146 1147 1148 1149 1150 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1162 1163 1163 1164 1164 1165 1166 1167 1168 1169 1172 1172 1172 1173 1173 1174 1174 1174 1174 1174 1175 1189 1189 1203 1205 1213 1213 1214 1218 1219 1220 1220 1221

26

Multichannel Buffered Serial Port (McBSP)
26.1

....................................................................... 1171

26.2

26.3
16

Introduction .............................................................................................................. 26.1.1 Purpose of the Peripheral ................................................................................... 26.1.2 Features ....................................................................................................... 26.1.3 Functional Block Diagram ................................................................................... 26.1.4 Industry Standard Compliance Statement ................................................................ Architecture .............................................................................................................. 26.2.1 Clock Control .................................................................................................. 26.2.2 Signal Descriptions ........................................................................................... 26.2.3 Pin Multiplexing ............................................................................................... 26.2.4 Endianness Considerations ................................................................................. 26.2.5 Clock, Frames, and Data .................................................................................... 26.2.6 McBSP Buffer FIFO (BFIFO) ............................................................................... 26.2.7 McBSP Standard Operation ................................................................................ 26.2.8 μ-Law/A-Law Companding Hardware Operation ......................................................... 26.2.9 Multichannel Selection Modes .............................................................................. 26.2.10 SPI Operation Using the Clock Stop Mode .............................................................. 26.2.11 Resetting the Serial Port: RRST, XRST, GRST, and RESET ........................................ 26.2.12 McBSP Initialization Procedure ........................................................................... 26.2.13 Interrupt Support ............................................................................................ 26.2.14 EDMA Event Support ....................................................................................... 26.2.15 Power Management ........................................................................................ 26.2.16 Emulation Considerations .................................................................................. Registers .................................................................................................................

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26.3.1 26.3.2 26.3.3 26.3.4 26.3.5 26.3.6 26.3.7 26.3.8 26.3.9 26.3.10 26.3.11 26.3.12 26.3.13 26.3.14 26.3.15

Data Receive Register (DRR) .............................................................................. Data Transmit Register (DXR) .............................................................................. Serial Port Control Register (SPCR) ....................................................................... Receive Control Register (RCR) ........................................................................... Transmit Control Register (XCR) ........................................................................... Sample Rate Generator Register (SRGR) ................................................................ Multichannel Control Register (MCR) ...................................................................... Enhanced Receive Channel Enable Registers (RCERE0-RCERE3) .................................. Enhanced Transmit Channel Enable Registers (XCERE0-XCERE3) ................................. Pin Control Register (PCR) ................................................................................ BFIFO Revision Identification Register (BFIFOREV) .................................................. Write FIFO Control Register (WFIFOCTL) .............................................................. Write FIFO Status Register (WFIFOSTS) ............................................................... Read FIFO Control Register (RFIFOCTL) ............................................................... Read FIFO Status Register (RFIFOSTS) ................................................................

1222 1222 1223 1225 1227 1229 1230 1234 1236 1238 1240 1241 1242 1243 1244 1246 1246 1246 1246 1246 1247 1247 1248 1249 1249 1251 1253 1254 1256 1256 1258 1261 1262 1262 1262 1263 1263 1266 1268 1268 1270 1270 1272 1272 1274 1274 1275 1276 1277 1278 1280 1281
17

27

Multimedia Card (MMC)/Secure Digital (SD) Card Controller
27.1

................................................ 1245

27.2

27.3

27.4

Introduction .............................................................................................................. 27.1.1 Purpose of the Peripheral ................................................................................... 27.1.2 Features ....................................................................................................... 27.1.3 Functional Block Diagram ................................................................................... 27.1.4 Supported Use Case Statement ............................................................................ 27.1.5 Industry Standard(s) Compliance Statement ............................................................. Architecture .............................................................................................................. 27.2.1 Clock Control .................................................................................................. 27.2.2 Signal Descriptions ........................................................................................... 27.2.3 Protocol Descriptions ........................................................................................ 27.2.4 Data Flow in the Input/Output FIFO ........................................................................ 27.2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) .......................................... 27.2.6 FIFO Operation During Card Read Operation ............................................................ 27.2.7 FIFO Operation During Card Write Operation ............................................................ 27.2.8 Reset Considerations ........................................................................................ 27.2.9 Initialization .................................................................................................... 27.2.10 Interrupt Support ............................................................................................ 27.2.11 DMA Event Support ........................................................................................ 27.2.12 Power Management ........................................................................................ 27.2.13 Emulation Considerations .................................................................................. Procedures for Common Operations ................................................................................ 27.3.1 Card Identification Operation ............................................................................... 27.3.2 MMC/SD Mode Single-Block Write Operation Using CPU .............................................. 27.3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA ....................................... 27.3.4 MMC/SD Mode Single-Block Read Operation Using the CPU ......................................... 27.3.5 MMC/SD Mode Single-Block Read Operation Using EDMA ........................................... 27.3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU ............................................ 27.3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA .......................................... 27.3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU ............................................ 27.3.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA .......................................... 27.3.10 SDIO Card Function ........................................................................................ Registers ................................................................................................................. 27.4.1 MMC Control Register (MMCCTL) ......................................................................... 27.4.2 MMC Memory Clock Control Register (MMCCLK) ....................................................... 27.4.3 MMC Status Register 0 (MMCST0) ........................................................................ 27.4.4 MMC Status Register 1 (MMCST1) ........................................................................ 27.4.5 MMC Interrupt Mask Register (MMCIM) ..................................................................
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27.4.6 27.4.7 27.4.8 27.4.9 27.4.10 27.4.11 27.4.12 27.4.13 27.4.14 27.4.15 27.4.16 27.4.17 27.4.18 27.4.19 27.4.20 27.4.21 27.4.22

MMC Response Time-Out Register (MMCTOR) ......................................................... MMC Data Read Time-Out Register (MMCTOD) ........................................................ MMC Block Length Register (MMCBLEN) ................................................................ MMC Number of Blocks Register (MMCNBLK) .......................................................... MMC Number of Blocks Counter Register (MMCNBLC) .............................................. MMC Data Receive Register (MMCDRR) ............................................................... MMC Data Transmit Register (MMCDXR) ............................................................... MMC Command Register (MMCCMD) ................................................................... MMC Argument Register (MMCARGHL) ................................................................ MMC Response Registers (MMCRSP0-MMCRSP7) .................................................. MMC Data Response Register (MMCDRSP) ........................................................... MMC Command Index Register (MMCCIDX) ........................................................... SDIO Control Register (SDIOCTL) ....................................................................... SDIO Status Register 0 (SDIOST0) ...................................................................... SDIO Interrupt Enable Register (SDIOIEN) ............................................................. SDIO Interrupt Status Register (SDIOIST) .............................................................. MMC FIFO Control Register (MMCFIFOCTL) ..........................................................

1283 1284 1285 1286 1286 1287 1287 1288 1290 1291 1293 1293 1294 1295 1296 1296 1297 1300 1300 1300 1300 1301 1301 1301 1301 1302 1304 1305 1306 1306 1306 1306 1307 1308 1308 1309 1310 1310 1311 1311 1312 1312 1313 1314 1315 1315 1316 1317 1318 1319 1320 1321

28

Real-Time Clock (RTC)
28.1

.................................................................................................... 1299

28.2

28.3

Introduction .............................................................................................................. 28.1.1 Purpose of the Peripheral ................................................................................... 28.1.2 Features ....................................................................................................... 28.1.3 Block Diagram ................................................................................................ Architecture .............................................................................................................. 28.2.1 Clock Source .................................................................................................. 28.2.2 Signal Descriptions ........................................................................................... 28.2.3 Isolated Power Supply ....................................................................................... 28.2.4 Operation ...................................................................................................... 28.2.5 Interrupt Requests ............................................................................................ 28.2.6 Register Protection Against Spurious Writes ............................................................. 28.2.7 General-Purpose Scratch Registers ....................................................................... 28.2.8 Real-Time Clock Response to Low Power Modes (Idle Configurations) .............................. 28.2.9 Emulation Modes of the Real-Time Clock ................................................................. 28.2.10 Reset Considerations ....................................................................................... Registers ................................................................................................................. 28.3.1 Second Register (SECOND) ................................................................................ 28.3.2 Minute Register (MINUTE) .................................................................................. 28.3.3 Hour Register (HOUR) ....................................................................................... 28.3.4 Day of the Month Register (DAY) .......................................................................... 28.3.5 Month Register (MONTH) ................................................................................... 28.3.6 Year Register (YEAR) ....................................................................................... 28.3.7 Day of the Week Register (DOTW) ........................................................................ 28.3.8 Alarm Second Register (ALARMSECOND) ............................................................... 28.3.9 Alarm Minute Register (ALARMMINUTE) ................................................................. 28.3.10 Alarm Hour Register (ALARMHOUR) .................................................................... 28.3.11 Alarm Day of the Month Register (ALARMDAY) ........................................................ 28.3.12 Alarm Month Register (ALARMMONTH) ................................................................ 28.3.13 Alarm Year Register (ALARMYEAR) ..................................................................... 28.3.14 Control Register (CTRL) ................................................................................... 28.3.15 Status Register (STATUS) ................................................................................. 28.3.16 Interrupt Register (INTERRUPT) ......................................................................... 28.3.17 Compensation (LSB) Register (COMPLSB) ............................................................. 28.3.18 Compensation (MSB) Register (COMPMSB) ........................................................... 28.3.19 Oscillator Register (OSC) ..................................................................................

18

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28.3.20 Scratch Registers (SCRATCH0-SCRATCH2) .......................................................... 1322 28.3.21 Kick Registers (KICK0R, KICK1R) ....................................................................... 1322

29

Serial ATA (SATA) Controller
29.1

........................................................................................... 1323
1324 1324 1324 1325 1325 1326 1327 1328 1328 1329 1329 1329 1330 1330 1330 1331 1331 1331 1332 1333 1333 1333 1334 1348 1350 1351 1353 1355 1356 1357 1358 1358 1359 1360 1361 1362 1364 1364 1365 1365 1366 1367 1368 1369 1370 1370 1371 1371 1372 1374
19

29.2

29.3

29.4

Introduction .............................................................................................................. 29.1.1 Purpose of the Peripheral ................................................................................... 29.1.2 Features Supported .......................................................................................... 29.1.3 Features Not Supported ..................................................................................... 29.1.4 Functional Block Diagram ................................................................................... 29.1.5 Terminology Used in this Document ....................................................................... 29.1.6 Industry Standard(s) Compliance .......................................................................... Architecture .............................................................................................................. 29.2.1 Clock Control .................................................................................................. 29.2.2 Signal Description ............................................................................................ 29.2.3 Pin Multiplexing ............................................................................................... 29.2.4 Interfacing to Single and Multiple Devices ................................................................ 29.2.5 DMA ............................................................................................................ 29.2.6 Transport Layer ............................................................................................... 29.2.7 Link Layer ..................................................................................................... 29.2.8 Phy ............................................................................................................. 29.2.9 Reset ........................................................................................................... 29.2.10 Initialization .................................................................................................. 29.2.11 Interrupt Support ............................................................................................ 29.2.12 EDMA Event Support ....................................................................................... 29.2.13 Power Management ........................................................................................ Use Cases ............................................................................................................... 29.3.1 General Utilities: Structures and Subroutines Sample Program Uses ................................ 29.3.2 Example on Initialization and Spinning Up Device ....................................................... 29.3.3 Example of DMA Write Transfer ............................................................................ 29.3.4 Example of DMA Read Transfer ........................................................................... Registers ................................................................................................................. 29.4.1 HBA Capabilities Register (CAP) ........................................................................... 29.4.2 Global HBA Control Register (GHC) ....................................................................... 29.4.3 Interrupt Status Register (IS) ............................................................................... 29.4.4 Ports Implemented Register (PI) ........................................................................... 29.4.5 AHCI Version Register (VS) ................................................................................ 29.4.6 Command Completion Coalescing Control Register (CCC_CTL) ..................................... 29.4.7 Command Completion Coalescing Ports Register (CCC_PORTS) .................................... 29.4.8 BIST Active FIS Register (BISTAFR) ...................................................................... 29.4.9 BIST Control Register (BISTCR) ........................................................................... 29.4.10 BIST FIS Count Register (BISTFCTR) ................................................................... 29.4.11 BIST Status Register (BISTSR) ........................................................................... 29.4.12 BIST DWORD Error Count Register (BISTDECR) ..................................................... 29.4.13 BIST DWORD Error Count Register (TIMER1MS) ..................................................... 29.4.14 Global Parameter 1 Register (GPARAM1R) ............................................................ 29.4.15 Global Parameter 2 Register (GPARAM2R) ............................................................ 29.4.16 Port Parameter Register (PPARAMR) ................................................................... 29.4.17 Test Register (TESTR) ..................................................................................... 29.4.18 Version Register (VERSIONR) ............................................................................ 29.4.19 ID Register (IDR) ............................................................................................ 29.4.20 Port Command List Base Address Register (P0CLB) .................................................. 29.4.21 Port FIS Base Address Register (P0FB) ................................................................. 29.4.22 Port Interrupt Status Register (P0IS) ..................................................................... 29.4.23 Port Interrupt Enable Register (P0IE) ....................................................................
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29.4.24 29.4.25 29.4.26 29.4.27 29.4.28 29.4.29 29.4.30 29.4.31 29.4.32 29.4.33 29.4.34 29.4.35

Port Port Port Port Port Port Port Port Port Port Port Port

Command Register (P0CMD) ....................................................................... Task File Data Register (P0TFD) ................................................................... Signature Register (P0SIG) .......................................................................... Serial ATA Status (SStatus) Register (P0SSTS) ................................................. Serial ATA Control (SControl) Register (P0SCTL) ............................................... Serial ATA Error (SError) Register (P0SERR) .................................................... Serial ATA Active (SActive) Register (P0SACT) .................................................. Command Issue Register (P0CI) ................................................................... Serial ATA Notification Register (P0SNTF) ........................................................ DMA Control Register (P0DMACR) ................................................................ PHY Control Register (P0PHYCR) ................................................................. PHY Status Register (P0PHYSR) ...................................................................

1375 1378 1378 1379 1380 1381 1383 1383 1384 1385 1387 1391 1394 1394 1394 1395 1395 1396 1396 1396 1396 1397 1398 1400 1401 1402 1404 1406 1408 1411 1412 1412 1414 1414 1415 1415 1415 1416 1422 1422 1423 1425 1427 1428 1430 1431 1432 1433 1434 1435 1436 1437

30

Serial Peripheral Interface (SPI)
30.1

....................................................................................... 1393

30.2

30.3

Introduction .............................................................................................................. 30.1.1 Purpose of the Peripheral ................................................................................... 30.1.2 Features ....................................................................................................... 30.1.3 Functional Block Diagram ................................................................................... 30.1.4 Industry Standard(s) Compliance Statement ............................................................. Architecture .............................................................................................................. 30.2.1 Clock ........................................................................................................... 30.2.2 Signal Descriptions ........................................................................................... 30.2.3 Operation Modes ............................................................................................. 30.2.4 Programmable Registers .................................................................................... 30.2.5 Master Mode Settings ........................................................................................ 30.2.6 Slave Mode Settings ......................................................................................... 30.2.7 SPI Operation: 3-Pin Mode ................................................................................. 30.2.8 SPI Operation: 4-Pin with Chip Select Mode ............................................................. 30.2.9 SPI Operation: 4-Pin with Enable Mode ................................................................... 30.2.10 SPI Operation: 5-Pin Mode ................................................................................ 30.2.11 Data Formats ................................................................................................ 30.2.12 Interrupt Support ............................................................................................ 30.2.13 DMA Events Support ....................................................................................... 30.2.14 Robustness Features ....................................................................................... 30.2.15 Reset Considerations ....................................................................................... 30.2.16 Power Management ........................................................................................ 30.2.17 General-Purpose I/O Pin ................................................................................... 30.2.18 Emulation Considerations .................................................................................. 30.2.19 Initialization .................................................................................................. 30.2.20 Timing Diagrams ............................................................................................ Registers ................................................................................................................. 30.3.1 SPI Global Control Register 0 (SPIGCR0) ................................................................ 30.3.2 SPI Global Control Register 1 (SPIGCR1) ................................................................ 30.3.3 SPI Interrupt Register (SPIINT0) ........................................................................... 30.3.4 SPI Interrupt Level Register (SPILVL) ..................................................................... 30.3.5 SPI Flag Register (SPIFLG) ................................................................................ 30.3.6 SPI Pin Control Register 0 (SPIPC0) ...................................................................... 30.3.7 SPI Pin Control Register 1 (SPIPC1) ...................................................................... 30.3.8 SPI Pin Control Register 2 (SPIPC2) ...................................................................... 30.3.9 SPI Pin Control Register 3 (SPIPC3) ...................................................................... 30.3.10 SPI Pin Control Register 4 (SPIPC4) .................................................................... 30.3.11 SPI Pin Control Register 5 (SPIPC5) .................................................................... 30.3.12 SPI Transmit Data Register 0 (SPIDAT0) ............................................................... 30.3.13 SPI Transmit Data Register 1 (SPIDAT1) ...............................................................

20

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30.3.14 30.3.15 30.3.16 30.3.17 30.3.18 30.3.19

SPI SPI SPI SPI SPI SPI

Receive Buffer Register (SPIBUF) .................................................................. Emulation Register (SPIEMU) ....................................................................... Delay Register (SPIDELAY) .......................................................................... Default Chip Select Register (SPIDEF) ............................................................. Data Format Registers (SPIFMTn) .................................................................. Interrupt Vector Register 1 (INTVEC1) .............................................................

1438 1440 1441 1444 1445 1447 1450 1450 1450 1451 1451 1451 1451 1463 1465 1465 1465 1466 1467 1467 1467 1467 1468 1469 1469 1470 1471 1472 1473 1474 1476 1477 1478 1478 1479 1479 1480 1481 1484 1484 1484 1484 1484 1486 1486 1488 1488 1488 1490 1494 1494
21

31

64-Bit Timer Plus
31.1

............................................................................................................ 1449

31.2

31.3

Introduction .............................................................................................................. 31.1.1 Purpose of the Peripheral ................................................................................... 31.1.2 Features ....................................................................................................... 31.1.3 Block Diagram ................................................................................................ 31.1.4 Industry Standard Compatibility Statement ............................................................... Architecture .............................................................................................................. 31.2.1 Architecture – General-Purpose Timer Mode ............................................................. 31.2.2 Architecture – Watchdog Timer Mode ..................................................................... 31.2.3 Reset Considerations ........................................................................................ 31.2.4 Interrupt Support .............................................................................................. 31.2.5 DMA Event Support .......................................................................................... 31.2.6 TM64P_OUT Event Support ................................................................................ 31.2.7 External Timer Pin GPIO Mode ............................................................................ 31.2.8 Interrupt/DMA Event Generation Control and Status .................................................... 31.2.9 Power Management .......................................................................................... 31.2.10 Emulation Considerations .................................................................................. Registers ................................................................................................................. 31.3.1 Revision ID Register (REVID) .............................................................................. 31.3.2 Emulation Management Register (EMUMGT) ............................................................ 31.3.3 GPIO Interrupt Control and Enable Register (GPINTGPEN) ........................................... 31.3.4 GPIO Data and Direction Register (GPDATGPDIR) ..................................................... 31.3.5 Timer Counter Registers (TIM12 and TIM34) ............................................................ 31.3.6 Timer Period Registers (PRD12 and PRD34) ............................................................ 31.3.7 Timer Control Register (TCR) .............................................................................. 31.3.8 Timer Global Control Register (TGCR) .................................................................... 31.3.9 Watchdog Timer Control Register (WDTCR) ............................................................. 31.3.10 Timer Reload Register 12 (REL12) ....................................................................... 31.3.11 Timer Reload Register 34 (REL34) ....................................................................... 31.3.12 Timer Capture Register 12 (CAP12) ..................................................................... 31.3.13 Timer Capture Register 34 (CAP34) ..................................................................... 31.3.14 Timer Interrupt Control and Status Register (INTCTLSTAT) .......................................... 31.3.15 Timer Compare Registers (CMP0-CMP7) ............................................................... Introduction .............................................................................................................. 32.1.1 Purpose of the Peripheral ................................................................................... 32.1.2 Features ....................................................................................................... 32.1.3 Functional Block Diagram ................................................................................... 32.1.4 Industry Standard(s) Compliance Statement ............................................................. Peripheral Architecture ................................................................................................ 32.2.1 Clock Generation and Control .............................................................................. 32.2.2 Signal Descriptions ........................................................................................... 32.2.3 Pin Multiplexing ............................................................................................... 32.2.4 Protocol Description .......................................................................................... 32.2.5 Operation ...................................................................................................... 32.2.6 Reset Considerations ........................................................................................ 32.2.7 Initialization ....................................................................................................
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32

Universal Asynchronous Receiver/Transmitter (UART)
32.1

....................................................... 1483

32.2

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32.3

32.2.8 Interrupt Support .............................................................................................. 32.2.9 DMA Event Support .......................................................................................... 32.2.10 Power Management ........................................................................................ 32.2.11 Emulation Considerations .................................................................................. 32.2.12 Exception Processing ...................................................................................... Registers ................................................................................................................. 32.3.1 Receiver Buffer Register (RBR) ............................................................................ 32.3.2 Transmitter Holding Register (THR) ....................................................................... 32.3.3 Interrupt Enable Register (IER) ............................................................................. 32.3.4 Interrupt Identification Register (IIR) ....................................................................... 32.3.5 FIFO Control Register (FCR) ............................................................................... 32.3.6 Line Control Register (LCR) ................................................................................ 32.3.7 Modem Control Register (MCR) ............................................................................ 32.3.8 Line Status Register (LSR) .................................................................................. 32.3.9 Modem Status Register (MSR) ............................................................................. 32.3.10 Scratch Pad Register (SCR) .............................................................................. 32.3.11 Divisor Latches (DLL and DLH) ........................................................................... 32.3.12 Revision Identification Registers (REVID1 and REVID2) .............................................. 32.3.13 Power and Emulation Management Register (PWREMU_MGMT) ................................... 32.3.14 Mode Definition Register (MDR) .......................................................................... Introduction .............................................................................................................. 33.1.1 Purpose of the Peripheral ................................................................................... 33.1.2 Features ....................................................................................................... 33.1.3 Functional Block Diagram ................................................................................... Architecture .............................................................................................................. 33.2.1 Clock Generation and Control .............................................................................. 33.2.2 Signal Description ............................................................................................ 33.2.3 Pin Multiplexing ............................................................................................... 33.2.4 Internal DMA Controller Description ....................................................................... 33.2.5 Protocol Description .......................................................................................... 33.2.6 Initialization and Operation .................................................................................. 33.2.7 Reset Considerations ........................................................................................ 33.2.8 Interrupt Support .............................................................................................. 33.2.9 Power Management .......................................................................................... 33.2.10 Emulation Considerations .................................................................................. 33.2.11 Transmit and Receive FIFOs .............................................................................. Registers ................................................................................................................. 33.3.1 uPP Peripheral Identification Register (UPPID) .......................................................... 33.3.2 uPP Peripheral Control Register (UPPCR) ............................................................... 33.3.3 uPP Digital Loopback Register (UPDLB) .................................................................. 33.3.4 uPP Channel Control Register (UPCTL) .................................................................. 33.3.5 uPP Interface Configuration Register (UPICR) ........................................................... 33.3.6 uPP Interface Idle Value Register (UPIVR) ............................................................... 33.3.7 uPP Threshold Configuration Register (UPTCR) ........................................................ 33.3.8 uPP Interrupt Raw Status Register (UPISR) .............................................................. 33.3.9 uPP Interrupt Enabled Status Register (UPIER) ......................................................... 33.3.10 uPP Interrupt Enable Set Register (UPIES) ............................................................. 33.3.11 uPP Interrupt Enable Clear Register (UPIEC) .......................................................... 33.3.12 uPP End of Interrupt Register (UPEOI) .................................................................. 33.3.13 uPP DMA Channel I Descriptor 0 Register (UPID0) ................................................... 33.3.14 uPP DMA Channel I Descriptor 1 Register (UPID1) ................................................... 33.3.15 uPP DMA Channel I Descriptor 2 Register (UPID2) ...................................................

1494 1496 1496 1496 1496 1497 1498 1499 1500 1501 1502 1504 1506 1507 1510 1511 1511 1513 1514 1515 1518 1518 1518 1518 1521 1521 1522 1523 1523 1526 1531 1536 1536 1537 1537 1537 1538 1538 1539 1540 1541 1543 1545 1546 1547 1549 1551 1553 1555 1555 1556 1556

33

Universal Parallel Port (uPP) ............................................................................................ 1517
33.1

33.2

33.3

22

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33.3.16 33.3.17 33.3.18 33.3.19 33.3.20 33.3.21 33.3.22 33.3.23 33.3.24

uPP uPP uPP uPP uPP uPP uPP uPP uPP

DMA DMA DMA DMA DMA DMA DMA DMA DMA

Channel Channel Channel Channel Channel Channel Channel Channel Channel

I Status 0 Register (UPIS0) ........................................................ I Status 1 Register (UPIS1) ........................................................ I Status 2 Register (UPIS2) ........................................................ Q Descriptor 0 Register (UPQD0) ................................................. Q Descriptor 1 Register (UPQD1) ................................................. Q Descriptor 2 Register (UPQD2) ................................................. Q Status 0 Register (UPQS0) ..................................................... Q Status 1 Register (UPQS1) ..................................................... Q Status 2 Register (UPQS2) .....................................................

1557 1557 1558 1559 1559 1560 1561 1561 1562 1564 1564 1565 1565 1566 1566 1567 1568 1568 1568 1569 1570 1570 1572 1573 1574 1575 1576 1576 1577 1577 1578 1578 1579 1579 1580 1580 1581 1581 1582 1583 1584 1585 1587 1590 1590 1590 1590 1591 1591 1591 1593
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34

Universal Serial Bus OHCI Host Controller
34.1 34.2

........................................................................ 1563

34.3

Introduction .............................................................................................................. 34.1.1 Purpose of the Peripheral ................................................................................... Architecture .............................................................................................................. 34.2.1 Clock and Reset .............................................................................................. 34.2.2 Open Host Controller Interface Functionality ............................................................. 34.2.3 Differences From OHCI Specification for USB ........................................................... 34.2.4 Implementation of OHCI Specification for USB1.1 ....................................................... 34.2.5 OHCI Interrupts ............................................................................................... 34.2.6 USB1.1 Host Controller Access to System Memory ..................................................... 34.2.7 Physical Addressing .......................................................................................... Registers ................................................................................................................. 34.3.1 OHCI Revision Number Register (HCREVISION) ....................................................... 34.3.2 HC Operating Mode Register (HCCONTROL) ........................................................... 34.3.3 HC Command and Status Register (HCCOMMANDSTATUS) ......................................... 34.3.4 HC Interrupt and Status Register (HCINTERRUPTSTATUS) .......................................... 34.3.5 HC Interrupt Enable Register (HCINTERRUPTENABLE) .............................................. 34.3.6 HC Interrupt Disable Register (HCINTERRUPTDISABLE) ............................................. 34.3.7 HC HCAA Address Register (HCHCCA) .................................................................. 34.3.8 HC Current Periodic Register (HCPERIODCURRENTED) ............................................. 34.3.9 HC Head Control Register (HCCONTROLHEADED) ................................................... 34.3.10 HC Current Control Register (HCCONTROLCURRENTED) .......................................... 34.3.11 HC Head Bulk Register (HCBULKHEADED) ............................................................ 34.3.12 HC Current Bulk Register (HCBULKCURRENTED) ................................................... 34.3.13 HC Head Done Register (HCDONEHEAD) ............................................................. 34.3.14 HC Frame Interval Register (HCFMINTERVAL) ........................................................ 34.3.15 HC Frame Remaining Register (HCFMREMAINING) .................................................. 34.3.16 HC Frame Number Register (HCFMNUMBER) ......................................................... 34.3.17 HC Periodic Start Register (HCPERIODICSTART) .................................................... 34.3.18 HC Low-Speed Threshold Register (HCLSTHRESHOLD) ............................................ 34.3.19 HC Root Hub A Register (HCRHDESCRIPTORA) ..................................................... 34.3.20 HC Root Hub B Register (HCRHDESCRIPTORB) ..................................................... 34.3.21 HC Root Hub Status Register (HCRHSTATUS) ........................................................ 34.3.22 HC Port 1 Status and Control Register (HCRHPORTSTATUS1) .................................... 34.3.23 HC Port 2 Status and Control Register (HCRHPORTSTATUS2) .................................... Introduction .............................................................................................................. 35.1.1 Purpose of the Peripheral ................................................................................... 35.1.2 Features ....................................................................................................... 35.1.3 Functional Block Diagram ................................................................................... 35.1.4 Industry Standard(s) Compliance Statement ............................................................. Architecture .............................................................................................................. 35.2.1 Clock Control .................................................................................................. 35.2.2 Signal Descriptions ...........................................................................................
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35

Universal Serial Bus 2.0 (USB) Controller
35.1

.......................................................................... 1589

35.2

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35.3

35.4

35.2.3 Indexed and Non-Indexed Registers ....................................................................... 35.2.4 USB PHY Initialization ....................................................................................... 35.2.5 VBUS Voltage Sourcing Control ............................................................................ 35.2.6 Dynamic FIFO Sizing ........................................................................................ 35.2.7 USB Controller Host and Peripheral Modes Operation .................................................. 35.2.8 Communications Port Programming Interface (CPPI) 4.1 DMA Overview ........................... 35.2.9 Test Modes .................................................................................................... 35.2.10 Reset Considerations ....................................................................................... 35.2.11 Interrupt Support ............................................................................................ 35.2.12 DMA Event Support ........................................................................................ 35.2.13 Power Management ........................................................................................ Use Cases ............................................................................................................... 35.3.1 User Case 1: Example of How to Initialize the USB Controller ........................................ 35.3.2 User Case 2: Example of How to Program the USB Endpoints in Peripheral Mode ................ 35.3.3 User Case 3: Example of How to Program the USB Endpoints in Host Mode ....................... 35.3.4 User Case 4: Example of How to Program the USB DMA Controller ................................. Registers ................................................................................................................. 35.4.1 Revision Identification Register (REVID) .................................................................. 35.4.2 Control Register (CTRLR) ................................................................................... 35.4.3 Status Register (STATR) .................................................................................... 35.4.4 Emulation Register (EMUR) ................................................................................ 35.4.5 Mode Register (MODE) ...................................................................................... 35.4.6 Auto Request Register (AUTOREQ) ....................................................................... 35.4.7 SRP Fix Time Register (SRPFIXTIME) ................................................................... 35.4.8 Teardown Register (TEARDOWN) ......................................................................... 35.4.9 USB Interrupt Source Register (INTSRCR) ............................................................... 35.4.10 USB Interrupt Source Set Register (INTSETR) ......................................................... 35.4.11 USB Interrupt Source Clear Register (INTCLRR) ...................................................... 35.4.12 USB Interrupt Mask Register (INTMSKR) ............................................................... 35.4.13 USB Interrupt Mask Set Register (INTMSKSETR) ..................................................... 35.4.14 USB Interrupt Mask Clear Register (INTMSKCLRR) .................................................. 35.4.15 USB Interrupt Source Masked Register (INTMASKEDR) ............................................. 35.4.16 USB End of Interrupt Register (EOIR) ................................................................... 35.4.17 Generic RNDIS EP1 Size Register (GENRNDISSZ1) ................................................. 35.4.18 Generic RNDIS EP2 Size Register (GENRNDISSZ2) ................................................. 35.4.19 Generic RNDIS EP3 Size Register (GENRNDISSZ3) ................................................. 35.4.20 Generic RNDIS EP4 Size Register (GENRNDISSZ4) ................................................. 35.4.21 Function Address Register (FADDR) ..................................................................... 35.4.22 Power Management Register (POWER) ................................................................. 35.4.23 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) ........................ 35.4.24 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) ............................................ 35.4.25 Interrupt Enable Register for INTRTX (INTRTXE) ...................................................... 35.4.26 Interrupt Enable Register for INTRRX (INTRRXE) ..................................................... 35.4.27 Interrupt Register for Common USB Interrupts (INTRUSB) ........................................... 35.4.28 Interrupt Enable Register for INTRUSB (INTRUSBE) ................................................. 35.4.29 Frame Number Register (FRAME) ....................................................................... 35.4.30 Index Register for Selecting the Endpoint Status and Control Registers (INDEX) ................. 35.4.31 Register to Enable the USB 2.0 Test Modes (TESTMODE) .......................................... 35.4.32 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) .......................... 35.4.33 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ......................... 35.4.34 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ............................... 35.4.35 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) ......................... 35.4.36 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ...............................

1593 1594 1594 1594 1595 1631 1655 1657 1657 1657 1657 1658 1658 1662 1663 1665 1670 1677 1677 1678 1678 1679 1681 1682 1682 1683 1684 1685 1686 1687 1688 1689 1690 1690 1691 1691 1692 1692 1693 1694 1695 1696 1696 1697 1698 1698 1699 1699 1700 1701 1702 1703 1704

24

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35.4.37 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) .......................... 35.4.38 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ......................... 35.4.39 Control Status Register for Host Receive Endpoint (HOST_RXCSR) ............................... 35.4.40 Count 0 Register (COUNT0) .............................................................................. 35.4.41 Receive Count Register (RXCOUNT) .................................................................... 35.4.42 Type Register (Host mode only) (HOST_TYPE0) ...................................................... 35.4.43 Transmit Type Register (Host mode only) (HOST_TXTYPE) ......................................... 35.4.44 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) .......................................... 35.4.45 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ................................ 35.4.46 Receive Type Register (Host mode only) (HOST_RXTYPE) ......................................... 35.4.47 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) ................................ 35.4.48 Configuration Data Register (CONFIGDATA) ........................................................... 35.4.49 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) ........................................ 35.4.50 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) ........................................ 35.4.51 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) ........................................ 35.4.52 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) ........................................ 35.4.53 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) ........................................ 35.4.54 Device Control Register (DEVCTL) ....................................................................... 35.4.55 Transmit Endpoint FIFO Size (TXFIFOSZ) .............................................................. 35.4.56 Receive Endpoint FIFO Size (RXFIFOSZ) .............................................................. 35.4.57 Transmit Endpoint FIFO Address (TXFIFOADDR) ..................................................... 35.4.58 Receive Endpoint FIFO Address (RXFIFOADDR) ..................................................... 35.4.59 Hardware Version Register (HWVERS) ................................................................. 35.4.60 Transmit Function Address (TXFUNCADDR) ........................................................... 35.4.61 Transmit Hub Address (TXHUBADDR) .................................................................. 35.4.62 Transmit Hub Port (TXHUBPORT) ....................................................................... 35.4.63 Receive Function Address (RXFUNCADDR) ........................................................... 35.4.64 Receive Hub Address (RXHUBADDR) .................................................................. 35.4.65 Receive Hub Port (RXHUBPORT) ........................................................................ 35.4.66 CDMA Revision Identification Register (DMAREVID) .................................................. 35.4.67 CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) ............................... 35.4.68 CDMA Emulation Control Register (DMAEMU) ......................................................... 35.4.69 CDMA Transmit Channel n Global Configuration Registers (TXGCR[0]-TXGCR[3]) .............. 35.4.70 CDMA Receive Channel n Global Configuration Registers (RXGCR[0]-RXGCR[3]) .............. 35.4.71 CDMA Receive Channel n Host Packet Configuration Registers A (RXHPCRA[0]-RXHPCRA[3]) ................................................................................ 35.4.72 CDMA Receive Channel n Host Packet Configuration Registers B (RXHPCRB[0]-RXHPCRB[3]) ................................................................................ 35.4.73 CDMA Scheduler Control Register (DMA_SCHED_CTRL) ........................................... 35.4.74 CDMA Scheduler Table Word n Registers (WORD[0]-WORD[63]) .................................. 35.4.75 Queue Manager Revision Identification Register (QMGRREVID) .................................... 35.4.76 Queue Manager Queue Diversion Register (DIVERSION) ............................................ 35.4.77 Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) .................. 35.4.78 Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) .................. 35.4.79 Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) .................. 35.4.80 Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) .................. 35.4.81 Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) .................. 35.4.82 Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) .............................. 35.4.83 Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) .................. 35.4.84 Queue Manager Queue Pending Register 0 (PEND0) ................................................ 35.4.85 Queue Manager Queue Pending Register 1 (PEND1) ................................................ 35.4.86 Queue Manager Memory Region R Base Address Registers (QMEMRBASE[0]-QMEMRBASE[15]) ...................................................................... 35.4.87 Queue Manager Memory Region R Control Registers (QMEMRCTRL[0]-QMEMRCTRL[15]) ...
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1705 1706 1707 1708 1708 1709 1709 1710 1710 1711 1712 1713 1714 1714 1715 1715 1716 1716 1717 1717 1718 1718 1719 1720 1720 1720 1721 1721 1721 1722 1722 1723 1723 1724 1725 1726 1727 1727 1729 1729 1730 1731 1732 1733 1733 1734 1734 1735 1735 1736 1737
25

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35.4.88 35.4.89 35.4.90 35.4.91

Queue Queue Queue Queue

Manager Queue N Control Register D (CTRLD[0]-CTRLD[63]) ............................. Manager Queue N Status Register A (QSTATA[0]-QSTATA[63]) ........................... Manager Queue N Status Register B (QSTATB[0]-QSTATB[63]) ........................... Manager Queue N Status Register C (QSTATC[0]-QSTATC[63]) ..........................

1738 1739 1739 1740

36

Video Port Interface (VPIF)
36.1

36.2

36.3

.............................................................................................. 1741 Introduction .............................................................................................................. 1742 36.1.1 Overview ....................................................................................................... 1742 36.1.2 Features ....................................................................................................... 1743 36.1.3 Features Not Supported ..................................................................................... 1743 36.1.4 Functional Block Diagram ................................................................................... 1743 36.1.5 Supported Use Cases ....................................................................................... 1745 Architecture .............................................................................................................. 1746 36.2.1 Clock Control .................................................................................................. 1746 36.2.2 Signal Descriptions ........................................................................................... 1746 36.2.3 Interlaced and Progressive Video .......................................................................... 1747 36.2.4 Memory Interface ............................................................................................. 1748 36.2.5 Video Transmit ................................................................................................ 1750 36.2.6 Video Receive ................................................................................................ 1751 36.2.7 Raw Data Capture ............................................................................................ 1752 36.2.8 VBI Ancillary Data ............................................................................................ 1755 36.2.9 Clipping Function for Output ................................................................................ 1756 36.2.10 Reset Considerations ....................................................................................... 1757 36.2.11 Initialization .................................................................................................. 1758 36.2.12 Interrupt Support ............................................................................................ 1758 36.2.13 Emulation Considerations .................................................................................. 1760 36.2.14 Rules for Module Control .................................................................................. 1762 36.2.15 Standard Video Modes ..................................................................................... 1762 Registers ................................................................................................................. 1767 36.3.1 VPIF Revision Register ID (REVID) ........................................................................ 1770 36.3.2 Channel 0 Control Register (C0CTRL) .................................................................... 1770 36.3.3 Channel 1 Control Register (C1CTRL) .................................................................... 1772 36.3.4 Channel 2 Control Register (C2CTRL) .................................................................... 1773 36.3.5 Channel 3 Control Register (C3CTRL) .................................................................... 1775 36.3.6 Interrupt Enable Register (INTEN) ......................................................................... 1777 36.3.7 Interrupt Enable Set Register (INTSET) ................................................................... 1778 36.3.8 Interrupt Enable Clear Register (INTCLR) ................................................................ 1779 36.3.9 Interrupt Status Register (INTSTAT) ....................................................................... 1780 36.3.10 Interrupt Status Clear Register (INTSTATCLR) ......................................................... 1781 36.3.11 Emulation Suspend Control Register (EMUCTRL) ..................................................... 1782 36.3.12 DMA Size Control Register (REQSIZE) .................................................................. 1782 36.3.13 Channel n Top Field Luminance Address Register (CnTLUMA) ..................................... 1783 36.3.14 Channel n Bottom Field Luminance Address Register (CnBLUMA) ................................. 1783 36.3.15 Channel n Top Field Chrominance Address Register (CnTCHROMA) .............................. 1784 36.3.16 Channel n Bottom Field Chrominance Address Register (CnBCHROMA) .......................... 1784 36.3.17 Channel n Top Field Horizontal Ancillary Address Register (CnTHANC) ........................... 1785 36.3.18 Channel n Bottom Field Horizontal Ancillary Address Register (CnBHANC) ....................... 1785 36.3.19 Channel n Top Field Vertical Ancillary Address Register (CnTVANC) .............................. 1786 36.3.20 Channel n Bottom Field Vertical Ancillary Address Register (CnBVANC) .......................... 1786 36.3.21 Channel n Image Address Offset Register (CnIMGOFFSET) ........................................ 1787 36.3.22 Channel n Horizontal Ancillary Address Offset Register (CnHANCOFFSET) ...................... 1787 36.3.23 Channel n Horizontal Size Configuration Register (C0HCFG and C1HCFG) ...................... 1788 36.3.24 Channel n Vertical Size Configuration 0 Register (C0VCFG0 and C1VCFG0) ..................... 1789 36.3.25 Channel n Vertical Size Configuration 1 Register (C0VCFG1 and C1VCFG1) ..................... 1789
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36.3.26 Channel n Vertical Size Configuration 2 Register (C0VCFG2 and C1VCFG2) ..................... 36.3.27 Channel n Vertical Image Size Register (C0VSIZE and C1VSIZE) .................................. 36.3.28 Channel n Horizontal Size Configuration Register (C2HCFG and C3HCFG) ...................... 36.3.29 Channel n Vertical Size Configuration 0 Register (C2VCFG0 and C3VCFG0) ..................... 36.3.30 Channel n Vertical Size Configuration 1 Register (C2VCFG1 and C3VCFG1) ..................... 36.3.31 Channel n Vertical Size Configuration 2 Register (C2VCFG2 and C3VCFG2) ..................... 36.3.32 Channel n Vertical Image Size Register (C2VSIZE and C3VSIZE) .................................. 36.3.33 Channel n Top Field Horizontal Ancillary Position Register (C2THANCPOS and C3THANCPOS) ................................................................................................ 36.3.34 Channel n Top Field Horizontal Ancillary Size Register (C2THANCSIZE and C3THANCSIZE) . 36.3.35 Channel n Bottom Field Horizontal Ancillary Position Register (C2BHANCPOS and C3BHANCPOS) ............................................................................................... 36.3.36 Channel n Bottom Field Horizontal Ancillary Size Register (C2BHANCSIZE and C3BHANCSIZE) ............................................................................................... 36.3.37 Channel n Top Field Vertical Ancillary Position Register (C2TVANCPOS and C3TVANCPOS) . 36.3.38 Channel n Top Field Vertical Ancillary Size Register (C2TVANCSIZE and C3TVANCSIZE) .... 36.3.39 Channel n Bottom Field Vertical Ancillary Position Register (C2BVANCPOS and C3BVANCPOS) ................................................................................................ 36.3.40 Channel n Bottom Field Vertical Ancillary Size Register (C2BVANCSIZE and C3BVANCSIZE)

1790 1790 1791 1792 1792 1793 1793 1794 1795 1796 1797 1798 1799 1800 1801

A

Revision History

............................................................................................................ 1803

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List of Figures
1-1. 3-1. 4-1. 6-1. 6-2. 6-3. 6-4. 6-5. 6-6. 6-7. 6-8. 6-9. 6-10. 6-11. 6-12. 6-13. 6-14. 6-15. 6-16. 6-17. 6-18. 6-19. 7-1. 7-2. 7-3. 7-4. 7-5. 7-6. 7-7. 8-1. 8-2. 8-3. 8-4. 8-5. 8-6. 8-7. 8-8. 8-9. 8-10. 8-11. 8-12. 8-13. 8-14. 8-15. 8-16. 8-17. 8-18.
28

OMAP-L138 Applications Processor Block Diagram System Interconnect Block Diagram

.................................................................

84 105

TMS320C674x Megamodule Block Diagram .......................................................................... 96

..................................................................................

MPU Block Diagram ..................................................................................................... 112 Permission Fields ........................................................................................................ 115 Revision ID Register (REVID) .......................................................................................... 120

..................................................................................... Interrupt Raw Status/Set Register (IRAWSTAT)..................................................................... Interrupt Enable Status/Clear Register (IENSTAT) .................................................................. Interrupt Enable Set Register (IENSET) .............................................................................. Interrupt Enable Clear Register (IENCLR) ............................................................................ Fixed Range Start Address Register (FXD_MPSAR) ............................................................... Fixed Range End Address Register (FXD_MPEAR) ................................................................ Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) ....................................... MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) ..................................... MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) ..................................... MPU1 Programmable Range n End Address Register (PROGn_MPEAR) ...................................... MPU2 Programmable Range n End Address Register (PROGn_MPEAR) ...................................... Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) ........................ Fault Address Register (FLTADDRR) ................................................................................. Fault Status Register (FLTSTAT) ...................................................................................... Fault Clear Register (FLTCLR)......................................................................................... Overall Clocking Diagram ............................................................................................... USB Clocking Diagram .................................................................................................. DDR2/mDDR Memory Controller Clocking Diagram ................................................................ EMIFA Clocking Diagram ............................................................................................... EMAC Clocking Diagram................................................................................................ uPP Clocking Diagram .................................................................................................. McASP Clocking Diagram .............................................................................................. PLLC Structure ........................................................................................................... PLLC0 Revision Identification Register (REVID) .................................................................... PLLC1 Revision Identification Register (REVID) .................................................................... Reset Type Status Register (RSTYPE) ............................................................................... Reset Control Register (RSCTRL) ..................................................................................... PLLC0 Control Register (PLLCTL) .................................................................................... PLLC1 Control Register (PLLCTL) .................................................................................... PLLC0 OBSCLK Select Register (OCSEL)........................................................................... PLLC1 OBSCLK Select Register (OCSEL)........................................................................... PLL Multiplier Control Register (PLLM) ............................................................................... PLLC0 Pre-Divider Control Register (PREDIV) ...................................................................... PLLC0 Divider 1 Register (PLLDIV1) ................................................................................. PLLC1 Divider 1 Register (PLLDIV1) ................................................................................. PLLC0 Divider 2 Register (PLLDIV2) ................................................................................. PLLC1 Divider 2 Register (PLLDIV2) ................................................................................. PLLC0 Divider 3 Register (PLLDIV3) ................................................................................. PLLC1 Divider 3 Register (PLLDIV3) ................................................................................. PLLC0 Divider 4 Register (PLLDIV4) .................................................................................
Configuration Register (CONFIG)

120 121 122 123 123 124 124 125 126 126 127 127 128 129 130 131 135 138 140 141 142 144 145 149 154 155 155 156 157 158 159 160 161 161 162 162 163 163 164 164 165

List of Figures
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8-19. 8-20. 8-21. 8-22. 8-23. 8-24. 8-25. 8-26. 8-27. 8-28. 8-29. 8-30. 8-31. 8-32. 8-33. 8-34. 8-35. 8-36. 8-37. 8-38. 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 9-7. 9-8. 9-9. 9-10. 9-11. 9-12. 9-13. 9-14. 9-15. 9-16. 9-17. 9-18. 9-19. 10-1. 11-1. 11-2. 11-3. 11-4. 11-5. 11-6. 11-7. 11-8. 11-9.

................................................................................. PLLC0 Divider 6 Register (PLLDIV6) ................................................................................. PLLC0 Divider 7 Register (PLLDIV7) ................................................................................. PLLC0 Oscillator Divider 1 Register (OSCDIV) ...................................................................... PLLC1 Oscillator Divider 1 Register (OSCDIV) ...................................................................... PLL Post-Divider Control Register (POSTDIV) ...................................................................... PLL Controller Command Register (PLLCMD)....................................................................... PLL Controller Status Register (PLLSTAT)........................................................................... PLLC0 Clock Align Control Register (ALNCTL)...................................................................... PLLC1 Clock Align Control Register (ALNCTL)...................................................................... PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) ...................................................... PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) ...................................................... PLLC0 Clock Enable Control Register (CKEN) ...................................................................... PLLC1 Clock Enable Control Register (CKEN) ...................................................................... PLLC0 Clock Status Register (CKSTAT) ............................................................................. PLLC1 Clock Status Register (CKSTAT) ............................................................................. PLLC0 SYSCLK Status Register (SYSTAT) ......................................................................... PLLC1 SYSCLK Status Register (SYSTAT) ......................................................................... Emulation Performance Counter 0 Register (EMUCNT0) .......................................................... Emulation Performance Counter 1 Register (EMUCNT1) .......................................................... Revision Identification Register (REVID) ............................................................................. Interrupt Evaluation Register (INTEVAL) ............................................................................. PSC0 Module Error Pending Register 0 (MERRPR0) .............................................................. PSC1 Module Error Pending Register 0 (MERRPR0) .............................................................. PSC0 Module Error Clear Register 0 (MERRCR0).................................................................. PSC1 Module Error Clear Register 0 (MERRCR0).................................................................. Power Error Pending Register (PERRPR) ............................................................................ Power Error Clear Register (PERRCR) ............................................................................... Power Domain Transition Command Register (PTCMD) ........................................................... Power Domain Transition Status Register (PTSTAT) ............................................................... Power Domain 0 Status Register (PDSTAT0) ....................................................................... Power Domain 1 Status Register (PDSTAT1) ....................................................................... Power Domain 0 Control Register (PDCTL0) ........................................................................ Power Domain 1 Control Register (PDCTL1) ........................................................................ Power Domain 0 Configuration Register (PDCFG0) ................................................................ Power Domain 1 Configuration Register (PDCFG1) ................................................................ Module Status n Register (MDSTATn) ................................................................................ PSC0 Module Control n Register (MDCTLn) ......................................................................... PSC1 Module Control n Register (MDCTLn) ......................................................................... Deep Sleep Mode Sequence ........................................................................................... Revision Identification Register (REVID) ............................................................................. Device Identification Register 0 (DEVIDR0) .......................................................................... Boot Configuration Register (BOOTCFG) ............................................................................ Kick 0 Register (KICK0R) ............................................................................................... Kick 1 Register (KICK1R) ............................................................................................... Host 0 Configuration Register (HOST0CFG) ......................................................................... Host 1 Configuration Register (HOST1CFG) ......................................................................... Interrupt Raw Status/Set Register (IRAWSTAT)..................................................................... Interrupt Enable Status/Clear Register (IENSTAT) ..................................................................
PLLC0 Divider 5 Register (PLLDIV5)
List of Figures
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165 166 166 167 167 168 168 169 170 171 172 173 174 174 175 176 177 178 179 179 192 192 193 193 194 194 195 195 196 197 198 199 200 201 202 203 204 205 206 221 231 231 232 233 233 234 235 236 237
29

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11-10. Interrupt Enable Register (IENSET) ................................................................................... 238 11-11. Interrupt Enable Clear Register (IENCLR) ............................................................................ 238 11-12. End of Interrupt Register (EOI) ......................................................................................... 239 11-13. Fault Address Register (FLTADDRR) ................................................................................. 239 11-14. Fault Status Register (FLTSTAT) ...................................................................................... 240 11-15. Master Priority 0 Register (MSTPRI0)................................................................................. 241 11-16. Master Priority 1 Register (MSTPRI1)................................................................................. 242 11-17. Master Priority 2 Register (MSTPRI2)................................................................................. 243 11-18. Pin Multiplexing Control 0 Register (PINMUX0) ..................................................................... 244 11-19. Pin Multiplexing Control 1 Register (PINMUX1) ..................................................................... 246 11-20. Pin Multiplexing Control 2 Register (PINMUX2) ..................................................................... 248 11-21. Pin Multiplexing Control 3 Register (PINMUX3) ..................................................................... 250 11-22. Pin Multiplexing Control 4 Register (PINMUX4) ..................................................................... 252 11-23. Pin Multiplexing Control 5 Register (PINMUX5) ..................................................................... 254 11-24. Pin Multiplexing Control 6 Register (PINMUX6) ..................................................................... 256 11-25. Pin Multiplexing Control 7 Register (PINMUX7) ..................................................................... 258 11-26. Pin Multiplexing Control 8 Register (PINMUX8) ..................................................................... 260 11-27. Pin Multiplexing Control 9 Register (PINMUX9) ..................................................................... 262 11-28. Pin Multiplexing Control 10 Register (PINMUX10) .................................................................. 264 11-29. Pin Multiplexing Control 11 Register (PINMUX11) .................................................................. 266 11-30. Pin Multiplexing Control 12 Register (PINMUX12) .................................................................. 268 11-31. Pin Multiplexing Control 13 Register (PINMUX13) .................................................................. 270 11-32. Pin Multiplexing Control 14 Register (PINMUX14) .................................................................. 272 11-33. Pin Multiplexing Control 15 Register (PINMUX15) .................................................................. 274 11-34. Pin Multiplexing Control 16 Register (PINMUX16) .................................................................. 277 11-35. Pin Multiplexing Control 17 Register (PINMUX17) .................................................................. 279 11-36. Pin Multiplexing Control 18 Register (PINMUX18) .................................................................. 281 11-37. Pin Multiplexing Control 19 Register (PINMUX19) .................................................................. 283 11-38. Suspend Source Register (SUSPSRC) ............................................................................... 285 11-39. Chip Signal Register (CHIPSIG) ....................................................................................... 288 11-40. Chip Signal Clear Register (CHIPSIG_CLR) ......................................................................... 289 11-41. Chip Configuration 0 Register (CFGCHIP0) .......................................................................... 290 11-42. Chip Configuration 1 Register (CFGCHIP1) .......................................................................... 291 11-43. Chip Configuration 2 Register (CFGCHIP2) .......................................................................... 294 11-44. Chip Configuration 3 Register (CFGCHIP3) .......................................................................... 296 11-45. Chip Configuration 4 Register (CFGCHIP4) .......................................................................... 297 11-46. VTP I/O Control Register (VTPIO_CTL) .............................................................................. 298 11-47. DDR Slew Register (DDR_SLEW)..................................................................................... 300 11-48. Deep Sleep Register (DEEPSLEEP) .................................................................................. 301 11-49. Pullup/Pulldown Enable Register (PUPD_ENA) ..................................................................... 302 11-50. Pullup/Pulldown Select Register (PUPD_SEL) 11-51. 11-52. 12-1. 12-2. 12-3. 12-4. 12-5. 12-6.
30

...................................................................... RXACTIVE Control Register (RXACTIVE)............................................................................ Power Down Control Register (PWRDN) ............................................................................. AINTC Interrupt Mapping ............................................................................................... Flow of System Interrupts to Host ..................................................................................... Revision Identification Register (REVID) ............................................................................. Control Register (CR) ................................................................................................... Global Enable Register (GER) ......................................................................................... Global Nesting Level Register (GNLR) ...............................................................................
Copyright © 2011, Texas Instruments Incorporated

302 304 304 306 309 314 315 316 316

List of Figures

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12-7. 12-8. 12-9.

System Interrupt Status Indexed Set Register (SISR) .............................................................. 317 System Interrupt Status Indexed Clear Register (SICR)............................................................ 317 System Interrupt Enable Indexed Set Register (EISR)

.............................................................

318

12-10. System Interrupt Enable Indexed Clear Register (EICR) ........................................................... 318 12-11. Host Interrupt Enable Indexed Set Register (HEISR) ............................................................... 319 12-12. Host Interrupt Enable Indexed Clear Register (HIEICR)............................................................ 319 12-13. Vector Base Register (VBR) ............................................................................................ 320 12-14. Vector Size Register (VSR) ............................................................................................. 320 12-15. Vector Null Register (VNR) ............................................................................................. 321 12-16. Global Prioritized Index Register (GPIR)

.............................................................................

321 322 323 323 324 324 325 325 326 326 327 327 328 328 329 329 330 330 331 331 332 332 333 334 334 343 344 345 348 349 350 351 352 353 354 354 357 358 359
31

12-17. Global Prioritized Vector Register (GPVR) ........................................................................... 322 12-18. System Interrupt Status Raw/Set Register 1 (SRSR1) 12-19. System Interrupt Status Raw/Set Register 2 (SRSR2) 12-20. 12-21. 12-22. 12-23. 12-24. 12-25. 12-26. 12-27. 12-28. 12-29. 12-30. 12-31. 12-32. 12-33. 12-34. 12-35. 12-36. 12-37. 12-38. 12-39. 12-40. 12-41. 15-1. 15-2. 15-3. 15-4. 15-5. 15-6. 15-7. 15-8. 15-9. 15-10. 15-11. 15-12. 15-13. 15-14.

............................................................. ............................................................. System Interrupt Status Raw/Set Register 3 (SRSR3) ............................................................. System Interrupt Status Raw/Set Register 4 (SRSR4) ............................................................. System Interrupt Status Enabled/Clear Register 1 (SECR1) ...................................................... System Interrupt Status Enabled/Clear Register 2 (SECR2) ...................................................... System Interrupt Status Enabled/Clear Register 3 (SECR3) ...................................................... System Interrupt Status Enabled/Clear Register 4 (SECR4) ...................................................... System Interrupt Enable Set Register 1 (ESR1) ..................................................................... System Interrupt Enable Set Register 2 (ESR2) ..................................................................... System Interrupt Enable Set Register 3 (ESR3) ..................................................................... System Interrupt Enable Set Register 4 (ESR4) ..................................................................... System Interrupt Enable Clear Register 1 (ECR1) .................................................................. System Interrupt Enable Clear Register 2 (ECR2) .................................................................. System Interrupt Enable Clear Register 3 (ECR3) .................................................................. System Interrupt Enable Clear Register 4 (ECR4) .................................................................. Channel Map Registers (CMRn) ....................................................................................... Host Interrupt Prioritized Index Register 1 (HIPIR1) ................................................................ Host Interrupt Prioritized Index Register 2 (HIPIR2) ................................................................ Host Interrupt Nesting Level Register 1 (HINLR1) .................................................................. Host Interrupt Nesting Level Register 2 (HINLR2) .................................................................. Host Interrupt Enable Register (HIER) ................................................................................ Host Interrupt Prioritized Vector Register 1 (HIPVR1) .............................................................. Host Interrupt Prioritized Vector Register 2 (HIPVR2) .............................................................. Data Paths to DDR2/mDDR Memory Controller ..................................................................... DDR2/mDDR Memory Controller Clock Block Diagram ............................................................ DDR2/mDDR Memory Controller Signals............................................................................. Refresh Command ....................................................................................................... DCAB Command ......................................................................................................... DEAC Command ......................................................................................................... ACTV Command ......................................................................................................... DDR2/mDDR READ Command ........................................................................................ DDR2/mDDR WRT Command ......................................................................................... DDR2/mDDR MRS and EMRS Command ........................................................................... Byte Alignment ........................................................................................................... Logical Address-to-DDR2/mDDR SDRAM Address Map ........................................................... DDR2/mDDR SDRAM Column, Row, and Bank Access ........................................................... Address Mapping Diagram (IBANKPOS = 1) ........................................................................
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15-15. SDRAM Column, Row, Bank Access (IBANKPOS = 1) 15-16. 15-17. 15-18. 15-19. 15-20. 15-21. 15-22. 15-23. 15-24. 15-25. 15-26. 15-27. 15-28. 15-29. 15-30. 15-31. 15-32. 15-33. 15-34. 15-35. 15-36. 15-37. 15-38. 16-1. 16-2. 16-3. 16-4. 16-5. 16-6. 16-7. 16-8. 16-9. 16-10. 16-11. 16-12. 16-13. 16-14. 16-15. 16-16. 16-17. 16-18. 16-19. 16-20. 16-21. 16-22. 16-23. 16-24. 16-25.
32

............................................................ DDR2/mDDR Memory Controller FIFO Block Diagram ............................................................. DDR2/mDDR Memory Controller Reset Block Diagram ............................................................ DDR2/mDDR Memory Controller Power Sleep Controller Diagram............................................... Connecting DDR2/mDDR Memory Controller to a 16-Bit DDR2 Memory ........................................ Revision ID Register (REVID) .......................................................................................... SDRAM Status Register (SDRSTAT) ................................................................................ SDRAM Configuration Register (SDCR) ............................................................................. SDRAM Refresh Control Register (SDRCR) ........................................................................ SDRAM Timing Register 1 (SDTIMR1) ............................................................................... SDRAM Timing Register 2 (SDTIMR2) ............................................................................... SDRAM Configuration Register 2 (SDCR2) ......................................................................... Peripheral Bus Burst Priority Register (PBBPR) ..................................................................... Performance Counter 1 Register (PC1) ............................................................................... Performance Counter 2 Register (PC2) ............................................................................... Performance Counter Configuration Register (PCC) ................................................................ Performance Counter Master Region Select Register (PCMRS) .................................................. Performance Counter Time Register (PCT) .......................................................................... DDR PHY Reset Control Register (DRPYRCR) ..................................................................... Interrupt Raw Register (IRR) ........................................................................................... Interrupt Masked Register (IMR) ....................................................................................... Interrupt Mask Set Register (IMSR) ................................................................................... Interrupt Mask Clear Register (IMCR)................................................................................. DDR PHY Control Register 1 (DRPYC1R) ........................................................................... Multiple eCAP Modules ................................................................................................. Capture and APWM Modes of Operation ............................................................................. Capture Function Diagram .............................................................................................. Event Prescale Control .................................................................................................. Prescale Function Waveforms ......................................................................................... Continuous/One-shot Block Diagram.................................................................................. Counter and Synchronization Block Diagram ........................................................................ Interrupts in eCAP Module .............................................................................................. PWM Waveform Details Of APWM Mode Operation ................................................................ Capture Sequence for Absolute Time-Stamp, Rising Edge Detect ............................................... Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect ................................. Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect ............................................ Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect .............................. PWM Waveform Details of APWM Mode Operation ................................................................ Multichannel PWM Example Using 4 eCAP Modules ............................................................... Multiphase (channel) Interleaved PWM Example Using 3 eCAP Modules ....................................... Time-Stamp Counter Register (TSCTR) .............................................................................. Counter Phase Control Register (CTRPHS) ......................................................................... Capture 1 Register (CAP1) ............................................................................................ Capture 2 Register (CAP2) ............................................................................................. Capture 3 Register (CAP3) ............................................................................................. Capture 4 Register (CAP4) ............................................................................................. ECAP Control Register 1 (ECCTL1) .................................................................................. ECAP Control Register 2 (ECCTL2) .................................................................................. ECAP Interrupt Enable Register (ECEINT) ...........................................................................
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360 361 365 370 372 377 378 379 382 383 384 385 386 387 387 388 390 391 391 392 392 393 394 395 399 400 401 402 402 403 404 406 407 409 411 413 415 417 419 422 424 425 425 426 426 427 427 429 431

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16-26. ECAP Interrupt Flag Register (ECFLG) ............................................................................... 432 16-27. ECAP Interrupt Clear Register (ECCLR)

.............................................................................

433

16-28. ECAP Interrupt Forcing Register (ECFRC) ........................................................................... 434 16-29. Revision ID Register (REVID) .......................................................................................... 435 17-1. 17-2. 17-3. 17-4. 17-5. 17-6. 17-7. 17-8. 17-9. Multiple ePWM Modules ................................................................................................ 439 Submodules and Signal Connections for an ePWM Module ....................................................... 440 ePWM Submodules and Critical Internal Signal Interconnects .................................................... 441 Time-Base Submodule Block Diagram................................................................................ 446 Time-Base Submodule Signals and Registers ....................................................................... 448 Time-Base Frequency and Period ..................................................................................... 450 Time-Base Counter Synchronization Scheme 1 ..................................................................... 451 Time-Base Up-Count Mode Waveforms .............................................................................. 453 Time-Base Down-Count Mode Waveforms ........................................................................... 454

17-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on Synchronization Event .... 454 17-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on Synchronization Event ........ 455 17-12. Counter-Compare Submodule 17-13. 17-14. 17-15.

......................................................................................... Counter-Compare Submodule Signals and Registers .............................................................. Counter-Compare Event Waveforms in Up-Count Mode ........................................................... Counter-Compare Events in Down-Count Mode.....................................................................

456 456 459 459

17-16. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down on Synchronization Event .................................................................................................. 460 17-17. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on Synchronization Event ...................................................................................................................... 460 17-18. Action-Qualifier Submodule............................................................................................. 461 17-19. Action-Qualifier Submodule Inputs and Outputs ..................................................................... 462 17-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs .......................................... 463 17-21. Up-Down-Count Mode Symmetrical Waveform ...................................................................... 466 17-22. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB—Active High.................................................................................................. 467 17-23. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB—Active Low .................................................................................................. 469 17-24. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ............ 471 17-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB — Active Low ................................................................................................ 473 17-26. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB — Complementary........................................................................................... 475 17-27. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active Low......................................................................................................................... 477 17-28. Dead-Band Generator Submodule 17-29. 17-30. 17-31. 17-32. 17-33. 17-34.

.................................................................................... Configuration Options for the Dead-Band Generator Submodule ................................................. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) .................................................. PWM-Chopper Submodule ............................................................................................. PWM-Chopper Submodule Signals and Registers .................................................................. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ............................... PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses.......

479 480 482 483 484 485 485

17-35. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses ..................................................................................................................... 486 17-36. Trip-Zone Submodule ................................................................................................... 487 17-37. Trip-Zone Submodule Mode Control Logic ........................................................................... 490 17-38. Trip-Zone Submodule Interrupt Logic ................................................................................. 490 17-39. Event-Trigger Submodule ............................................................................................... 491
SPRUH77A – December 2011 Submit Documentation Feedback List of Figures
Copyright © 2011, Texas Instruments Incorporated

33

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17-40. Event-Trigger Submodule Inter-Connectivity to Interrupt Controller 17-41. 17-42. 17-43. 17-44. 17-45. 17-46. 17-47. 17-48. 17-49. 17-50. 17-51. 17-52. 17-53. 17-54. 17-55. 17-56. 17-57. 17-58. 17-59. 17-60. 17-61. 17-62. 17-63. 17-64. 17-65. 17-66. 17-67. 17-68. 17-69. 17-70. 17-71. 17-72. 17-73. 17-74. 17-75. 17-76. 17-77. 17-78. 17-79. 17-80. 17-81. 17-82. 17-83. 17-84. 17-85. 17-86. 17-87. 17-88.
34

.............................................. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs ....................................... Event-Trigger Interrupt Generator ..................................................................................... HRPWM System Interface .............................................................................................. Resolution Calculations for Conventionally Generated PWM ...................................................... Operating Logic Using MEP ............................................................................................ Required PWM Waveform for a Requested Duty = 40.5% ......................................................... Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz ............................... High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ............................... Simplified ePWM Module ............................................................................................... EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ..................................... Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 ................................................... Buck Waveforms for (Note: Only three bucks shown here) ........................................................ Control of Four Buck Stages. (Note: FPWM2 = N × FPWM1) ............................................................ Buck Waveforms for (Note: FPWM2 = FPWM1)) ........................................................................... Control of Two Half-H Bridge Stages (FPWM2 = N × FPWM1) .......................................................... Half-H Bridge Waveforms for (Note: Here FPWM2 = FPWM1 )......................................................... Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control .............................. 3-Phase Inverter Waveforms for (Only One Inverter Shown) ...................................................... Configuring Two PWM Modules for Phase Control ................................................................. Timing Waveforms Associated With Phase Control Between 2 Modules ........................................ Control of a 3-Phase Interleaved DC/DC Converter ................................................................ 3-Phase Interleaved DC/DC Converter Waveforms for ............................................................ Controlling a Full-H Bridge Stage (FPWM2 = FPWM1) ................................................................... ZVS Full-H Bridge Waveforms ......................................................................................... Time-Base Control Register (TBCTL) ................................................................................. Time-Base Status Register (TBSTS) .................................................................................. Time-Base Phase Register (TBPHS).................................................................................. Time-Base Counter Register (TBCNT)................................................................................ Time-Base Period Register (TBPRD) ................................................................................. Counter-Compare Control Register (CMPCTL) ...................................................................... Counter-Compare A Register (CMPA) ............................................................................... Counter-Compare B Register (CMPB) ................................................................................ Action-Qualifier Output A Control Register (AQCTLA) .............................................................. Action-Qualifier Output B Control Register (AQCTLB) .............................................................. Action-Qualifier Software Force Register (AQSFRC) ............................................................... Action-Qualifier Continuous Software Force Register (AQCSFRC) ............................................... Dead-Band Generator Control Register (DBCTL) ................................................................... Dead-Band Generator Rising Edge Delay Register (DBRED) ..................................................... Dead-Band Generator Falling Edge Delay Register (DBFED) ..................................................... PWM-Chopper Control Register (PCCTL) ............................................................................ Trip-Zone Select Register (TZSEL) .................................................................................... Trip-Zone Control Register (TZCTL) .................................................................................. Trip-Zone Enable Interrupt Register (TZEINT) ....................................................................... Trip-Zone Flag Register (TZFLG) ...................................................................................... Trip-Zone Clear Register (TZCLR) .................................................................................... Trip-Zone Force Register (TZFRC) .................................................................................... Event-Trigger Selection Register (ETSEL) ........................................................................... Event-Trigger Prescale Register (ETPS) .............................................................................
Copyright © 2011, Texas Instruments Incorporated

492 492 494 495 496 497 499 501 501 502 503 504 505 507 508 510 511 513 514 517 518 519 520 523 524 526 528 529 529 530 531 532 533 534 535 536 537 538 539 539 540 541 542 542 543 544 544 545 546

List of Figures

SPRUH77A – December 2011 Submit Documentation Feedback

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17-89. Event-Trigger Flag Register (ETFLG) ................................................................................. 547 17-90. Event-Trigger Clear Register (ETCLR)................................................................................ 547 17-91. Event-Trigger Force Register (ETFRC) ............................................................................... 548 17-92. Time-Base Phase High-Resolution Register (TBPHSHR) .......................................................... 549 17-93. Counter-Compare A High-Resolution Register (CMPAHR) ........................................................ 549 17-94. HRPWM Configuration Register (HRCNFG) ......................................................................... 550 18-1. 18-2. 18-3. 18-4. 18-5. 18-6. 18-7. 18-8. 18-9. 18-10. 18-11. 18-12. 18-13. 18-14. 18-15. 18-16. 18-17. 18-18. 18-19. 18-20. 18-21. 18-22. 18-23. 18-24. 18-25. 18-26. 18-27. 18-28. 18-29. 18-30. 18-31. 18-32. 18-33. 18-34. 18-35. 18-36. 18-37. 18-38. 18-39. 18-40. 18-41. 18-42. 18-43. EDMA3 Controller Block Diagram ..................................................................................... 555 EDMA3 Channel Controller (EDMA3CC) Block Diagram ........................................................... 558 EDMA3 Transfer Controller (EDMA3TC) Block Diagram ........................................................... 559 Definition of ACNT, BCNT, and CCNT

............................................................................... ..................................................

560 562 571 572 579 581 586 589 596 600 601 602 602 603 604 605 606 607 607 608 609 610 612 613 614 614 616 616 617 618 620 620 621 621 622 623 623 627
35

A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .................................................... 561 AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) Linked Transfer Example PaRAM Set ............................................................................................................... 563

............................................................................................... Link-to-Self Transfer Example .......................................................................................... QDMA Channel to PaRAM Mapping .................................................................................. Shadow Region Registers .............................................................................................. Interrupt Diagram ........................................................................................................ Error Interrupt Operation ................................................................................................ EDMA3 Prioritization..................................................................................................... Block Move Example .................................................................................................... Block Move Example PaRAM Configuration ......................................................................... Subframe Extraction Example .......................................................................................... Subframe Extraction Example PaRAM Configuration ............................................................... Data Sorting Example ................................................................................................... Data Sorting Example PaRAM Configuration ........................................................................ Servicing Incoming McBSP Data Example ........................................................................... Servicing Incoming McBSP Data Example PaRAM ................................................................. Servicing Peripheral Burst Example ................................................................................... Servicing Peripheral Burst Example PaRAM ......................................................................... Servicing Continuous McBSP Data Example ........................................................................ Servicing Continuous McBSP Data Example PaRAM .............................................................. Servicing Continuous McBSP Data Example Reload PaRAM ..................................................... Ping-Pong Buffering for McBSP Data Example ..................................................................... Ping-Pong Buffering for McBSP Example PaRAM .................................................................. Ping-Pong Buffering for McBSP Example Pong PaRAM ........................................................... Ping-Pong Buffering for McBSP Example Ping PaRAM ............................................................ Intermediate Transfer Completion Chaining Example .............................................................. Single Large Block Transfer Example ................................................................................. Smaller Packet Data Transfers Example ............................................................................. Channel Options Parameter (OPT) .................................................................................... Channel Source Address Parameter (SRC) .......................................................................... A Count/B Count Parameter (A_B_CNT) ............................................................................. Channel Destination Address Parameter (DST) ..................................................................... Source B Index/Destination B Index Parameter (SRC_DST_BIDX) .............................................. Link Address/B Count Reload Parameter (LINK_BCNTRLD) ...................................................... Source C Index/Destination C Index Parameter (SRC_DST_CIDX) .............................................. C Count Parameter (CCNT) ............................................................................................ Revision ID Register (REVID) ..........................................................................................
List of Figures
Copyright © 2011, Texas Instruments Incorporated

SPRUH77A – December 2011 Submit Documentation Feedback

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18-44. EDMA3CC Configuration Register (CCCFG) 18-45. 18-46. 18-47. 18-48. 18-49. 18-50. 18-51. 18-52. 18-53. 18-54. 18-55. 18-56. 18-57. 18-58. 18-59. 18-60. 18-61. 18-62. 18-63. 18-64. 18-65. 18-66. 18-67. 18-68. 18-69. 18-70. 18-71. 18-72. 18-73. 18-74. 18-75. 18-76. 18-77. 18-78. 18-79. 18-80. 18-81. 18-82. 18-83. 18-84. 18-85. 18-86. 18-87. 18-88. 18-89. 18-90. 18-91. 18-92.
36

........................................................................ QDMA Channel n Mapping Register (QCHMAPn) .................................................................. DMA Channel Queue Number Register n (DMAQNUMn) .......................................................... QDMA Channel Queue Number Register (QDMAQNUM) ......................................................... Event Missed Register (EMR) .......................................................................................... Event Missed Clear Register (EMCR)................................................................................. QDMA Event Missed Register (QEMR) ............................................................................... QDMA Event Missed Clear Register (QEMCR)...................................................................... EDMA3CC Error Register (CCERR) .................................................................................. EDMA3CC Error Clear Register (CCERRCLR) ...................................................................... Error Evaluate Register (EEVAL) ...................................................................................... DMA Region Access Enable Register for Region m (DRAEm) .................................................... QDMA Region Access Enable for Region m (QRAEm) ............................................................ Event Queue Entry Registers (QxEy) ................................................................................. Queue n Status Register (QSTATn) ................................................................................... Queue Watermark Threshold A Register (QWMTHRA) ............................................................ EDMA3CC Status Register (CCSTAT)................................................................................ Event Register (ER) ..................................................................................................... Event Clear Register (ECR) ............................................................................................ Event Set Register (ESR) ............................................................................................... Chained Event Register (CER)......................................................................................... Event Enable Register (EER) .......................................................................................... Event Enable Clear Register (EECR) ................................................................................. Event Enable Set Register (EESR) .................................................................................... Secondary Event Register (SER) ...................................................................................... Secondary Event Clear Register (SECR) ............................................................................. Interrupt Enable Register (IER) ........................................................................................ Interrupt Enable Clear Register (IECR) ............................................................................... Interrupt Enable Set Register (IESR).................................................................................. Interrupt Pending Register (IPR) ....................................................................................... Interrupt Clear Register (ICR) .......................................................................................... Interrupt Evaluate Register (IEVAL) ................................................................................... QDMA Event Register (QER) .......................................................................................... QDMA Event Enable Register (QEER) ............................................................................... QDMA Event Enable Clear Register (QEECR) ...................................................................... QDMA Event Enable Set Register (QEESR) ......................................................................... QDMA Secondary Event Register (QSER) ........................................................................... QDMA Secondary Event Clear Register (QSECR) .................................................................. Revision ID Register (REVID) .......................................................................................... EDMA3TC Configuration Register (TCCFG) ......................................................................... EDMA3TC Channel Status Register (TCSTAT) ..................................................................... Error Status Register (ERRSTAT) ..................................................................................... Error Enable Register (ERREN) ....................................................................................... Error Clear Register (ERRCLR) ........................................................................................ Error Details Register (ERRDET) ...................................................................................... Error Interrupt Command Register (ERRCMD) ...................................................................... Read Command Rate Register (RDRATE) ........................................................................... Source Active Options Register (SAOPT) ............................................................................ Source Active Source Address Register (SASRC) ..................................................................
Copyright © 2011, Texas Instruments Incorporated

627 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 646 647 648 649 650 651 651 652 652 653 654 654 655 656 657 658 659 660 660 661 662 664 665 666 667 668 669 670 671 672 673 674

List of Figures

SPRUH77A – December 2011 Submit Documentation Feedback

............................. 750 19-29...................................................... Source Active Destination Address B-Reference Register (SADSTBREF) ...... 18-108.................................. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) ....................... 677 18-99............................................................... List of Figures 750 751 753 37 19-28..... MDIO Revision ID Register (REVID) .......................... 19-11... 19-5...... Destination FIFO Options Register n (DFOPTn) ...... EMAC Module Block Diagram ............................................................................. EMAC Control Module Revision ID Register (REVID) ................. 19-12...................................... 746 19-24. Source Active Count Reload Register (SACNTRLD) ...............com 18-93........................... Ethernet Configuration—RMII Connections ......................... 747 19-25................................................................................... 19-10................. 743 19-21........................ EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) ......... 19-14....................................... MDIO Module Block Diagram ............................... 741 19-19................................... 19-9................................................................ 19-13................. Destination FIFO Source Address Register n (DFSRCn) ............. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) .............................................. ...... EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register (CnRXTHRESHSTAT) ................. 677 18-98.. Source Active Count Register (SACNT) .................................. Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) ........................... 676 18-97........... 675 18-95........ 19-1. Destination FIFO Set Count Reload Register (DFCNTRLD) 678 18-101... 740 19-18.... 19-6.... EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT) ..... 19-3.... 681 .................... EMAC Control Module Block Diagram .... .............................................. 18-106............................................. Destination FIFO Count Register n (DFCNTn) ............................ EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register (CnRXTHRESHEN) .................................................... EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) .......................................... 19-4................................. 752 19-31.............. 678 18-100....................... EMAC Control Module Interrupt Control Register (INTCONTROL) ................................................ Receive Buffer Descriptor Format .. 739 19-17..... 679 18-102...................................................... 679 18-103.......................... 19-2... EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT).......... 681 18-105....................................................... 674 18-94.................................................................. Basic Descriptor Format ............................................. 18-107..... 675 18-96..................................... Destination FIFO B-Index Register n (DFBIDXn) ... 748 19-26...... Source Active B-Index Register (SABIDX) ................. PHY Acknowledge Status Register (ALIVE) .......................................................... 680 18-104....................... 742 19-20................................ Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) .. Texas Instruments Incorporated ...................................................................................... 745 19-23....................... 738 19-16................................ti......... 19-8...... Transmit Buffer Descriptor Format......... Source Active Source Address B-Reference Register (SASRCBREF) ... 744 19-22........... Ethernet Frame Format .................................................................. EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) ........... Source Active Destination Address Register (SADST) ............... 19-7................ Source Active Memory Protection Proxy Register (SAMPPRXY) .................................................................................................................... Ethernet Configuration—MII Connections ....... MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) SPRUH77A – December 2011 Submit Documentation Feedback Copyright © 2011............................................. EMAC and MDIO Block Diagram .................................................................................................................................................... MDIO Control Register (CONTROL) ..................................................................... EMAC Control Module Software Reset Register (SOFTRESET)........ Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) ................................................................................................................. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN) ........... MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 19-30.......www..... Typical Descriptor Linked List ................................... MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ............................................................................................. PHY Link Status Register (LINK) ........... Destination FIFO Destination Address Register n (DFDSTn) 682 682 683 689 692 694 695 696 697 700 703 707 709 713 735 736 737 19-15... ....................... 749 19-27........................

..........com 19-32.................................. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) ..............ti.................... MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ............. Soft Reset Register (SOFTRESET) .......... MAC Configuration Register (MACCONFIG) ......... MAC Control Register (MACCONTROL) ...... Texas Instruments Incorporated 764 765 766 766 767 768 769 770 771 772 773 774 775 776 777 778 778 779 779 780 783 784 785 785 786 786 787 788 790 792 792 793 793 794 794 795 795 796 796 797 797 List of Figures SPRUH77A – December 2011 Submit Documentation Feedback . 19-42............................................................................... 19-50........... Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) . Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ....... 19-77.................. 19-55............... 19-46................ Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ....................... Emulation Control Register (EMCONTROL) .............................................. Receive Teardown Register (RXTEARDOWN) ............. Receive Control Register (RXCONTROL) ................. 19-66......... MDIO User PHY Select Register 1 (USERPHYSEL1) .................. 19-56....... Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) .................................. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ...... 760 19-39...................................................... MAC Hash Address Register 1 (MACHASH1) ...................... 38 ............................. Transmit Interrupt Mask Set Register (TXINTMASKSET) ......................... 19-44. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) .............................................................................................. Copyright © 2011................... Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)... Receive Unicast Clear Register (RXUNICASTCLEAR) ................................................................................................................................ 764 19-40..................................................... 19-45...www..... MDIO User PHY Select Register 0 (USERPHYSEL0) ...... Transmit Pause Timer Register (TXPAUSE) ................................... 19-57.................................................. Receive Revision ID Register (RXREVID) ...... Back Off Random Number Generator Test Register (BOFFTEST) .. 19-43.......................................................................... MAC Interrupt Mask Set Register (MACINTMASKSET) ........................... 19-74...... 19-80................................ 19-67............................. 19-78.................. 19-54.................................................................................... 19-63.......................... 19-62........ MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ..... MDIO User Access Register 0 (USERACCESS0)........................................................................................ 19-71....... MAC Source Address High Bytes Register (MACSRCADDRHI) ......... 19-51................................................ MDIO User Access Register 1 (USERACCESS1)...... 19-52........................................... 19-69....................................................................................................... 755 19-34......................................................... 19-59.......................... Transmit Pacing Algorithm Test Register (TPACETEST) ............................................................ MAC Input Vector Register (MACINVECTOR) ............................ 19-61.......... MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ...................... Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ................................................................................... 756 19-35................................................................................ 19-68......... 19-72.......................... 19-79. 759 19-38... 19-75........... 19-49...... MAC Hash Address Register 2 (MACHASH2) ........................................... 757 19-36............................ Transmit Control Register (TXCONTROL) 19-41............ 19-60........... MAC End Of Interrupt Vector Register (MACEOIVECTOR) ....................... Transmit Revision ID Register (TXREVID) ...... MAC Status Register (MACSTATUS) ............................................................ Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ..................... Receive Buffer Offset Register (RXBUFFEROFFSET) ................................... Receive Pause Timer Register (RXPAUSE) .. 19-73........................................................ 19-58.......................................... MAC Source Address Low Bytes Register (MACSRCADDRLO) ............................. 19-64................................. 19-47............................. Receive Unicast Enable Set Register (RXUNICASTSET)............. 754 19-33............. 19-48............ Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) .................................................................................. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ............................................................ 19-76............................................... 19-70.............................................. 19-65.................................. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) .... Receive Maximum Length Register (RXMAXLEN) ........................................................ Transmit Teardown Register (TXTEARDOWN).. Receive Interrupt Mask Set Register (RXINTMASKSET) ........... 19-53.................................................. 758 19-37....... FIFO Control Register (FIFOCONTROL) .................

............................................................................................................................... Statistics Register . 20-4..........................................................................com 19-81.................... 20-3. Module ID Register (MIDR) .......... Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode .... EMIFA Reset Block Diagram ........... 20-36.................................................... 828 20-10........ 20-39................. Timing Waveform of a NAND Flash Command Write .......... 798 19-82.............. 834 20-12................................... ........................... Receive Channel n Completion Pointer Register (RXnCP) ...................................................................... 838 20-14....... Timing Waveform of a NAND Flash Data Write ............................................... EMIFA Functional Block Diagram........ Timing Waveform of an ASRAM Read with PCB Delays ... 853 20-19............ 817 EMIFA to 512K × 16 × 2 bank SDRAM Interface ............................................. 799 19-84................................................................................................................................. 20-34..................... EMIFA PSC Block Diagram .................................................. 801 19-88.......................... 20-9................. Timing Waveform of an ASRAM Write .......... 854 20-20..... Timing Waveform of an ASRAM Read 20-24.................................. 20-31............................................................... Asynchronous n Configuration Register (CEnCFG) . EMIFA Interrupt Mask Set Register (INTMSKSET) ........................ 802 20-1..................................................... 800 19-85......... 800 19-86.................... EMIFA Interrupt Raw Register (INTRAW) ...... SDRAM Timing Register (SDTIMR) ........................................... 845 20-17............................www............ Example Configuration Interface ................. 20-29....................................... Timing Waveform of an ASRAM Write with PCB Delays .......................................... 836 20-13......................ti............... 20-30......................................................................... 812 Timing Waveform of SDRAM PRE Command ......... 832 20-11..................... SDRAM Configuration Register (SDCR) ........................... ..... Asynchronous Wait Cycle Configuration Register (AWCCR) ........................ 20-5..................................................................................... 850 20-18................................... Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) ...................... EMIFA Interrupt Mask Register (INTMSK) .......... Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode .................................................... 20-32.... 799 19-83........... 817 Timing Waveform for Basic SDRAM Read Operation ............................................................. 801 19-87........................ Timing Waveform of a NAND Flash Read ............................... SDRAM Timing Register (SDTIMR) ......... List of Figures Copyright © 2011............................. 825 EMIFA Asynchronous Interface .............. 20-25............ 20-8....................... ECC Value for 8-Bit NAND Flash ................. 20-28............................. 20-26........................................... 20-2......... 840 20-15................................................ 856 20-23................................................. SDRAM Refresh Control Register (SDRCR) ................................................ 20-27............... 20-38........................................................................................................................................................ 20-33.............................................................................................................. 20-40..... SDRAM Configuration Register (SDCR) ................................. 824 Timing Waveform for Basic SDRAM Write Operation....... Timing Waveform of an Asynchronous Write Cycle in Normal Mode ...................................................................................................... MAC Index Register (MACINDEX) ......... 20-41............ Timing Waveform of an Asynchronous Read Cycle in Normal Mode ........ SDRAM Self Refresh Exit Timing Register (SDSRETR) 855 20-21............................................................................................................................................................................... 20-37............................. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) .................................................................................. Timing Waveform of a NAND Flash Address Write ......................................................................................................... Texas Instruments Incorporated 858 859 861 862 867 869 869 870 875 875 877 879 880 881 882 883 884 885 886 39 SPRUH77A – December 2011 Submit Documentation Feedback .... EMIFA to NAND Flash Interface ............... EMIFA Interrupt Mask Clear Register (INTMSKCLR) .......................................... 827 EMIFA to 8-bit/16-bit Memory Interface .................................... SDRAM Self Refresh Exit Timing Register (SDSRETR) .... 828 Common Asynchronous Interface ... MAC Address Low Bytes Register (MACADDRLO) ................... 20-7.......................................... 855 20-22........ 842 20-16............................................................... 20-35...................... Transmit Channel n Completion Pointer Register (TXnCP) ................................................................................... 20-6.......................... 816 EMIFA to 2M × 16 × 4 bank SDRAM Interface ........................ MAC Address High Bytes Register (MACADDRHI) ............................................................ SDRAM Refresh Control Register (SDRCR) ............................................................

................ GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23) .......................................... 21-6........................................ 893 20-50....... GPIO Block Diagram ............ 21-31.......ti............................................. GPIO Banks 2 and 3 Set Data Register (SET_DATA23) .......................................................... GPIO Bank 8 Set Data Register (SET_DATA8) ................... 892 20-47.... GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01) ..... 21-9....... NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) .... GPIO Banks 6 and 7 Set Data Register (SET_DATA67) ............ GPIO Banks 4 and 5 Input Data Register (IN_DATA45) ............... 21-33............................... 912 21-11...... GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_RIS_TRIG45) ...................... 890 20-45.............www.................... 21-7...... GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_RIS_TRIG01) ............... 21-5..... 21-2...................... 40 ................................................................. 899 Revision ID Register (REVID) .................................................................................... 21-35................................................ 918 21-25...................................................................... 914 21-18........... GPIO Banks 4 and 5 Set Rise Trigger Register (SET_RIS_TRIG45) ............................................... 889 20-44.................. NAND Flash Control Register (NANDFCR) ........... 914 21-15.............. GPIO Banks 2 and 3 Input Data Register (IN_DATA23) ...................................................................................... GPIO Banks 0 and 1 Set Data Register (SET_DATA01) ..... 912 21-10.................... 918 21-28.................................................. 21-36....................... 916 21-20......................com 20-42..................... 918 21-26.......................... NAND Flash n ECC Register (NANDFnECC) ................. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_RIS_TRIG67) ................ 912 21-12...................................... GPIO Banks 2 and 3 Output Data Register (OUT_DATA23) ........ NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) ............ 21-32..................... 916 21-22....... NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) ...... Texas Instruments Incorporated 920 920 920 920 921 922 922 922 922 List of Figures SPRUH77A – December 2011 Submit Documentation Feedback ........ 919 21-29. 918 21-27...... GPIO Banks 6 and 7 Input Data Register (IN_DATA67) ...................................... GPIO Banks 6 and 7 Clear Data Register (CLR_DATA67) ............................................................ NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) ........................................... 914 21-16................................... GPIO Bank 8 Input Data Register (IN_DATA8) ................................................ 891 20-46....................................... 910 GPIO Banks 4 and 5 Direction Register (DIR45) ............................................. 895 20-53................................................ GPIO Banks 6 and 7 Output Data Register (OUT_DATA67) ................................................ 911 GPIO Banks 0 and 1 Output Data Register (OUT_DATA01) ............................................ GPIO Bank 8 Clear Data Register (CLR_DATA8) ........................... 912 21-13.. 21-3.................... 893 20-49..................... NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) ...... 916 21-23........................................................................................................ 910 GPIO Banks 6 and 7 Direction Register (DIR67) ...................................................................................................... NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) ........................ 910 GPIO Bank 8 Direction Register (DIR8) ............................................................................................................ 917 21-24.......... 21-37..................... 21-8....................................................................... GPIO Banks 4 and 5 Output Data Register (OUT_DATA45) .................................. GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_RIS_TRIG23) .......... 914 21-17........................................ 894 20-52............... GPIO Bank 8 Output Data Register (OUT_DATA8) ............... GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45) ........................................... NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) .................................................................... NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) ................ GPIO Bank 8 Set Rise Trigger Register (SET_RIS_TRIG8) ............................... NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD)......................................................... 21-4............ 21-34........... 913 21-14..... 887 20-43........... 908 GPIO Interrupt Per-Bank Enable Register (BINTEN) ...... 892 20-48.......................... 894 20-51........................ GPIO Banks 0 and 1 Set Rise Trigger Register (SET_RIS_TRIG01) 21-30................... GPIO Banks 2 and 3 Set Rise Trigger Register (SET_RIS_TRIG23) ............ 915 21-19........ 895 21-1........................................................ GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_RIS_TRIG67) ........................... GPIO Banks 0 and 1 Input Data Register (IN_DATA01) ................ 909 GPIO Banks 0 and 1 Direction Register (DIR01) ......... Copyright © 2011.......................................................................... GPIO Banks 4 and 5 Set Data Register (SET_DATA45) .... NAND Flash Status Register (NANDFSR) .... 916 21-21......................... 910 GPIO Banks 2 and 3 Direction Register (DIR23) ...................................................................................................

.............................................. Host Port Interface Control Register (HPIC)–Host Access Permissions 22-25.................... GPIO Bank 8 Clear Rise Trigger Register (CLR_FAL_TRIG8) ........... Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write) .................................................................................................... GPIO Bank 8 Clear Rise Trigger Register (CLR_RIS_TRIG8) ............................... 21-49........................................................ 946 22-11.............................. 925 926 926 926 926 927 928 928 928 928 929 933 938 940 942 943 944 945 UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 1: HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle) ........................................ 958 22-21...... 22-27....................... GPIO Banks 6 and 7 Interrupt Status Register (INTSTAT67) ........................ 954 22-17............. 22-3................................................................................................ 924 21-40.... 948 22-15..................... 959 22-23....................................................... FIFO Not Empty Before Write) ......................... HPI Strobe and Select Logic ........................................................................................ 22-26.................................................................. GPIO Banks 6 and 7 Set Rise Trigger Register (SET_FAL_TRIG67) ............................... 21-48............................. GPIO Direction 2 Register (GPIO_DIR2) ........................................................ CPU-to-Host Interrupt State Diagram ....... 22-5.......com 21-38.... I2C Peripheral Block Diagram ................................................................................ 946 22-13........................... GPIO Banks 4 and 5 Set Rise Trigger Register (SET_FAL_TRIG45) ........................ UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 3: Autoincrementing Selected..... Host Port Interface Control Register (HPIC)–CPU Access Permissions ... 924 21-43....................... 21-47....................... 945 22-10................ UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 2: Autoincrementing Selected. GPIO Banks 6 and 7 Clear Rise Trigger Register (CLR_FAL_TRIG67) .................... 22-2................................................................. 21-53................. GPIO Banks 0 and 1 Set Rise Trigger Register (SET_FAL_TRIG01) .................................................................. Multiple I2C Modules Connected ................................................................................ti............. FIFO Empty Before Write) ................................................... 21-46........... GPIO Banks 4 and 5 Clear Rise Trigger Register (CLR_FAL_TRIG45) ................................................ 21-52............. 957 22-20.................................................................................................... 22-1... GPIO Data 1 Register (GPIO_DAT1) ........ GPIO Bank 8 Interrupt Status Register (INTSTAT8) ................. Host Port Interface Write Address Register (HPIAW) ................ 22-6................................................ GPIO Direction 1 Register (GPIO_DIR1) .................................................www................................................. 923 21-39..... Multiplexed-Mode Host Write Cycle ................................. GPIO Bank 8 Set Rise Trigger Register (SET_FAL_TRIG8) 21-44. 23-2. Power and Emulation Management Register (PWREMU_MGMT) ................................ Host-to-CPU Interrupt State Diagram ................................................................................................... GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01) ............ 960 22-24....................................................... 22-8.. 956 22-19................................... .................................................................... 22-7...................................................... HPI Block Diagram......................... 22-9........ 21-51................................... 953 22-16.............. Multiplexed-Mode Host Read Cycle . Example of Host-Processor Signal Connections .................................................................... UHPI_HRDY Behavior During a Data Write Operation in the Multiplexed Mode (Case 1: No Autoincrementing) ...... Host Port Interface Read Address Register (HPIAR) ................................ GPIO Banks 2 and 3 Clear Rise Trigger Register (CLR_FAL_TRIG23) ......... 924 21-42............................................ 958 22-22........................ GPIO Banks 4 and 5 Interrupt Status Register (INTSTAT45) .... 924 21-41........................................... GPIO Banks 2 and 3 Set Rise Trigger Register (SET_FAL_TRIG23) ... 23-1............... GPIO Enable Register (GPIO_EN) . GPIO Data 2 Register (GPIO_DAT2) .................................... UHPI_HRDY Behavior During an HPIC Write Cycle in the Multiplexed Mode ..... UHPI_HRDY Behavior During an HPIC or HPIA Read Cycle in the Multiplexed Mode ................. ....... 21-45....................................... 945 UHPI_HRDY Behavior During a Data Read Operation in the Multiplexed Mode (Case 2: HPIA Write Cycle Followed by Autoincrement HPID Read Cycles) ....................... 22-4............... 947 22-14............. GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23) ................................................................... Texas Instruments Incorporated 961 961 963 963 967 968 41 SPRUH77A – December 2011 Submit Documentation Feedback ....... 21-50.......... 946 22-12.. Revision Identification Register (REVID) ......................................... 956 22-18................. FIFOs in the HPI ................................ GPIO Banks 0 and 1 Clear Rise Trigger Register (CLR_FAL_TRIG01) ........................... List of Figures Copyright © 2011..................

................. 24-11.................... I2C Interrupt Status Register (ICSTR) ..................... 23-29.......................................................................................................................... 981 23-14............................................ I2C Peripheral Data Transfer ........... 42 ............. 23-26........................................................................... 2............................. 995 I2C Extended Mode Register (ICEMDR) ................ Texas Instruments Incorporated .................. I2C Mode Register (ICMDR) 23-23.................... 976 23-13............................................................... I2C Data Transmit Register (ICDXR) .......................... 23-28.................................................................................... 973 23-11............................... 24-2......................... XA = 0 in ICMDR) ......... 23-31..................................................... 24-12................................... XA = 1 in ICMDR) ............................ 1004 I2C Pin Data Clear Register (ICPDCLR) ..................................................... 23-6............................................................................................. 4.......... 23-24..................... 997 I2C Revision Identification Register 1 (REVID1) ...... 983 23-16...... 994 I2C Interrupt Vector Register (ICIVR) ............ I2C Own Address Register (ICOAR) ........................................ Bit Transfer on the I2C-Bus..................... 999 I2C Pin Function Register (ICPFUNC) ................................... 24-7......................... 23-9........................................................ 986 23-18..... 23-4......................................................................................................................................................... 1025 SPRUH77A – December 2011 Submit Documentation Feedback List of Figures Copyright © 2011.............. 1021 1-BPP Data Memory Organization ........... 23-33....................................... I2C Interrupt Mask Register (ICIMR) . 1002 I2C Pin Data Out Register (ICPDOUT) ...................... 1020 4-BPP Data Memory Organization ............. 988 23-20........................ 986 23-17............................ 990 23-22.. 23-5......... 24-8........................................................................... XA = 0 in ICMDR) .............................................................................................. 989 23-21..............................................................................................................................................................................................com 23-3.................... 23-25................................ 998 I2C DMA Control Register (ICDMAC) ............... 23-34....... 982 23-15............................................... 23-32...... 24-15............................................................................ Arbitration Procedure Between Two Master-Transmitters .................................................... I2C Peripheral Free Data Format (FDF = 1 in ICMDR) .....................www............................................. 12..... 24-6............................ 1019 12-BPP Data Memory Organization—Little Endian ................. 973 23-12.......... 991 Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit ...................................................................... 1020 2-BPP Data Memory Organization .......... 23-27............................................................................................................................ I2C Clock Low-Time Divider Register (ICCLKL) ............... I2C Peripheral START and STOP Conditions ............................... 1005 LCD Controller ......................................................... I2C Peripheral 7-Bit Addressing Format (FDF = 0................................................ 23-30.... 24-3............ 1001 I2C Pin Data In Register (ICPDIN) .......... 1009 Logical Data Path for Raster Controller ................. 24-14.................... 1016 Frame Buffer Structure ......................................................................................... 1018 256-Entry Palette/Buffer Format (8 BPP) ....................... 23-8....................... .......................... 23-7......................... 24-9....................................... 23-35.................................... 1021 Monochrome and Color Output .................. 987 23-19............................................. 1019 16-BPP Data Memory Organization (TFT Mode Only)—Little Endian ................................................ 16 BPP) .............. 973 23-10.............. 996 I2C Prescaler Register (ICPSC) .... 24-10.... 24-4......................................... 998 I2C Revision Identification Register 2 (REVID2) ................. I2C Peripheral 7-Bit Addressing Format With Repeated START Condition (FDF = 0........................................................................................................................... Synchronization of Two I2C Clock Generators During Arbitration......... 1000 I2C Pin Direction Register (ICPDIR) ................... 24-1............... 1024 LCD Revision Identification Register (REVID) ............................... I2C Clock High-Time Divider Register (ICCLKH) .......................... 24-5.... 1020 8-BPP Data Memory Organization .... 1023 Raster Mode Display Format .......................ti... I2C Data Count Register (ICCNT) .................................................................... 1003 I2C Pin Data Set Register (ICPDSET)..................................................................... I2C Data Receive Register (ICDRR) ....................................... 24-13..................... Clocking Diagram for the I2C Peripheral 969 970 971 971 972 972 I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing to Slave-Receiver (FDF = 0.............................. I2C Slave Address Register (ICSAR) ........................................ 1008 Input and Output Clocks ........ 1017 16-Entry Palette/Buffer Format (1................................................................

................. Subpanel Display: SPEN = 1............................................................. 25-12......... McASP to Parallel 2-Channel DACs ....................... 25-20........................ List of Figures Copyright © 2011................... SYNC_CTRL = 0........................ Vertical Front Porch (VFP) ......... LCD LIDD CSn Data Read/Write Register (LIDD_CSn_DATA) ............................................................Active Mode.. 25-9.......... Vertical Synchronization Pulse Width (VSW) ..................................................... 1032 24-20...... 1028 24-18.......................... 25-16.......... 25-5........... Bit Order and Word Alignment Within a Slot Examples ........... Active Mode Pixel Clock and Data Pin Timing ....................... 1040 24-27... 1046 24-34................................. LCD Raster Subpanel Display Register (RASTER_SUBPANEL) .. 1026 24-17...... 25-1..... SYNC_CTRL = 1........................................ 25-21... 25-18............. HOLS = 1 24-40................................................ LCD LIDD Control Register (LIDD_CTRL) ........ 1035 24-23................................. 25-6............ 1039 24-26.... McASP Block Diagram................ 16-BPP STN Mode ................... 25-15.................................. LCD Raster Timing Register 0 (RASTER_TIMING_0) ................................................ IPC = 1 in TFT Mode .. LCD DMA Frame Buffer n Base Address Register (LCDDMA_FBn_BASE) ................. 25-8.......................... 25-14.......... 25-3......................................... 25-4....... McASP to 6-Channel DAC and 2-Channel DAC ........................................ LCD DMA Frame Buffer n Ceiling Address Register (LCDDMA_FBn_CEILING) ......................................................................................................... 24-43........................................................................................................ Word.............................................. 25-2.............. SYNC_EDGE = 0.... ............................................. 25-11................... S/PDIF Frame Format .. 24-42........ TDM Format Bit Delays from Frame Sync .......... 25-7......................................................................................... 1045 24-33................................................................................................................................................................................................................................ Monochrome Passive Mode Pixel Clock and Data Pin Timing .............................................. Receive Format Unit .............................. Frame Sync Generator Block Diagram . LCD Control Register (LCD_CTRL) ........ TFT Alternate Signal Mapping Output .................... 1038 24-24........................................... 1042 24-31.......................... Inter-IC Sound (I2S) Format ........ 1041 24-28....................... and IPC = 1 ................... 1047 24-35........................... 24-41............................................. 1052 24-39........................... Vertical Back Porch (VBP) ........................................ Individual Serializer and Connections Within McASP ....................................................................................................................................................................................................... Biphase-Mark Code (BMC) .................. 1041 24-30..... LCD LIDD CSn Configuration Register (LIDD_CSn_CONF) .............................. LCD DMA Control Register (LCDDMA_CTRL) ................................... Texas Instruments Incorporated 1053 1053 1054 1055 1055 1060 1061 1061 1062 1062 1063 1064 1064 1065 1066 1067 1068 1069 1070 1072 1073 1074 1075 1076 1077 1079 43 SPRUH77A – December 2011 Submit Documentation Feedback .................................................. 25-17.... 1051 24-38................ Subpanel Display: SPEN = 1........... 25-13......................................................... 16-Bit STN Data in Frame Buffer ..................................................................................... S/PDIF Subframe Format ................................ LCD Status Register (LCD_STAT) ........................... LCD Raster Timing Register 2 (RASTER_TIMING_2) .................................................. 25-10............................................................ 1050 24-37.........ti.......................... HOLS = 0 ................. 1044 24-32................... TDM Format–6 Channel TDM Example ................... LCD Raster Timing Register 1 (RASTER_TIMING_1) ....................... McASP as Digital Audio Encoder ................................. LCD LIDD CSn Address Read/Write Register (LIDD_CSn_ADDR) .................................................................................................... McASP I/O Pin Control Block Diagram ........................................................................... 1034 24-22.................................. LCD Raster Control Register (RASTER_CTRL) .................................... Transmit Format Unit............ and Slot .................. Receive Clock Generator Block Diagram ...............................................................................................................com 24-16........ 1038 24-25........................................ Definition of Frame and Frame Sync Width ..................................................................... 12-Bit STN Data in Frame Buffer .......... Definition of Bit................................................ 25-19...................................................................................................................................... McASP to Digital Amplifier .................... 1048 24-36.................................................................... Color Passive Mode Pixel Clock and Data Pin Timing ...... 1033 24-21...........www............................................................ Transmit Clock Generator Block Diagram...................... 1030 24-19............. 1041 24-29.....................................

......................... 25-67............................................... Pin Data Clear Register (PDCLR) ............................. 25-37..................... 25-44.......... 44 ................... Receiver Global Control Register (RGBLCTL) .................com 25-22...................... 25-59................. Transmit Format Unit Bit Mask Register (XMASK) ........................................................................ 25-63................................ Audio Mute Control Register (AMUTE) .......................................................................................................................... Transmitter DMA Event Control Register (XEVTCTL) ........ Current Receive TDM Time Slot Registers (RSLOT) ... Pin Direction Register (PDIR) ...........ti................................... 25-53....................... 1080 25-23.. Receive Format Unit Bit Mask Register (RMASK) ........... 25-52......................... 1085 25-24................. 25-43.......... Receive High-Frequency Clock Control Register (AHCLKRCTL) ................................................................................... Pin Data Input Register (PDIN) ........................................................................... 1097 25-28........................................................ Data Flow Through Transmit Format Unit ................ Receiver Interrupt Control Register (RINTCTL) ................... 25-55.......................................................................................................................... 1088 25-25........................ 25-57........ 25-56..... 1098 1103 1105 1109 1110 1111 1117 1117 1119 1121 1123 1125 1127 1129 1131 1133 1134 1135 1136 1137 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 25-29.................................... 25-62.... Transmitter Interrupt Control Register (XINTCTL) ............ Global Control Register (GBLCTL) ............................................................................................. 25-50........ Transmitter Status Register (XSTAT) ............................................................................................. 1101 ...................... Burst Frame Sync Mode ............................................................ Audio Mute (AMUTE) Block Diagram .......................................... Digital Loopback Control Register (DLBCTL) .......................................... McASP I/O Pin to Control Register Mapping ................................................... 25-49............................................................................................ Serializer Control Registers (SRCTLn) ...... 25-32............................ 25-64.................................... Data Flow Through Receive Format Unit 25-31......................... 25-54......................................... 25-70....................................... 25-33.............................. Transmit Bit Stream Format Register (XFMT) ............................................... Texas Instruments Incorporated List of Figures SPRUH77A – December 2011 Submit Documentation Feedback ............... Receive Frame Sync Control Register (AFSRCTL).......................................................................................................................... Pin Function Register (PFUNC) ............................ Transmit DMA Event (AXEVT) Generation in TDM Time Slots .................................................................... Receiver Status Register (RSTAT).............................................. Transmitter Global Control Register (XGBLCTL) ........................... 25-60................... Pin Data Set Register (PDSET) ...... 25-58........ Transmit TDM Time Slot Register (XTDM) . DSP Service Time Upon Transmit DMA Event (AXEVT) ..... Transmit Clock Control Register (ACLKXCTL) ................................ 25-38........................................................ 25-35..................... 25-40..... 25-47............. 25-41......................... Transmit Frame Sync Control Register (AFSXCTL) ..................................................................................................... 25-66....... Pin Data Output Register (PDOUT) ............................ Receive Clock Check Control Register (RCLKCHK) ............................................................................... Serializers in Loopback Mode ................................... Current Transmit TDM Time Slot Register (XSLOT) .... Transmit High-Frequency Clock Control Register (AHCLKXCTL) .................................... Revision Identification Register (REV) ........ DSP Service Time Upon Receive DMA Event (AREVT) ................. 25-61............................................ 25-45............................................. 25-46............................................................ Receive Clock Failure Detection Circuit Block Diagram....................................................... McASP Audio FIFO (AFIFO) Block Diagram 25-30.... 25-42..................................... 25-51............. 25-65................................. Receive TDM Time Slot Register (RTDM) ................................ Digital Mode Control Register (DITCTL) ........................................... Copyright © 2011......................... 25-34............................................................................................. Receive Bit Stream Format Register (RFMT) ............................................. 1093 25-26............................ 25-39................................................ Receiver DMA Event Control Register (REVTCTL).............. 25-69.. 25-68.......... Transmit Clock Failure Detection Circuit Block Diagram .. Receive Clock Control Register (ACLKRCTL) .........................................................................................................................................www.................. 1095 25-27........................................ 25-36.......... DMA Events in an Audio Example–Two Events......................... 25-48................................. Transmit Clock Check Control Register (XCLKCHK) .................

............................................ 2-Bit Data Delay Used to Discard Framing Bit .... Unexpected Receive Frame Synchronization Pulse ..... 1162 25-72.... 26-38................................ McBSP Buffer FIFO (BFIFO) Block Diagram .......................... Digital Loopback Mode List of Figures Copyright © 2011............... Write FIFO Control Register (WFIFOCTL) ......................................... McBSP Standard Operation............................................... 26-7......................... 26-25................................... 26-10................ 1169 McBSP Block Diagram................... 26-13......................................................................................www.... Single-Phase Frame of Four 8-Bit Elements ........................................................ti. Transmit Operation ......... 26-12............................................................................................. 1163 25-74............................................................................................................................................................................................................................... 1177 CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 ................................................................................................................ Companding Data Formats . 26-8............................................................................................................................. Data Delay..................................................................................... 26-15............................................................................... DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) ............................................................................................. Maximum Frame Frequency for Transmit and Receive ...................................... 1165 25-78.................................. Dual-Phase Frame Example ..................................... Companding Flow ........................................... Programmable Frame Period and Width .................................. 26-9....... 1173 Clock and Frame Generation ................................. Maximum Frame Frequency Operation With 8-Bit Data ........................................................................................ Write FIFO Status Register (WFIFOSTS) .................... 1180 ................................ 26-24............................................................. 1176 Sample Rate Generator Block Diagram .............. Serial Port Receive Overrun Avoided ....... Alternating Between the Channels of Partition A and the Channels of Partition B ................................ 26-30.......... AFIFO Revision Identification Register (AFIFOREV) ............................................ 26-37................ DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) .................... Receive Buffer Registers (RBUFn).......................................................... 26-5................. Transmit With Data Overwrite ........................ Unexpected Frame Synchronization With (R/X)FIG = 0 ................................................. 1168 25-81.......................... Transmit Empty ............................ 26-2...... 1176 Receive Data Clocking................... Read FIFO Status Register (RFIFOSTS) .............................. 26-31.. 26-32.com 25-71.................................................................................................. Receive Operation.............. 26-34.................. 26-3............ 26-29........................................................................................ 1167 25-80...... Transmit Data Companding Format in DXR ........................................... 26-11................................................................... 26-20............................... Decision Tree Response to Receive Frame Synchronization Pulse...................................... 26-19.......................................... Unexpected Frame Synchronization With (R/X)FIG = 1 .............................................. Data Packing at Maximum Frame Frequency With (R/X)FIG = 1 ................................ 1163 25-75........... 1166 25-79.................................... Read FIFO Control Register (RFIFOCTL) 26-1.................................................. 26-28........................................ Serial Port Receive Overrun ................... Decision Tree Response to Transmit Frame Synchronization Pulse ......... Transmit Empty Avoided .................. 26-33................ 1175 Transmit Data Clocking ........ Texas Instruments Incorporated 1181 1183 1185 1186 1187 1187 1188 1189 1190 1190 1191 1192 1193 1193 1194 1195 1195 1196 1197 1197 1198 1198 1200 1200 1201 1203 1203 1203 1204 1206 1208 45 SPRUH77A – December 2011 Submit Documentation Feedback ............... 26-14........................................... 26-26.. 1180 CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 ........ Single-Phase Frame of One 32-Bit Element ............. 26-27...... DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) ........................ Unexpected Transmit Frame Synchronization Pulse .... 26-6..................................................................................... 26-16... 26-18.................. 26-23.. 1162 25-73.................................................. 26-36.................................. DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) ........................................................................ Companding of Internal Data ................................................................................. Transmit Buffer Registers (XBUFn) ........................................................................ 26-17........................................ 26-35.... 1164 25-76...................................................... 1164 25-77............... 26-4.............................. .................. DX Timing for Multichannel Operation .................................................... 26-21........................... 26-22.......................

.................................................................................................................. MMC Status Register 1 (MMCST1) ............... Receive Control Register (RCR) .............................................. 26-49........................................................................ MMC Memory Clock Control Register (MMCCLK) ........ 27-31..... Enhanced Receive Channel Enable Register n (RCEREn) .......... Serial Port Control Register (SPCR) ..................................................... MMC Response Time-Out Register (MMCTOR) ........ 27-16........ 27-22............. Sample Rate Generator Register (SRGR) ................................................................................................................................................................. MMC Configuration and SD Configuration Diagram ... 27-21............ MMC/SD Multiple-Block Write Operation ...................................... Read FIFO Control Register (RFIFOCTL) ....................... MMC Data Read Time-Out Register (MMCTOD) ....................................................... Texas Instruments Incorporated 1208 1209 1212 1222 1222 1223 1225 1227 1229 1230 1234 1236 1238 1240 1241 1242 1243 1244 1246 1247 1248 1249 1250 1251 1252 1253 1255 1257 1264 1265 1267 1269 1271 1273 1276 1277 1278 1280 1281 1283 1284 1285 1286 1286 1287 1287 1288 1289 1290 List of Figures SPRUH77A – December 2011 Submit Documentation Feedback ...................................................................................... 27-5............... Little-Endian Access to MMCDXR/MMCDRR from the CPU or the EDMA ........................................ MMC/SD Card Controller Block Diagram ............................................ 27-6............ 27-14..................................................... MMC Card Identification Procedure ................................ MMC Command Register (MMCCMD) .............. McBSP Data Transfer in the 8-Partition Mode ... 27-26....................................................... 26-41...............................................................................www......................................... 27-29.................................................. Transmit Control Register (XCR) ..................... 46 .................................................... Write FIFO Control Register (WFIFOCTL) ....................................................................... MMC/SD Mode Read Sequence Timing Diagram ................... 26-48............................................................................................................................................................................ 27-2... 27-9.............. 27-10.......................................................................................... MMC Control Register (MMCCTL) ............................. 27-19................................................................................ 27-28........ 26-42.......................................................................................................... 27-27................................................... FIFO Operation During Card Write Diagram ................................ 26-53..................................... MMC Number of Blocks Register (MMCNBLK) .... MMC/SD Mode Single-Block Write Operation ....com 26-39. MMC Data Transmit Register (MMCDXR) ... MMC/SD Mode Single-Block Read Operation ....................................... 26-45.... MMC Interrupt Mask Register (MMCIM)...... 27-7...... 27-20.......................................................................................................................................................... 26-44....................................... 27-24................................. Read FIFO Status Register (RFIFOSTS) .................................................................................................... 27-13............ 27-1............................ MMC Number of Blocks Counter Register (MMCNBLC) ... Reassigning Channel Blocks Throughout a McBSP Data Transfer 26-40..................................... 27-18..... Data Receive Register (DRR) ............................... 27-25... MMC Block Length Register (MMCBLEN) ........................ MMC Argument Register (MMCARGHL) ............... 27-8.................................................. 26-56........................................................... Data Transmit Register (DXR) ............................. 26-47.......................... FIFO Operation Diagram ................ Enhanced Transmit Channel Enable Register n (XCEREn) ...................................................... 27-15....................................................... MMC Data Receive Register (MMCDRR) ........................................................................ 26-43..................... 26-46.................................................... Multichannel Control Registers (MCR) ............................................................ FIFO Operation During Card Read Diagram . 26-55........................................ Command Format ............................ SD Card Identification Procedure ................................................................................................... BFIFO Revision Identification Register (BFIFOREV) ................. 27-30...... MMC/SD Controller Clocking Diagram ..................... Write FIFO Status Register (WFIFOSTS) ................... 27-4...... 27-11......... 26-50.................................. 26-52........ 27-3.............. MMC/SD Mode Write Sequence Timing Diagram ..... 27-12................ Activity on McBSP Pins for the Possible Values of XMCM .......... 26-54............................................................. 27-17.......................................... MMC/SD Controller Interface Diagram ........................................ 27-23................ 26-51................................................... MMC Status Register 0 (MMCST0) ..........ti.......................................... Copyright © 2011.... Pin Control Register (PCR) ....... MMC/SD Mode Multiple-Block Read Operation ...............................

... 29-7.................................... 1308 Hour Register (HOUR) .................... 29-5.............. 1314 28-15...................................com 27-32..................................................................................................................... 28-2................................................................................................................................. Ports Implemented Register (PI) ............................................................ 1300 32-kHz Oscillator Counter Compensation ................... 28-6....... BIST Active FIS Register (BISTAFR) ..................................... 29-2.......... Alarm Second Register (ALARMSECOND) ............................................................................................... MMC Data Response Register (MMCDRSP) ............................. 29-11................................................ MMC Command Index Register (MMCCIDX).......................................... 28-9................... MMC Response Register 6 and 7 (MMCRSP67) ................................................... 1293 27-38............................................ 1316 28-18................................................................ HBA Capabilities Register (CAP) ..........ti................... 1308 Minute Register (MINUTE) ..................................................... 28-5. Interrupt Register (INTERRUPT) . 1291 27-36............ Interrupt Status Register (IS) ....................... 1291 27-35...................... 29-8...................................... 1291 27-33....................... BIST FIS Count Register (BISTFCTR) . 1311 28-10.................... List of Figures Copyright © 2011..................................................................................................................................... 1309 Days Register (DAY) ......... Alarm Day Register (ALARMDAY) ................ Alarm Minute Register (ALARMMINUTE) ......... Command Completion Coalescing Ports Register (CCC_PORTS) ........................................................... 1291 27-34.......... 28-8...................................... 1319 28-21................. BIST Control Register (BISTCR) ............................. SATA Subsystem Functional Block Diagram .......................................................................................................................................................... 1311 28-11............................ SDIO Interrupt Enable Register (SDIOIEN) .................................... 29-10....................................................................................................... 1317 28-19............................... Kick Registers (KICKnR) ........ MMC FIFO Control Register (MMCFIFOCTL) ...................... 29-9............................................ Alarm Hour Register (ALARMHOUR)........................................................ MMC Response Register 2 and 3 (MMCRSP23) ....................................................................... 1315 28-17.. 1294 27-39...................................... Status Register (STATUS) ...................................................................................................................................................................... Global HBA Control Register (GHC) ......................................................................................................................................................................... 29-1............................................................................................................................... 29-12.............................................. 1313 28-14..... SDIO Interrupt Status Register (SDIOIST) ....... 29-14............. SDIO Control Register (SDIOCTL) ......... Alarm Year Register (ALARMYEAR) ............................................ Texas Instruments Incorporated 1321 1322 1322 1325 1326 1355 1356 1357 1358 1358 1359 1360 1361 1362 1364 1364 1365 47 SPRUH77A – December 2011 Submit Documentation Feedback ............................. Command Completion Coalescing Control Register (CCC_CTL)......................www......................................................... AHCI Version Register (VS) ...................................................... SATA Core Block Diagram ......................... 1310 Month Register (MONTH) .. Alarm Month Register (ALARMMONTH) ............ Scratch Registers (SCRATCHn) ............................................................................................................................... Day of the Week Register (DOTW) ............................................ MMC Response Register 0 and 1 (MMCRSP01) .................................... 1293 27-37............................................................................. 28-7............... 1310 Year Register (YEAR) ................................. ........ 28-23...................... Real-Time Clock Block Diagram..................................................... 1312 28-13........................ Oscillator Register (OSC) 28-24............................................. Compensation (LSB) Register (COMPLSB) ................................ 29-3.............................................................................. 28-3..................................................... 28-4....... 1320 28-22.... 29-4......... 1295 27-40......... Control Register (CTRL) .......................... 1312 28-12.......... Compensation (MSB) Register (COMPMSB) . 1296 27-42....................................................................................................................................... 1304 Kick State Machine ............. 1315 28-16............................................. 29-13....................................... 29-6...... BIST Status Register (BISTSR) ....................................................... MMC Response Register 4 and 5 (MMCRSP45) ............................ 1296 27-41................................. 1318 28-20....................... BIST DWORD Error Count Register (BISTDECR) .............................. 1305 Second Register (SECOND) ........... 1297 28-1............... SDIO Status Register 0 (SDIOST0)........................................

................................. 30-15................ 29-20........................................................ 30-14...................... SPI Pin Control Register 0 (SPIPC0) ................................... SPI Block Diagram ............................................................ 30-19........ 30-13..................................... 30-9.................... Port Serial ATA Active Register (P0SACT) ................... 30-16....................................... Global Parameter 2 Register (GPARAM2R) ........ Texas Instruments Incorporated 1365 1366 1367 1368 1369 1370 1370 1371 1371 1372 1374 1375 1378 1378 1379 1380 1381 1383 1383 1384 1385 1387 1391 1395 1401 1403 1405 1407 1408 1408 1409 1410 1410 1410 1411 1416 1417 1418 1420 1421 1422 1423 1425 1427 1428 1430 1431 1432 1433 List of Figures SPRUH77A – December 2011 Submit Documentation Feedback ............................................................................. 30-17.............................. Port FIS Base Address Register (P0FB) .............................. 30-6. 30-3..................... 29-26............................................................. 30-20.................. 30-18. SPI Interrupt Level Register (SPILVL) ..................................................... 30-10........ SPI 4-Pin with SPIx_ENA Mode Demonstrating T2EDELAY and WDELAY .... SPI 4-Pin Option with SPIx_SCS[n] ................ 30-22................... Port Interrupt Enable Register (P0IE) .................................................................................... ID Register (IDR) ....com 29-15.......................................................................................................................... Five Bits per Character (5-Pin Option).......................... SPI 4-Pin with SPIx_SCS[n] Mode with T2CDELAY.................................. 29-19...................................... Port DMA Control Register (P0DMACR) ................ 29-32................... 29-24................................ 30-11... Port Serial ATA Status Register (P0SSTS) ................................................................................................................................... SPI 3-Pin Master Mode with WDELAY ............................................ SPI Global Control Register 0 (SPIGCR0) ............................................................ 30-25......................................................................................... 30-26....................... Port Parameter Register (PPARAMR) ....................... Port PHY Status Register (P0PHYSR) ............................ Clock Mode with POLARITY = 1 and PHASE = 0 ..........................www............................................................... Copyright © 2011......................................................................................... 30-2............................................ SPI 5-Pin Option with SPIx_ENA and SPIx_SCS[n] ....... 29-31........................................... 30-4...................................................... 29-29..ti............... Port Interrupt Status Register (P0IS) ..................................................... Port Command List Base Address Register (P0CLB) ............................................................................................................................. 29-37........................................................ 29-18........................ Port Serial ATA Active (SActive) Register (P0SACT) ........ SPI 4-Pin Option with SPIx_ENA .... SPI Pin Control Register 2 (SPIPC2) ......................................................................... SPI Pin Control Register 3 (SPIPC3) ............. SPI Pin Control Register 1 (SPIPC1) ............................................................... 30-8....... Port Task File Data Register (P0TFD) ...................... 29-34................................... 30-21................................................................................... 29-23........... Format for 10-Bit Received Word ..................................................................... SPI 5-Pin Mode Demonstrating C2TDELAY and C2EDELAY ............................................................................................................................................ 48 ...................................... 30-23..... 30-1............. Format for Transmitting 12-Bit Word ................. Port PHY Control Register (P0PHYCR) ........... 29-30.... 30-5............... BIST DWORD Error Count Register (TIMER1MS) 29-16...... and WDELAY .. 30-24............................................................ Port Command Register (P0CMD) .............. Port Serial ATA Notification Register (POSNTF) ...... SPI Global Control Register 1 (SPIGCR1) ........................................ SPI 5-Pin Mode Demonstrating T2CDELAY.... 29-33............ 29-28............ Port Serial ATA Error Register (P0SERR) .......................................... Version Register (VERSIONR) ....................................................................................................... 29-21............................... 29-25........... Port Serial ATA Control Register (P0SCTL) ........................................................................... WDELAY................................................................ and C2TDELAY ................ SPI Flag Register (SPIFLG) ........................................................... 30-7.. Clock Mode with POLARITY = 0 and PHASE = 1 ..................................... Test Register (TESTR) ........ Global Parameter 1 Register (GPARAM1R) ............................................................. 29-36................ 29-27.......................................................... Port Signature Register (P0SIG) ............... SPI Interrupt Register (SPIINT0) .......................................... T2EDELAY.... 30-12...... 29-22. 29-17........................................................................................................................................................... Clock Mode with POLARITY = 0 and PHASE = 0 ......................... SPI 3-Pin Option ....... 29-35.............. Clock Mode with POLARITY = 1 and PHASE = 1 .......

..................................................... 1437 30-31.................... Autoflow Functional Timing Waveforms for UARTn_RTS .......... UART Block Diagram ................ UART Protocol Formats ......... 31-27................................... Watchdog Timer Control Register (WDTCR) ... Watchdog Timer Mode Block Diagram ..... SPI Data Register 0 (SPIDAT0) ....... Timer Interrupt Control and Status Register (INTCTLSTAT) ...................... 31-26.......................................................... 30-39. Example: tT2CDELAY = 4 SPI Module Clock Cycles 30-36........................................................ SPI Data Register 1 (SPIDAT1) ................................... 31-2.....com 30-27............................................................................................................................. 1440 30-33.............. 31-1....... SPI Interrupt Vector Register 1 (INTVEC1) ............................................................ 31-6......................................................... Dual 32-Bit Timers Unchained Mode Block Diagram ....... Timer Clock Source Block Diagram ........................................................................... 32-6.................... 31-14............................................................ 31-5.................................................... Timer Capture Register 12 (CAP12) . SPI Pin Control Register 5 (SPIPC5) ......................................................... Texas Instruments Incorporated 1442 1443 1443 1443 1444 1445 1447 1451 1452 1453 1456 1456 1458 1459 1462 1464 1464 1466 1466 1469 1469 1470 1471 1472 1472 1473 1473 1474 1476 1477 1478 1478 1479 1479 1480 1481 1485 1486 1487 1489 1492 1493 49 SPRUH77A – December 2011 Submit Documentation Feedback ......................................... Timer Compare Register (CMPn) ..................... SPI Buffer Register (SPIBUF) ........................................ BCLK.................................................................. Dual 32-Bit Timers Unchained Mode Example ..................... UART Interface Using Autoflow Diagram ........... GPIO Data and Direction Register (GPDATGPDIR) ................ Example: tC2TDELAY = 8 SPI Module Clock Cycles 30-35................... 32-5..... Timer Counter Register 34 (TIM34) ............................................ Timer Capture Register 34 (CAP34) .. 1435 30-29...................................................................................................................................................... 1441 30-34. 31-8.................................................................................................................... UART Clock Generation Diagram ................. 31-13....................................................................... Transmit-Data-Finished-to-SPIx_ENA-Inactive-Timeout ...... 31-4.......................... 1438 30-32...................................................... 30-40........ 31-23.............................. List of Figures Copyright © 2011... 31-19........ Timer Counter Register 12 (TIM12) ...... 31-16................. 31-22.......... Timer Operation in Clock Mode (CPn = 1) ........ SPI Data Format Register (SPIFMTn) .................. 31-29............................................................................... SPI Default Chip Select Register (SPIDEF) ....... 31-3..................................................... Timer Period Register 12 (PRD12) ...................................................................... Timer Reload Register 34 (REL34) ........... Timer Operation in Pulse Mode (CPn = 0) ............ 31-9..................... 1434 30-28........................................... SPI Pin Control Register 4 (SPIPC4) ......................................... 31-17.................................................................................................... 1436 30-30.....................................................................................www...................... SPI Delay Register (SPIDELAY) .............................. Watchdog Timer Operation State Diagram ...................................................... Timer Control Register (TCR)............................................................................................................ Relationships Between Data Bit................................................................................. Revision ID Register (REVID) ............... ... Emulation Management Register (EMUMGT) ................. 31-25................................................... 31-7........................................................................................................... 64-Bit Timer Mode Block Diagram .................... 32-3................................................................. 32-2............................................... Timer Global Control Register (TGCR) .......... 31-12.................................... 31-20......................................... 31-11............................. GPIO Interrupt Control and Enable Register (GPINTGPEN) .......................................................................................................... Timer Period Register 34 (PRD34) ..................................... 31-24................ 32-1....... 30-37........... 32-Bit Timer Counter Overflow Example .............................................................................................. 31-21..................... 31-28... Dual 32-Bit Timers Chained Mode Block Diagram ......................................................................................... 30-38...... .............................................................. Dual 32-Bit Timers Chained Mode Example ........... SPI Emulation Register (SPIEMU) ..................................... and UART Input Clock ................................................................................... 31-15... Chip-Select-Active-to-SPIx_ENA-Signal-Active-Timeout ............ti................... Timer Block Diagram ................................................................. 31-18................................................................... 32-4......................... Timer Reload Register 12 (REL12) ............. 31-10..................................

................................. uPP DMA Channel I Descriptor 1 Register (UPID1) ............................................................DDRDEMUX) ....................... 1529 33-15.............................. 32-8............ 33-10........................................ 33-1....... UART Interrupt Request Enable Paths ... 33-3.............. 33-29............................. 32-22....................... Copyright © 2011................... 33-20................ Data Flow for Digital Loopback (DLB) Mode (Duplex Mode 0) . Signal Timing for uPP Channel in Transmit Mode with Single Data Rate ....................... Line Status Register (LSR) .................................................................................................................... uPP Interrupt Enable Set Register (UPIES) .............. Signal Timing for uPP Channel in Receive Mode with Double Data Rate and Data Interleave Enabled (via UPCTL.............................................................. 33-21.. Signal Timing for uPP Channel in Receive Mode with Single Data Rate ..................................... uPP Threshold Configuration Register (UPTCR) ....................................................................... uPP Interrupt Enabled Status Register (UPIER) ................................ 33-4............................................................ Receiver Buffer Register (RBR) ............................. Transmitter Holding Register (THR) ... Data Flow for Single-Channel Transmit with Data Interleave ......................... 33-27...... 32-24..................... 33-23................................................... ............ Structure of DMA Window and Lines in Memory .......... 33-19.................................................. 33-12...................................................................................................... uPP Peripheral Control Register (UPPCR) 33-18....................... 32-12................................... Interrupt Identification Register (IIR) ............................SDRTXIL) ........ uPP DMA Channel I Descriptor 0 Register (UPID0) ............................................................. Divisor LSB Latch (DLL) ............................................ Texas Instruments Incorporated 1539 1540 1541 1543 1545 1546 1547 1549 1551 1553 1555 1555 1556 List of Figures SPRUH77A – December 2011 Submit Documentation Feedback ............. Data Flow for Single-Channel Transmit Mode ...... Modem Status Register (MSR) ..... Data Flow for Single-Channel Receive Mode ............................................................................................................. 32-17.......................................................................................................... 33-22.. uPP Functional Block Diagram ................... Signal Timing for uPP Channel in Receive Mode with Double Data Rate ................... Signal Timing for uPP Channel in Transmit Mode with Double Data Rate and Data Interleave Enabled (via UPCTL.............. 1529 33-14.......................... 33-25.................................... Power and Emulation Management Register (PWREMU_MGMT) ............... 33-8................................................................................................................................................................................................................................................... uPP Digital Loopback Register (UPDLB) ....... Revision Identification Register 1 (REVID1) .. 33-5.............................. Line Control Register (LCR) ......DDRDEMUX) ................ 32-18............................................ Clock Generation for a Channel Configured in Transmit Mode ............................................ Clock Generation for a Channel Configured in Receive Mode ................................................................ 33-11................................... 33-2.................................................................. Signal Timing for uPP Channel in Transmit Mode with Single Data Rate and Data Interleave Enabled (via UPCTL........ uPP Interrupt Raw Status Register (UPISR) ........ 33-9. 32-9........................................................ 32-16.............................................................. 33-24............... 32-23........................ FIFO Control Register (FCR) ............................................................ uPP Interface Configuration Register (UPICR) ............. Divisor MSB Latch (DLH) .................................................. 32-20............... uPP End of Interrupt Register (UPEOI) .............................................................................................................. Scratch Pad Register (SCR) ................................................................. uPP Channel Control Register (UPCTL) ......................... 33-6.................... 32-21..................... 32-13........... uPP Peripheral Identification Register (UPPID) ............... 32-10................................ti................................. 1529 33-16............. 33-26............................. Modem Control Register (MCR) ............................................... Autoflow Functional Timing Waveforms for UARTn_CTS 1493 1495 1498 1499 1500 1501 1503 1504 1506 1507 1510 1511 1512 1512 1513 1513 1514 1515 1519 1519 1519 1520 1520 1521 1521 1524 1527 1528 1528 1528 33-13................................................ Mode Definition Register (MDR)....................... 32-19.............................com 32-7................. uPP Interface Idle Value Register (UPIVR) ... uPP Interrupt Enable Clear Register (UPIEC) .......................................... 32-14...........www................................ 33-7..................................... Signal Timing for uPP Channel in Transmit Mode with Double Data Rate .. Interrupt Enable Register (IER) ........... Revision Identification Register 2 (REVID2) .................................................................................................................. 32-11....................... 33-28....................... 50 ...................................................................... 1538 33-17.. 32-15..........................................................

..... 34-5...................................................................................................... uPP DMA Channel I Descriptor 2 Register (UPID2) .... 1576 HC Current Periodic Register (HCPERIODCURRENTED) .................. HC Current Bulk Register (HCBULKCURRENTED) ..... 1561 33-39...... 34-7........................................................... 34-8.. 35-14.................... 34-6.......................................... HC Current Control Register (HCCONTROLCURRENTED) ....................................................... 34-3...................................... List of Figures Copyright © 2011...................................... 1577 34-12.......................................................................... 34-4......................... 1581 34-19.......................... USB Clocking Diagram ..................... 35-6............... HC Root Hub B Register (HCRHDESCRIPTORB) 34-22.......... HC Root Hub Status Register (HCRHSTATUS) ..................... uPP DMA Channel Q Descriptor 2 Register (UPID2) ......... uPP DMA Channel Q Descriptor 1 Register (UPQD1) ............. 35-13.................................. 1559 33-36............................................................................................................................ Service Endpoint 0 Flow Chart ............................. TX Mode Flow Chart ............................... uPP DMA Channel I Status 0 Register (UPIS0) .... uPP DMA Channel Q Status 1 Register (UPQS1) ................................................................................................................ 35-8................................................. 1559 33-35..................................... 1572 HC Interrupt and Status Register (HCINTERRUPTSTATUS) ................................. IN Data Phase Flow Chart ........... 35-15.......................................................................................................................ti...................... Completion of IN Data Phase Flow Chart .. 1562 34-1.............................................. 35-5.......................................... Interrupt Service Routine Flow Chart ................................................................................................... 1575 HC HCAA Address Register (HCHCCA) ......... 1580 34-18............ 35-7........... HC Frame Number Register (HCFMNUMBER) .............. 34-2. CPU Actions at Transfer Phases .................. 1574 HC Interrupt Disable Register (HCINTERRUPTDISABLE) .............. Completion of SETUP or OUT Data Phase Flow Chart ......... Setup Phase of a Control Transaction Flow Chart ......................................................... 1578 34-13........................... uPP DMA Channel I Status 1 Register (UPIS1) ................... 1573 HC Interrupt Enable Register (HCINTERRUPTENABLE).. 1577 34-11..... HC Head Done Register (HCDONEHEAD) ........................ uPP DMA Channel Q Descriptor 0 Register (UPQD0) ........ uPP DMA Channel Q Status 0 Register (UPQS0) .......................................... RX Mode Flow Chart ....... 1561 33-38..... HC Port 2 Status and Control Register (HCRHPORTSTATUS2) ..... 1557 33-33........................................................................................................ 35-3.................... 35-11................................ OUT Data Phase Flow Chart ............. 1576 34-10....................................... uPP DMA Channel I Status 2 Register (UPIS2) .............. 35-4...................................................... IDLE Mode Flow Chart .......................... HC Head Bulk Register (HCBULKHEADED) ................... 1579 34-15........... 1570 HC Operating Mode Register (HCCONTROL) ................................................................................... HC Head Control Register (HCCONTROLHEADED). Sequence of Transfer .................... 1560 33-37................. HC Low-Speed Threshold Register (HCLSTHRESHOLD)........................ Relationships Between Virtual Address Physical Address ....................... 35-10..................................................... 34-24.................. 1578 34-14.................... 1556 33-31......... ......................................... HC Port 1 Status and Control Register (HCRHPORTSTATUS1) ......... 35-12..................................................................................................... ............................................ HC Root Hub A Register (HCRHDESCRIPTORA) 34-21.......................................................................... 35-2.. 1570 HC Command and Status Register (HCCOMMANDSTATUS) ................................................................................www............................................. Functional Block Diagram ......... HC Periodic Start Register (HCPERIODICSTART) ............................................................................... HC Frame Interval Register (HCFMINTERVAL) .............................................................................................................................. 1558 33-34................................ 1581 34-20................................................................................... USB Controller Block Diagram ... uPP DMA Channel Q Status 2 Register (UPQS2) ........ Texas Instruments Incorporated 1582 1583 1584 1585 1587 1590 1591 1596 1601 1601 1603 1604 1605 1606 1616 1618 1620 1622 1624 1631 51 SPRUH77A – December 2011 Submit Documentation Feedback ......................... 35-9............. 1579 34-16......... HC Frame Remaining Register (HCFMREMAINING) ............................................................................................................ 34-23..................... 1580 34-17.......................................... 35-1... 1557 33-32................... 1568 OHCI Revision Number Register (HCREVISION) ...........................................................................................com 33-30.............................................................................. 34-9.........................

................................................................................................................ 35-52........................... 35-31. Revision Identification Register (REVID) ............. Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX) ......... 35-29...................... Host Buffer Descriptor Layout ................ Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) .................................... 35-60.................................. 35-38.......................... Control Status Register for Host Transmit Endpoint (HOST_TXCSR) .................................................................................................... Interrupt Register for Common USB Interrupts (INTRUSB) .......................... 35-35.............. 35-37............................................................................................ 35-59........................................................... USB Interrupt Source Masked Register (INTMASKEDR) ..... 35-26....................................... 35-23...... 35-64.......................................................... 35-41........................................ Receive USB Data Flow Example (Completion) ........................................ 35-22... Generic RNDIS EP4 Size Register (GENRNDISSZ4) .................. 35-46............................................ Copyright © 2011................................ Mode Register (MODE) ...................................... Relationship Between Memory Regions and Linking RAM ....... USB Interrupt Source Register (INTSRCR) .......... Texas Instruments Incorporated 1634 1637 1639 1642 1648 1649 1650 1651 1652 1652 1653 1677 1677 1678 1678 1679 1681 1682 1682 1683 1684 1685 1686 1687 1688 1689 1690 1690 1691 1691 1692 1692 1693 1694 1695 1696 1696 1697 1698 1698 1699 1699 1700 1701 1702 1703 1704 1705 1706 List of Figures SPRUH77A – December 2011 Submit Documentation Feedback . 35-39............................... Transmit Descriptors and Queue Status Configuration ....................... 35-21............ 35-36........ Status Register (STATR) ............................. 35-53................ Teardown Descriptor Layout .............. 35-25......................... 35-19....... Interrupt Enable Register for INTRUSB (INTRUSBE) .. 35-50........................................... 35-28................................... 35-20.............................................................................. 35-61.................................................................. Interrupt Enable Register for INTRRX (INTRRXE) ... 35-54............................ USB Interrupt Mask Clear Register (INTMSKCLRR) ................................ 35-51....... 35-42............. Receive Descriptors and Queue Status Configuration .......... Register to Enable the USB 2....... USB Interrupt Source Set Register (INTSETR) ................. Interrupt Enable Register for INTRTX (INTRTXE) ................................... High-Level Transmit and Receive Data Transfer Example ......................................... Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) ............ Generic RNDIS EP2 Size Register (GENRNDISSZ2) ...................................... Auto Request Register (AUTOREQ) . 35-45........... SRP Fix Time Register (SRPFIXTIME)........................................ti................ 35-27................... Generic RNDIS EP3 Size Register (GENRNDISSZ3) ..................................................................................... Control Register (CTRLR) ............ Host Packet Descriptor Layout 35-17.... 35-56............................................. Transmit USB Data Flow Example (Initialization) ..................................................................................... Index Register for Selecting the Endpoint Status and Control Registers (INDEX) ...........com 35-16........................... 35-48................. Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ................................................................. Generic RNDIS EP1 Size Register (GENRNDISSZ1) .............. Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)... 35-18.................. Transmit USB Data Flow Example (Completion)...................................................................................... 35-57............................................... 35-63.............................................................................................................. 35-58. 35-62..... USB Interrupt Source Clear Register (INTCLRR) ................................................................................................................. 35-55............ Emulation Register (EMUR)....................................................................... 35-49.............. 35-43........... USB End of Interrupt Register (EOIR) ............................................................. Function Address Register (FADDR) . Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ...................................................................................... 35-33......................................... 35-30.... 35-44............... Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ... Frame Number Register (FRAME) ...... 35-24............................................................................... 35-32................................0 Test Modes (TESTMODE) ......................................... Teardown Register (TEARDOWN) . USB Interrupt Mask Register (INTMSKR) .....................www.................. Power Management Register (POWER) ..... 52 .................... Receive USB Data Flow Example (Initialization) ............................ 35-47.............................................. 35-40............................................................... Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) ................................................................................ 35-34................................................. USB Interrupt Mask Set Register (INTMSKSETR) ............................

................. Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) .. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) . 35-76.............................................. Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) .................. Transmit Function Address (TXFUNCADDR) ........ Receive Endpoint FIFO Size (RXFIFOSZ) .... 35-111.... 35-104.......... 35-80........................................................................ 35-108........... 35-70..com 35-65......www............................ Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) ................................................................................................ Queue Manager Queue Pending Register 1 (PEND1) .................................. Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) .... Transmit Endpoint FIFO Size (TXFIFOSZ) ....... 35-71..... Device Control Register (DEVCTL) .................................... Type Register (Host mode only) (HOST_TYPE0) SPRUH77A – December 2011 Submit Documentation Feedback List of Figures Copyright © 2011.......................................... 35-103................................................ 35-101. Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) ................................... 35-88... 35-90... 35-112.............................. Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) ............ Receive Function Address (RXFUNCADDR) ........................................... Transmit Hub Address (TXHUBADDR) ................................... Transmit Type Register (Host mode only) (HOST_TXTYPE) ................. NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ................. CDMA Emulation Control Register (DMAEMU) .............. 35-72.................................................................... Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) .............................. 35-69...................................................................................................... 35-92............................................................. Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) ... 35-95... Receive Hub Address (RXHUBADDR) .............................. 35-97............... 35-67............................................................... 35-73.. Receive Endpoint FIFO Address (RXFIFOADDR) ...... 1708 ...................... 35-85......... Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) ... 35-98... 35-109....................................................... Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) ........................................................ 35-84............ Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) ....... CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) ..................................................................................... 35-81.................... 35-113........................................................ Receive Interval Register (Host mode only) (HOST_RXINTERVAL) ............................................. 35-78...........ti............ 35-106.................................... 35-79....... 35-107..................................................... 35-82.......................... Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) ........................ CDMA Scheduler Table Word n Registers (WORD[n]) ....... Configuration Data Register (CONFIGDATA) .................................. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) ..................................... 35-91.... 35-75............. 1707 35-66. Transmit Endpoint FIFO Address (TXFIFOADDR)..................................... CDMA Revision Identification Register (DMAREVID) ........... Count 0 Register (COUNT0) ....... CDMA Scheduler Control Register (DMA_SCHED_CTRL) . 35-96............... 35-93......... Texas Instruments Incorporated 1708 1709 1709 1710 1710 1711 1712 1713 1714 1714 1715 1715 1716 1716 1717 1717 1718 1718 1719 1720 1720 1720 1721 1721 1721 1722 1722 1723 1723 1724 1725 1726 1727 1727 1729 1729 1730 1731 1732 1733 1733 1734 1734 1735 1735 1736 1737 53 ......................... 35-100........................ 35-105.................................................................. Queue Manager Queue Pending Register 0 (PEND0) .................................................................... 35-74.............. ............... 35-94............................................... Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) ................................................. Queue Manager Revision Identification Register (QMGRREVID) ........... CDMA Teardown Free Descriptor Queue Control Register (TDFDQ)................................................... Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) ...................................................... 35-87.............................. Queue Manager Queue Diversion Register (DIVERSION) . Control Status Register for Host Receive Endpoint (HOST_RXCSR)........................................ 35-77........ Receive Type Register (Host mode only) (HOST_RXTYPE) .......................................................................... 35-110.................................................. 35-86................................................ Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) ............................................. 35-99.................................. 35-89.................... Transmit Hub Port (TXHUBPORT) ....................... 35-83....................... 35-102............................... Receive Count Register (RXCOUNT) 35-68......... Hardware Version Register (HWVERS) ................................. CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) ................... Receive Hub Port (RXHUBPORT) ..

.............................................................................................. Interrupt Enable Clear Register (INTCLR) ..... Queue Manager Queue N Status Register B (QSTATB[N])...... Data Areas and Clipping Function ......... Texas Instruments Incorporated 1744 1747 1748 1749 1752 1753 1754 1754 1755 1756 1757 1757 1759 1759 1760 1761 1762 1763 1765 1766 1767 1770 1770 1772 1773 1775 1777 1778 1779 1780 1781 1782 1782 1783 1783 1784 1784 1785 1785 1786 1786 1787 1787 List of Figures SPRUH77A – December 2011 Submit Documentation Feedback ........................ 36-29.................................................................................................... 36-34.......... 36-16........ 36-10................................................. 36-4.... 36-17....... Queue Manager Queue N Status Register C (QSTATC[N]) ......... 36-22...... 36-36............. 36-26..................... Interrupt Status Register (INTSTAT) ............................ 36-40............................................. 36-15........... 1739 35-116............ Interrupt Enable Register (INTEN) ..........................................................................................com 35-114........... 36-27................................. VPIF Architecture Block Diagram Interlaced Video Copyright © 2011.................................................. 36-23..................... 36-25.......................... 36-31............ VPIF Revision ID Register (REVID) ... Channel 1 Control Register (C1CTRL) .......... 36-30....................... 36-20................... Memory Storage Modes for Interlaced Video .................................................................. Channel 3 Control Register (C3CTRL) .................... Module Performance with Emulation Suspend Signal ............................................ 36-9....................... 36-21................ Channel 0 Control Register (C0CTRL) ... 36-3.... 36-35.................... Emulation Suspend Function on Channels 2 and 3 (Transmit) ...................................... 36-28................................................................................................................... Register Bit Assignment on Clipping Function....................... 36-24................................................................................................... Relationship Between the First Interrupt and Incoming Data ........ 36-33.................................. 1742 Video Port Interface (VPIF) Block Diagram .......................... 1740 36-1........... Channel n Bottom Field Horizontal Ancillary Address Register (CnBHANC)........ 36-18............ 36-42....................... 36-39............ Channel n Image Address Offset Register (CnIMGOFFSET) ......................................................... Relationship Between Register and Data Access ........................................................................................................................................... Image of Specific Ancillary Data on NTSC ...................................................... 36-19..................................................... Relationship Between the First Interrupt and Outgoing Data ...................... Channel n Horizontal Ancillary Address Offset Register (CnHANCOFFSET) .......... 36-11............................................................... Channel n Top Field Luminance Address Register (CnTLUMA) .............................. Channel 2 Control Register (C2CTRL) . Channel n Top Field Chrominance Address Register (CnTCHROMA) ........ DMA Size Control Register (REQSIZE) .................................. Channel n Bottom Field Luminance Address Register (CnBLUMA) .............................................................................................................................. Progressive Video ........................... 36-32.......................... 36-7................................................. Functional Image of Raw Data Capturing Mode ........... VBI Result Data Transmit Image for Interlaced Image .......................... Emulation Suspend Control Register (EMUCTRL)......... 36-43.......................... 36-38............ 1738 35-115.............. Channel n Top Field Vertical Ancillary Address Register (CnTVANC) ... Raw Capture Progressive Mode........... 36-14...................................... Queue Manager Queue N Control Register D (CTRLD[N]) ........................................ 36-8................... 54 Input and Output Channels of VPIF ...ti............. 36-41. Channel n Bottom Field Vertical Ancillary Data Buffer Start Address Register (CnBVANC) ..........www............................ Clock Control on Video Input and Output with SDTV Encoding .................... 1743 .......................... 36-44................................ Interrupt Enable Set Register (INTSET) .............................................................................................................................................. 36-12....... Stuffing Manner in Storage Memory ... Channel n Bottom Field Chrominance Address Register (CnBCHROMA) .......... Clock Control on Video Input and Output with HDTV Encoding ............ Queue Manager Queue N Status Register A (QSTATA[N]).............................. Method for Turning off Module Channel ................................................................................................................ 36-5.............. ................................ 1739 35-117.................................................................... Clock Control on Video Input and Output with HDTV Encoding ....... 36-13................................................................. 36-45...................................................................................... 36-2.................................................. 36-37.... 36-6............................................................................................. Raw Capture Interlaced Mode ........... Interrupt Status Clear Register (INTSTATCLR) ................... Channel n Top Field Horizontal Ancillary Address Register (CnTHANC) ....................................

.................................. Channel n Vertical Image Size Register (CnVSIZE) ..................................................................... Channel n Horizontal Size Configuration Register (CnHCFG) .......... 1788 36-48. Texas Instruments Incorporated 55 ............. Channel n Bottom Field Horizontal Ancillary Size Register (CnBHANCSIZE) ....................................................... 1798 36-63.... 1797 36-62. Channel n Vertical Image Size Register (CnVSIZE) .... 1793 36-58.................. 1792 36-55........ Channel n Top Field Horizontal Ancillary Position Register (CnTHANCPOS) ............ Channel n Bottom Field Vertical Ancillary Position Register (CnBVANCPOS) 36-65............... 1789 36-51................. 1789 36-50...... Channel n Top Field Vertical Ancillary Position Register (CnTVANCPOS)..................... ........................... Channel n Top Field Vertical Ancillary Size Register (CnTVANCSIZE)................................................. 1788 36-47.....................................................ti................. Channel n Bottom Field Vertical Ancillary Size Register (CnBVANCSIZE)......... Channel n Vertical Size Configuration 2 Register (CnVCFG2) ..... 1790 36-53........................... 1791 36-54.. 1792 36-56...... Channel n Vertical Size Configuration 2 Register (CnVCFG2) ..... 1790 36-52............................. 1794 36-59.. 1788 36-49..................... Horizontal Distance in Y/C Mode ................................ 1799 36-64. Channel n Top Field Horizontal Ancillary Size Register (CnTHANCSIZE) ......... 1796 36-61................ Channel n Vertical Data Size Configuration 1 Register (CnVCFG1) ............................................................................. 1800 1801 SPRUH77A – December 2011 Submit Documentation Feedback List of Figures Copyright © 2011..................com 36-46........................................... Horizontal Distance in CCD/CMOS Mode.................................... 1793 36-57....................................... 1795 36-60.................... Channel n Vertical Size Configuration 1 Register (CnVCFG1) ..... Channel n Horizontal Size Configuration Register (CnHCFG) .... Channel n Vertical Size Configuration 0 Register (CnVCFG0) ...............................www............................................................... Channel n Bottom Field Horizontal Ancillary Position Register (CnBHANCPOS) ............................... Channel n Vertical Size Configuration 0 Register (CnVCFG0) .........................

.. MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions ......................................................... Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions ................................................................... PLLC1 Revision Identification Register (REVID) Field Descriptions ..... 7-8................. 8-6.. PLL Controller 0 (PLLC0) Registers ........ 8-9.............................. 6-12........................................................................................... 6-9............ OMAP-L138 Applications Processor System Interconnect Matrix ................... PLL Controller 1 (PLLC1) Registers ......... 7-6................................................................................................ Interrupt Enable Clear Register (IENCLR) Field Descriptions ..... 4-1.................................... Different Address Types in ARM System 92 97 104 113 113 113 115 117 118 118 120 120 121 122 123 123 125 126 126 127 127 128 129 130 131 134 134 137 138 140 141 143 144 146 150 153 154 154 155 155 156 157 158 159 160 161 List of Tables Copyright © 2011................ Reset Type Status Register (RSTYPE) Field Descriptions. 6-4.......................................... 8-8.......................... 6-21.................. 8-12....................................................................... 6-13.. 7-1......ti........................... Fault Address Register (FLTADDRR) Field Descriptions ............... Revision ID Register (REVID) Field Descriptions ............................................................ Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) Field Descriptions .................................. PLLC0 Revision Identification Register (REVID) Field Descriptions ....................................................... 6-3............... Memory Protection Unit 1 (MPU1) Registers..................... 8-4.......................... 6-14..................................................................................................................... System Clock Domains ............................................ DDR2/mDDR Memory Controller MCLK Frequencies ........................... 7-9...................................................................... 90 .............................. Fault Status Register (FLTSTAT) Field Descriptions...................... MPU_BOOTCFG_ERR Interrupt Sources ........ 6-2. 7-7........................... Device Clock Inputs ........................... 6-6............ Configuration Register (CONFIG) Field Descriptions ............... EMAC Reference Clock Frequencies ....... 8-7................................................................................................. PLL Multiplier Control Register (PLLM) Field Descriptions ..................................................................................................................................... Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions ..................................................www............... MPU Memory Regions ......................................................................................... 7-5........................... 6-15........................ Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback ...................... 7-4........................................................................................................................................................................................................................ 6-16................... 6-5.................................................. 6-10.. PLLC0 Control Register (PLLCTL) Field Descriptions ................................................ 6-1......................................... 2-2.......................................................... Peripherals .............. 8-2.. 8-5....... 6-11...................................................................................... 6-18.................................................................... 8-11......................com List of Tables 2-1.... 8-10........ 6-17............................................................................... PLLC1 Control Register (PLLCTL) Field Descriptions ................ 6-19...................... 56 Exception Vector Table for ARM .............................................. 6-22......... 6-7................... Interrupt Enable Set Register (IENSET) Field Descriptions ................. Request Type Access Controls ............................................... MPU Default Configuration .. Example PLL Frequencies ............................ System PLLC Output Clocks ....... MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ................... 8-1......... PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions ..... 8-3... Memory Protection Unit 2 (MPU2) Registers............................... uPP Transmit Clock Selection .. MPU1 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions .......................... Fault Clear Register (FLTCLR) Field Descriptions ............. 7-2.............. 6-8....... 6-20.. 7-3............................................................... USB Clock Multiplexing Options .......................... EMIFA Frequencies.......... DSP Interrupt Map ........................................... MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ................................. Reset Control Register (RSCTRL) Field Descriptions .......... PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions ....... Device Master Settings ............................. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions ............ 3-1..........................................................................................

........ 192 PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions ......................................... 8-40.......................................................................................................... 186 IcePick Emulation Commands ........................................................................................................ 188 PSC Interrupt Events ... 8-39.................... 9-21......................................................................... 169 PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions ............................. 191 Revision Identification Register (REVID) Field Descriptions ............................................................................................ 177 PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions ......... 193 PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions ................................................................... 8-36.................................................................................................. 175 PLLC1 Clock Status Register (CKSTAT) Field Descriptions ....................................................... 171 PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions .. 9-15.................. 179 PSC0 Default Module Configuration..... 8-25... 8-21............ Power Domain 0 Status Register (PDSTAT0) Field Descriptions ...... PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions ................. 9-10.............................................................. 8-18. 8-16............ Power Domain Transition Command Register (PTCMD) Field Descriptions Power Domain Transition Status Register (PTSTAT) Field Descriptions List of Tables Copyright © 2011........ Texas Instruments Incorporated 196 197 198 199 200 201 202 203 57 SPRUH77A – December 2011 Submit Documentation Feedback ... 188 Power and Sleep Controller 0 (PSC0) Registers ........................................ 9-1................................................................................ Power Domain 0 Configuration Register (PDCFG0) Field Descriptions .......... 8-24......... 9-4............. 8-23.............................................................. 166 PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions ............. 192 Interrupt Evaluation Register (INTEVAL) Field Descriptions .............. Power Domain 1 Control Register (PDCTL1) Field Descriptions .. 183 PSC1 Default Module Configuration............................ 164 PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions .................................................................................................. 183 Module States .............................................ti.......... Power Domain 0 Control Register (PDCTL0) Field Descriptions ... 179 Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions ............................................ 8-20................ 168 PLL Controller Status Register (PLLSTAT) Field Descriptions ......... 162 PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions ........ 9-14........................ 8-14.................com 8-13................. 8-22........... 164 PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions ........ 8-19...................................... 174 PLLC0 Clock Status Register (CKSTAT) Field Descriptions ............................. 9-2......... 178 Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions ....... 195 Power Error Clear Register (PERRCR) Field Descriptions ..............www....... 172 PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ...................... 8-29......................................................... 9-20..................................... 8-27............... 9-9............................................. 9-18............. 9-13.................................... 167 PLL Post-Divider Control Register (POSTDIV) Field Descriptions ................. 8-34.................................................... 191 Power and Sleep Controller 1 (PSC1) Registers ......... 161 PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions .... 9-3................... 8-28........................................... 8-35....................... 168 PLL Controller Command Register (PLLCMD) Field Descriptions ......................... 8-38........................... 9-8.......... 167 PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions.......... 166 PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions.................. 9-12...................................... 8-33..... 9-5.......... 8-31..................... 163 PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions ............... 163 PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions ....................................................... 174 PLLC1 Clock Enable Control Register (CKEN) Field Descriptions ............. 9-6......................................... 165 PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions ....................... 8-32...... Power Domain 1 Status Register (PDSTAT1) Field Descriptions ............... 173 PLLC0 Clock Enable Control Register (CKEN) Field Descriptions .......................... 162 PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions .......................... ............................. 195 .................. 9-11..... 8-30..... 8-37... 9-7............................. Power Domain 1 Configuration Register (PDCFG1) Field Descriptions ............... 8-17........................... 194 Power Error Pending Register (PERRPR) Field Descriptions ............................ 170 PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions ........ 8-26. 165 PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions ................. 9-17................................................................................................................................... 9-16.......... 9-19......... 8-15................................................... 176 PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions ................................

.................................................. System Configuration Module 0 (SYSCFG0) Registers ................. 11-15................................................... 11-12.... Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions .................. Host 0 Configuration Register (HOST0CFG) Field Descriptions ................... 11-28........ 11-25....................... Module Status n Register (MDSTATn) Field Descriptions Copyright © 2011............................... Boot Configuration Register (BOOTCFG) Field Descriptions .................... 11-22................................ Host 1 Configuration Register (HOST1CFG) Field Descriptions ................................................................. Master Priority 2 Register (MSTPRI2) Field Descriptions ............... 11-44..................................................... 11-30.......................................... 11-41..................... Chip Configuration 0 Register (CFGCHIP0) Field Descriptions ........................... Fault Address Register (FLTADDRR) Field Descriptions ..................................................................................... Default Master Priority .... 11-9.......... Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions ....... Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions ................. PSC0 Module Control n Register (MDCTLn) Field Descriptions ......................... 11-39............................... Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions ....... 11-10. 11-23................... 11-17........................................................................................ Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions ................................. 11-19.... 9-23............................................. Fault Status Register (FLTSTAT) Field Descriptions....... Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions . 11-42.......................................... Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions ........ Interrupt Enable Register (IENSET) Field Descriptions ....... Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions .......... Revision Identification Register (REVID) Field Descriptions .................................................................................. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions ........... 11-36............................ 11-6........................... Interrupt Enable Clear Register (IENCLR) Field Descriptions .............. 11-24............... 11-37........www......................................................... 10-1........................... 11-34................................. End of Interrupt Register (EOI) Field Descriptions .......................................................................... 11-5....... 11-29............................................................ 11-2............................................................................................................................................ 11-38............................. Master IDs ....................................... Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions ...com 9-22....... 11-20....... 11-21...................................... 11-8......................................................... Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions ............................................................................................... Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions ............ Device Identification Register 0 (DEVIDR0) Field Descriptions ........... Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions .................................... Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions ............. 11-13................................... Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions ........................ Suspend Source Register (SUSPSRC) Field Descriptions ........... Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions ............. 11-35.................. 58 ............ Master Priority 1 Register (MSTPRI1) Field Descriptions ............. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions .................. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions .............................................................................................. 11-11............................... Texas Instruments Incorporated 204 205 206 209 227 228 229 230 231 231 232 233 233 234 235 236 237 238 238 239 239 240 241 242 243 244 246 248 250 252 254 256 258 260 262 264 266 268 270 272 274 277 279 281 283 285 288 289 290 List of Tables SPRUH77A – December 2011 Submit Documentation Feedback ................................ Chip Signal Register (CHIPSIG) Field Descriptions ......... Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions ........... Master Priority 0 Register (MSTPRI0) Field Descriptions ..................... Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions .... Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions ........... Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions ............ 9-24... 11-32..... 11-18........... 11-27.......................................................... 11-33..................................................................................................................... 11-45............................. 11-14............... Kick 0 Register (KICK0R) Field Descriptions............. 11-16.. 11-4......... 11-7......... 11-43......................ti........................ Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions ......................................... 11-1.............................. Power Management Features .......................... 11-40........ System Configuration Module 1 (SYSCFG1) Registers ........................ 11-26..... 11-31. PSC1 Module Control n Register (MDCTLn) Field Descriptions ......... Kick 1 Register (KICK1R) Field Descriptions..................... 11-3.........

.................................................................. Host Interrupt Enable Indexed Set Register (HEISR) Field Descriptions. System Interrupt Status Raw/Set Register 1 (SRSR1) Field Descriptions .......... System Interrupt Enable Clear Register 3 (ECR3) Field Descriptions ..................... Vector Base Register (VBR) Field Descriptions ..... Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions ............ System Interrupt Enable Set Register 3 (ESR3) Field Descriptions ......... Control Register (CR) Field Descriptions ..... 12-12...................................................................... VTP I/O Control Register (VTPIO_CTL) Field Descriptions ................. System Interrupt Enable Clear Register 4 (ECR4) Field Descriptions ............. 12-13... 11-53.. 12-14.. 12-26........................................................................... Global Prioritized Vector Register (GPVR) Field Descriptions ...... 11-49........ Texas Instruments Incorporated 292 294 296 297 298 300 301 302 302 303 304 304 307 313 314 315 316 316 317 317 318 318 319 319 320 320 321 321 322 322 323 323 324 324 325 325 326 326 327 327 328 328 329 329 330 330 331 331 332 59 SPRUH77A – December 2011 Submit Documentation Feedback ..................... Global Nesting Level Register (GNLR) Field Descriptions ................ RXACTIVE Control Register (RXACTIVE) Field Descriptions .... Host Interrupt Prioritized Index Register 1 (HIPIR1) Field Descriptions ...... 12-15................................. 12-5................ 12-11........................ Global Enable Register (GER) Field Descriptions .. System Interrupt Enable Set Register 4 (ESR4) Field Descriptions ................................ System Interrupt Status Enabled/Clear Register 2 (SECR2) Field Descriptions .. 12-25............... System Interrupt Status Enabled/Clear Register 3 (SECR3) Field Descriptions .............................................................................. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions ....................... Power Down Control Register (PWRDN) Field Descriptions ............................. 12-17..... System Interrupt Status Enabled/Clear Register 1 (SECR1) Field Descriptions ....................................... 12-16............... 11-56.................................................................. 12-22................................................................................................... 12-27................................... 12-18...................... 12-10.............................. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions ........................................ System Interrupt Enable Set Register 1 (ESR1) Field Descriptions ............................................................. 11-52........................................... 12-36............ Pullup/Pulldown Select Register (PUPD_SEL) Default Values ...................................................www................................. System Interrupt Enable Set Register 2 (ESR2) Field Descriptions .. Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions ..............................ti............................. 11-51. 11-54...... System Interrupt Status Raw/Set Register 3 (SRSR3) Field Descriptions .... 12-3........... Channel Map Registers (CMRn) Field Descriptions ... 12-29........... Host Interrupt Nesting Level Register 1 (HINLR1) Field Descriptions .... Chip Configuration 1 Register (CFGCHIP1) Field Descriptions 11-47.............................................................. Global Prioritized Index Register (GPIR) Field Descriptions .......................... 12-28............................................ System Interrupt Status Indexed Clear Register (SICR) Field Descriptions .... 12-33........................ 11-57.....................................com 11-46........................................... System Interrupt Status Indexed Set Register (SISR) Field Descriptions ........ 12-23........................... System Interrupt Enable Clear Register 1 (ECR1) Field Descriptions ....................................................... ARM Interrupt Controller (AINTC) Registers ......................... 11-48......... Revision Identification Register (REVID) Field Descriptions ............................. Vector Null Register (VNR) Field Descriptions ..... .. 12-8......... Deep Sleep Register (DEEPSLEEP) Field Descriptions ............................................................... 12-2............................... 12-35........... 12-31............................ 12-32.. DDR Slew Register (DDR_SLEW) Field Descriptions ........................... System Interrupt Status Enabled/Clear Register 4 (SECR4) Field Descriptions ...... 12-21.................. 12-37......... 12-6............................. 12-19....... 11-50............................................ System Interrupt Status Raw/Set Register 4 (SRSR4) Field Descriptions .......................... 12-24................................... System Interrupt Enable Indexed Set Register (EISR) Field Descriptions .............. 12-30................ 11-55.............. 12-4.... System Interrupt Status Raw/Set Register 2 (SRSR2) Field Descriptions .................................. Host Interrupt Enable Indexed Clear Register (HIEICR) Field Descriptions .......................... Vector Size Register (VSR) Field Descriptions ........................................ AINTC System Interrupt Assignments ................................................ List of Tables Copyright © 2011..... System Interrupt Enable Indexed Clear Register (EICR) Field Descriptions................. 12-34.............................................. 12-1.............. Host Interrupt Prioritized Index Register 2 (HIPIR2) Field Descriptions ......................................................... 12-7...................................................................................... 12-20.............. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions ....... 12-9................. System Interrupt Enable Clear Register 2 (ECR2) Field Descriptions ..

..... Copyright © 2011.......................................... 15-4........................... 15-23................. 15-29.............. Texas Instruments Incorporated 364 365 367 367 367 368 373 374 374 375 375 376 377 377 378 379 382 383 384 385 386 387 387 388 389 390 391 391 392 392 393 394 395 410 412 414 List of Tables SPRUH77A – December 2011 Submit Documentation Feedback ........ 15-26........................... 15-2.......... 15-3........ DDR2 SDRAM Configuration by MRS Command ....... SDTIMR2 Configuration ................................................................................................ Rising and Falling Edge Trigger .................. 333 12-40...................... 15-33...... Mobile DDR SDRAM Configuration by MRS Command ..... SDTIMR1 Configuration .... 15-37........................................ 347 Addressable Memory Ranges ......................................................................... Interrupt Mask Clear Register (IMCR) Field Descriptions ................... DDR PHY Control Register 1 (DRPYC1R) Field Descriptions ...................... 356 Address Mapping Diagram for 16-Bit SDRAM (IBANKPOS = 1) ................ SDRAM Configuration Register 2 (SDCR2) Field Descriptions ..... 15-15... 15-39................... Interrupt Mask Set Register (IMSR) Field Descriptions ............................................ SDRAM Refresh Control Register (SDRCR) Field Descriptions .......................................................... 346 Truth Table for DDR2/mDDR SDRAM Commands .............................................. ECAP Initialization for CAP Mode Delta Time................... Performance Counter 1 Register (PC1) Field Descriptions .................................................. 15-42.................. 358 DDR2/mDDR Memory Controller FIFO Description ....... 16-3..............................................www..... 15-7....................... Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions .................................................................................................................... DRPYC1R Configuration ...............com 12-38.................................................. 334 15-1.......... SDRAM Configuration Register (SDCR) Field Descriptions ... DDR2/mDDR Memory Controller Registers .............. 15-21.......................................................... 15-35............................................................................ 15-24........... 15-22...................... DDR PHY Reset Control Register (DRPYRCR) ............ SDCR Configuration .............. 15-13......................... 360 Refresh Urgency Levels...... 15-9.......................................... Revision ID Register (REVID) Field Descriptions .............. Rising Edge Trigger ............................................................ 15-18................... 16-1............................. 15-8.................................................................... 15-12..................................................................... 60 DDR2/mDDR Memory Controller Signal Descriptions ...................................... 15-19.......... 15-36.. SDRAM Timing Register 1 (SDTIMR1) Field Descriptions ................................................... 334 12-41................ 15-30............................... 15-41.................................................. SDRAM Status Register (SDRSTAT) Field Descriptions ............................... 15-16............................................................................................................... 15-38............... Host Interrupt Nesting Level Register 2 (HINLR2) Field Descriptions .......... SDRCR Configuration ...................................... ECAP Initialization for CAP Mode Absolute Time..................... 15-17...................................... ECAP Initialization for CAP Mode Absolute Time................................. 15-27............................................................................................................................................................... Rising Edge Trigger .................. Mobile DDR SDRAM Configuration by EMRS(1) Command ...................... 346 DDR2/mDDR SDRAM Commands ..................... Host Interrupt Enable Register (HIER) Field Descriptions ...... DDR2 SDRAM Configuration by EMRS(1) Command .................. 15-31........ SDRAM Timing Register 2 (SDTIMR2) Field Descriptions ........................... Interrupt Masked Register (IMR) Field Descriptions .......... Interrupt Raw Register (IRR) Field Descriptions ......................... 15-14.................. 363 15-10......... 15-40. 15-34......................... Configuration Bit Field for Partial Array Self-refresh ........................ 355 Logical Address-to-DDR2/mDDR SDRAM Address Map for 16-bit SDRAM ............................................................... Performance Counter Time Register (PCT) Field Description ..ti........ 15-25............................ Performance Counter Filter Configuration ..................... DDR2 Memory Refresh Specification ................................................... 15-11..................................................................... 15-20........................... 15-6..................................................... 16-2.............................................. 354 Configuration Register Fields for Address Mapping ............. Performance Counter Configuration Register (PCC) Field Descriptions ................................................... Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions .............. Reset Sources ............................. Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions ....................... Performance Counter Master Region Select Register (PCMRS) Field Descriptions ............. 15-28.. Performance Counter 2 Register (PC2) Field Descriptions .......................................................................................... 332 12-39.................................................................. 15-32........................ 15-5................

..... ePWM Module Control and Status Registers Grouped by Submodule .................................. Capture 3 Register (CAP3) Field Descriptions ............................. 16-11..................... Submodule Configuration Parameters .............................. 16-14.................................................................................................................................................................. Control and Status Register Set ........ EPWMx Run Time Changes for ..................................................................................................... ECAP1 Initialization for Multichannel PWM Generation with Phase Control ...................................... ECAP3 Initialization for Multichannel PWM Generation with Synchronization ............................................................ 17-8............................ 17-17................www................................................................................... Action-Qualifier Event Priority for Up-Count Mode .................................... 17-25................... 16-7.. 17-14............... 16-15..................................................................... Rising and Falling Edge Triggers List of Tables Copyright © 2011................................. 16-13............................................... 16-19........................ Classical Dead-Band Operating Modes ...................... ECAP Interrupt Clear Register (ECCLR) Field Descriptions ............................................... 16-25. EPWMx Run Time Changes for .................................. Capture 2 Register (CAP2) Field Descriptions ........................................... ECAP Control Register 1 (ECCTL1) Field Descriptions .................. ................................ ECAP4 Initialization for Multichannel PWM Generation with Synchronization ..... ECAP Initialization for APWM Mode ................. 17-10......................................................................................... Dead-Band Generator Submodule Registers ............. 16-6.......... Capture 4 Register (CAP4) Field Descriptions ............................... ECAP Initialization for CAP Mode Delta Time........................ 17-13........................................................................................................ EPWMx Initialization for .............. ECAP Interrupt Enable Register (ECEINT) Field Descriptions .......................................... 16-9....... ECAP Interrupt Flag Register (ECFLG) Field Descriptions .................... 17-9................ ECAP2 Initialization for Multichannel PWM Generation with Synchronization .......... Key Time-Base Signals ............................................ Texas Instruments Incorporated 416 418 420 420 420 420 423 423 423 424 424 425 425 426 426 427 427 429 431 432 433 434 435 442 443 448 449 457 457 461 462 464 464 464 465 468 468 470 470 472 472 474 474 476 476 478 478 479 481 61 SPRUH77A – December 2011 Submit Documentation Feedback ........................................ 16-10................................ EPWMx Initialization for .......com 16-4.................................................... 17-21....... Time-Stamp Counter Register (TSCTR) Field Descriptions ........................................................................... Revision ID Register (REVID) Field Descriptions ................. 16-26.............. Action-Qualifier Event Priority for Down-Count Mode ............................................................. Action-Qualifier Submodule Registers ..... 16-21............................................................ 17-22............................................. 17-12............................................................ 17-19............. 17-3.....................ti........................................ Counter-Compare Submodule Key Signals ............ 16-24.................................................................................... EPWMx Initialization for ......... 17-24. 16-8.......................... 17-23.......................................................................... 17-1.......................... 17-15.................................................. EPWMx Initialization for ............................... 17-16... ECAP3 Initialization for Multichannel PWM Generation with Phase Control ... EPWMx Initialization for ................... Action-Qualifier Submodule Possible Input Events .................... 16-17............................................................... 16-5....................... 16-22............ EPWMx Run Time Changes for .................. Counter-Compare Submodule Registers .... 16-16.. ECAP1 Initialization for Multichannel PWM Generation with Synchronization . Action-Qualifier Event Priority for Up-Down-Count Mode ............................................................................................................ Behavior if CMPA/CMPB is Greater than the Period.. 17-20. 17-26................................... Capture 1 Register (CAP1) Field Descriptions ............................................................................ EPWMx Run Time Changes for . 17-6............................. Counter Phase Control Register (CTRPHS) Field Descriptions .................. 16-18.......................... 16-12...... ECAP Interrupt Forcing Register (ECFRC) Field Descriptions ............................................................... 17-7.................................................... 16-20................................ ECAP2 Initialization for Multichannel PWM Generation with Phase Control ..... EPWMx Run Time Changes for .... 17-4..................... 17-5............................................ ECAP Control Register 2 (ECCTL2) Field Descriptions .......... 17-11......................................................................................... 16-23................ EPWMx Run Time Changes for .......................... 17-18...................................... 17-2............................................................ EPWMx Initialization for ................................................ Time-Base Submodule Registers .......................................................

............... EPWM2 Initialization for ................. 17-47................... 17-53...................... 17-50.......... Dead-Band Generator Control Register (DBCTL) Field Descriptions ...... Texas Instruments Incorporated 491 496 497 498 499 506 506 506 509 509 512 512 515 515 516 521 521 522 525 525 526 526 527 528 529 529 530 530 531 532 533 533 534 535 536 537 537 538 539 539 540 541 541 542 542 543 List of Tables SPRUH77A – December 2011 Submit Documentation Feedback .................................................... 17-71............................................ Action-Qualifier Software Force Register (AQSFRC) Field Descriptions .. 17-37... EPWM1 Initialization for ...................... 17-56......................... 17-66................. 17-74................ 483 17-28............................ 17-36...... 17-69. Time-Base Counter Register (TBCNT) Field Descriptions .................. Time-Base Status Register (TBSTS) Field Descriptions ......................... 17-35. and [CMPA:CMPAHR] vs Duty (right) . 17-70............................................... Action-Qualifier Submodule Registers . HRPWM Submodule Registers ...................................... EPWM3 Initialization for .................................................................................. 17-52.......................................................................................... EPWM1 Initialization for .................................... 17-49.........................www........................................... Time-Base Control Register (TBCTL) Field Descriptions ................................................ EPWM1 Initialization for .............................................. 17-32.................. 17-33.................................................... 17-44..................... EPWM2 Initialization for ..................... 62 ............................................................. 17-48.............................................................................................................................. 17-65.................................................................... EPWM1 Initialization for ..................... 17-72..................................................... 488 17-29......... Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions ....................................................................................... Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions...... 17-38........ 17-40............................................................................................................................. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions ....... EPWM2 Initialization for ........................ 17-73.............. Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions ................................................................................................................................................... PWM-Chopper Control Register (PCCTL) Bit Descriptions ................................................ 17-61.......... Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions ... Resolution for PWM and HRPWM .. Submodule Registers .................. 17-63.................................................................................................................... Counter-Compare Control Register (CMPCTL) Field Descriptions .....................................com 17-27............... 17-34..... EPWM3 Initialization for ............. EPWM1 Initialization for ............................................ Counter-Compare A Register (CMPA) Field Descriptions ............ PWM-Chopper Submodule Registers ............. 17-46....... Possible Actions On a Trip Event ....................... 17-59...................................................................................... EPWM2 Initialization for ......................... 17-54........................................................... CMPA vs Duty (left)......................................................................... 17-51................. Copyright © 2011... 17-41........................... EPWM2 Initialization for ...................................................... Dead-Band Generator Submodule Registers .......................................... 17-55..... 17-67....................... 17-64........................ EPWM1 Initialization for .................................. 17-42............................... 17-60................ Relationship Between MEP Steps...................... Time-Base Phase Register (TBPHS) Field Descriptions ......... EPWM3 Initialization for ......................... 17-58........................................... 489 17-30................................................................................................................. Trip-Zone Control Register (TZCTL) Field Descriptions ....... EPWM2 Initialization for ............................................................ Trip-Zone Submodule Registers .. PWM Frequency and Resolution .............................. Trip-Zone Flag Register (TZFLG) Field Descriptions .......................... Time-Base Period Register (TBPRD) Field Descriptions . Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions .................................... 17-57.......... 17-68............................ Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions .... Event-Trigger Submodule Registers 17-31........................................................................................... 17-62............ 17-43.............................. Time-Base Submodule Registers . Counter-Compare B Register (CMPB) Field Descriptions ............................................................................................ 17-45............ Trip-Zone Submodule Registers ......................................................... 17-75.... Counter-Compare Submodule Registers ...............................................................................................................................................................................................ti....................................................................................................... 17-39...............

.......... QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions .................... 17-86... Event-Trigger Flag Register (ETFLG) Field Descriptions .............................................. 18-26...................................................................... Event-Trigger Submodule Registers .......................................................... HRPWM Configuration Register (HRCNFG) Field Descriptions ............................................ DMA Region Access Enable Register for Region m (DRAEm) Field Descriptions............................................... EDMA3 Transfer Controller Configurations ....... Event Missed Clear Register (EMCR) Field Descriptions .... 18-25............. Error Evaluate Register (EEVAL) Field Descriptions ............................ 18-22.............................................................................................. Event-Trigger Force Register (ETFRC) Field Descriptions ......................................................................... Trip-Zone Force Register (TZFRC) Field Descriptions ....... 18-1............................. 18-20..................................................................... High-Resolution PWM Submodule Registers ................................. 18-6.... Event-Trigger Prescale Register (ETPS) Field Descriptions ............................................... 17-84.......................... QDMA Event Missed Clear Register (QEMCR) Field Descriptions ........................................................... Channel Source Address Parameter (SRC) Field Descriptions ....... 18-17........................... 18-12................................... Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions ........... Read/Write Command Optimization Rules ..... Revision ID Register (REVID) Field Descriptions ............................. 18-15......................... 18-19............ 17-82.................................................................... Dummy and Null Transfer Request ...................... Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions ................................ 17-81.... 18-23.......................................... EDMA3 Channel Parameter Description . 18-9............................... 18-28............................................................................ EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions . Bits in DMAQNUMn ........................... 18-24........... Event-Trigger Selection Register (ETSEL) Field Descriptions .... 17-87.......................................... ................................... 17-80.......................... Chain Event Triggers .................. 18-32......................... 17-85.......................... 18-34......... Parameter Updates in EDMA3CC (for Non-Null................. 18-7................ 18-37. 18-18................ 17-78................ EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries .......... QDMA Event Missed Register (QEMR) Field Descriptions ... DMA Channel Queue Number Register n (DMAQNUMn) Field Descriptions .............................. 18-3.... EDMA3 Transfer Completion Interrupts ......................... 18-11....................................................................................... List of Tables Copyright © 2011................................................... Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions .. 18-13................................. Number of Interrupts .................................................................................... Channel Options Parameters (OPT) Field Descriptions ............................................................................................................................. 18-2............... 18-5....... Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping... Event Missed Register (EMR) Field Descriptions . 17-83........ Event-Trigger Clear Register (ETCLR) Field Descriptions ..................................................... Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions ....................... 18-14............ 18-36. 18-4.......... 18-10... EDMA3CC Configuration Register (CCCFG) Field Descriptions ................................................................................................ 18-31................ Shadow Region Registers . 18-29......................... Non-Dummy PaRAM Set) .......................................................................................................................... Counter-Compare A High-Resolution Register (CMPAHR) Field Descriptions .... QDMA Channel n Mapping Register (QCHMAPn) Field Descriptions .................................................................. 18-21...... EDMA3 Error Interrupts ................... EDMA3CC Error Register (CCERR) Field Descriptions .www......... 18-16................................. 18-27.................... 18-33...................................... 18-35.......................................... EDMA3 Channel Controller (EDMA3CC) Registers ... 18-30....................... Trip-Zone Clear Register (TZCLR) Field Descriptions 17-77...................... A Count/B Count Parameter (A_B_CNT) Field Descriptions .. 17-79............................................................................................................ EDMA3 DMA Channel to PaRAM Mapping ...ti........... C Count Parameter (CCNT) Field Descriptions .............com 17-76....... 18-8.............................. Channel Destination Address Parameter (DST) Field Descriptions ......... Expected Number of Transfers for Non-Null Transfer .................................................................... Texas Instruments Incorporated 544 544 545 545 546 547 547 548 548 549 549 550 564 567 568 576 578 580 583 583 584 584 585 592 598 617 618 620 620 621 621 622 623 623 624 627 628 629 630 630 631 632 633 634 635 636 637 638 639 63 SPRUH77A – December 2011 Submit Documentation Feedback .............................................................

................... Queue n Status Register (QSTATn) Field Descriptions ....... Source Active Count Reload Register (SACNTRLD) Field Descriptions ....................................................................... 18-58.......................................... 18-73............................................ Error Enable Register (ERREN) Field Descriptions ..................................................................................................................... Event Queue Entry Registers (QxEy) Field Descriptions .............. 18-86.............. QDMA Event Register (QER) Field Descriptions .......................... 18-75.............ti................ Chained Event Register (CER) Field Descriptions ..................................... 651 18-49......................... Destination FIFO Set Count Reload Register (DFCNTRLD) Field Descriptions .... QDMA Event Enable Clear Register (QEECR) Field Descriptions ........... Error Details Register (ERRDET) Field Descriptions.................................... 18-53............. 642 18-41................................................................. 18-84......... Error Status Register (ERRSTAT) Field Descriptions ..... Interrupt Enable Clear Register (IECR) Field Descriptions .................... QDMA Region Access Enable for Region m (QRAEm) Field Descriptions ....... 18-80................... Interrupt Pending Register (IPR) Field Descriptions ............... 18-62........................ QDMA Secondary Event Register (QSER) Field Descriptions.. 18-55................................................................ Event Enable Register (EER) Field Descriptions ....................... Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions ....................................... Read Command Rate Register (RDRATE) Field Descriptions .................... 18-79............................................ QDMA Event Enable Register (QEER) Field Descriptions .. Interrupt Clear Register (ICR) Field Descriptions ........................... Source Active Count Register (SACNT) Field Descriptions ................................................. 18-76........ Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) Field Descriptions ....... 18-83.... 18-67......... Event Enable Clear Register (EECR) Field Descriptions .............. 18-78..... 649 18-47.............................. Destination FIFO Options Register n (DFOPTn) Field Descriptions ...................... Interrupt Enable Register (IER) Field Descriptions ................................................. 18-59........................................ Event Register (ER) Field Descriptions ..................................... 640 18-39.................... Source Active B-Index Register (SABIDX) Field Descriptions ..... Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions ........................................................ 18-56.......................... Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions .. 644 18-43.................. Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) Field Descriptions ....................................... QDMA Secondary Event Clear Register (QSECR) Field Descriptions ...... Event Enable Set Register (EESR) Field Descriptions .............. QDMA Event Enable Set Register (QEESR) Field Descriptions ..... 18-65................................ 18-70.................. 652 18-51.............................. 647 18-45............. 18-74.............................................com 18-38............ 646 18-44................ 651 652 653 654 654 655 656 657 658 659 660 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 674 675 675 676 677 677 678 678 679 679 680 18-50.................... Error Interrupt Command Register (ERRCMD) Field Descriptions ........ 18-64........................................................ 18-71.................. Event Clear Register (ECR) Field Descriptions .......... Event Set Register (ESR) Field Descriptions .. Texas Instruments Incorporated List of Tables SPRUH77A – December 2011 Submit Documentation Feedback ............................ 18-68...... Revision ID Register (REVID) Field Descriptions ................................... EDMA3CC Status Register (CCSTAT) Field Descriptions ........ 648 18-46...... 18-61.......... 18-60................... 18-63..... 18-69.... Interrupt Evaluate Register (IEVAL) Field Descriptions . 18-66............................................ 18-82.......................................................................................................................................... 18-57......................................... 643 18-42.............................................................................................. Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions ................. Copyright © 2011................................... EDMA3TC Channel Status Register (TCSTAT) Field Descriptions ............... 64 .......................... 18-54........................................................ Source Active Destination Address Register (SADST) Field Descriptions .......... Interrupt Enable Set Register (IESR) Field Descriptions . Secondary Event Clear Register (SECR) Field Descriptions 18-52.................................................................................................................................. 650 18-48.................. EDMA3 Transfer Controller (EDMA3TC) Registers ........ Source Active Source Address Register (SASRC) Field Descriptions .... 18-77....................... 18-72.................................... 18-81.................... 18-85.........................................................................................www.. EDMA3TC Configuration Register (TCCFG) Field Descriptions ........................................ Secondary Event Register (SER) Field Descriptions.. 641 18-40............. Source Active Options Register (SAOPT) Field Descriptions ... Error Clear Register (ERRCLR) Field Descriptions .

................................................ Emulation Control .............................................................................. EMAC Control Module Interrupt Control Register (INTCONTROL) ...... EMAC and MDIO Signals for RMII Interface ................... 18-92. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field Descriptions ... Destination FIFO B-Index Register n (DFBIDXn) Field Descriptions 18-91.. 741 19-16............................................... 759 19-36.............................. EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register (CnRXTHRESHEN) ................................ti............................. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions........ 19-24........................................................................ MDIO User Access Register 1 (USERACCESS1) Field Descriptions .... 740 19-15................................................. 19-6................ MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions ....................... ................. Receive Frame Treatment Summary .................. 19-29.. EMAC Control Module Registers ............................................................................. Debug List................... EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (CnMISCSTAT). MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions .. Destination FIFO Source Address Register n (DFSRCn) Field Descriptions ....................... 19-20........ EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (CnTXEN) .................... Texas Instruments Incorporated 65 ............. Middle of Frame Overrun Treatment ................................. 19-4........ 19-31......... 19-9............. 19-8........ 19-30............... 760 19-37............................................................................. 19-28.............................. 19-22......................................... MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions ........................... 19-3............................................ . Transmit Teardown Register (TXTEARDOWN) Field Descriptions .................................... 757 19-34.............www......... MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions.......................... PHY Link Status Register (LINK) Field Descriptions ........... 19-10.............. Transmit Revision ID Register (TXREVID) Field Descriptions ....... PHY Acknowledge Status Register (ALIVE) Field Descriptions ..... 764 19-39................................................................................ MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions .......................... EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (CnRXSTAT) ............. 19-11... MDIO User Access Register 0 (USERACCESS0) Field Descriptions .............................. 681 18-89................. 765 19-41................................... Ethernet Frame Description ........ MDIO Control Register (CONTROL) Field Descriptions .......... 19-5.. 744 745 746 747 748 748 749 750 750 751 752 753 754 755 19-32...................................................................................... EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (CnTXIMAX) ...... 681 18-88......... MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions................. 682 682 683 684 693 694 695 697 722 723 733 734 735 736 737 19-12. 19-21...... 758 19-35...... 19-2....................... Destination FIFO Destination Address Register n (DFDSTn) Field Descriptions 18-90....................... 19-1............. ................ Ethernet Media Access Controller (EMAC) Registers ................................................................ EMAC and MDIO Signals for MII Interface . 766 SPRUH77A – December 2011 Submit Documentation Feedback List of Tables Copyright © 2011......... 738 19-13........................................... 756 19-33... 743 19-18...... EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (CnMISCEN) .............................................................................. Destination FIFO Count Register n (DFCNTn) Field Descriptions ........ EMAC Control Module Software Reset Register (SOFTRESET).... 739 19-14.. 19-27................................................... EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register (CnRXTHRESHSTAT) ............................................................................. 742 19-17.......... 19-23....................... Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn) Field Descriptions ............ Transmit Control Register (TXCONTROL) Field Descriptions ................ EMAC Control Module Revision ID Register (REVID) Field Descriptions ........................................................................... 19-25.............................................................................. 19-7........ Basic Descriptor Description ...... 19-26.................... EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (CnRXEN) ........................................................................................................ 764 19-40........................... 761 19-38.................................. MDIO Revision ID Register (REVID) Field Descriptions ........com 18-87................ Receive Revision ID Register (RXREVID) Field Descriptions ............................ EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT) 19-19.... EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (CnRXIMAX) .......... Management Data Input/Output (MDIO) Registers ...................

................................................................ 19-82........................ 786 786 787 788 790 792 792 793 793 794 794 795 795 796 796 797 797 798 799 799 800 800 801 801 813 814 814 List of Tables Copyright © 2011...... 783 19-60............................................. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions ............................. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ... Transmit Pause Timer Register (TXPAUSE) Field Descriptions .................................... 19-77.... 19-57.................................. 20-3.......... 19-83...... Receive Maximum Length Register (RXMAXLEN) Field Descriptions.............. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions ........................... MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ...... 19-69... Receive Control Register (RXCONTROL) Field Descriptions............ Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions ........... Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ................. 66 ..... MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ................................ 766 19-43... 767 19-44. 19-49.................................... 19-78....... 770 19-47.................................. MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions ......... Emulation Control Register (EMCONTROL) Field Descriptions ............ Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions ... 19-55......... 19-84............. 19-56............................................................ 19-80........................................ 19-73.................................. 19-76............................... MAC Status Register (MACSTATUS) Field Descriptions .........................................................................com 19-42........ 19-72. 19-66........................ ..................................... 769 19-46........ MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................................................................ Back Off Test Register (BOFFTEST) Field Descriptions ................ EMIFA Pins Used to Access Both SDRAM and Asynchronous Memories .. MAC Hash Address Register 2 (MACHASH2) Field Descriptions...................................................................................... 20-1.............. EMIFA Pins Specific to SDRAM .. MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions .................. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions 19-64............... 19-85................. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions .................... Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ... EMIFA Pins Specific to Asynchronous Memory .... MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ......... Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions ................. MAC Configuration Register (MACCONFIG) Field Descriptions .... MAC Address High Bytes Register (MACADDRHI) Field Descriptions ..... MAC Index Register (MACINDEX) Field Descriptions ................................... MAC Control Register (MACCONTROL) Field Descriptions ................................................... Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions ........................................ Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions .......... Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions ................................................................ Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions ......... 785 19-62....... Soft Reset Register (SOFTRESET) Field Descriptions .............................. 19-53..... 19-50............... Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions ................. 780 19-59. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions........... 19-51..................... 19-54................. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions ......... 19-74.............. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ............ Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions ........................ 768 19-45.... 20-2............................................. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback ............................ Receive Teardown Register (RXTEARDOWN) Field Descriptions ..............www... 785 19-63. 19-86............. 19-52.................ti.. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions....................... 771 772 773 774 775 776 777 778 778 779 779 19-58................ Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions ............................................. 19-79.............................. FIFO Control Register (FIFOCONTROL) Field Descriptions .......................... 19-75............ Receive Pause Timer Register (RXPAUSE) Field Descriptions .. 19-68...... MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions ......... 19-67................ MAC Hash Address Register 1 (MACHASH1) Field Descriptions..... 19-71......... 19-81....................... 784 19-61........ Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions 19-48.................................................... 19-65................... 19-70...............................

............. SDRAM Refresh Control Register (SDRCR) Field Descriptions ..... 20-7.................................. 20-29............. 20-38....... Description of the NAND Flash Control Register (NANDFCR) ............. 20-16....................................................................... 20-14.... Asynchronous Read Operation in Select Strobe Mode .. 20-51............................................................ 20-21............................................... ASRAM Input Timing Requirements for a Write .......................................................................................................................... 20-43............... Texas Instruments Incorporated 815 817 818 818 819 819 820 821 826 827 829 830 831 831 831 833 835 837 839 845 847 852 854 855 855 856 857 857 857 858 860 863 863 863 865 865 866 866 868 871 871 873 873 874 875 876 877 879 67 SPRUH77A – December 2011 Submit Documentation Feedback . EMIFA SDRAM Commands ............ Description of the Asynchronous Wait Cycle Configuration Register (AWCC) .........................www......................................................................................... Description of the Asynchronous m Configuration Register (CEnCFG) ............................................................................................................ NAND Flash Timing Requirements for HY27UA081G1M Example ..................................................................................................................................................................................... ASRAM Input Timing Requirement for a Read ................... 20-30. 20-22.................. 20-23............. ASRAM Output Timing Characteristics ............. 20-31................................................................ Interrupt Monitor and Control Bit Fields ........... 20-34...................... 20-19.................................................. NAND Flash Write Timing Requirements ............... 20-44................................. 20-46................... 20-6................ External Memory Interface (EMIFA) Registers ......................... Description of the SDRAM Refresh Control Register (SDRCR) .......................... Description of the SDRAM Timing Register (SDTIMR) .............. Module ID Register (MIDR) Field Descriptions ................................................................................................................ 20-32................................................... Configuring NANDFCR for HY27UA081G1M Example ...... 20-48.................................................... Asynchronous Read Operation in Normal Mode ............................................... EMIFA Timing Requirements for TC5516100FT-12 Example ...................................................... EMIFA Input Timing Requirements ..... 20-40.........................com 20-4..... 20-50.................................. 20-41........................................ 20-28.............................. 20-10.................................................. SDRAM Configuration Register (SDCR) Field Descriptions ...... Truth Table for SDRAM Commands 16-bit EMIFA Address Pin Connections List of Tables Copyright © 2011................................................ Reset Sources .................................. RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface ............. Description of the SDRAM Configuration Register (SDCR) .................... SDTIMR Field Calculations for the EMIFA to K4S641632H-TC(L)70 Interface . Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions ..................................... 20-42............. Description of the SDRAM Self Refresh Exit Timing Register (SDSRETR)........................ EMIFA Read Timing Requirements ..... 20-37............................ Configuring CE2CFG for HY27UA081G1M Example .................................. 20-9........ 20-26..... ASRAM Timing Requirements With PCB Delays .... 20-18................................ 20-20..................................... 20-8.............. Normal Mode vs.. 20-5............ 815 ................................................ 20-11....................................... 20-39......................................... 20-17............................................................................. 20-25............... 20-33.... Measured PCB Delays for TC5516100FT-12 Example ....... ASRAM Timing Requirements for TC5516100FT-12 Example ................. Mapping from Logical Address to EMIFA Pins for 16-bit SDRAM ..... 20-35........... Description of the EMIFA Interrupt Mast Clear Register (INTMSKCLR) ................................ 20-52......................................... Asynchronous Write Operation in Normal Mode .......................... 20-36................................................. 20-13........................................ NAND Flash Read Timing Requirements ...... Description of the EMIFA Interrupt Mask Set Register (INTMSKSET) ........................ 20-15................. 20-49. 20-24......................... 20-12................................................................................................... Configuring CE3CFG for TC5516100FT-12 Example.......... SDRAM LOAD MODE REGISTER Command ............................................. SR Field Value For the EMIFA to K4S641632H-TC(L)70 Interface .............................. Select Strobe Mode ......... RR Calculation for the EMIFA to K4S641632H-TC(L)70 Interface ..... 20-47...... SDCR Field Values For the EMIFA to K4S641632H-TC(L)70 Interface ....... EMIFA Timing Requirements for HY27UA081G1M Example ............................................. 20-27............................. Asynchronous Write Operation in Select Strobe Mode ............................................. Refresh Urgency Levels........................... ....................................................... Recommended Margins ............................ 20-45...........................................................ti..........................

............. GPIO Direction 1 Register (GPIO_DIR1) Field Descriptions ................... 22-3....... 22-9............. NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) Field Descriptions ........................................................................................................................ 21-10........................... GPIO Data 1 Register (GPIO_DAT1) Field Descriptions . GPIO Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions ............ Revision Identification Register (REVID) Field Descriptions ................................................ GPIO Register Bits and Banks Associated With GPIO Signals..... EMIFA Interrupt Mask Clear Register (INTMSKCLR) Field Descriptions ............................................................. GPIO Set Data Register (SET_DATAn) Field Descriptions .............. 22-8....... Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions ....................................... 21-4.......................................... Revision ID Register (REVID) Field Descriptions ................ 20-69......... 21-14. Cycle Types Selectable With the UHPI_HCNTL and UHPI_HR/W Signals .................. 20-59........ 20-67.......... EMIFA Interrupt Mask Set Register (INTMSKSET) Field Descriptions ............................ 20-56.............................. NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) Field Descriptions ....... GPIO Registers....... Host Port Interface Read Address Register (HPIAR) Field Descriptions ......... 20-64................... 22-16............................................................................. 20-71.................................................. GPIO Set Falling Edge Trigger Interrupt Register (SET_FAL_TRIGn) Field Descriptions ......................................... 22-10............... EMIFA Interrupt Mask Register (INTMSK) Field Descriptions .................................... 21-8................................ 22-6.................................. GPIO Data 2 Register (GPIO_DAT2) Field Descriptions .. SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions ......................................................... Host Port Interface Write Address Register (HPIAW) Field Descriptions ......................... Host Port Interface Control Register (HPIC) Field Descriptions ... GPIO Direction 2 Register (GPIO_DIR2) Field Descriptions ... GPIO Interrupt Status Register (INTSTATn) Field Descriptions ...................................... HPI Registers ...... NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) Field Descriptions ............................ 22-13......... GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn) Field Descriptions..... 20-70............. 21-5.... 20-68.............. 21-12........................................... 20-61...................................... 22-12............... HPI Pins ......................... 22-4................ EMIFA Interrupt Raw Register (INTRAW) Field Descriptions ......................................................................... 21-3.............. Options for Connecting Host and HPI Data Strobe Pins ... NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) Field Descriptions .................................... 21-13................................. Texas Instruments Incorporated 880 881 882 883 884 885 886 887 889 890 891 892 892 893 893 894 894 895 895 900 907 908 909 911 913 915 917 919 921 923 925 927 929 935 936 940 941 941 955 956 956 957 958 958 959 960 962 963 963 List of Tables SPRUH77A – December 2011 Submit Documentation Feedback .................................. NAND Flash Status Register (NANDFSR) Field Descriptions ................ 20-55.................................................................................. 20-66...... 20-63........................................ 22-15.............. Value on Optional Pins when Configured as General-Purpose I/O ............. Copyright © 2011........................................ NAND Flash Control Register (NANDFCR) Field Descriptions .......................... GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions . 22-14.............. 22-7........................................................................... 21-11............................................ GPIO Output Data Register (OUT_DATAn) Field Descriptions ...com 20-53.................... 20-60............................. NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD) Field Descriptions .....www.................... 22-11...... GPIO Set Rising Edge Trigger Interrupt Register (SET_RIS_TRIGn) Field Descriptions .............. NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) Field Descriptions ............................................... GPIO Clear Data Register (CLR_DATAn) Field Descriptions .. 21-7...................... 21-6............................... 20-62.................... NAND Flash n ECC Register (NANDFnECC) Field Descriptions ..... GPIO Input Data Register (IN_DATAn) Field Descriptions ................... NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) Field Descriptions .. SDRAM Timing Register (SDTIMR) Field Descriptions .................. 20-65............................... NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1) Field Descriptions ........................ 22-2......... 21-1..................................... 68 .......... Asynchronous n Configuration Register (CEnCFG) Field Descriptions 20-54.............. 20-58...... 21-2............................... Access Types Selectable With the UHPI_HCNTL Signals .................... GPIO Direction Register (DIRn) Field Descriptions .............ti.... 22-5................. 22-1...... GPIO Enable Register (GPIO_EN) Field Descriptions ...................................................................................... 21-9................................... 20-57........ NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) Field Descriptions ...........................................

...................... 23-26................................. 1012 LIDD I/O Name Map ................................................... 991 23-15.......................... How the MST and FDF Bits Affect the Role of TRX Bit 23-17. 23-28............................................ 1003 I2C Pin Data Set Register (ICPDSET) Field Descriptions .... 987 23-11................ 1001 I2C Pin Data In Register (ICPDIN) Field Descriptions........................................... 24-14...... 24-7....................................................... 1025 LCD Control Register (LCD_CTRL) Field Descriptions ......................................... 988 23-12............................ 1034 LCD Raster Control Register (RASTER_CTRL) Field Descriptions .........................www. Master-Transmitter/Receiver Bus Activity Defined by RM........................ 1035 LCD Controller Data Pin Utilization for Mono/Color Passive/Active Panels ..................................... 23-2............................... 1005 LCD External I/O Signals .................................... 23-27........................ 24-10........................ 24-15... Operating Modes of the I2C Peripheral ... 24-6........com 23-1............. 24-13.................... 1033 LCD LIDD CSn Data Read/Write Register (LIDD_CSn_DATA) Field Descriptions .................................. 24-20..................... STT................................................................... 1032 LCD LIDD CSn Address Read/Write Register (LIDD_CSn_ADDR) Field Descriptions ....................... 975 Descriptions of the I2C Interrupt Events ............................. 24-2..... 23-24....... 997 I2C Revision Identification Register 1 (REVID1) Field Descriptions ....... I2C Mode Register (ICMDR) Field Descriptions ..... 996 I2C Prescaler Register (ICPSC) Field Descriptions ........................ 1025 LCD Revision Identification Register (REVID) Field Descriptions .................... 990 23-14........ 986 23-10......... 1042 LCD Raster Timing Register 1 (RASTER_TIMING_1) Field Descriptions ........ and STP Bits ................... 1011 Register Configuration for DMA Engine Programming ...................................................................... 23-6............................................................................. 1018 Color/Grayscale Intensities and Modulation Rates ....................................................... 1017 Frame Buffer Size According to BPP ............... 980 I2C Own Address Register (ICOAR) Field Descriptions .... 24-19....................................... 24-16..... ...... 23-9.................... 23-22.......... 999 I2C Pin Function Register (ICPFUNC) Field Descriptions .................. 23-3............... 24-5.................................. 23-20.. I2C Slave Address Register (ICSAR) Field Descriptions ........... I2C Data Transmit Register (ICDXR) Field Descriptions ................................. 1037 LCD Raster Timing Register 0 (RASTER_TIMING_0) Field Descriptions ......................................... 982 I2C Interrupt Status Register (ICSTR) Field Descriptions ........................ 23-8.................................................................................................................. 23-18...............................................ti.. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback 69 ... 993 I2C Interrupt Vector Register (ICIVR) Field Descriptions ................................ 24-12............................. I2C Data Receive Register (ICDRR) Field Descriptions ........................................................................................... 23-21............... 986 I2C Clock High-Time Divider Register (ICCLKH) Field Descriptions ............................................................ 24-17......................................................... 983 I2C Clock Low-Time Divider Register (ICCLKL) Field Descriptions ......... 1030 LCD LIDD CSn Configuration Register (LIDD_CSn_CONF) Field Descriptions .............................. 1027 LCD Status Register (LCD_STAT) Field Descriptions... 24-8....... 24-21................... 981 I2C Interrupt Mask Register (ICIMR) Field Descriptions ............................................................................................................................................................................................. 1026 Pixel Clock Frequency Programming Limitations .......... 1000 I2C Pin Direction Register (ICPDIR) Field Descriptions .................................... 993 23-16...... 995 I2C Extended Mode Register (ICEMDR) Field Descriptions ............... 1028 LCD LIDD Control Register (LIDD_CTRL) Field Descriptions .... 23-19........ 23-23....................... 1004 I2C Pin Data Clear Register (ICPDCLR) Field Descriptions ........... 989 23-13............... 974 Ways to Generate a NACK Bit .................................................. 24-11............ 998 I2C DMA Control Register (ICDMAC) Field Descriptions......... 23-4.................... 24-18.......................................... 23-7................... 23-5......... I2C Data Count Register (ICCNT) Field Descriptions ............... 24-3..................................... 998 I2C Revision Identification Register 2 (REVID2) Field Descriptions ...................... 1022 Number of Colors/Shades of Gray Available on Screen ...... 1014 Operation Modes Supported by Raster Controller ................................... 1002 I2C Pin Data Out Register (ICPDOUT) Field Descriptions ......... 24-4.......................................................................................... 979 Inter-Integrated Circuit (I2C) Registers.................................. 23-25................... 1044 List of Tables Copyright © 2011................................................................ 1022 LCD Controller (LCDC) Registers ................................................................................................. 24-1........................................... 24-9.......................................... 1015 Bits-Per-Pixel Encoding for Palette Entry 0 Buffer ..........................

.......................... 25-27............................... 25-21.................... Pin Data Set Register (PDSET) Field Descriptions .............................com 24-22...................... 25-17.............. 25-2................. LCD DMA Control Register (LCDDMA_CTRL) Field Descriptions............. 25-12. Transmit Clock Control Register (ACLKXCTL) Field Descriptions ....... 25-20................... 25-38.............................. McASP Registers Accessed Through Peripheral Configuration Port .................................. 25-5............... Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions ....................................................... 25-13.................................................................... Revision Identification Register (REV) Field Descriptions ...................................................... 25-41......... Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions .. 25-11............................ 25-16........................................................ 25-4................... Receiver Interrupt Control Register (RINTCTL) Field Descriptions .............. Pin Data Input Register (PDIN) Field Descriptions............... Receive Clock Control Register (ACLKRCTL) Field Descriptions .................. 1048 24-23.................. Receiver Global Control Register (RGBLCTL) Field Descriptions .............................. 25-40......................... Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions .............. Biphase-Mark Encoder Copyright © 2011..................................................... 25-18........................................... 25-29............................................................................................................................................ 25-35.............................................................................................. Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions ................................... Receive Frame Sync Control Register (AFSRCTL) Field Descriptions ......... Global Control Register (GBLCTL) Field Descriptions ....................................................... 25-26....................... Channel Status and User Data for Each DIT Block ................... 25-36............................. Texas Instruments Incorporated 1065 1066 1092 1100 1102 1112 1113 1115 1115 1116 1117 1118 1120 1122 1124 1126 1128 1129 1131 1133 1134 1135 1136 1137 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1152 1153 1154 1155 1156 1157 1158 1159 List of Tables SPRUH77A – December 2011 Submit Documentation Feedback .... 25-37......... Digital Mode Control Register (DITCTL) Field Descriptions ................ Preamble Codes ..... Bits With Restrictions on When They May be Changed ...... EDMA Events ............ Receiver DMA Event Control Register (REVTCTL) Field Descriptions ......................................... 25-6............... 25-8............................... McASP Registers Accessed Through DMA Port ............... 25-9.... 25-24........ LCD DMA Frame Buffer n Base Address Register (LCDDMA_FBn_BASE) Field Descriptions .......................www........................................... 25-44............................... 25-23.................................................. 25-7.................................... Pin Data Output Register (PDOUT) Field Descriptions ........................... LCD Raster Subpanel Display Register (RASTER_SUBPANEL) Field Descriptions ................ 25-15.................................... Transmit Bit Stream Format Register (XFMT) Field Descriptions............................................... 25-19.............. 25-43............ Receive TDM Time Slot Register (RTDM) Field Descriptions ........................ Transmit Clock Check Control Register (XCLKCHK) Field Descriptions ............ 25-14. 25-25............................... McASP AFIFO Registers Accessed Through Peripheral Configuration Port ............... 25-22................. Pin Function Register (PFUNC) Field Descriptions ............. Transmitter Global Control Register (XGBLCTL) Field Descriptions ....................... 1054 24-25......................ti......... Receive Clock Check Control Register (RCLKCHK) Field Descriptions ...................................................... LCD Raster Timing Register 2 (RASTER_TIMING_2) Field Descriptions .... 25-34.... LCD DMA Frame Buffer n Ceiling Address Register (LCDDMA_FBn_CEILING) Field Descriptions ...................... 25-32............. Receive Format Unit Bit Mask Register (RMASK) Field Descriptions . Receive Bit Stream Format Register (RFMT) Field Descriptions ........... Digital Loopback Control Register (DLBCTL) Field Descriptions .......... Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions ....... 70 ........McASP ........ Transmit Bitstream Data Alignment .. Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions . 25-28........................ Audio Mute Control Register (AMUTE) Field Descriptions.. Pin Data Clear Register (PDCLR) Field Descriptions ............................. 25-33............ Transmitter Interrupt Control Register (XINTCTL) Field Descriptions ..................... 1052 24-24... 25-3. Transmitter Status Register (XSTAT) Field Descriptions ....................................................... 1055 25-1........... 25-39....................... 25-31................ Transmit TDM Time Slot Register (XTDM) Field Descriptions ............................................................................... Receiver Status Register (RSTAT) Field Descriptions .................. 25-10................................. 25-42...................................................................... 1055 24-26..................................................... 25-30......................................... Receive Bitstream Data Alignment ...................................... Pin Direction Register (PDIR) Field Descriptions ..........................

......................................... Transmit Channel Assignment and Control When Two Transmit Partitions are Used . 26-27..... Texas Instruments Incorporated 1160 1161 1165 1166 1167 1168 1169 1174 1178 1181 1182 1183 1184 1185 1185 1186 1188 1188 1204 1207 1207 1209 1209 1210 1213 1214 1214 1220 1221 1222 1222 1223 1225 1227 1229 1230 1234 1235 1236 1237 1238 1240 1241 1242 1243 1244 1249 1250 1251 71 SPRUH77A – December 2011 Submit Documentation Feedback ......................................... Multichannel Control Register (MCR) Field Descriptions ..............................................................................www............. 26-19...................................................................................................................................... Serial Port Control Register (SPCR) Field Descriptions............................................ 26-10............................... 26-15.............................. Receive Control Register (RCR) Field Descriptions ....... MMC/SD Mode Read Sequence ... Reset State of McBSP Pins ................................................... McBSP Registers ......................... 27-2........................... Receive/Transmit Element Length Configuration .... Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions 25-46................................................................................................................ 25-47................................ 26-26......................................................................................................... Receive Channel Assignment and Control When Eight Receive Partitions are Used ......... 26-18........ Effect of RJUST Bit Values With 12-Bit Example Data ABCh .......................................................................................... List of Tables Copyright © 2011..... 26-35.. Receiver Clock and Frame Configurations ......................................... 26-17.... Read FIFO Control Register (RFIFOCTL) Field Descriptions . 26-29.................................................... AFIFO Revision Identification Register (AFIFOREV) Field Descriptions ........... 26-13.. 26-20.............................. Write FIFO Control Register (WFIFOCTL) Field Descriptions ....................................... 26-5. McBSP Interface Signals ................................................ 26-38......................................... Enhanced Receive Channel Enable Register n (RCEREn) Field Descriptions ...................... Read FIFO Control Register (RFIFOCTL) Field Descriptions .. Enhanced Transmit Channel Enable Register n (XCEREn) Field Descriptions.. Transmit Clock Selection .... Write FIFO Status Register (WFIFOSTS) Field Descriptions...................... 26-4....... 26-23........ 26-22..................................................................... RCR/XCR Fields Controlling Elements per Frame and Bits per Element............................................... 26-7.........................ti........................................................................... Write FIFO Control Register (WFIFOCTL) Field Descriptions ........ Transmit Channel Assignment and Control When Eight Transmit Partitions are Used .................. ...... McBSP Emulation Modes Selectable With the FREE and SOFT Bits of SPCR .. Sample Rate Generator Register (SRGR) Field Descriptions ......... 26-36.......................................... 26-6.................................................................. Selecting a Transmit Multichannel Selection Mode With the XMCM Bits ...... 25-50....... 26-39.................................... 26-2...................... 26-8....................... Justification of Expanded Data in DRR ................ 26-28.................................................................................... 26-21........... Transmitter Clock and Frame Configurations ................... Effect of RJUST Bit Values With 20-Bit Example Data ABCDEh ......... Read FIFO Status Register (RFIFOSTS) Field Descriptions ............................ 27-3....... 26-24.................................. BFIFO Revision Identification Register (BFIFOREV) Field Descriptions ........... 26-32.................. 25-49.......................... 26-3.................................. 26-34........ Receive Channel Assignment and Control When Two Receive Partitions are Used ....com 25-45... Receive Frame Synchronization Selection ................................... Receive Clock Selection ................................ 26-14............... 26-16................................................................................ Serializer Control Registers (SRCTLn) Field Descriptions ....... MMC/SD Controller Pins Used in Each Mode .. Receive/Transmit Frame Length Configuration .... 26-25.............................. 26-37................... Read FIFO Status Register (RFIFOSTS) Field Descriptions ..................... 26-12........................................................... Pin Control Register (PCR) Field Descriptions ...... 26-30...................................................................................... 26-1..... Data Receive Register (DRR) Field Descriptions ..................... 26-11...................... 26-33....................... 25-51............. Data Transmit Register (DXR) Field Descriptions ............... Transmit Control Register (XCR) Field Descriptions .............................. Use of the Transmit Channel Enable Registers ................... Transmit Frame Synchronization Selection ...................... 26-9....................................... Use of the Receive Channel Enable Registers ................ 27-1.................. 25-48. MMC/SD Mode Write Sequence ....................................................................................................................... 26-31............................................................................ Choosing an Input Clock for the Sample Rate Generator With the SCLKME and CLKSM Bits .......................... Write FIFO Status Register (WFIFOSTS) Field Descriptions..........

... MMC Command Register (MMCCMD) Field Descriptions ....................... MMC Status Register 0 (MMCST0) Field Descriptions ....................................... 28-15.... 27-15........................... 27-5...................................................... 27-10........................... Day Register (DAY) Field Descriptions ................. MMC Data Read Time-Out Register (MMCTOD) Field Descriptions ...................................... Minute Register (MINUTE) Field Descriptions ....................... 28-14.............................................................................. 28-16........................................................................ 28-18...... Month Register (MONTH) Field Descriptions ...................................... R4................. Alarm Second Register (ALARMSECOND) Field Descriptions ......................................................... 28-9............... 28-13.................... Second Register (SECOND) Field Descriptions.................................. Real-Time Clock Signals ......................................... 28-3................. 28-12....................................... Hour Register (HOUR) Field Descriptions ........................................................................................................................................... Oscillator Register (OSC) Field Descriptions .............. 28-6......... 27-22.............. Control Register (CTRL) Field Descriptions .................. MMC Data Transmit Register (MMCDXR) Field Descriptions ...................................................... 27-29............................................................................. MMC FIFO Control Register (MMCFIFOCTL) Field Descriptions .................. 27-23...... MMC Block Length Register (MMCBLEN) Field Descriptions ............................................................ 1275 MMC Control Register (MMCCTL) Field Descriptions ................................................... 27-13........... 27-21....................................................... 27-12.................. Alarm Years Register (ALARMYEARS) Field Descriptions ................................. MMC Number of Blocks Register (MMCNBLK) Field Descriptions ............................................. Kick Registers (KICKnR) Field Descriptions .. 28-17.................... 72 Description of MMC/SD Interrupt Requests ....................................................... SDIO Interrupt Enable Register (SDIOIEN) Field Descriptions ............. 28-19.....com 27-4......... or R6 Response (48 Bits) ...................... 27-8...... 28-21.................... Texas Instruments Incorporated 1277 1278 1280 1281 1283 1284 1285 1286 1286 1287 1287 1288 1289 1290 1292 1292 1293 1293 1294 1295 1296 1296 1297 1301 1307 1308 1308 1309 1310 1310 1311 1311 1312 1312 1313 1314 1315 1315 1316 1317 1318 1319 1320 1321 1322 1322 List of Tables SPRUH77A – December 2011 Submit Documentation Feedback ....... MMC Memory Clock Control Register (MMCCLK) Field Descriptions Copyright © 2011................. 28-22.......................................... Interrupt Register (INTERRUPT) Field Descriptions ........................................................... Status Register (STATUS) Field Descriptions .................................................. Day of the Week Register (DOTW) Field Descriptions ..... 27-7....................................................................... R1........ 1261 Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers ..... MMC Interrupt Mask Register (MMCIM) Field Descriptions ...................................................... 28-11.................................................. SDIO Status Register 0 (SDIOST0) Field Descriptions ................................... Compensations Register (COMPMSB) Field Descriptions......................................... 27-26........ Scratch Registers (SCRATCHn) Field Descriptions ....... 27-11................................. Year Register (YEAR) Field Descriptions ........................................................................... 28-4....... 28-1.............................. 27-14..... Command Format ............................ 27-9.. 27-16.......... Alarm Day Register (ALARMDAY) Field Descriptions ........ Compensations Register (COMPLSB) Field Descriptions ....... 27-17................................................................................................. 1276 ........... R5......................... 27-28. Real-Time Clock (RTC) Registers ........................ MMC Status Register 1 (MMCST1) Field Descriptions ................... 28-10.... SDIO Control Register (SDIOCTL) Field Descriptions .................www...... MMC Response Time-Out Register (MMCTOR) Field Descriptions ......................................... R3..................... 28-8............................................. 27-18............... 27-19..... 28-20.................................. 27-27.................... Alarm Month Register (ALARMMONTH) Field Descriptions ..................... 27-24.......... 28-23....................... 27-6.......................... MMC Data Response Register (MMCDRSP) Field Descriptions ................................ 27-25............... 28-5.............................................................................................................................. MMC Command Index Register (MMCCIDX) Field Descriptions ...................................................................... 28-7......... MMC Argument Register (MMCARGHL) Field Descriptions.. SDIO Interrupt Status Register (SDIOIST) Field Descriptions ......... MMC Number of Blocks Counter Register (MMCNBLC) Field Descriptions ......... Alarm Hour Register (ALARMHOUR) Field Descriptions .......................... 28-2............ 27-20................... MMC Data Receive Register (MMCDRR) Field Descriptions ... Alarm Minute Register (ALARMMINUTE) Field Descriptions ......................................... R2 Response (136 Bits) .........................................................ti........................

............... 1356 Interrupt Status Register (IS) Field Descriptions .................................... Port Serial ATA Notification Register (POSNTF) Field Description ..... Port Interrupt Status Register (P0IS) Field Descriptions ...................................... 29-28.................... 1328 Signal Descriptions ............................................ 29-19.... ID Register (IDR) Field Description ....... 30-9..................... BIST Status Register (BISTSR) Field Description ...................................................... Clocking Modes ........................... 30-1.......................... SPI Registers .... 30-5...................................................... Port Interrupt Enable Register (P0IE) Field Descriptions ..................................... BIST DWORD Error Count Register (BISTDECR) Field Description ........ ................................................................... 30-8......... Port Signature Register (P0SIG) Field Description ........ BIST Control Register (BISTCR) Field Descriptions ...... 1329 SATASS Memory Summary ......................................... Port Serial ATA Error Register (P0SERR) Field Descriptions ............................................. Global Parameter 2 Register (GPARAM2R) Field Descriptions.. 30-3.................. SPI Pins.................................... 29-26... Version Register (VERSIONR) Field Description ................... Command Completion Coalescing Control Register (CCC_CTL) Field Descriptions ..................................................................... 29-20.................. 29-33... Global Parameter 1 Register (GPARAM1R) Field Descriptions............................................... 29-3...... 29-32................ 29-31.......... 1359 29-11. 30-4.................... SPI Register Settings Defining Master Modes........................................................... 29-6........... 1353 1355 SATA Controller Registers ................................. BIST FIS Count Register (BISTFCTR) Field Description 29-15..... ............................................................................ SPI Global Control Register 1 (SPIGCR1) Field Descriptions..................................................................................................................... 30-7.......................................................................... Allowed SPI Register Settings in Master Modes ............................................... Port Task File Data Register (P0TFD) Field Descriptions . 29-23.............. 29-25.................................................... Test Register (TESTR) Field Descriptions ........................................ 29-9.................................................................................................................. Port PHY Control Register (P0PHYCR) Field Descriptions .................................................................................................................. 29-36... 29-35.................. 1358 29-10........ 29-38.................................... 29-17............................... 1357 Ports Implemented Register (PI) Field Descriptions ................. Port Command List Base Address Register (P0CLB) Field Description ........ List of Tables Copyright © 2011................................................................... 29-8.......... Allowed SPI Register Settings in Slave Modes......... 30-10............................www................................................ 29-22....ti..................................... SPI Registers ............................................... Texas Instruments Incorporated 1364 1364 1365 1365 1366 1367 1368 1369 1370 1370 1371 1371 1372 1374 1375 1378 1378 1379 1380 1381 1383 1383 1384 1385 1387 1391 1396 1397 1398 1398 1400 1400 1409 1422 1422 1423 73 SPRUH77A – December 2011 Submit Documentation Feedback ................................................................ 1362 29-14....................com 29-1.. 29-37.................................. 29-2........... BIST Active FIS Register (BISTAFR) Field Descriptions .. 29-29........................................................... MPY Bit Field of P0PHYCR ........ Port FIS Base Address Register (P0FB) Field Description ................................................................ 1354 HBA Capabilities Register (CAP) Field Descriptions Global HBA Control Register (GHC) Field Descriptions.............................. 29-5....................... 29-21................................................................................................................................................... 29-4..................... Port Parameter Register (PPARAMR) Field Descriptions ............................ 30-2.............................. Port Command Register (P0CMD) Field Descriptions. SPI Global Control Register 0 (SPIGCR0) Field Descriptions......... Port Serial ATA Active Register (P0SACT) Field Description ................................................................. 30-6......... Port DMA Control Register (P0DMACR) Field Description ...... Port Serial ATA Control Register (P0SCTL) Field Descriptions ...... 29-7............................................ 29-30................ 29-27.................................................................... Command Completion Coalescing Ports Register (CCC_PORTS) Field Description ........................................... BIST DWORD Error Count Register (TIMER1MS) Field Description .............. Port Serial ATA Active (SActive) Register (P0SACT) Field Description ...................................................... 1358 AHCI Version Register (VS) Field Descriptions . Port PHY Status Register (P0PHYSR) Field Description .............................. 1361 29-13.......................... 29-34............. 1360 29-12.................... 29-39............................................................ 29-24.......................... 29-18.................................... Port Serial ATA Status Register (P0SSTS) Field Descriptions .................... 29-16............. SPI Register Settings Defining Slave Modes ........................................................................

.... SPI Data Format Register (SPIFMTn) Field Descriptions..... Timer Capture Register 34 (CAP34) Field Descriptions............................................................................... 32-3. 31-16............... 31-19................................................ SPI Pin Control Register 2 (SPIPC2) Field Descriptions ......................................... 32-1................................................................. Timer Counter Register 34 (TIM34) Field Descriptions ............................ Timer Counter Register 12 (TIM12) Field Descriptions . Timer Reload Register 34 (REL34) Field Descriptions .............. 31-18.................... 31-24.... 1444 30-26...................... 74 Timer Clock Source Selection .......... Receiver Buffer Register (RBR) Field Descriptions .................................. SPI Pin Control Register 4 (SPIPC4) Field Descriptions ........................... 31-22...... SPI Flag Register (SPIFLG) Field Descriptions ......................... Timer Global Control Register (TGCR) Field Descriptions....................... Emulation Management Register (EMUMGT) Field Descriptions ........... Baud Rate Examples for 150-MHZ UART Input Clock and 13× Over-sampling Mode ........ SPI Data Register 0 (SPIDAT0) Field Descriptions ......................................................... 1428 30-14.................................................................................... 1452 64-Bit Timer Configurations ............. Timer Registers .............................................................. 1434 30-19................ Texas Instruments Incorporated 1466 1468 1468 1469 1469 1470 1471 1472 1472 1473 1473 1474 1476 1477 1478 1478 1479 1479 1480 1481 1487 1487 1488 1491 1495 1497 1498 List of Tables SPRUH77A – December 2011 Submit Documentation Feedback ....... 31-11............. SPI Emulation Register (SPIEMU) Field Descriptions ................ 31-3............................................. SPI Interrupt Level Register (SPILVL) Field Descriptions............................. SPI Interrupt Register (SPIINT0) Field Descriptions ............. 31-9............................................................ Timer Period Register (PRD34) Field Descriptions .................................... 32-7............ 1441 30-25................ Timer Period Register (PRD12) Field Descriptions ............................................................................................ SPI Pin Control Register 0 (SPIPC0) Field Descriptions .............. Revision ID Register (REVID) Field Descriptions ............ 1433 30-18..................................................... UART Registers ....... 31-21............................................................................................... 1431 30-16...... SPI Data Register 1 (SPIDAT1) Field Descriptions ................................................ SPI Interrupt Vector Register 1 (INTVEC1) Field Descriptions ................. GPIO Data and Direction Register (GPDATGPDIR) Field Descriptions ....................ti...... SPI Pin Control Register 3 (SPIPC3) Field Descriptions ............... Timer Capture Register 12 (CAP12) Field Descriptions.......................................................... Timer Interrupt Control and Status Register (INTCTLSTAT) Field Descriptions ............................................... 1437 30-22................................................................. 1460 Counter and Period Registers Used in GP Timer Modes ..................................................... 31-25.. 31-14.... 31-12.............................................................................. 1432 30-17...................................www.................................... 31-5. TSTAT Parameters in Pulse and Clock Modes Timer Emulation Modes Selection Copyright © 2011............................................. 32-4.... 31-4..................................................... 1425 30-12...... 1440 30-24... 32-6........................... 31-15........................... 31-2............................................. GPIO Interrupt Control and Enable Register (GPINTGPEN) Field Descriptions ....................... 32-2......................... Timer Reload Register 12 (REL12) Field Descriptions ................................................................................................................ 1436 30-21............. 1435 30-20. SPI Buffer Register (SPIBUF) Field Descriptions ....................................... SPI Pin Control Register 5 (SPIPC5) Field Descriptions .............................. ........................ Timer Compare Register (CMPn) Field Descriptions ...................... 31-17.......................................................................................................................................... UART Interrupt Requests Descriptions .. Baud Rate Examples for 150-MHZ UART Input Clock and 16× Over-sampling Mode .............. 31-7... 1445 30-27..... Timer Control Register (TCR) Field Descriptions .................... SPI Delay Register (SPIDELAY) Field Descriptions ........................... SPI Pin Control Register 1 (SPIPC1) Field Descriptions .. 1457 32-Bit Timer Unchained Mode Configurations ............................... 31-20................ Watchdog Timer Control Register (WDTCR) Field Descriptions ............................ 31-8........... UART Signal Descriptions ....................................................................................................................................................................................... 1462 ....... 1427 30-13........................................................ 1447 31-1............. 31-10.......................................................... 32-5.............. 1438 30-23....................................... 31-6................... 31-13...................... 1430 30-15............................com 30-11.......................... 31-23........................................................................... SPI Default Chip Select Register (SPIDEF) Field Descriptions ............... 1454 32-Bit Timer Chained Mode Configurations .............. Character Time for Word Lengths ...

............................. uPP Peripheral Identification Register (UPPID) Field Descriptions ....... uPP DMA Channel Q Descriptor 2 Register (UPID2) Field Descriptions ................. uPP Parameters Useful for System Tuning ............... EPS....................................................... 33-8................................................ 1501 32-11..... 33-4.................................................. Relationship Between ST........... 33-24................................. Revision Identification Register 2 (REVID2) Field Descriptions .................................. Line Control Register (LCR) Field Descriptions ................ 33-19............................. 33-7........................................................... 33-13................... List of Tables Copyright © 2011........................ uPP Interface Configuration Register (UPICR) Field Descriptions.............................................................................................. uPP Digital Loopback Register (UPDLB) Field Descriptions ...... 33-23........ 33-31............. uPP DMA Channel Q Descriptor 1 Register (UPQD1) Field Descriptions .................. I/O Clock Speeds for Channel in Transmit Mode Given 150 MHz Transmit Clock .............................. Interrupt Identification Register (IIR) Field Descriptions ........ 33-9........................................ 33-26...........www............... 1502 32-12........ 33-5............................... Revision Identification Register 1 (REVID1) Field Descriptions .......................... Number of STOP Bits Generated ...................................... 1503 32-13..................................ti........ 33-25................. Divisor LSB Latch (DLL) Field Descriptions............................................................................. 1505 32-16................... uPP Interrupt Raw Status Register (UPISR) Field Descriptions .............. 33-30................. uPP Interrupt Enable Set Register (UPIES) Field Descriptions .......................................................... 33-20.... uPP Interrupt Enable Clear Register (UPIEC) Field Descriptions...... and PEN Bits in LCR .............. Interrupt Identification and Interrupt Clearing Information ..................................................................................... DATA and XDATA Pin Assignments to Channels A and B According to Operating Mode .......... uPP Interrupt Enabled Status Register (UPIER) Field Descriptions .......................... Data Packing Examples for 12-Bit Data Words .......................................................... 33-12............... Sample uPP Parameters for Duplex Mode 0 ......................... Modem Control Register (MCR) Field Descriptions. Required Signals for Various Modes.............. Basic Operating Mode Selection .................................. 1504 32-14........ 33-29........................................ Scratch Pad Register (MSR) Field Descriptions 32-21................. 1512 ........................... Divisor MSB Latch (DLH) Field Descriptions 32-22.......................... 33-11.................. uPP Channel Control Register (UPCTL) Field Descriptions ...... uPP Registers .................... 1510 32-19............................ 33-3............. 33-6........ Modem Status Register (MSR) Field Descriptions .......................... 33-16..................... uPP Interface Idle Value Register (UPIVR) Field Descriptions ......... FIFO Control Register (FCR) Field Descriptions ................................. 33-28........ 1499 Interrupt Enable Register (IER) Field Descriptions .................................. Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions ..................... uPP DMA Channel I Descriptor 2 Register (UPID2) Field Descriptions.............. 33-22...................... Mode Definition Register (MDR) Field Descriptions .............................................................................................................................. 33-14........................................ 1506 32-17....................................................... 1500 32-10........................... 33-18.......................................................................................... uPP End of Interrupt Register (UPEOI) Field Descriptions ................................................ 32-23............... 32-9... 33-2....................... uPP Threshold Configuration Register (UPTCR) Field Descriptions ........... 33-10..................... 33-21.................. 32-20................ uPP DMA Channel I Descriptor 0 Register (UPID0) Field Descriptions........................ uPP Peripheral Control Register (UPPCR) Field Descriptions ...................... 32-24.......................................... Interface and DMA Channel Mapping for Various Operating Modes ........................................................... Transmitter Holding Register (THR) Field Descriptions .......... uPP DMA Channel I Descriptor 1 Register (UPID1) Field Descriptions................................... 33-15........................... 33-27. uPP DMA Channel Q Descriptor 0 Register (UPQD0) Field Descriptions .................................................................................. uPP DMA Channel I Status 2 Register (UPIS2) Field Descriptions ...... uPP DMA Channel I Status 1 Register (UPIS1) Field Descriptions .com 32-8.... uPP Signal Descriptions .................... 33-1......................................................... Line Status Register (LSR) Field Descriptions ....................... 1507 1511 1512 1513 1513 1514 1515 1522 1522 1523 1525 1526 1530 1532 1533 1534 1538 1538 1539 1540 1541 1543 1545 1546 1547 1549 1551 1553 1555 1555 1556 1556 1557 1557 1558 1559 1559 1560 75 32-18............................................................... Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback ...... 1505 32-15...... 32-25............... 33-17........................................................... ............... uPP DMA Channel I Status 0 Register (UPIS0) Field Descriptions ..

............... Host Packet Descriptor Word 4 (HPD Word 4) ............................ 1579 34-15............................................................................. PHY PLL Clock Frequencies Supported ........................................... USB Clock Multiplexing Options .................................. 35-6...... 1578 34-13............ HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions....... 76 ............................... PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions ............................................................ 1569 OHCI Revision Number Register (HCREVISION) Field Descriptions ................. 34-4............................................................................................ HC Frame Interval Register (HCFMINTERVAL) Field Descriptions ........................... Host Packet Descriptor Word 7 (HPD Word 7) ................................................................ 35-11................ Host Packet Descriptor Word 5 (HPD Word 5) ....... 35-18......... HC Periodic Start Register (HCPERIODICSTART) Field Descriptions 34-19........... 1571 HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions............................ 34-22.......................................... Host Packet Descriptor Word 6 (HPD Word 6) .............................. 35-20.... HC Current Control Register (HCCONTROLCURRENTED) Field Descriptions ............... 35-7................ 1574 HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions ........... 35-16..... HC Low-Speed Threshold Register (HCLSTHRESHOLD) Field Descriptions ............................................................................................................ HC Root Hub Status Register (HCRHSTATUS) Field Descriptions .............. 34-6...........................com 33-32.... Host Buffer Descriptor Word 6 (HBD Word 6) ................................ 35-3....................... 1570 HC Operating Mode Register (HCCONTROL) Field Descriptions ....................................... HC Head Control Register (HCCONTROLHEADED) Field Descriptions ...................... 35-8......... HC Root Hub B Register (HCRHDESCRIPTORB) Field Descriptions .... 1562 34-1....... 1575 HC HCAA Address Register (HCHCCA) Field Descriptions ..........................1 Host Controller Registers .... Host Buffer Descriptor Word 0 (HBD Word 0) ................................................... 35-1...............................................www.......................................... Host Buffer Descriptor Word 1 (HBD Word 1) ............ 34-24........................................... 35-2........... PERI_TXCSR Register Bit Configuration for Bulk IN Transactions.... 35-17.......... HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions............ Copyright © 2011....................................................... 34-9..................................................................................................... 35-10................ HC Frame Remaining Register (HCFMREMAINING) Field Descriptions ..................... 35-19....... 34-2..................... 35-15.......... Host Buffer Descriptor Word 3 (HBD Word 3) .... 34-23........................ Host Buffer Descriptor Word 2 (HBD Word 2) ............... USB1........ 35-9................. 34-7...................................................... 1561 33-33............................... 34-3..................ti....................................................... 35-12............... PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions ....... uPP DMA Channel Q Status 0 Register (UPQS0) Field Descriptions .......................... 1573 HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions ........................................... 35-14.... USB Terminal Functions ........ 1572 HC Interrupt and Status Register (HCINTERRUPTSTATUS) Field Descriptions ...................... Host Buffer Descriptor Word 4 (HBD Word 4) .............................................................................. 1577 34-11................... 34-5.......................... 35-22................................................................................. uPP DMA Channel Q Status 1 Register (UPQS1) Field Descriptions ................................................ Texas Instruments Incorporated 1581 1581 1582 1583 1584 1585 1587 1592 1592 1593 1608 1609 1611 1613 1634 1634 1635 1635 1635 1635 1636 1636 1637 1637 1637 1637 1638 1638 1638 List of Tables SPRUH77A – December 2011 Submit Documentation Feedback .......................... 34-8. 35-21......... 1561 33-34.......................... Host Packet Descriptor Word 0 (HPD Word 0) .... 1576 34-10............................ Host Packet Descriptor Word 1 (HPD Word 1) ......... HC Frame Number Register (HCFMNUMBER) Field Descriptions .......... uPP DMA Channel Q Status 2 Register (UPQS2) Field Descriptions ..... 1580 34-18..................... 1579 34-16................. 1577 34-12.................................................... 1580 34-17..... HC Head Done Register (HCDONEHEAD) Field Descriptions .............................................................. Host Buffer Descriptor Word 5 (HBD Word 5) ... 35-4................. Host Packet Descriptor Word 3 (HPD Word 3) ....... 1576 HC Current Periodic Register (HCPERIODCURRENTED) Field Descriptions ..................................... Host Packet Descriptor Word 2 (HPD Word 2) ....................... 35-5.............................. 35-13....... HC Root Hub A Register (HCRHDESCRIPTORA) Field Descriptions ................................. 1578 34-14........................ 34-20................... HC Head Bulk Register (HCBULKHEADED) Field Descriptions ....... PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions ... 34-21......... HC Current Bulk Register (HCBULKCURRENTED) Field Descriptions....................................

.............................................................. Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions ..................... Frame Number Register (FRAME) Field Descriptions...................... Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions ...................... Generic RNDIS EP1 Size Register (GENRNDISSZ1) Field Descriptions ................. 35-39........................................... 35-57. Host Buffer Descriptor Word 7 (HBD Word 7) .......................... USB Interrupt Source Clear Register (INTCLRR) Field Descriptions ................ 1678 35-35............ti.......... 35-68.......................................................................................... 35-52........ Texas Instruments Incorporated 1679 1681 1682 1682 1683 1684 1685 1686 1687 1688 1689 1690 1690 1691 1691 1692 1692 1693 1694 1695 1696 1696 1697 1698 1698 1699 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1708 77 SPRUH77A – December 2011 Submit Documentation Feedback ........................................ 1677 35-32.... Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions ............ 35-62...... 35-38.... Auto Request Register (AUTOREQ) Field Descriptions ..... 1654 35-28............................. 35-58................. Teardown Descriptor Words 1-7... Status Register (STATR) Field Descriptions .......... 35-64..................... Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions ......... 1657 35-30........ Revision Identification Register (REVID) Field Descriptions .... Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) Field Descriptions ........................ 1640 35-27........................................................ Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions ............................................................................... 35-36.............. Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)Field Descriptions ................ 1638 35-24................. Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions ............... Index Register for Selecting the Endpoint Status and Control Registers (INDEX)Field Descriptions .... Control Register (CTRLR) Field Descriptions. Generic RNDIS EP4 Size Register (GENRNDISSZ4) Field Descriptions ............................... 35-53........ Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) Field Descriptions .................................... 1639 35-25....... 35-47...................... USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions ............................ 1654 35-29..... Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Field Descriptions ...... USB Interrupt Source Set Register (INTSETR) Field Descriptions .............. 35-55........................... USB Interrupt Conditions ............. 35-54............. 35-69...... Count 0 Register (COUNT0) Field Descriptions ............ 35-50... 1639 35-26........ 35-42................. USB Interrupts ............................................. 35-44............ Universal Serial Bus OTG (USB0) Registers ............................................. 1677 35-33........ 35-59......................................................... Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Field Descriptions ............................................................ SRP Fix Time Register (SRPFIXTIME) Field Descriptions .......................................................... 35-46.... Power Management Register (POWER) Field Descriptions .. Teardown Register (TEARDOWN) Field Descriptions .............. Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions ................. 35-49...........0 Test Modes (TESTMODE) Field Descriptions ....... 35-41.......... 35-63...................... Emulation Register (EMUR) Field Descriptions ....................................... Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions ..... Teardown Descriptor Word 0 .................. Function Address Register (FADDR) Field Descriptions ........................................................ 35-56................................................................. USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions ............. 1670 35-31................ 35-61.................................... List of Tables Copyright © 2011............................. 35-70........... 1678 35-34........................................... Allocation of Queues ............................................................................................www........... 35-60................. Register to Enable the USB 2................................. USB Interrupt Source Register (INTSRCR) Field Descriptions ........... 35-66......................... Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions ........ 35-43..................................................... 35-40........ USB End of Interrupt Register (EOIR) Field Descriptions................................................................ ............. 35-71................................. Interrupts Generated by the USB Controller ............... USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions ......... Receive Count Register (RXCOUNT) Field Descriptions .............................................................. 35-45......com 35-23............................ 35-51............................... 35-67............................ Generic RNDIS EP3 Size Register (GENRNDISSZ3) Field Descriptions ............................................................... Mode Register (MODE) Field Descriptions 35-37.. 35-65........................................................... USB Interrupt Mask Register (INTMSKR) Field Descriptions ........ Generic RNDIS EP2 Size Register (GENRNDISSZ2) Field Descriptions ................ 35-48.......................................

............... 35-109........ CDMA Scheduler Table Word n Registers (WORD[n]) Field Descriptions ..................... 35-79...................................... 1709 35-74.................. 35-107.. Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) Field Descriptions........... 35-81....... 35-114.....www....................... 35-88............. Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions .. 35-76...... Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) Field Descriptions ... Queue Manager Queue Pending Register 0 (PEND0) Field Descriptions .............................................................. CDMA Scheduler Control Register (DMA_SCHED_CTRL) Field Descriptions ...... Hardware Version Register (HWVERS) Field Descriptions .............................................. Queue Manager Queue Pending Register 1 (PEND1) Field Descriptions . Configuration Data Register (CONFIGDATA) Field Descriptions .... Transmit Hub Address (TXHUBADDR) Field Descriptions .................com 35-72....................................... Device Control Register (DEVCTL) Field Descriptions ....................... Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions ...... 35-103............................................. CDMA Emulation Control Register (DMAEMU) Field Descriptions .......................... 35-92....... 35-99... .......... Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) Field Descriptions .......ti. 35-86...... 1710 35-75................. Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) Field Descriptions ........... 35-78......... CDMA Revision Identification Register (DMAREVID) Field Descriptions .......... 35-87..... Transmit Hub Port (TXHUBPORT) Field Descriptions .......................................... 35-106. 1710 ....... Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions....... Queue Manager Queue Diversion Register (DIVERSION) Field Descriptions ............ 35-89.. Receive Type Register (Host mode only) (HOST_RXTYPE) Field Descriptions 35-77....................... Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) Field Descriptions ......... 35-108......................... Texas Instruments Incorporated 1711 1712 1713 1714 1714 1715 1715 1716 1716 1717 1717 1718 1718 1719 1720 1720 1720 1721 1721 1721 1722 1722 1723 1723 1724 1725 1726 1727 1727 1729 1729 1730 1731 1732 1733 1733 1734 1734 1735 1735 1736 1737 1738 1739 1739 SPRUH77A – December 2011 Submit Documentation Feedback ............................................... Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) Field Descriptions ........... Type Register (Host mode only) (HOST_TYPE0) Field Descriptions ......... 35-118. 35-105....................................... 35-116........ Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) Field Descriptions ...... Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions.................. Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) Field Descriptions ............................... Queue Manager Queue N Status Register B (QSTATB[N]) Field Descriptions ........................................................................... Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions ........................................... 35-120....................... Queue Manager Queue N Control Register D (CTRLD[N]) Field Descriptions ... 35-111....... 35-94........................................... NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) Field Descriptions .. Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) Field Descriptions........... Receive Hub Address (RXHUBADDR) Field Descriptions .. 35-98... Receive Hub Port (RXHUBPORT) Field Descriptions ..... Queue Manager Queue N Status Register A (QSTATA[N]) Field Descriptions .............. 35-112.. 35-100....................................... 35-110... 1709 35-73. 35-96...... 35-117........... Receive Function Address (RXFUNCADDR) Field Descriptions...... 35-91.. 35-80................. 35-83................... Transmit Function Address (TXFUNCADDR) Field Descriptions ....................................... Queue Manager Revision Identification Register (QMGRREVID) Field Descriptions. 35-104.................. 35-101..... 35-113...... Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions............ Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) Field Descriptions ........... 35-97.............................................................. CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) Field Descriptions ....................... Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions 78 List of Tables Copyright © 2011................................ 35-115.................. Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) Field Descriptions .. Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) Field Descriptions ......... Transmit Type Register (Host mode only) (HOST_TXTYPE) Field Descriptions .. Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Field Descriptions.. CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) Field Descriptions ....... 35-93....... 35-85........ 35-95.. 35-119............................... 35-84............. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions..... CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) Field Descriptions.............................. 35-90.................. 35-102........... Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions .................. 35-82...............

... Channel n Vertical Size Configuration 2 Register (CnVCFG2) Field Descriptions .............. Channel n Bottom Field Horizontal Ancillary Address Register (CnBHANC) Field Descriptions ........ 36-22................ 36-4..................................... 36-35...................... Emulation Suspend Control Register (EMUCTRL) Field Descriptions .......... DMA Size Control Register (REQSIZE) Field Descriptions .... 36-43.. Channel n Top Field Horizontal Ancillary Position Register (CnTHANCPOS) Field Descriptions .............. 1746 Register Configuration on BT................ Channel 2 Control Register (C2CTRL) Field Descriptions ..... 36-26........ 1777 36-16..................................... Channel n Vertical Size Configuration 1 Register (CnVCFG1) Field Descriptions ..... Channel 0 Control Register (C0CTRL) Field Descriptions .......... Channel n Top Field Horizontal Ancillary Address Register (CnTHANC) Field Descriptions ..................... Channel n Vertical Size Configuration 2 Register (CnVCFG2) Field Descriptions . .............................................. Channel n Bottom Field Luminance Address Register (CnBLUMA) Field Descriptions ............................................. 1767 36-10. 1745 Receive Pin Multiplexing Control ........ 36-2.............. 1786 36-30............ 1788 ................................ 36-25............................... 1764 Register Configuration on SMPTE 296M Input/Output (Unit Size = Byte in unsigned) . Channel n Bottom Field Vertical Ancillary Data Buffer Start Address Register (CnBVANC) Field Descriptions .......... 36-5................................................................................................ 36-23.................................. Channel n Vertical Image Size Register (CnVSIZE) Field Descriptions ................................................... Channel n Horizontal Size Configuration Register (CnHCFG) Field Descriptions ... 36-20.....................ti..................... 1773 36-14...............656 Input/Output (Unit Size = Byte in unsigned) .... Interrupt Status Register (INTSTAT) Field Descriptions ............... Channel 1 Control Register (C1CTRL) Field Descriptions ...... VPIF Revision ID Register (REVID) Field Descriptions ................... Channel n Image Address Offset Register (CnIMGOFFSET) Field Descriptions .................. Interrupt Status Clear Register (INTSTATCLR) Field Descriptions ............ Channel n Horizontal Size Configuration Register (CnHCFG) Field Descriptions ..... 1770 36-11.................................. 36-41......................... 1778 1779 1780 1781 1782 1782 1783 1783 1784 1784 1785 1785 1786 36-29............... 36-9........ 36-44........ Interrupt Enable Register (INTEN) Field Descriptions ...... 36-8........... Supported Formats on VPIF ..... List of Tables Copyright © 2011.... Channel 3 Control Register (C3CTRL) Field Descriptions ........................................................... Channel n Top Field Luminance Address Register (CnTLUMA) Field Descriptions ......................... 1772 36-13..................................................................................... 36-45............. 36-27................................................................................................................. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback ........................... 36-38.................... 1740 36-1..www..................... 36-19..... 36-21............ 1787 36-31........ 36-7. Channel n Top Field Vertical Ancillary Position Register (CnTVANCPOS) Field Descriptions ............. 36-40.................... 36-46............................ Channel n Vertical Image Size Register (CnVSIZE) Field Descriptions ..................................................... 1766 Video Port Interface (VPIF) Registers ................................................. 36-3.. 36-24................... 36-37... Channel n Top Field Horizontal Ancillary Size Register (CnTHANCSIZE) Field Descriptions ........................................................... Interrupt Enable Set Register (INTSET) Field Descriptions 36-17............... Queue Manager Queue N Status Register C (QSTATC[N]) Field Descriptions .................. Channel n Bottom Field Chrominance Address Register (CnBCHROMA) Field Descriptions ............... 1762 Register Configuration on BT..........1120 (1125/60/2:1 and 1250/50/2:1 System) Input/Output (Unit Size = Byte in unsigned) .......1120 (1080-30p System) Input/Output (Unit Size = Byte in unsigned) ....... .......... 36-18................. Channel n Bottom Field Horizontal Ancillary Position Register (CnBHANCPOS) Field Descriptions ................. 36-28....................... Channel n Vertical Size Configuration 0 Register (CnVCFG0) Field Descriptions ............................................................ Interrupt Enable Clear Register (INTCLR) Field Descriptions ................. Channel n Top Field Vertical Ancillary Address Register (CnTVANC) Field Descriptions ... Channel n Top Field Chrominance Address Register (CnTCHROMA) Field Descriptions ..... 1764 Register Configuration on BT.............. Channel n Vertical Size Configuration 1 Register (CnVCFG1) Field Descriptions .......................................... 1770 36-12............... Channel n Horizontal Ancillary Address Offset Register (CnHANCOFFSET) Field Descriptions 36-33...................................... 36-36....... 1745 Input and Output Usage Combinations on VPIF ......................... 1775 36-15................ 36-39. Channel n Vertical Size Configuration 0 Register (CnVCFG0) Field Descriptions 36-34.................. Channel n Bottom Field Horizontal Ancillary Size Register (CnBHANCSIZE) Field Descriptions ................. 36-6........ 1787 1789 1789 1790 1790 1791 1792 1792 1793 1793 1794 1795 1796 1797 1798 79 36-32. 36-42.. 1746 Transmit Pin Multiplexing Control ...........com 35-121........

...................www.... Document Revision History ... 1803 80 List of Tables Copyright © 2011... 1801 A-1...................... 1800 36-49. Channel n Bottom Field Vertical Ancillary Position Register (CnBVANCPOS) Field Descriptions ................... 1799 36-48.. Channel n Bottom Field Vertical Ancillary Size Register (CnBVANCSIZE) Field Descriptions .......... Channel n Top Field Vertical Ancillary Size Register (CnTVANCSIZE) Field Descriptions ........com 36-47........................ Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .........ti.................

Each field is labeled with its bit name. SD is a trademark of SanDisk Corporation. Explains the fundamentals of memory caches and describes how the two-level cache-based internal memory architecture in the TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications. SPI is a trademark of Motorola. the following number is 40 hexadecimal (decimal 64): 40h. – Reserved bits in a register figure designate a bit that is used for future device expansion. The internal memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level.com/c6000. Describes the TMS320C674x digital signal processor (DSP) megamodule. instruction set.com. Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls. For example.ti. bandwidth management. SPRUG82— TMS320C674x DSP Cache User's Guide. memory protection. SPRUFE8— TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture. Shows how to maintain coherence with external memory. Related Documentation From Texas Instruments Copies of these documents are available on the Internet at www. and interrupts for the TMS320C674x digital signal processors (DSPs). and its read/write properties below. If the data requested by the CPU is not contained in cache.ti. the power-down controller. The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added functionality and an expanded instruction set. how to use DMA to reduce memory latencies. The SoC consists of the following primary components: • ARM subsystem and associated memories • DSP subsystem and associated memories • A set of I/O peripherals Notational Conventions This document uses the following conventions. pipeline.Preface SPRUH77A – December 2011 Read This First About This Manual This Technical Reference Manual (TRM) describes the System-on-Chip (SoC) and each peripheral in the device. and how to optimize your code to improve cache efficiency. Included is a discussion on the internal direct memory access (IDMA) controller. is available in the C6000 DSP product folder at: www.com. The current documentation that describes related peripherals and other technical collateral. Code Composer Studio is a trademark of Texas Instruments.ti. Inc. Tip: Enter the literature number in the search box provided at www. its beginning and ending bit numbers above. it is fetched from the next lower memory level. ARM926EJ-S. and the memory and cache.. Jazelle are trademarks of ARM Limited. Texas Instruments Incorporated 81 . L2 or external memory. SPRUH77A – December 2011 Submit Documentation Feedback Read This First Copyright © 2011. • Hexadecimal numbers are shown with the suffix h. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the register. SPRUFK5— TMS320C674x DSP Megamodule Reference Guide. A legend explains the notation used for the properties. the interrupt controller.

Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .82 Read This First Copyright © 2011.

...................................... DSP Subsystem .........5 84 84 84 84 85 SPRUH77A – December 2011 Submit Documentation Feedback Overview Copyright © 2011...................................................................................... ARM Subsystem ................................................................2 1......................................................................3 1...............................................................1 1................................................................. Page 1.............................................................................. Texas Instruments Incorporated 83 ...............4 1...............................Chapter 1 SPRUH77A – December 2011 Overview Topic ....................... DMA Subsystem ........................ Introduction ... Block Diagram .................................................

The OMAP-L138 Applications Processor consists of the following primary components: • ARM subsystem and associated memories • DSP subsystem and associated memories • A set of I/O peripherals • A powerful DMA subsystem and SDRAM EMIF interface 1. and a powerful DSP to efficiently handle communication and audio processing tasks.4 ARM Subsystem The ARM926EJ-S™ 32-bit RISC CPU in the ARM subsystem (ARMSS) acts as the overall system controller. Figure 1-1. OMAP-L138 Applications Processor Block Diagram JTAG Interface System Control Input Clock(s) PLL/Clock Generator w/OSC GeneralPurpose Timer (x3) RTC/ 32-kHz OSC ARM926EJ-S CPU With MMU 4KB ETB 16KB 16KB I-Cache D-Cache 8KB RAM (Vector Table) 64KB ROM C674x™ DSP CPU AET 32KB L1 Pgm 32KB L1 RAM ARM Subsystem DSP Subsystem Power/Sleep Controller Pin Multiplexing 256KB L2 RAM 1024KB L2 ROM Switched Central Resource (SCR) Peripherals DMA Audio Ports Serial Interfaces Display Video Parallel Port Shared Memory Customizable Interface EDMA3 (x2) McASP w/FIFO McBSP (x2) I2C (x2) SPI (x2) UART (x3) LCD Ctlr VPIF uPP 128KB RAM PRU Subsystem Control Timers Connectivity External Memory Interfaces eHRPWM (x2) eCAP (x3) USB2. L1D.ti. 84 Overview Copyright © 2011. power management.Introduction www. The DSP Subsystem chapter describes the DSPSS components.3 DSP Subsystem The DSP subsystem (DSPSS) includes TI’s standard TMS320C674x megamodule and several blocks of internal memory (L1P. configuration. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .1 Introduction The OMAP-L138 Applications Processor contains two primary CPU cores: an ARM RISC CPU for general-purpose processing and systems control. The ARM Subsystem chapter describes the ARMSS components and system control functions that the ARM core performs. and L2). 1.0 OTG Ctlr PHY USB1. and user command implementation. 1. such as system initialization.2 Block Diagram A block diagram for the OMAP-L138 Applications Processor is shown in Figure 1-1. The ARM CPU performs general system control tasks.1 OHCI Ctlr PHY EMAC 10/100 MDIO (MII/RMII) HPI MMC/SD (8b) (x2) SATA EMIFA(8b/16B) NAND/Flash 16b SDRAM DDR2/mDDR Memory Controller Note: Not all peripherals are available at the same time due to multiplexing.com 1. user interface.

5 DMA Subsystem The DMA subsystem includes two instances of the enhanced DMA controller (EDMA3).ti. For more information.www.com DMA Subsystem 1. see the Enhanced Direct Memory Access (EDMA3) Controller chapter. Texas Instruments Incorporated 85 . SPRUH77A – December 2011 Submit Documentation Feedback Overview Copyright © 2011.

86 Overview Copyright © 2011. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

.. Processor Status Registers .................5 2...... Operating States/Modes ...........................................6 2................................................ 16-BIS/32-BIS Advantages .............................................................3 2.......................................................................................................................................4 2......... Page 2......7 88 89 89 90 91 91 92 SPRUH77A – December 2011 Submit Documentation Feedback ARM Subsystem Copyright © 2011......1 2...Chapter 2 SPRUH77A – December 2011 ARM Subsystem Topic ...... Texas Instruments Incorporated 87 ...................................................................................................................................... Exceptions and Exception Vectors .....2 2..................... Co-Processor 15 (CP15) ...................................................................................................... The 16-BIS/32-BIS Concept .................................................................................................. Introduction ...............

ti. The RAM/ROM locations are not accessible by the DSP or any other master peripherals. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debugging. etc. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem. The ARM926EJ-S processor targets multi-tasking applications where full memory management. The ARM subsystem consists of the following components: • ARM926EJ-S™ 32-bit RISC CPU • 16-KB Instruction cache • 16-KB Data cache • Memory Management Unit (MMU) • Co-Processor 15 (CP15) to control MMU. enabling you to trade off between high performance and high code density. the ARM has DMA and CFG bus master ports via the AHB interface. high performance. including the following: • An ARM926EJ-S integer core • A Memory Management Unit (MMU) • Separate instruction and data Advanced Microcontroller Bus Architecture (AHBA) Advanced High Performance Bus (AHB) bus interfaces NOTE: There is no TCM memory and interface on this device. low die size. and low power are all important. This includes features for efficient execution of Java byte codes and providing Java performance similar to Just in Time (JIT) Java interpreter without associated code overhead.Introduction www. The ARM926EJ-S core includes NEON signal processing extensions to enhance 16-bit fixed-point performance using a single-cycle 32 × 16 multiply-accumulate (MAC) unit.com 2.1 Introduction This chapter describes the ARM subsystem and its associated memories. Furthermore. The ARM926EJ-S processor implements ARM architecture version 5TEJ. cache. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . 88 ARM Subsystem Copyright © 2011. • Jazelle™ Java Accelerator • ARM Internal Memory – 8 KB RAM – 64 KB built-in ROM • Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) • Features: – The main write buffer has a 16-word data buffer and a 4-address buffer – Support for 32-bit ARM/16-bit THUMB instruction sets – Fixed little-endian memory format – Enhanced DSP instructions The ARM926EJ-S processor is a member of the ARM9 family of general-purpose microprocessors. The ARM core also has 8 KB RAM (typically used for vector table) and 64 KB ROM (for boot images) associated with it. The ARM926EJ-S processor supports the 32-bit ARM and the 16-bit THUMB instruction sets.

F bit: Disable FIQ (F = 1) or enable FIQ (F = 0) • Bit 5 . The 8 least-significant bits PSR[7:0] are the control bits of the processor.2 Operating States/Modes The ARM can operate in two states: ARM (32-bit) mode and THUMB (16-bit) mode. You can only enter privileged modes (system or supervisor) from other privileged modes. To enter supervisor mode from user mode.N bit: Negative or less than • Bit 30 . PSR[27:8] are reserved bits and PSR[31:28] are status registers. Different stacks must be set up for different modes. usually for the execution of most application programs.T bit: Controls whether the processor is in thumb mode (T = 1) or ARM mode (T = 0) • Bits 4:0 Mode: Controls the mode of operation of the processor – PSR [4:0] = 10000 : User mode – PSR [4:0] = 10001 : FIQ mode – PSR [4:0] = 10010 : IRQ mode – PSR [4:0] = 10011 : Supervisor mode – PSR [4:0] = 10111 : Abort mode – PSR [4:0] = 11011 : Undefined mode – PSR [4:0] = 11111 : System mode Status bits show the result of the most recent ALU operation.com Operating States/Modes 2. downloadable from http://infocenter. The ARM can operate in the following modes: • User mode (USR): Non-privileged mode.www. • Fast interrupt mode (FIQ): Fast interrupt processing • Interrupt mode (IRQ): Normal interrupt processing • Supervisor mode (SVC): Protected mode of execution for operating systems • Abort mode (ABT): Mode of execution after a data abort or a pre-fetch abort • System mode (SYS): Privileged mode of execution for operating systems • Undefined mode (UND): Executing an undefined instruction causes the ARM to enter undefined mode.V bit: Overflow or underflow NOTE: See the Programmer’s Model of the ARM926EJ-S Technical Reference Manual (TRM). The details of status bits are: • Bit 31 .I bit: Disable IRQ (I =1) or enable IRQ (I = 0) • Bit 6 .ti. An IRQ interrupt causes the processor to enter the IRQ mode. The details of the control bits are: • Bit 7 . 2. You can switch the ARM926EJ-S processor between ARM mode and THUMB mode using the BX instruction.C bit: Carry or borrow • Bit 28 . SPRUH77A – December 2011 Submit Documentation Feedback ARM Subsystem Copyright © 2011.3 Processor Status Registers The processor status register (PSR) controls the enabling and disabling of interrupts and setting the mode of operation of the processor.jsp for more detailed information. The stack pointer (SP) automatically changes to the SP of the mode that was entered.arm. An FIQ interrupt causes the processor to enter the FIQ mode.com/help/index.Z bit: Zero • Bit 29 . generate a software interrupt (SWI). Texas Instruments Incorporated 89 .

The ARM is configured with the VINITHI signal set high (VINITHI = 1). This address maps to the beginning of the ARM local RAM (8 KB). pre-fetch abort. undefined instruction. data abort. it is not recommended to set VINITHI = 0. Table 2-1. Exception Vector Table for ARM Vector Offset Address 0h 4h 8h Ch 10h 14h 18h 1Ch Exception Reset Undefined instruction Software interrupt Pre-fetch abort Data abort Reserved IRQ FIQ Mode on entry Supervisor Undefined Supervisor Abort Abort — IRQ FIQ I Bit State on Entry Set Set Set Set Set — Set Set F Bit State on Entry Set Unchanged Unchanged Unchanged Unchanged — Unchanged Set 90 ARM Subsystem Copyright © 2011. as the device has no physical memory in the 0000 0000h address region.ti. SWI and undefined instruction have the same priority. The abort could be a pre-fetch abort or a data abort. • SWI interrupt: use software interrupt to enter supervisor mode. The default vector table is shown in Table 2-1. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . However. FIQ.4 Exceptions and Exception Vectors Exceptions arise when the normal flow of the program must be temporarily halted. such that the vector table is located at address FFFF 0000h. The exceptions that occur in an ARM system are given below: • Reset exception: processor reset • FIQ interrupt: fast interrupt • IRQ interrupt: normal interrupt • Abort exception: abort indicates that the current memory access could not be completed.com 2. NOTE: The VINITHI signal is configurable by way of the register setting in CP15. and SWI. • Undefined exception: occurs when the processor executes an undefined instruction The exceptions in the order of highest priority to lowest priority are: reset.Exceptions and Exception Vectors www. IRQ.

The advantage is the ability to switch back to full 32-bit code and execute at full speed. not all of the code in a program processes 32-bit data (for example.ti. and has better than one half of the performance of the 32-bit architecture. code that performs character string handling). a 16-bit architecture takes at least two instructions to perform the same task as a single 32-bit instruction. The 16-bit instruction breaks this constraint by implementing a 16-bit instruction length on a 32-bit architecture. The overhead of switching from 16-bit code to 32-bit code is folded into sub-routine entry time. The major advantage of a 32-bit architecture over a 16-bit architecture is its ability to manipulate 32-bit integers with single instructions. SPRUH77A – December 2011 Submit Documentation Feedback ARM Subsystem Copyright © 2011. However. Various portions of a system can be optimized for speed or for code density by switching between 16-BIS and 32-BIS execution. then the 16-bit architecture has better code density overall.com The 16-BIS/32-BIS Concept 2. critical loops for applications such as fast interrupts and DSP algorithms can be coded using the full 32-BIS and linked with 16-BIS code.6 16-BIS/32-BIS Advantages 16-bit instructions operate with the standard 32-bit register configuration. and to address a large address space efficiently. If a 16-bit architecture only has 16-bit instructions. and a 32-bit architecture only has 32-bit instructions. Each 16-bit instruction has a corresponding 32-bit instruction with the same effect on the processor model. Clearly. with better code density than a 32-bit architecture. making the processing of 32-bit data efficient with compact instruction coding.5 The 16-BIS/32-BIS Concept The key idea behind 16-BIS is that of a super-reduced instruction set. Texas Instruments Incorporated 91 . The 16-BIS also has a major advantage over other 32-bit architectures with 16-bit instructions. as appropriate. This provides far better performance than a 16-bit architecture. Essentially. This is possible because 16-BIS code operates on the same 32-bit register set as 32-BIS code. Thus.www. When processing 32-bit data. 16-bit code can provide up to 65% of the code size of the 32-bit code and 160% of the performance of an equivalent 32-BIS processor connected to a 16-bit memory system. 32-bit performance comes at the cost of code density. 2. and some instructions (like branches) do not process any data at all. the ARM926EJ processor has two instruction sets: • ARM mode or 32-BIS: the standard 32-bit instruction set • THUMB mode or 16-BIS: a 16-bit instruction set The 16-bit instruction length (16-BIS) allows the 16-BIS to approach twice the density of standard 32-BIS code while retaining most of the 32-BIS’s performance advantage over a traditional 16-bit processor using 16-bit registers. allowing excellent inter-operability between 32-BIS and 16-BIS states.

jsp for more detailed information. then the MMU translates the MVA to produce the PA. the instruction data is returned to the ARM9EJ-S core. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Tightly-Coupled Memories (TCMs). downloadable from http://infocenter. 2.Co-Processor 15 (CP15) www. using CP15 register 8 • Invalidate TLB entry. Different Address Types in ARM System Domain Address type ARM9EJ-S Virtual Address (VA) Caches and MMU Modified Virtual Address (MVA) TCM and AMBA Bus Physical Address (PA) An example of the address manipulation that occurs when the ARM9EJ-S core requests an instruction is shown in Example 2-1 Example 2-1. and access protection scheme. 92 ARM Subsystem Copyright © 2011. using CP15 register 8 • Lockdown of TLB entries. using CP15 register 10 NOTE: See the Memory Management Unit of the ARM926EJ-S Technical Reference Manual (TRM). and memory region attributes for both data and instruction accesses. Memory Management Units (MMUs). selected by MVA. NOTE: See the Programmers Model of the ARM926EJ-S Technical Reference Manual (TRM). The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables.com/help/index.7 Co-Processor 15 (CP15) The system control coprocessor (CP15) is used to configure and control instruction and data caches. Table 2-2. If the protection check carried out by the MMU on the MVA does not abort and the MVA tag is in the Icache.com/help/index. domains.1 Addresses in an ARM926EJ-S System Three different types of addresses exist in an ARM926EJ-S system. and many system functions.jsp for more detailed information.ti. If the protection check carried out by the MMU on the MVA does not abort. 2. permission checks.arm. WindowsCE.7. The VA is translated to the MVA. and the MVA tag is not in the cache. Address Manipulation The VA of the instruction is issued by the ARM9EJ-S core. 4 KB (small pages) and 1 KB (tiny pages) • Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions) • Hardware page table walks • Invalidate entire TLB. and Linux.7.com 2.2 Memory Management Unit (MMU) The ARM926EJ-S MMU provides virtual memory features required by operating systems such as SymbianOS. They are listed in Table 2-2.arm. 64 KB (large pages). downloadable from http://infocenter. The CP15 registers are only accessible with MRC and MCR instructions by the ARM in a privileged mode like supervisor mode or system mode. The Instruction Cache (Icache) and Memory Management Unit (MMU) detect the MVA. • Mapping sizes are 1 MB (sections). The MMU features are as follows: • Standard ARM architecture v4 and v5 MMU mapping sizes. A single set of two level page tables stored in main memory controls the address translation.

com/help/index. addressed using the Modified Virtual Address (MVA) • Four-way set associative. The MCR drain write buffer enables both write buffers to be drained under software control. • Cache maintenance operations to provide efficient invalidation of the following: – The entire Dcache or Icache – Regions of the Dcache or Icache – The entire Dcache – Regions of virtual memory • They also provide operations for efficient cleaning and invalidation of the following: – The entire Dcache – Regions of the Dcache – Regions of virtual memory The write buffer is used for all writes to a non-cachable bufferable region. Texas Instruments Incorporated 93 . removing the possibility of TLB misses related to the write-back address. instruction cache is 16 KB. The Dcache write-back has eight data word entries and a single address entry. selected by memory region using the C and B bits in the MMU translation tables • Perform critical-word first cache refilling • Cache lockdown registers enable control over which cache ways are used for allocation on a line fill. • Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAGRAM for use during the cache line write-backs. with a cache line length of eight words per line (32 bytes per line).ti. The caches have the following features: • Virtual index. write-through region. and write misses to a write-back region. The MCR wait for interrupt causes both write buffers to be drained and the ARM926EJ-S processor to be put into a low power state until an interrupt occurs. providing a mechanism for both lockdown and controlling cache pollution. in addition to the Virtual Address TAG stored in the TAG RAM. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. downloadable from http://infocenter.jsp for more detailed information. NOTE: See the Caches and Write Buffer of the ARM926EJ-S Technical Reference Manual (TRM). and two dirty bits in the Dcache • Dcache supports write-through and write-back (or copy back) cache operation.www. virtual tag.com Co-Processor 15 (CP15) 2. and write buffer is 17 bytes. SPRUH77A – December 2011 Submit Documentation Feedback ARM Subsystem Copyright © 2011. This means that the MMU is not involved in Dcache write-back operations.3 Caches and Write Buffer The ARM926EJ-S processor includes: • An Instruction cache (Icache) • A Data cache (Dcache) • A write buffer The size of the data cache is 16 KB.arm. The main write buffer has a 16-word data buffer and a four-address buffer.7.

94 ARM Subsystem Copyright © 2011. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

.............3 3... 97 Memory Map ......................Chapter 3 SPRUH77A – December 2011 DSP Subsystem Topic . 102 Advanced Event Triggering (AET) ............................... Texas Instruments Incorporated 95 .................................................................................. 102 SPRUH77A – December 2011 Submit Documentation Feedback DSP Subsystem Copyright © 2011....................2 3........................1 3.....................................................................................................................4 Introduction .............................................................................................. 96 TMS320C674x Megamodule ....................................... Page 3..................................

Introduction www.ti. the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8). This chapter provides an overview of the DSP subsystem and the following considerations associated with it: • Memory mapping • Interrupts • Power management For more information on the TMS320C674x megamodule. TMS320C674x Megamodule Block Diagram 32K bytes L1P RAM/ cache 256 256 Cache control Memory protect Bandwidth Mgmt 256 Instruction fetch C674x Fixed/floating point CPU Register file A 64 Bandwidth Mgmt Memory protect Cache control Register file B 64 L1P 256K bytes L2 RAM 256 1M bytes L2 ROM 256 Cache control Memory protect Bandwidth Mgmt 256 256 L2 256 Power down Interrupt Controller IDMA 256 Port 32 Configuration peripherals bus L1D EMC MDMA Port 64 64 SDMA Port 64 64 8x32 32K bytes L1D RAM/ cache High performance switch fabric 96 DSP Subsystem Copyright © 2011. and L2).com 3. Figure 3-1. see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5). and the TMS320C674x DSP Cache User’s Guide (SPRUG82). Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . L1D.1 Introduction The DSP subsystem (Figure 3-1) includes TI’s standard TMS320C674x megamodule and several blocks of internal memory (L1P.

com TMS320C674x Megamodule 3. 3. Level 2 memory (L2) can also be split into L2 RAM (normal addressable on-chip memory) and L2 cache for caching external memory locations. BWM.www. 3.2 Internal Peripherals The C674x megamodule includes the following internal peripherals: • DSP interrupt controller (INTC) • DSP power-down controller (PDC) • Bandwidth manager (BWM) • Internal DMA (IDMA) controller This section briefly describes the INTC. All DSP device events are listed in Table 3-1. For more information on these internal peripherals. PDC. Level 1 memory (L1) is split into separate program memory (L1P memory) and data memory (L1D memory). and IDMA controller.2. For the ARM interrupt controller (AINTC) event mappings.1 Interrupt Controller (INTC) The C674x megamodule includes an interrupt controller (INTC) to manage CPU interrupts. see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5). Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback 97 . L1D.2. see the ARM Interrupt Controller (AINTC) chapter. and L2 memories.2. The interrupt events listed in Table 3-1 are for the DSP interrupt controller (INTC) only. 3.2 TMS320C674x Megamodule The C674x megamodule (Figure 3-1) consists of the following components: • TMS320C674x CPU • Internal memory controllers: – Level 1 program memory controller (PMC) – Level 1 data memory controller (DMC) – Level 2 unified memory controller (UMC) – Extended memory controller (EMC) – Internal direct memory access (IDMA) controller • Internal peripherals: – Interrupt controller (INTC) – Power-down controller (PDC) – Bandwidth manager (BWM) • Advanced event triggering (AET) For more information about each of these controllers. L1 memory is accessible to the CPU without stalls. Table 3-1. see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).1 Internal Memory Controllers The C674x megamodule implements a two-level internal cache-based memory architecture with external memory support. The INTC is fully described in the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).2. DSP Interrupt Map Event 0 1 2 3 Interrupt Name EVT0 EVT1 EVT2 EVT3 Source C674x Interrupt Control 0 C674x Interrupt Control 1 C674x Interrupt Control 2 C674x Interrupt Control 3 DSP Subsystem Copyright © 2011.ti. The INTC maps DSP device events to 12 CPU interrupts. The internal direct memory access controller (IDMA) manages DMA among the L1P.

Core 0 Receive Interrupt EMAC . Texas Instruments Incorporated Interrupt Name T64P0_TINT12 SYSCFG_CHIPINT2 PRU_EVTOUT0 EHRPWM0 EDMA3_0_CC0_INT1 EMU-DTDMA EHRPWM0TZ EMU-RTDXRX EMU-RTDXTX IDMAINT0 IDMAINT1 MMCSD0_INT0 MMCSD0_INT1 PRU_EVTOUT1 EHRPWM1 USB0_INT USB1_HCINT USB1_R/WAKEUP PRU_EVTOUT2 EHRPWM1TZ SATA_INT T64P2_TINTALL EMAC_C0RXTHRESH EMAC_C0RX EMAC_C0TX EMAC_C0MISC EMAC_C1RXTHRESH EMAC_C1RX EMAC_C1TX EMAC_C1MISC UHPI_DSPINT PRU_EVTOUT3 IIC0_INT SPI0_INT UART0_INT PRU_EVTOUT5 T64P1_TINT12 GPIO_B1INT IIC1_INT SPI1_INT PRU_EVTOUT6 ECAP0 UART_INT1 ECAP1 T64P1_TINT34 GPIO_B2INT PRU_EVTOUT7 Source Timer64P0 Interrupt (TINT12) SYSCFG CHIPSIG Register PRUSS Interrupt HiResTimer/PWM0 Interrupt EDMA3_0 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt C674x-ECM HiResTimer/PWM0 Trip Zone Interrupt C674x-RTDX C674x-RTDX C674x-EMC C674x-EMC MMCSD0 MMC/SD Interrupt MMCSD0 SDIO Interrupt PRUSS Interrupt HiResTimer/PWM1 Interrupt USB0 (USB2.ti.1) Remote Wakeup Interrupt PRUSS Interrupt HiResTimer/PWM1 Trip Zone Interrupt SATA Controller Interrupt Timer64P2 Combined Interrupt (TINT12 and TINT34) EMAC .Core 1 Transmit Interrupt EMAC .Core 1 Receive Threshold Interrupt EMAC .Core 1 Receive Interrupt EMAC .com Table 3-1.0) Interrupt USB1 (USB1.Core 0 Transmit Interrupt EMAC .Core 0 Miscellaneous Interrupt EMAC .Core 1 Miscellaneous Interrupt HPI DSP Interrupt PRUSS Interrupt I2C0 Interrupt SPI0 Interrupt UART0 Interrupt PRUSS Interrupt Timer64P1 Interrupt (TINT12) GPIO Bank 1 Interrupt I2C1 Interrupt SPI1 Interrupt PRUSS Interrupt ECAP0 Interrupt UART1 Interrupt ECAP1 Interrupt Timer64P1 Interrupt (TINT34) GPIO Bank 2 Interrupt PRUSS Interrupt SPRUH77A – December 2011 Submit Documentation Feedback .Core 0 Receive Threshold Interrupt EMAC .TMS320C674x Megamodule www. DSP Interrupt Map (continued) Event 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 98 DSP Subsystem Copyright © 2011.1) OHCI Host Controller Interrupt USB1 (USB1.

Compare Interrupt 3 Timer64P2 .Compare Interrupt 7 Timer64P3 Combined Interrupt (TINT12 and TINT34) McBSP0 Receive Interrupt McBSP0 Transmit Interrupt McBSP1 Receive Interrupt McBSP1 Transmit Interrupt EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt EDMA3_1 Channel Controller 0 Error Interrrupt EDMA3_1 Transfer Controller 0 Error Interrrupt uPP Combined Interrupt VPIF Combined Interrupt C674x-Interrupt Control C674x-EMC Reserved DSP Subsystem Copyright © 2011.Compare Interrupt 4 Timer64P2 .Compare Interrupt 0 Timer64P2 .Compare Interrupt 2 Timer64P2 .ti.www.Compare Interrupt 6 Timer64P2 .com TMS320C674x Megamodule Table 3-1. DSP Interrupt Map (continued) Event 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76-77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98-112 Interrupt Name ECAP2 GPIO_B3INT MMCSD1_INT1 GPIO_B4INT EMIFA_INT EDMA3_0_CC0_ERRINT EDMA3_0_TC0_ERRINT EDMA3_0_TC1_ERRINT GPIO_B5INT DDR2_MEMERR MCASP0_INT GPIO_B6INT RTC_IRQS T64P0_TINT34 GPIO_B0INT PRU_EVTOUT4 SYSCFG_CHIPINT3 MMCSD1_INT0 UART2_INT PSC0_ALLINT PSC1_ALLINT GPIO_B7INT LCDC_INT PROTERR GPIO_B8INT — T64P2_CMPINT0 T64P2_CMPINT1 T64P2_CMPINT2 T64P2_CMPINT3 T64P2_CMPINT4 T64P2_CMPINT5 T64P2_CMPINT6 T64P2_CMPINT7 T64P3_TINTALL MCBSP0_RINT MCBSP0_XINT MCBSP1_RINT MCBSP1_XINT EDMA3_1_CC0_INT1 EDMA3_1_CC0_ERRINT EDMA3_1_TC0_ERRINT UPP_INT VPIF_INT INTERR EMC_IDMAERR — Source ECAP2 Interrupt GPIO Bank 3 Interrupt MMCSD1 SDIO Interrupt GPIO Bank 4 Interrupt EMIFA Interrupt EDMA3_0 Channel Controller 0 Error Interrrupt EDMA3_0 Transfer Controller 0 Error Interrrupt EDMA3_0 Transfer Controller 1 Error Interrrupt GPIO Bank 5 Interrupt DDR2 Memory Error Interrupt McASP0 Combined RX/TX Interrupt GPIO Bank 6 Interrupt RTC Combined Interrupt Timer64P0 Interrupt (TINT34) GPIO Bank 0 Interrupt PRUSS Interrupt SYSCFG CHIPSIG Register MMCSD1 MMC/SD Interrupt UART2 Interrupt PSC0 PSC1 GPIO Bank 7 Interrupt LCD Controller Interrupt SYSCFG Protection Shared Interrupt GPIO Bank 8 Interrupt Reserved Timer64P2 . Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback 99 .Compare Interrupt 1 Timer64P2 .Compare Interrupt 5 Timer64P2 .

2. The NMI interrupt is controlled by two registers in the System Configuration Module. see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5). the DSP also supports a special interrupt that behaves more like an exception.ti. DSP Interrupt Map (continued) Event 113 114-115 116 117 118 119 120 121 122 123 124 125 126 127 Interrupt Name PMC_ED — UMC_ED1 UMC_ED2 PDC_INT SYS_CMPA PMC_CMPA PMC_CMPA DMC_CMPA DMC_CMPA UMC_CMPA UMC_CMPA EMC_CMPA EMC_BUSERR Source C674x-PMC Reserved C674x-UMC C674x-UMC C674x-PDC C674x-SYS C674x-PMC C674x-PMC C674x-DMC C674x-DMC C674x-UMC C674x-UMC C674x-EMC C674x-EMC 3.2 NMI Interrupt In addition to the interrupts listed in Table 3-1.2. The PDC can power-down all of the following components of the C674x megamodule and internal memories of the DSP subsystem: • C674x CPU • Level 1 program memory controller (PMC) • Level 1 data memory controller (DMC) • Level 2 unified memory controller (UMC) • Extended memory controller (EMC) • Internal direct memory access (IDMA) controller • L1P memory • L1D memory • L2 memory 100 DSP Subsystem Copyright © 2011.2.TMS320C674x Megamodule www.1 Interrupt Controller Registers For more information on the DSP interrupt controller (INTC) registers.2.1.com Table 3-1. non-maskable interrupt (NMI). see the System Configuration (SYSCFG) Module chapter.1. The NMI interrupt is cleared by writing a 1 to the CHIPSIG4 bit in CHIPSIG_CLR. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .2. The NMI interrupt is asserted by writing a 1 to the CHIPSIG4 bit in CHIPSIG. 3.2 Power-Down Controller (PDC) The C674x megamodule includes a power-down controller (PDC). the chip signal register (CHIPSIG) and the chip signal clear register (CHIPSIG_CLR). 3. For more information on CHIPSIG and CHIPSIG_CLR.2.

4 Internal DMA (IDMA) Controller The IDMA controller performs fast block transfers between any two memory locations local to the C674x megamodule. which include the following: • EDMA3-initiated DMA transfers (and resulting coherency operations) • DSP subsystem IDMA-initiated transfers (and resulting coherency operations) • Programmable cache coherency operations – Block based coherency operations – Global coherency operations • CPU direct-initiated transfers – Data access (load/store) – Program access The resources include the following: • L1P memory • L1D memory • L2 memory • Resources outside of the C674x megamodule: external memory. DSP subsystem IDMA. When requests for a single resource contend. or in the external peripheral configuration (CFG) port. 3.) is assigned a priority level on a per-transfer basis. Each requestor (EDMA3. The IDMA is fully described in the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5). The bandwidth manager implements a weighted-priority-driven bandwidth allocation. where priority zero is the highest priority and priority eight is the lowest priority. on-chip peripherals.2.2. registers Since any given requestor could potentially block a resource for extended periods of time. Texas Instruments Incorporated 101 . The TMS320C674x DSP Megamodule Reference Guide (SPRUFK5) describes the power-down control in more detail. 3. For more information on the PDC. When the contention occurs for multiple successive cycles. where n is programmable.www.ti. Local memory locations are defined as those in Level 1 program (L1P).2. see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5). SPRUH77A – December 2011 Submit Documentation Feedback DSP Subsystem Copyright © 2011. the bandwidth manager is implemented to assure fairness for all requesters. CPU. Static power-down (clock gating) affects all components of the C674x megamodule and all internal memories.2. a contention counter assures that the lower-priority requestor gets access to the resource every 1 out of n arbitration cycles. and Level 2 (L2) memories. There are a total of nine priority levels. The programmable priority level has a single meaning throughout the system. • Static power-down: The PDC initiates power-down (clock gating) of the entire C674x megamodule and all internal memories immediately upon command from software. The IDMA cannot transfer data to or from the internal DSP memory-mapped register space.3 Bandwidth Manager (BWM) The bandwidth manager (BWM) provides a programmable interface for optimizing bandwidth among the requesters for resources.com TMS320C674x Megamodule This device supports the static power-down feature from the C674x megamodule. A priority level of -1 represents a transfer whose priority has been increased due to expiration of the contention counter or a transfer that is fixed as the highest-priority transfer to a given resource. access is granted to the highest-priority requestor. Software can initiate static power-down by way of a register bit in the power-down controller command register (PDCCMD) of the PDC. etc. Level 1 data (L1D).

4 Advanced Event Triggering (AET) The C674x megamodule supports advanced event triggering (AET). • State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences.com 3. 3. • Counters: count the occurrence of an event or cycles for performance monitoring. AET provides the following capabilities: • Hardware Program Breakpoints: specify addresses or address ranges that can generate events such as halting the processor or triggering the trace capture.3 Memory Map Refer to your device-specific data manual for the addresses of the memory-map registers. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . 3. This capability can be used to debug complex problems as well as understand performance characteristics of user applications. or data values that can generate events such as halting the processor or triggering the trace capture.3.1 DSP Internal Memory See the System Memory chapter for a description of the DSP internal memory.3.2 External Memory See the System Interconnect chapter and the System Memory chapter for a description of the additional memory and peripherals that the DSP has access to. address ranges.Memory Map www. 3. 102 DSP Subsystem Copyright © 2011.ti. • Data Watchpoints: specify data variable addresses.

..........2 Introduction ................................................................................................. 104 System Interconnect Block Diagram .Chapter 4 SPRUH77A – December 2011 System Interconnect Topic .. Page 4.... Texas Instruments Incorporated 103 ................................................................... 105 SPRUH77A – December 2011 Submit Documentation Feedback System Interconnect Copyright © 2011...................................................................1 4.............................................

The supported connections are designated by an X in Table 4-1. RTC. VPIF. TIMER64P0. SATA. the ARM. EMAC.com 4. EDMA3_0_CC0. 104 System Interconnect Copyright © 2011. the ARM. UART0. and the device peripherals are interconnected through a switch fabric architecture (see Section 4. Bridges are mainly used to perform bus-width conversion as well as bus operating frequency conversion. SPI1. AINTC ARM RAM DSP SDMA DDR2/ mDDR Slaves 128K RAM EDMA3_0_ TC0/TC1 X X X X X X X X X X EDMA3_1_ TC0 Peripheral Group (1) Master EDMA3_0_CC0 EDMA3_1_CC0 EDMA3_0_TC0 EDMA3_0_TC1 PRU0 PRU1 ARM I ARM D DSP CFG DSP MDMA EDMA3_1_TC0 EMAC SATA uPP USB1. eHRPWM0. and the various device peripherals can be classified into two categories: master peripherals and slave peripherals. eCAP1. SPI0. GPIO. PLLC1. HPI. LCDC. eCAP0. TIMER64P2. Table 4-1. eHRPWM1.2). HPI. uPP. PRU RAM0. PRU subsystem. McBSP0. McASP0. the Programmable Real-Time Unit (PRU) subsystem. EDMA3_1_CC0. I2C1. the PRU subsystem. PRU Config. The HPI does not have access to all registers in the SYSCFG module because it operates with the User Privilege Level. OMAP-L138 Applications Processor System Interconnect Matrix Masters Default Priority 0 0 0 0 0 0 2 2 2 2 4 4 4 4 4 4 4 5 6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X (2) X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X ARM ROM. eCAP2. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Master peripherals are typically capable of initiating read and write transfers in the system and do not rely on the EDMA3 or on a CPU to perform transfers to and from them. Through the SCRs. PRU RAM1. SATA.Introduction www. MMC/SD0.0). VPIF. The switch fabric is composed of multiple switched central resources (SCRs) and multiple bridges. McBSP1. MMC/SD1.0 VPIF LCDC HPI (1) EMIFA (2) Peripheral group: SYSCFG. and USB DMAs. the EDMA3 transfer controllers.ti. I2C0. the ARM. uPP. the DSP can send data to the EMIF without affecting a data transfer between a device peripheral and internal shared memory. PSC0.1). The DSP. MDIO. PLLC0. PSC1. the EDMA3 transfer controllers.1 USB2. UART1. EMAC.1 Introduction The DSP. USB0 (USB2. the EDMA3 transfer controllers. the SCRs provide priority-based arbitration and facilitate concurrent data movement between master and slave peripherals. The SCRs establish low-latency connectivity between master peripherals and slave peripherals. USB1 (USB1. LCDC. UART2. Not all master peripherals may connect to all slave peripherals. Additionally. TIMER64P3. TIMER64P1. The system master peripherals include the DSP.

System Interconnect Block Diagram HPI USB0 VBUSP USB0 CDMA Clock Domain: SYSCLK4 [CPU/4 Synchronous] EMAC USB1 SCR F1 BR F1 BR F7 SCR F3 MPU2 DDR2/mDDR SCR F0 BR F0 BR F6 DSP SDMA (L1D/L2) 128 KB Shared RAM SCR F4 MPU1 DSP MDMA rd wr rd wr rd wr SCR1 LCDC EDMA3_0_TC0 EDMA3_0_CC1 EDMA3_0_CC1 Clock Domain: SYSCLK4 [CPU/4 Synchronous] EDMA3_1_CC0 USB0 Cfg HPI PSC0 SCR5 PLLC0 SYSCFG0 SCR F5 LCDC uPP VPIF SATA MMC/SD1 EDMA3_0_TC1 EDMA3_1_TC0 uPP DMA VPIF DMA0 VPIF DMA1 SATA BR F2 SCR F2 BR5 Clock Domain: SYSCLK4 [CPU/4 Synchronous] Async 2 Clock Domain Clock Domain: SYSCLK6 [CPU/1 Synchronous] ARM-I ARM-D SCR0 BR1 BR2 BR0 BR3 BR4 SCR6 Timer64P0 Timer64P1 I2C0 RTC BR6 SCR F6 SYSCFG1 EMAC EMAC MDIO USB1 Cfg GPIO PSC1 I2C1 PLLC1 Async 1 Clock Domain AINTC Clock Domain: SYSCLK4 [CPU/4 Synchronous] Async 3 [PLL1] Clock Domain DSP CFG PRU0 PRU1 PRU CFG McBSP0 ARM ROM ARM RAM SCR2 MMC/SD0 SCR4 Legend: 32-bit BUS 64-bit BUS IP Module Synchronous Bridge Asynchronous Bridge SCR Paths with dashed lines cross the subchip boundary EDMA3_0_TC0 EDMA3_0_TC1 BR F5 SCR F8 SPI0 UART0 eHRPWM0 eHRPWM1 Timer64P2 Timer64P3 eCAP0 eCAP1 eCAP2 SPI1 EDMA3_0_CC0 EDMA3_0_CC0 BR F4 SCR F7 McBSP1 UART1 UART2 McASP0 BR7 EMIFA BR F3 BR8 SPRUH77A – December 2011 Submit Documentation Feedback System Interconnect Copyright © 2011.com System Interconnect Block Diagram 4.ti.www. Figure 4-1. Texas Instruments Incorporated 105 .2 System Interconnect Block Diagram Figure 4-1 shows a system interconnect block diagram.

106 System Interconnect Copyright © 2011. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

........................................................................ External Memories ........................................................4 5............ DSP Memories ................................................................Chapter 5 SPRUH77A – December 2011 System Memory Topic ..............................................1 5.......................................................... Peripherals ................. Shared RAM Memory ................................. ARM Memories ....... Page 5...................3 5............................... Introduction ...................................... Internal Peripherals .................................................................................. Texas Instruments Incorporated 107 .............................................................................................................................5 5.....................7 108 108 108 108 108 109 109 SPRUH77A – December 2011 Submit Documentation Feedback System Memory Copyright © 2011...............................6 5..............................................................................2 5....

4 KB. To help simplify software development. 8 KB. 16 KB. The DSP data memory controller (DMC) allows you to configure part of the L1D RAM as normal data RAM or as cache.3 DSP Memories The DSP internal memories are accessible by the ARM and other master peripherals (as dictated by the connectivity matrix) via the system interconnect through the DSP SDMA port. 32 KB. 4 KB.2 ARM Memories The configuration for the ARM internal memory is: • 8 KB ARM local RAM • 64 KB ARM local ROM • 16 KB Instruction Cache and 16 KB Data cache The ARM RAM/ROM are only accessible by ARM. or 32 KB of the 32 KB of RAM. The DSP unified memory controller (UMC) allows you to configure part or all of the L2 RAM as normal RAM or as cache. and is also accessible by several master peripherals. The DSP internal memory configuration is: • L1P memory includes 32 KB of RAM. 8 KB. 5. • L2 memory also includes 1024 KB of ROM. 16 KB. see the detailed memory-map information in the device-specific data manual. NAND Flash. 16 KB. • L2 memory includes 256 KB of RAM. Writes to this RAM by all masters is atomic. You can configure cache sizes of 0 KB. 5. and NOR Flash (up to 4 devices) – 8/16-bit wide NAND Flash with 4-bit ECC (up to 4 devices) – 16-bit SDRAM with 128-MB address space • DDR2/mDDR memory controller: – 16-bit DDR2 with up to 512-MB memory address space – 16-bit mDDR with up to 256-MB memory address space 108 System Memory Copyright © 2011. The default configuration is 256 KB normal RAM. This shared RAM is accessible by both the ARM and the DSP.1 Introduction This device has multiple on-chip/off-chip memories and several external device interfaces associated with its two CPUs and various subsystems. The DSP internal memory consists of L1P. 64 KB. or 32 KB of the 32 KB of RAM. a unified memory-map is used wherever possible to maintain a consistent view of device resources across all masters. 5.com 5. or 256 KB of the 256 KB of RAM. The default configuration is 32 KB cache.5 External Memories This device has two external memory interfaces that provide multiple external memory options accessible by the CPU and master peripherals: • EMIF: – 8/16-bit wide asynchronous EMIF module that supports asynchronous devices such as ASRAM. The default configuration is 32 KB cache. and L2. For details on the memory addresses. 128 KB.Introduction www. 4 KB.4 Shared RAM Memory This device also offers an on-chip 128-KB shared single-port RAM. apart from the ARM and the DSP internal memories. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . You can configure cache sizes of 0 KB. 8 KB. The DSP program memory controller (PMC) allows you to configure part or all of the L1P RAM as normal program RAM or as cache. L1D. actual memory supported and accessibility by various bus masters. • L1D memory includes 32 KB of RAM. You can configure cache sizes of 0 KB.ti. 5.

See the device-specific data manual for the complete list of peripherals supported on your device.ti. 5. see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).com Internal Peripherals 5. The peripheral only accessible by the ARM is the ARM interrupt controller (AINTC). and the system configuration module (SYSCFG). Texas Instruments Incorporated 109 .www. SPRUH77A – December 2011 Submit Documentation Feedback System Memory Copyright © 2011.7 Peripherals The ARM and the DSP have access to all peripherals. see the ARM Interrupt Controller (AINTC) chapter.6 Internal Peripherals The following peripherals are internal to the DSP subsystem and are only accessible to the DSP: • DSP interrupt controller (INTC) • DSP power down controller (PDC) • Bandwidth manager (BWM) • Internal DMA (IDMA) For more information on the internal peripherals. the power and sleep controller (PSC). For more information on the AINTC. This also includes system modules like the PLL controller (PLLC).

110 System Memory Copyright © 2011. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

............................................................ Page 6.......Chapter 6 SPRUH77A – December 2011 Memory Protection Unit (MPU) Topic .. 118 SPRUH77A – December 2011 Submit Documentation Feedback Memory Protection Unit (MPU) Copyright © 2011. 113 MPU Registers ............. Texas Instruments Incorporated 111 ................................................................................................................................................................................................3 Introduction .....................1 6..............2 6............................. 112 Architecture .....................................................................................

1 Purpose of the MPU The memory protection unit (MPU) is provided to manage access to memory.Introduction www. or invalid access.1. the transfer is passed unmodified to the output data bus. The MPU can record a detected fault. and saves violating transfer parameters • Supports L1/L2 cache accesses • Supports protection of its own registers 6.3 Block Diagram Figure 6-1 shows a block diagram of the MPU.2 Features The MPU supports the following features: • Supports multiple programmable address ranges • Supports 0 or 1 fixed range • Supports read. The MPU allows you to define multiple ranges and limit access to system masters based on their privilege ID.com 6.ti.1. 6. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . 6. the MPU checks the memory address on the input data bus against fixed and programmable ranges. and execute access privileges • Supports privilege ID associations with ranges • Generates an interrupt when there is a protection violation. If allowed. During an access. write. MPU Block Diagram MPU Input Data Bus Protection Checks Output Data Bus MPU_ADDR_ERR_INT MMRs MPU_PROT_ERR_INT MPU Register Bus 112 Memory Protection Unit (MPU) Copyright © 2011. and notify the system through an interrupt. An access to a protected memory must pass through the MPU. Figure 6-1. MPU1 supports the 128KB shared RAM and MPU2 supports the DDR2/mDDR SDRAM.1 Introduction This device supports two memory protection units (MPU1 and MPU2). If the transfer fails the protection check then the MPU does not pass the transfer to the output bus but rather services the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as well as generating an interrupt about the fault.1. The MPU generates two interrupts: an address error interrupt (MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT).

Device Master Settings Master EDMA3_0_CC0 EDMA3_0_TC0 and EDMA3_0_TC1 EDMA3_1_CC0 EDMA3_1_TC0 ARM (instruction access) Privilege ID Inherited Inherited Inherited Inherited 0 Privilege Level Inherited Inherited Inherited Inherited Software dependant Access Type DMA DMA DMA DMA Instruction SPRUH77A – December 2011 Submit Documentation Feedback Copyright © 2011. In some cases. the privilege level of this peripheral is fixed. user) and access type (instruction read vs.1 Privilege Levels The privilege level of a memory access determines what level of permissions the originator of the memory access might have. The privilege level is inherited from the code running on the CPU.4 MPU Default Configuration Two MPUs are supported on the device.2 Architecture 6. Two privilege levels are supported: supervisor and user. Table 6-1.1.com/help/index. Supervisor level is generally granted access to peripheral registers and the memory protection configuration. ARM and DSP CPU instruction and data accesses have a privilege level associated with them. Table 6-3.ti.www. one for the 128KB shared RAM and one for the DDR2/mDDR SDRAM. Table 6-3 also shows the privilege level (supervisor vs. MPU Memory Regions Memory Region Unit MPU1 MPU2 Memory Protection 128KB Shared RAM DDR2/mDDR SDRAM Start Address 8000 0000h C000 0000h End Address 8001 FFFFh DFFF FFFFh Table 6-2. Table 6-2 shows the configuration of each MPU. downloadable from http://infocenter. User level is generally confined to the memory spaces that the OS specifically designates for its use.com Architecture 6. Texas Instruments Incorporated Memory Protection Unit (MPU) 113 . Table 6-1 shows the memory regions protected by each MPU. Unlike the ARM and DSP CPU. See the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8) and the ARM926EJ-S Technical Reference Manual (TRM). Although master peripherals like the HPI do not execute code.jsp for more details on privilege levels of the DSP and ARM CPU.arm. data/DMA read or write) of each master on the device. Table 6-3 shows the privilege ID of the CPU and every mastering peripheral.2. MPU Default Configuration Setting Default permission Number of allowed IDs supported Number of fixed ranges supported Number of programmable ranges supported Compare width MPU1 Assume allowed 12 1 6 1 KB granularity MPU2 Assume allowed 12 0 12 64 KB granularity 6. they still have a privilege level associated with them. a particular setting depends on software being executed at the time of the access or the configuration of the master peripheral.

otherwise the access is not allowed. the unpopulated memory range must be protected in order to prevent unintended/disallowed aliased access to protected memory.1 USB2. For example. Addresses not covered by a range are either allowed or disallowed based on the configuration of the MPU.0 LCD Controller uPP SATA VPIF DMA0 VPIF DMA1 Privilege ID 0 1 2 3 4 5 6 7 8 9 10 11 Privilege Level Software dependant Software dependant Supervisor User Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Access Type Data Software dependant DMA DMA Data/DMA DMA DMA DMA DMA DMA DMA DMA 6. The MPU divides its assigned memory into address ranges. Device Master Settings (continued) Master ARM (data access) DSP PRU0/PRU1 HPI EMAC USB1. It is allowed to configure ranges such that they overlap each other. The programmable address range allows software to program the start and end addresses.2 Memory Protection Ranges NOTE: In some cases the amount of physical memory in actual use may be less than the maximum amount of memory supported by the device. One of the programmable address ranges could be used to detect accesses to this unpopulated memory.Architecture www. but your design may only populate 128 Mbytes. • Memory protection page attribute register (MPPA): Use to program the permission settings of the address range. 114 Memory Protection Unit (MPU) Copyright © 2011. the device may support a total of 512 Mbytes of SDRAM memory. The fixed address range is configured to an exact address.2. In this case.com Table 6-3. Each MPU can support one fixed address range and multiple programmable address ranges. Each address range has the following set of registers: • Range start and end address registers (MPSAR and MPEAR): Specifies the starting and ending address of the address range. In such cases. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . all the overlapped ranges must allow the access.ti. The MPU can be configured for assumed allowed or assumed disallowed mode as dictated by the ASSUME_ALLOWED bit in the configuration register (CONFIG). The final permissions given to the access are the lowest of each type of permission from any hit range.

when a master triggers a memory access command. 64 different encodings are permitted altogether.1 Requestor-ID Based Access Controls Each master on the device has an N-bit code associated with it that identifies it for privilege purposes. Figure 6-2.2. although programs might not use all of them. Execute refers to accesses associated with an instruction fetch. • AID0 through AID11 are used to specify the allowed privilege IDs.2.accesses originating via the load/store units on the CPU or via a master peripheral.ti. the AID bit denies access to the corresponding requestor. Request Type Access Controls Bit 5 4 3 2 1 0 Field SR SW SX UR UW UX Description Supervisor may read Supervisor may write Supervisor may execute User may read User may write User may execute SPRUH77A – December 2011 Submit Documentation Feedback Memory Protection Unit (MPU) Copyright © 2011. That is. and execute permissions independently for both user and supervisor mode. Each memory protection range has an allowed ID (AID) field associated with it that indicates which requestors may access the given address range. When set to 1. For each bit. AIDX. a 1 permits the access type and a 0 denies access. When cleared to 0. For example. write.www. the AID bit grants access to the corresponding ID. the privilege ID will be carried alongside the command. listed in Table 6-4. captures access made by all privilege IDs not covered by AID0 through AID11. Read and write refer to data accesses -. Permission Fields 31 Reserved AID11 15 AID5 14 AID4 13 AID3 12 Allowed IDs AID2 AID1 AID0 AIX 11 10 9 8 Reserved SR SW 6 5 AID10 4 22 21 20 19 AID9 3 SX 18 AID8 2 UR 17 AID7 1 UW 16 AID6 0 UX Allowed IDs Access Types 6. This privilege ID accompanies all memory accesses made on behalf of that master.2. Figure 6-2 shows the structure of a permission entry.com Architecture 6. Texas Instruments Incorporated 115 . UX = 1 means that User Mode may execute from the given page. This results in six permission bits.3.3 Permission Structures The MPU defines a per-range permission structure with three permission fields in a 32-bit permission entry. The MPU maps the privilege IDs of all the possible requestors to bits in the allowed IDs field in the memory protection page attribute registers (MPPA). The memory protection model allows controlling read. 6. and execute. write.3. The memory protection unit allows you to specify all six of these bits separately.2 Request-Type Based Permissions The memory protection model defines three fundamental functional access types: read. Table 6-4. • An additional allowed ID bit.

if a transfer matches 2 ranges.5 DSP L1/L2 Cache Controller Accesses A memory read access that originates from the DSP L1/L2 cache is treated differently to allow memory protection to be enforced by the DSP level. The permissions settings returned by the MPU are taken from MPPA that covers the address range of the original request—only the SR. The MPU can be configured for assumed allowed or assumed disallowed mode as dictated by the ASSUME_ALLOWED bit in the configuration register (CONFIG). The MPU first checks the transfers privilege ID against the AID settings. all the overlapped ranges must allow the access. then the range will not be checked. A protection fault can occur from a register write with invalid permissions and this triggers an interrupt just like a memory access. 6. 116 Memory Protection Unit (MPU) Copyright © 2011. If the transfer address range is not covered by an address range then the transfer is either allowed or disallowed based on the configuration of the MPU. write. one that is RW and one that is RX. the MPU checks if the address range of the input transfer overlaps one of the address ranges. SW. if the AID bit is 1. SW. The MPU has a special mechanism for handling DSP L1/L2 cache controller read accesses. and UX bits are passed. the UR.com 6. then the returned value is the logical-AND of all MPPA permissions. If the request address is covered by multiple address ranges. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .6 MPU Register Protection Access to the range start and end address registers (MPSAR and MPEAR) and memory protection page attribute registers (MPPA) is also protected. If the AID bit is 0. the permission settings stored in the memory protection page attribute registers (MPPA) are passed to the L1/L2 memory controllers along with the read data.2. All non-debug writes must be by a supervisor entity. For user mode accesses. UR. and UX bits are checked. 6.Architecture www.ti. UW. The final permissions given to the access are the lowest of each type of permission from any hit range.4 Protection Check During a memory access.2. There is a set of permissions for supervisor mode and a set for user mode. see Section 6. then the transfer parameters are checked against the memory protection page attribute register (MPPA) values to detect an allowed access. and execute permissions are also checked. In the case that a transfer spans multiple address ranges. Therefore. then the final permission is just R. and SX bits are checked.2. Instead the memory access is serviced directly by the L1/L2 memory controllers. During a cache memory read. the read. the SR.2.5 for more details. UW. If the transfer address range does not match any address range then the transfer is either allowed or disallowed based on the configuration of the MPU. For non-debug accesses. When the input transfer address is within a range the transfer parameters are checked against the address range permissions. Faults are not recorded (nor interrupts generated) for debug accesses. otherwise the access is not allowed. For supervisor mode accesses. SX. This is because a subsequent memory access that hits in the cache does not pass through the MPU.

The MPU_ADDR_ERR_INT is generated when there is an addressing violation due to an access to a non-existent location in the MPU register space.2. additional faults will be ignored. Table 6-5. 6.9. 6. The MPU can store the fault information for only one fault. The MPU_PROT_ERR_INT interrupt is generated when there is a protection violation of either in the defined ranges or to the MPU registers. the MPU does not pass the transfer to the output bus.7 Invalid Accesses and Exceptions When a transfer fails the protection check.2.2. the memory protection page attribute registers (MPPA) default to 0. Software must use the fault clear register (FLTCLR) to clear the fault status so that another fault can be recorded. 6. • For a write: The MPU receives all the write data and returns a protection error status.2.www. The combined interrupt is routed to the ARM and DSP interrupt controllers. Also.2. a protection error status.com Architecture 6. MPU_BOOTCFG_ERR Interrupt Sources Interrupt MPU1_ADDR_ERR_INT MPU1_PROT_ERR_INT MPU2_ADDR_ERR_INT MPU2_PROT_ERR_INT BOOTCFG_ADDR_ERR BOOTCFG_PROT_ERR Source MPU1 address error interrupt MPU1 protection interrupt MPU2 address error interrupt MPU2 protection interrupt Boot configuration address error Boot configuration protection error 6.ti.1 Interrupt Events and Requests The MPU generates two interrupts: an address error interrupt (MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT).9 Interrupt Support 6. Texas Instruments Incorporated 117 . This disables all protection features. The MPU captures system faults due to addressing or protection violations in its registers. The transfer parameters that caused the violation are saved in the MPU registers.9. The MPU instead services the transfer locally to prevent a hang and returns a protection error to the requestor.2 Interrupt Multiplexing The interrupts from both MPUs are combined with the boot configuration module into a single interrupt called MPU_BOOTCFG_ERR. SPRUH77A – December 2011 Submit Documentation Feedback Memory Protection Unit (MPU) Copyright © 2011. Faults are not recorded (no interrupts generated) for debug accesses. The behavior of the MPU depends on whether the access was a read or a write: • For a read: The MPU returns 0s.8 Reset Considerations After reset.10 Emulation Considerations Memory and MPU registers are not protected against emulation accesses. so the first detected fault is recorded into the fault registers and an interrupt is generated. Table 6-5 shows the interrupt sources that are combined to make MPU_BOOTCFG_ERR. a permission value is 0 (no access allowed).2. The MPU will not record another fault nor generate another interrupt until the existing fault has been cleared.

10.3.10.1 Section 6.10.8 Section 6.11.12 Section 6.5 Section 6.3.2 Section 6.1 Section 6. Table 6-6.11.11.3.3 Section 6.3.12 Section 6.3.10.1 Section 6.3.12 Section 6.10.3.3.3.3.3.3.3.12 Section 6.6 Section 6.3.3.3.1 Section 6.3.3 Section 6.3.3.11.3.3.1 Section 6.1 Section 6. Each MPU contains a set of memory-mapped registers. Table 6-7 lists the memory-mapped registers for the MPU2.3.7 Section 6.MPU Registers www. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .15 Table 6-7.3.ti.1 Section 6.com 6.3. Memory Protection Unit 1 (MPU1) Registers Address 01E1 4000h 01E1 4004h 01E1 4010h 01E1 4014h 01E1 4018h 01E1 401Ch 01E1 4200h 01E1 4204h 01E1 4208h 01E1 4210h 01E1 4214h 01E1 4218h 01E1 4220h 01E1 4224h 01E1 4228h 01E1 4230h 01E1 4234h 01E1 4238h 01E1 4240h 01E1 4244h 01E1 4248h 01E1 4250h 01E1 4254h 01E1 4258h 01E1 4300h 01E1 4304h 01E1 4308h Acronym REVID CONFIG IRAWSTAT IENSTAT IENSET IENCLR PROG1_MPSAR PROG1_MPEAR PROG1_MPPA PROG2_MPSAR PROG2_MPEAR PROG2_MPPA PROG3_MPSAR PROG3_MPEAR PROG3_MPPA PROG4_MPSAR PROG4_MPEAR PROG4_MPPA PROG5_MPSAR PROG5_MPEAR PROG5_MPPA PROG6_MPSAR PROG6_MPEAR PROG6_MPPA FLTADDRR FLTSTAT FLTCLR Register Description Revision identification register Configuration register Interrupt raw status/set register Interrupt enable status/clear register Interrupt enable set register Interrupt enable clear register Programmable range 1 start address register Programmable range 1 end address register Programmable range 1 memory protection page attributes register Programmable range 2 start address register Programmable range 2 end address register Programmable range 2 memory protection page attributes register Programmable range 3 start address register Programmable range 3 end address register Programmable range 3 memory protection page attributes register Programmable range 4 start address register Programmable range 4 end address register Programmable range 4 memory protection page attributes register Programmable range 5 start address register Programmable range 5 end address register Programmable range 5 memory protection page attributes register Programmable range 6 start address register Programmable range 6 end address register Programmable range 6 memory protection page attributes register Fault address register Fault status register Fault clear register Section Section 6.3. Memory Protection Unit 2 (MPU2) Registers Address 01E1 5000h 01E1 5004h 01E1 5010h 01E1 5014h 01E1 5018h 01E1 501Ch 01E1 5100h 01E1 5104h 01E1 5108h Acronym REVID CONFIG IRAWSTAT IENSTAT IENSET IENCLR FXD_MPSAR FXD_MPEAR FXD_MPPA Register Description Revision identification register Configuration register Interrupt raw status/set register Interrupt enable status/clear register Interrupt enable set register Interrupt enable clear register Fixed range start address register Fixed range end address register Fixed range memory protection page attributes register Section Section 6.14 Section 6.1 Section 6.3.3.13 Section 6.3.10.3.3.6 Section 6.1 Section 6.2 Section 6.11.12 Section 6.3.3.4 Section 6.1 Section 6.1 Section 6.12 Section 6.1 Section 6.3 MPU Registers There are two MPUs on the device.11.9 118 Memory Protection Unit (MPU) Copyright © 2011.3.3.1 Section 6.3.5 Section 6. Table 6-6 lists the memory-mapped registers for the MPU1.4 Section 6.1 Section 6.3.

3.14 Section 6.11.3.11.11.3.11.12 Section 6.3.12 Section 6.3.3.3.12 Section 6.2 Section 6.3.com MPU Registers Table 6-7.11.3. Memory Protection Unit 2 (MPU2) Registers (continued) Address 01E1 5200h 01E1 5204h 01E1 5208h 01E1 5210h 01E1 5214h 01E1 5218h 01E1 5220h 01E1 5224h 01E1 5228h 01E1 5230h 01E1 5234h 01E1 5238h 01E1 5240h 01E1 5244h 01E1 5248h 01E1 5250h 01E1 5254h 01E1 5258h 01E1 5260h 01E1 5274h 01E1 5268h 01E1 5270h 01E1 5274h 01E1 5278h 01E1 5280h 01E1 5284h 01E1 5288h 01E1 5290h 01E1 5294h 01E1 5298h 01E1 52A0h 01E1 52A4h 01E1 52A8h 01E1 52B0h 01E1 52B4h 01E1 52B8h 01E1 5300h 01E1 5304h 01E1 5308h Acronym PROG1_MPSAR PROG1_MPEAR PROG1_MPPA PROG2_MPSAR PROG2_MPEAR PROG2_MPPA PROG3_MPSAR PROG3_MPEAR PROG3_MPPA PROG4_MPSAR PROG4_MPEAR PROG4_MPPA PROG5_MPSAR PROG5_MPEAR PROG5_MPPA PROG6_MPSAR PROG6_MPEAR PROG6_MPPA PROG7_MPSAR PROG7_MPEAR PROG7_MPPA PROG8_MPSAR PROG8_MPEAR PROG8_MPPA PROG9_MPSAR PROG9_MPEAR PROG9_MPPA PROG10_MPSAR PROG10_MPEAR PROG10_MPPA PROG11_MPSAR PROG11_MPEAR PROG11_MPPA PROG12_MPSAR PROG12_MPEAR PROG12_MPPA FLTADDRR FLTSTAT FLTCLR Register Description Programmable range 1 start address register Programmable range 1 end address register Programmable range 1 memory protection page attributes register Programmable range 2 start address register Programmable range 2 end address register Programmable range 2 memory protection page attributes register Programmable range 3 start address register Programmable range 3 end address register Programmable range 3 memory protection page attributes register Programmable range 4 start address register Programmable range 4 end address register Programmable range 4 memory protection page attributes register Programmable range 5 start address register Programmable range 5 end address register Programmable range 5 memory protection page attributes register Programmable range 6 start address register Programmable range 6 end address register Programmable range 6 memory protection page attributes register Programmable range 7 start address register Programmable range 7 end address register Programmable range 7 memory protection page attributes register Programmable range 8 start address register Programmable range 8 end address register Programmable range 8 memory protection page attributes register Programmable range 9 start address register Programmable range 9 end address register Programmable range 9 memory protection page attributes register Programmable range 10 start address register Programmable range 10 end address register Programmable range 10 memory protection page attributes register Programmable range 11 start address register Programmable range 11 end address register Programmable range 11 memory protection page attributes register Programmable range 12 start address register Programmable range 12 end address register Programmable range 12 memory protection page attributes register Fault address register Fault status register Fault clear register Section Section 6.2 Section 6.15 SPRUH77A – December 2011 Submit Documentation Feedback Memory Protection Unit (MPU) Copyright © 2011.3.10.2 Section 6.10.10.2 Section 6.2 Section 6.12 Section 6.3.3.2 Section 6.3.2 Section 6.10.3.3.10.3.12 Section 6.3.10.2 Section 6.12 Section 6.12 Section 6.11.2 Section 6. Texas Instruments Incorporated 119 .3.10.2 Section 6.12 Section 6.10.3.3.12 Section 6.3.3.3.3.3.2 Section 6.11.3.2 Section 6.10.2 Section 6.2 Section 6.10.11.3.10.3.2 Section 6.13 Section 6.3.3.10.3.11.2 Section 6.3.3.2 Section 6.2 Section 6.11.3.3.2 Section 6.2 Section 6.3.3.2 Section 6.12 Section 6.www.12 Section 6.2 Section 6.2 Section 6.3.11.3.2 Section 6.ti.11.12 Section 6.

Revision ID Register (REVID) Field Descriptions Bit 31-0 Field REV Value 4E81 0101h Description Revision ID of the MPU. Number of supported AIDs. Number of fixed address ranges. this bit determines whether the transfer is assumed to be allowed or not allowed. not all AIDs may be supported on your device. See for a list of AIDs supported on your device. 6. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . -n = value after reset (1) (2) 24 23 NUM_FIXED R-0 (1) or 1 (2) 20 19 NUM_PROG R-6h (1) or Ch (2) 1 0 16 12 11 Reserved R-0 ASSUME_ALLOWED R-1 For MPU1. Revision ID Register (REVID) 31 REV R-4E81 0101h LEGEND: R = Read only. When an address is not covered by any MPU protection range.3. Unsupported AIDs should be cleared to 0 in the memory page protection attributes registers (MPPA).3. Assume is allowed. Table 6-9.2 Configuration Register (CONFIG) The configuration register (CONFIG) contains the configuration value of the MPU. The CONFIG is shown in Figure 6-4 and described in Table 6-9.MPU Registers www.com 6. Figure 6-4.ti. 120 Memory Protection Unit (MPU) Copyright © 2011. For MPU2. The REVID is shown in Figure 6-3 and described in Table 6-8. Number of programmable address ranges. Configuration Register (CONFIG) 31 ADDR_WIDTH R-0 (1) or 6h (2) 15 NUM_AIDS R-Ch LEGEND: R = Read only. Configuration Register (CONFIG) Field Descriptions Bit 31-24 23-20 19-16 15-12 11-1 0 Field ADDR_WIDTH NUM_FIXED NUM_PROG NUM_AIDS Reserved ASSUME_ALLOWED 0 1 Value 0-FFh 0-Fh 0-Fh 0-Fh 0 Description Address alignment (2n KByte alignment) for range checking. Assume is disallowed. Reserved Assume allowed. NOTE: Although the NUM_AIDS bit defaults to 12 (Ch).1 Revision Identification Register (REVID) The revision ID register (REVID) contains the MPU revision. Figure 6-3. -n = value after reset 0 Table 6-8.

Interrupt is set. writing 0 has no effect. Texas Instruments Incorporated 121 . Interrupt is not set. Reading this bit reflects the status of the interrupt. -n = value after reset 2 1 ADDRERR R/W-0 0 PROTERR R/W-0 16 Table 6-10. SPRUH77A – December 2011 Submit Documentation Feedback Memory Protection Unit (MPU) Copyright © 2011. Reading this bit reflects the status of the interrupt.com MPU Registers 6. Writes of 0 have no effect. writing 0 has no effect. Writing 1 sets the status. Interrupt Raw Status/Set Register (IRAWSTAT) 31 Reserved R-0 15 R-0 LEGEND: R/W = Read/Write. Interrupt is set. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions Bit 31-2 1 Field Reserved ADDRERR 0 1 0 PROTERR 0 1 Value 0 Description Reserved Address violation error. Interrupt is not set.ti. R = Read only.3 Interrupt Raw Status/Set Register (IRAWSTAT) Reading the interrupt raw status/set register (IRAWSTAT) returns the status of all interrupts. Writing 1 sets the status. Figure 6-5.3. Protection violation error. Software can write to IRAWSTAT to manually set an interrupt. The IRAWSTAT is shown in Figure 6-5 and described in Table 6-10. however.www. an interrupt is generated only if the interrupt is enabled in the interrupt enable set register (IENSET).

Interrupt Enable Status/Clear Register (IENSTAT) 31 Reserved R-0 15 R-0 LEGEND: R/W = Read/Write. 0 1 Interrupt is not set. 122 Memory Protection Unit (MPU) Copyright © 2011. Figure 6-6. writing 0 has no effect. If the interrupt is enabled. Writing 1 sets the status. If the interrupt is disabled. -n = value after reset 2 1 ADDRERR R/W-0 0 PROTERR R/W-0 16 Table 6-11. the interrupt is cleared from both IENSTAT and the interrupt raw status/set register (IRAWSTAT). writing 0 has no effect. reading this bit returns 0. Protection violation error. R = Read only. reading this bit reflects the status of the interrupt. If the interrupt is disabled. reading this bit returns 0. reading this bit reflects the status of the interrupt.com 6. Writing 1 sets the status.4 Interrupt Enable Status/Clear Register (IENSTAT) Reading the interrupt enable status/clear register (IENSTAT) returns the status of only those interrupts that are enabled in the interrupt enable set register (IENSET). If the interrupt is enabled. Interrupt is set.3.MPU Registers www. Interrupt is set.ti. Writes of 0 have no effect. The IENSTAT is shown in Figure 6-6 and described in Table 6-11. Software can write to IENSTAT to clear an interrupt. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . 0 1 0 PROTERR Interrupt is not set. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions Bit 31-2 1 Field Reserved ADDRERR Value 0 Description Reserved Address violation error.

-n = value after reset 2 1 ADDRERR_EN R/W-0 0 PROTERR_EN R/W-0 16 Table 6-12. Writing 0 has no effect.5 Interrupt Enable Set Register (IENSET) Reading the interrupt enable set register (IENSET) returns the interrupts that are enabled. Protection violation error disable. The IENCLR is shown in Figure 6-8 and described in Table 6-13. Interrupt Enable Set Register (IENSET) Field Descriptions Bit 31-2 1 Field Reserved ADDRERR_EN 0 1 0 PROTERR_EN 0 1 Value 0 Description Reserved Address violation error enable. Writing 0 has no effect. Interrupt is cleared/disabled.3.www. Interrupt Enable Clear Register (IENCLR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write. Writing 0 has no effect.com MPU Registers 6. Software can write to IENCLR to clear/disable an interrupt.3. Interrupt Enable Set Register (IENSET) 31 Reserved R-0 15 R-0 LEGEND: R/W = Read/Write. Writing 0 has no effect. R = Read only. R = Read only. The IENSET is shown in Figure 6-7 and described in Table 6-12. SPRUH77A – December 2011 Submit Documentation Feedback Memory Protection Unit (MPU) Copyright © 2011. Figure 6-7.ti. Writes of 0 have no effect. Interrupt is enabled. -n = value after reset 2 1 R/W-0 0 R/W-0 16 ADDRERR_CLR PROTERR_CLR Table 6-13. Interrupt Enable Clear Register (IENCLR) Field Descriptions Bit 31-2 1 Field Reserved ADDRERR_CLR 0 1 0 PROTERR_CLR 0 1 Value 0 Description Reserved Address violation error disable. Texas Instruments Incorporated 123 . Interrupt is enabled.6 Interrupt Enable Clear Register (IENCLR) Reading the interrupt enable clear register (IENCLR) returns the interrupts that are enabled. Figure 6-8. Writes of 0 have no effect. 6. Software can write to IENSET to enable an interrupt. Interrupt is cleared/disabled. Protection violation error enable.

MPU Registers www. Fixed Range Start Address Register (FXD_MPSAR) 31 Reserved R-0 LEGEND: R = Read only.3. -n = value after reset 0 124 Memory Protection Unit (MPU) Copyright © 2011. Figure 6-10. which instead read as 0.7 Fixed Range Start Address Register (FXD_MPSAR) The fixed range start address register (FXD_MPSAR) holds the start address for the fixed range.ti. The FXD_MPEAR is shown in Figure 6-10. Figure 6-9. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . However. these addresses are not indicated in FXD_MPSAR and the fixed range end address register (FXD_MPEAR). The fixed address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h– B000 7FFFh). However. -n = value after reset 0 6. The FXD_MPSAR is shown in Figure 6-9.com 6. Fixed Range End Address Register (FXD_MPEAR) 31 Reserved R-0 LEGEND: R = Read only.8 Fixed Range End Address Register (FXD_MPEAR) The fixed range end address register (FXD_MPEAR) holds the end address for the fixed range.3. The fixed address range manages access to the DDR2/mDDR SDRAM control registers (B000 0000h– B000 7FFFh). these addresses are not indicated in FXD_MPEAR and the fixed range start address register (FXD_MPSAR). which instead read as 0.

The FXD_MPPA is shown in Figure 6-11 and described in Table 6-14. Access is denied. Figure 6-11. This register is writeable by a supervisor entity only. Texas Instruments Incorporated 125 . Supervisor Write permission. Supervisor Read permission.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) The fixed range memory protection page attributes register (FXD_MPPA) holds the permissions for the fixed region. Access is granted. Access is denied. Access is denied. This bit must be written as 1. User Read permission.com MPU Registers 6. Access is allowed.3. R = Read only. Access is denied.www.ti. Access is allowed. User Write permission. Access is allowed. Access is allowed. Access is denied. -n = value after reset Table 6-14. User Execute permission. Access is granted. Access is allowed. Reserved Reserved. Reserved. This bit must be written as 1. Access is denied. SPRUH77A – December 2011 Submit Documentation Feedback Memory Protection Unit (MPU) Copyright © 2011. Access is allowed. Access is denied. Access is denied. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) 31 Reserved R-0 15 AID5 R/W-1 14 AID4 R/W-1 13 AID3 R/W-1 12 AID2 R/W-1 11 AID1 R/W-1 10 AID0 R/W-1 9 AIDX R/W-1 8 Rsvd R-0 26 25 Reserved R-Fh 7 Rsvd R/W-1 6 Rsvd R/W-1 22 21 AID11 R/W-1 5 SR R/W-1 20 AID10 R/W-1 4 SW R/W-1 19 AID9 R/W-1 3 SX R/W-1 18 AID8 R/W-1 2 UR R/W-1 17 AID7 R/W-1 1 UW R/W-1 16 AID6 R/W-1 0 UX R/W-1 LEGEND: R/W = Read/Write. Supervisor Execute permission. Controls access from ID > 11. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions Bit 31-26 25-22 21-10 Field Reserved Reserved AIDn 0 1 9 AIDX 0 1 8 7 6 5 Reserved Reserved Reserved SR 0 1 4 SW 0 1 3 SX 0 1 2 UR 0 1 1 UW 0 1 0 UX 0 1 0 1 1 Value 0 Fh Description Reserved Reserved Controls access from ID = n.

the device may support a total of 512 Mbytes of SDRAM memory. -n = value after reset 10 9 Reserved R-0 0 Table 6-15. The size of the page determines the width of the address field in PROGn_MPSAR and the programmable range n end address register (PROGn_MPEAR).ti. The programmable range n start address register (PROGn_MPSAR) holds the start address for the range n. write 8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.10 Programmable Range n Start Address Registers (PROGn_MPSAR) NOTE: In some cases the amount of physical memory in actual use may be less than the maximum amount of memory supported by the device. The size of the page depends on the MPU: the page size for MPU1 is 1 KBbyte. R = Read only.MPU Registers www. One of the programmable address ranges could be used to detect accesses to this unpopulated memory. Reserved 6. Figure 6-13.10. -n = value after reset 16 15 Reserved R-0 0 Table 6-16. the unpopulated memory range must be protected in order to prevent unintended/disallowed aliased access to protected memory. Figure 6-12. to protect a 64-KB page starting at byte address 8001 0000h. MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions Bit 31-10 9-0 Field START_ADDR Reserved Value 20 0000h– 20 007Fh 0 Description Start address for range N . MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) 31 START_ADDR R/W-C000h LEGEND: R/W = Read/Write. For example. but your design may only populate 128 Mbytes. R = Read only. Reserved 126 Memory Protection Unit (MPU) Copyright © 2011.3.1 MPU1 Programmable Range n Start Address Register (PROG1_MPSAR-PROG6_MPSAR) The PROGn_MPSAR for MPU1 is shown in Figure 6-12 and described in Table 6-15. The start address must be aligned on a page boundary. 6. The PROGn_MPSAR is writeable by a supervisor entity only. the page size for MPU2 is 64 KBytes.com 6. especially memory.2 MPU2 Programmable Range n Start Address Register (PROG1_MPSAR-PROG12_MPSAR) The PROGn_MPSAR for MPU2 is shown in Figure 6-13 and described in Table 6-16. MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) 31 START_ADDR R/W-20 0000h LEGEND: R/W = Read/Write. In such cases.3.3. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions Bit 31-16 15-0 Field START_ADDR Reserved Value C000h–DFFFh 0 Description Start address for range N. For example.10. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

Reserved 6. 6. -n = value after reset 16 15 Reserved R-FFFFh 0 Table 6-18.11.11. The end address must be aligned on a page boundary. Reserved SPRUH77A – December 2011 Submit Documentation Feedback Memory Protection Unit (MPU) Copyright © 2011. This register is writeable by a supervisor entity only.3.11 Programmable Range n End Address Registers (PROGn_MPEAR) The programmable range n end address register (PROGn_MPEAR) holds the end address for the range n. MPU2 Programmable Range n End Address Register (PROGn_MPEAR) 31 END_ADDR R/W-DFFFh LEGEND: R/W = Read/Write. Figure 6-15.2 MPU2 Programmable Range n End Address Register (PROG1_MPEAR-PROG12_MPEAR) The PROGn_MPEAR for MPU2 is shown in Figure 6-15 and described in Table 6-18. to protect a 64-KB page starting at byte address 8001 0000h. The size of the page depends on the MPU: the page size for MPU1 is 1 KByte. The size of the page determines the width of the address field in the programmable range n start address register (PROGn_MPSAR) and PROGn_MPEAR.ti. MPU1 Programmable Range n End Address Register (PROGn_MPEAR) 31 END_ADDR R/W-20 007Fh LEGEND: R/W = Read/Write. R = Read only.com MPU Registers 6.3. -n = value after reset 10 9 Reserved R-3FFh 0 Table 6-17. the page size for MPU2 is 64 KBytes.www. MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions Bit 31-16 15-0 Field END_ADDR Reserved Value C000h–DFFFh FFFFh Description Start address for range N. Figure 6-14. MPU1 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions Bit 31-10 9-0 Field END_ADDR Reserved Value 20 0000h– 20 007Fh 3FFh Description End address for range N. For example.1 MPU1 Programmable Range n End Address Register (PROG1_MPEAR-PROG6_MPEAR) The PROGn_MPEAR for MPU1 is shown in Figure 6-14 and described in Table 6-17. write 8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR.3. R = Read only. Texas Instruments Incorporated 127 .

Access is allowed. Access is denied. User Execute permission.ti. Access is allowed. Access is allowed. -n = value after reset Table 6-19. Access is denied. Reserved Reserved. User Read permission. R = Read only. Access is denied. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) Field Descriptions Bit 31-26 25-22 21-10 Field Reserved Reserved AIDn 0 1 9 AIDX 0 1 8 7 6 5 Reserved Reserved Reserved SR 0 1 4 SW 0 1 3 SX 0 1 2 UR 0 1 1 UW 0 1 0 UX 0 1 0 1 1 Value 0 Fh Description Reserved Reserved Controls access from ID = n. Access is allowed. Access is granted. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) 31 Reserved R-0 15 AID5 R/W-1 14 AID4 R/W-1 13 AID3 R/W-1 12 AID2 R/W-1 11 AID1 R/W-1 10 AID0 R/W-1 9 AIDX R/W-1 8 Rsvd R-0 26 25 Reserved R-Fh 7 Rsvd R/W-1 6 Rsvd R/W-1 22 21 AID11 R/W-1 5 SR R/W-1 20 AID10 R/W-1 4 SW R/W-1 19 AID9 R/W-1 3 SX R/W-1 18 AID8 R/W-1 2 UR R/W-1 17 AID7 R/W-1 1 UW R/W-1 16 AID6 R/W-1 0 UX R/W-1 LEGEND: R/W = Read/Write. Access is granted. This bit must be written as 1. Access is denied. The PROGn_MPPA is shown in Figure 6-16 and described in Table 6-19. Access is allowed. Access is denied. Figure 6-16. Supervisor Execute permission.12 Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA) The programmable range n memory protection page attributes register (PROGn_MPPA) holds the permissions for the region n. This bit must be written as 1. User Write permission. Access is denied.MPU Registers www. Supervisor Read permission. Access is denied. Access is denied. Reserved. 128 Memory Protection Unit (MPU) Copyright © 2011.com 6. Controls access from ID > 11. Supervisor Write permission.3. Access is allowed. This register is writeable only by a supervisor entity.

Fault Address Register (FLTADDRR) Field Descriptions Bit 31-0 Field FLTADDR Value 0-FFFF FFFFh Description Memory address of fault. Figure 6-17.13 Fault Address Register (FLTADDRR) The fault address register (FLTADDRR) holds the address of the first protection fault transfer. -n = value after reset 0 Table 6-20. Texas Instruments Incorporated 129 . The FLTADDRR is shown in Figure 6-17 and described in Table 6-20. SPRUH77A – December 2011 Submit Documentation Feedback Memory Protection Unit (MPU) Copyright © 2011.3. Fault Address Register (FLTADDRR) 31 FLTADDR R-0 LEGEND: R = Read only.www.ti.com MPU Registers 6.

Reserved Fault type.MPU Registers www. Figure 6-18. Reserved Supervisor read fault. -n = value after reset Table 6-21.ti.3. User write fault. No fault.14 Fault Status Register (FLTSTAT) The fault status register (FLTSTAT) holds the status and attributes of the first protection fault transfer. Reserved Privilege ID of fault transfer. The TYPE bit field is cleared when a 1 is written to the CLEAR bit in the fault clear register (FLTCLR). Reserved User read fault. Reserved Supervisor execute fault. Fault Status Register (FLTSTAT) 31 Reserved R-0 15 Reserved R-0 13 12 PRIVID R-0 9 8 Reserved R-0 6 5 TYPE R-0 24 23 MSTID R-0 0 16 LEGEND: R = Read only. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Reserved Supervisor write fault. Reserved Relaxed cache line fill fault. User execute fault.com 6. The FLTSTAT is shown in Figure 6-18 and described in Table 6-21. Fault Status Register (FLTSTAT) Field Descriptions Bit 31-24 23-16 15-13 12-9 8-6 5-0 Field Reserved MSTID Reserved PRIVID Reserved TYPE Value 0 0-FFh 0 0-Fh 0 0-3Fh 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 10h 11h 12h 13h-1Fh 20h 21h-3Eh 3Fh Description Reserved Master ID of fault transfer. Reserved Relaxed cache write back fault. 130 Memory Protection Unit (MPU) Copyright © 2011.

Only the TYPE bit field in FLTSTAT is cleared when a 1 is written to the CLEAR bit.com MPU Registers 6. Fault Clear Register (FLTCLR) Field Descriptions Bit 31-1 0 Field Reserved CLEAR 0 1 Value 0 Description Reserved Command to clear the current fault.ti. -n = value after reset 1 0 CLEAR W-0 16 Table 6-22. Fault Clear Register (FLTCLR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only.15 Fault Clear Register (FLTCLR) The fault clear register (FLTCLR) allows software to clear the current fault so that another can be captured in the fault status register (FLTSTAT) as well as produce an interrupt. Writing 0 has no effect. Figure 6-19. W = Write only.www. Clear the current fault. SPRUH77A – December 2011 Submit Documentation Feedback Memory Protection Unit (MPU) Copyright © 2011.3. Texas Instruments Incorporated 131 . No effect. The FLTCLR is shown in Figure 6-19 and described in Table 6-22.

132 Memory Protection Unit (MPU) Copyright © 2011. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

.......................................................................... 137 SPRUH77A – December 2011 Submit Documentation Feedback Device Clocking Copyright © 2011..... Page 7.................................................1 7...... 134 Frequency Flexibility ...........................................3 Overview .........................................2 7............................................................................................................................... 136 Peripheral Clocking ...............Chapter 7 SPRUH77A – December 2011 Device Clocking Topic .............................................. Texas Instruments Incorporated 133 ...

MMC/SDs. GPIO. Shared RAM. Texas Instruments Incorporated PLL0_SYSCLK6 PLL0_SYSCLK7 PLL0_AUXCLK PLL1_SYSCLK1 PLL1_SYSCLK3 ASYNC3 SPRUH77A – December 2011 Submit Documentation Feedback . HPI. AHCLKR. McASP0.0 PHY.Overview www. RTC. Device Clock Inputs Peripheral Oscillator/PLL RTC JTAG EMAC RMII EMAC MII USB2.com 7. DSP ports.1. System Clock Domains CPU/Device Peripherals DSP ARM RAM/ROM. SPI1 134 Device Clocking Copyright © 2011. In addition to the reference clocks required for the PLLCs and RTC module. Timer64P2/3.0 and USB1. McASP0 serial clock DDR2/mDDR PHY PLL0 input reference clock (not configured by default) ECAPs. eHRPWMs. such as the USB. PSCs. However. Timer64P0/P1.1 Overview This device requires two primary reference clocks: • One reference clock is required for the phase-locked loop controllers (PLLCs) • One reference clock is required for the real-time clock (RTC) module. may also require an input reference clock to be supplied. UART0. PLL0_SYSCLK4 I2C1. All possible input clocks are described in Table 7-1. PRU subsystem EMIFA System Clock Domain PLL0_SYSCLK1 PLL0_SYSCLK2 Fixed Ratio to CPU Clock Required? Yes Yes Default Ratio to CPU Clock 1:1 1:2 PLL0_SYSCLK3 No Yes Yes No Not Applicable Not Applicable Not Applicable Not Applicable 1:3 1:4 1:1 1:6 Not Applicable Not Applicable Not Applicable Not Applicable System configuration (SYSCFG).0. ACLKX. VPIF. USB2. For detailed specifications on clock frequency and voltage requirements. RTCK RMII_MHZ_50_CLK MII_TXCLK.1 I2Cs Timers SATA SPIs uPP VPIF McBSPs McASP0 Input Clock Signal Name OSCIN RTC_XI TCK.ti. Figure 7-1 shows the clocking architecture. The CPU and the majority of the device peripherals operate at fixed ratios of the primary system/CPU clock frequency. see the electrical specifications in your device-specific data manual. these are PLL0_SYSCLK3 and PLL0_SYSCLK7. as listed in Table 7-2. EDMA. SATA_REFCLKN SPIn_CLK UPP_CHn_CLK VPIF_CLKINn CLKSn. ARM INTC ARM EMAC RMII clock I2C0. CLKXn ACLKR. DDR2/mDDR (bus ports). PLLCs. SPI0. SATA. These reference clocks may be sourced from either the on-board oscillator via an externally supplied crystal or by a direct external oscillator input. McBSPs. uPP. EMAC/MDIO. some peripherals. USB1. there are two system clock domains that do not require a fixed ratio to the CPU. CLKRn. Table 7-1. AHCLKX Table 7-2. LCDC. USB2. UART1/2. MII_RXCLK USB_REFCLKIN I2Cn_SCL TM64Pn_IN12 SATA_REFCLKP.

See Section 7.3.3 for EMIFA clocking. See Section 7.1 for USB clocking.6 for McASP clocking.3.3. See Section 7.3. Overall Clocking Diagram PLL0 Multiplier Out SYSCLK3 (/3) SYSCLK6 (/1) SYSCLK1 (/1) ARM DSP ARM INTC SYSCLK4 (/4) System CFG PLL0 Controller PSCs I2C1 CLKSRC USB1.4 for EMAC clocking.5 1 EMIFA (C) 0+ Shared RAM CFGCHIP3[EMA_CLKSRC] ARM RAM/ROM EDMA SPI0 MMC/SDs LCDC HPI USB2.ti.0 (A) SATA uPP UART0 VPIF DDR2/mDDR (B) (E) A B C D E F See Section 7.2 for DDR2/mDDR clocking.1 (A) EXTCLKSRC EMAC/MDIO (D) GPIO I2C0 AUXCLK Timers0/1 RTC PLL Ref CLK SYSCLK2 (/2) SYSCLK2 (/2) PLL1 Controller SYSCLK3 (/3) + Default Mux Selection CLKSRC McASP0 (F) McBSPs eHRPWMs eCAPs SPI1 0+ PRU 1 CFGCHIP3[ASYNC3_CLKSRC] Timers2/3 UART1/2 Div 4.www. See Section 7. SPRUH77A – December 2011 Submit Documentation Feedback Device Clocking Copyright © 2011.3. Texas Instruments Incorporated 135 . See Section 7.3.5 for uPP clocking.com Overview Figure 7-1.

Div2. even though both of these modes would result in a CPU frequency of 200 MHz. Each PLL has two clocking modes: • PLL Bypass • PLL Active When the PLL is in Bypass mode. the lowest PLL multiplier (PLLM) setting should be chosen that achieves the desired frequency.Frequency Flexibility www. Div3. Div3. 1. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . as follows: • OSCIN input frequency is limited to a supported range. NOTE: PLL power consumption increases as the output frequency of the PLL multiplier increases. • The output of the PLL Multiplier must be within the range specified in the device-specific data manual. The combination of the PLL multiplier. respectively. along with the available PLL post-divider modes. and PLLDIV blocks provides flexibility in the frequencies that the system clock domains support. the EXTCLKSRC bit in PLLCTL can be configured to use PLL1_SYSCLK3 as the Bypass mode reference clock. the reference clock supplied on OSCIN passes directly to the system of PLLDIV blocks that creates each of the system clocks. Additional post-divider modes are supported and are documented in the Phase-Locked Loop Controller (PLLC) chapter. These limitations may vary based on core voltage and between devices. the PLL is enabled and the PLL multiplier setting is used to multiply the input clock frequency supplied on the OSCIN pin up to the desired frequency. and Div4 modes are shown here as an example. When the PLL operates in Active mode. Div2. For PLL0 only. NOTE: The above limitations are provided here as an example and are used to illustrate the recommended configuration of the PLL controller. Table 7-3 shows examples of possible PLL multiplier settings.com 7. The Div1. This means that when the PLL is in Bypass mode. See the device-specific data manual for more details. Each SYSCLKn has a PLLDIVn block associated with it. This flexibility does have limitations. and 3.ti. the reference clock supplied on OSCIN serves as the clock source from which all of the system clocks (SYSCLK1 to SYSCLK7) are derived. if 200 MHz is the desired CPU operating frequency and the OSCIN frequency is 25 MHz. lower power consumption is achieved by choosing a PLLM setting of ×16 and a post-divider (POSTDIV) setting of /2 instead of a PLLM setting of ×24 and a POSTDIV setting of /3. • The output of each PLLDIV block must be less than or equal to the maximum device frequency specified in the device-specific data manual. For example. It is this multiplied frequency that all system clocks are derived from in PLL Active mode. For Div1. the RATIO field would be programmed to 0. The output of the PLL multiplier passes through a post divider (POSTDIV) block and then is applied to the system of PLLDIV blocks that creates each of the system clock domains (SYSCLK1 to SYSCLK7). 2. 136 Device Clocking Copyright © 2011. and Div4 modes. The PLL post-divider modes are defined by the value programmed in the RATIO field of the PLL post-divider control register (POSTDIV).2 Frequency Flexibility There are two PLLs on the device with similar architecture and behavior. See the Phase-Locked Loop Controller (PLLC) chapter for more details on the PLL. To decrease PLL power consumption. POSTDIV.

The USB2. The 12 MHz clock is derived from the 48 MHz clock. then the USB2. See Table 7-4.www.1 subsystem is used and the 48 MHz clock input is sourced from the USB2. the USB2.0 PHY is prevented from stopping the 48 MHz clock during USB SUSPEND. The USB0PHY_PLLON bit in CFGCHIP2 controls the USB2.1 subsystem can be sourced from either the USB_REFCLKIN or from the 48 MHz clock provided by the USB2. The reference clock input to the USB2.0 subsystem is selected by programming the USB0PHYCLKMUX bit in the chip configuration 2 register (CFGCHIP2) of the System Configuration Module. The USB_REFCLKIN source should be selected when it is not possible (such as when specific audio rates are required) to operate the device at one of the allowed input frequencies to the USB2. The USB2. This reference clock can be sourced from either the USB_REFCLKIN pin or from the AUXCLK of the system PLL. When the USB0PHY_PLLON bit is set to 1.0 module.0 PHY. The 48 MHz clock required by the USB1.1 USB Clocking Figure 7-2 shows the clock connections for the USB2. NOTE: If the USB1. The USB1.0 subsystem peripheral bus clock is sourced from PLL0_SYSCLK2.0 PHY.1 subsystem peripheral bus clock is sourced from PLL0_SYSCLK4. SPRUH77A – December 2011 Submit Documentation Feedback Device Clocking Copyright © 2011. Texas Instruments Incorporated 137 .ti. the USB2.0 subsystem.0 subsystem requires a reference clock for its internal PLL.1 subsystem requires both a 48 MHz (CLK48) and a 12 MHz (CLK12) clock input. The CLK48 source is selected by programming the USB1PHYCLKMUX bit in CFGCHIP2 of the System Configuration Module.3 Peripheral Clocking 7. allowing or preventing it from stopping the 48 MHz clock during USB SUSPEND.5 105 100 7.0 PHY.0 PHY is allowed to stop the 48 MHz clock during USB SUSPEND. when the USB0PHY_PLLON bit is cleared to 0. Example PLL Frequencies OSCIN Frequency 20 24 25 30 20 24 25 30 25 PLL Multiplier 30 25 24 20 25 20 18 14 16 Multiplier Frequency 600 MHz 600 MHz 600 MHz 600 MHz 500 MHz 480 MHz 450 MHz 420 MHz 400 MHz Div1 600 600 600 600 500 480 450 420 400 Div2 300 300 300 300 250 240 225 210 200 Div3 200 200 200 200 167 160 150 140 133 Div4 150 150 150 150 125 120 112. The USB1.0 must be configured to always generate the 48 MHz clock.com Peripheral Clocking Table 7-3.3.

PLL0_AUXCLK must be 12. 26. 0 1 USB_REFCLKIN USB_REFCLKIN 1 0 PLL0_AUXCLK CLK48MHz output from USB2.com Figure 7-2. 48.Peripheral Clocking www.0 PHY Additional Conditions USB_REFCLKIN must be 12. 38. USB_REFCLKIN must be 48 MHz.2. 24. PLL0_AUXCLK must be 12. 19. The PLL inside the USB2. 26. 13.2. 20. 13. USB_REFCLKIN must be 48 MHz. The PLL inside the USB2.0 PHY can be configured to accept any of these input clock frequencies. USB Clock Multiplexing Options CFGCHIP2. or 40 MHz.0 PHY can be configured to accept any of these input clock frequencies.4. 13.0 PHY 0 1 CFGCHIP2[USB1PHYCLKMUX] /4 CLK48 USB 1.4.0 Subsystem (USB0) CLK48MHz From USB2.4. 24. The PLL inside the USB2. 19. 48.1 Subsystem (USB1) CLK12 Table 7-4. USB0PHYCLKMUX USB1PHYCLKMUX bit bit 0 0 USB2.0 Clock Source USB_REFCLKIN USB1.0 PHY can be configured to accept any of these input clock frequencies.0 PHY 1 1 PLL0_AUXCLK USB_REFCLKIN 138 Device Clocking Copyright © 2011.1 Clock Source CLK48MHz output from USB2.0 PHY can be configured to accept this input clock frequency. 38. The PLL inside the USB2. 19. 48. or 40 MHz.2. or 40 MHz. 20. 24. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . USB Clocking Diagram USB_ AUXCLK REFCLKIN CFGCHIP2[USB0PHYCLKMUX] 1 0 USB 2.ti. 38. 20. CFGCHIP2. 26.

• 2X_CLK is sourced from PLL1_SYSCLK1. This clock domain is clocked at the rate of the external DDR2/mDDR memory. This allows clock gating of the majority of the logic in the DDR2/mDDR memory controller via the LPSC while still providing a clock on the DDR_CLK and DDR_CLK. Table 7-5 shows example PLL register settings based on the OSCIN reference clock frequency of 25 MHz. 2X_CLK/2. NOTE: DDR_CLK and DDR_CLK are output clock signals. Texas Instruments Incorporated 139 .com Peripheral Clocking 7.3. write FIFO. the following observations are made: • To achieve the maximum frequency (150 MHz) supported by the DDR2/mDDR memory controller and the typical CPU frequency of 300 MHz. the output of the PLL multiplier should be set to be 300 MHz and the DDR_CLK source should be set to PLL1_SYSCLK1. If the DDR2/mDDR memory controller is not in use and the DDR_CLK and DDR_CLK are used in the application as a free running clock that could be used by an FPGA or for some other purpose.www. VCLK drives the interface to the peripheral bus. SPRUH77A – December 2011 Submit Documentation Feedback Device Clocking Copyright © 2011. and read FIFO of the DDR2/mDDR memory controller. a higher clock frequency can be achieved by selecting SYSCLK1 as the clock source for 2X_CLK. From this. • For certain PLL1 multiplier and PLL1 post-divider control register (POSTDIV) settings. • The frequency of the PLL1 direct output clock is fixed at the output frequency of the PLL1 multiplier block. then 2X_CLK should be used as the source for DDR_CLK and DDR_CLK and VCLK should be gated off. 2X_CLK clock is again divided down by 2 in the DDR PHY controller to generate a clock called MCLK. • The PLLDIV1 block that sets the divider ratio for SYSCLK1 can be changed to achieve various clock frequencies. From these example configurations.ti. The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped registers.2 DDR2/mDDR Memory Controller Clocking The DDR2/mDDR memory controller requires two input clocks to source VCLK and 2X_CLK (see Figure 7-3): • VCLK is sourced from PLL0_SYSCLK2/2 that clocks the command FIFO.

ti.2 for explanation of POSTDIV divider modes. 140 Device Clocking Copyright © 2011. DDR2/mDDR Memory Controller Clocking Diagram On Chip PLL0_SYSCLK2/2 LPSC #6 DDR2/mDDR Memory Controller DDR_CLK DDR_CLK VCLK PLL1_SYSCLK1 2X_CLK DDR PHY MCLK Table 7-5.Peripheral Clocking www.com Figure 7-3. DDR2/mDDR Memory Controller MCLK Frequencies PLL1 Multiplier Register Setting 18h 15h 14h PLL1 Multiplier Frequency 600 MHz 528 MHz 504 MHz PLL1 Post Divider Mode (1) OSCIN Frequency 24 24 24 (1) PLL1 POSTDIV Output Frequency 300 MHz 264 MHz 252 MHz PLL1 PLLDIV1 Register Setting 8000h 8000h 8000h PLL1_SYSCLK1 300 MHz 264 MHz 252 MHz MCLK 150 MHz 132 MHz 126 MHz Div2 Div2 Div2 See Section 7. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

3 EMIFA Clocking EMIFA requires a single input clock source. Figure 7-4.5 MHz 66.ti.6 MHz 100 MHz 75 MHz 56. • The PLLDIV3 block that sets the divider ratio for PLL0_SYSCLK3 can be changed to achieve various clock frequencies. is not supported. EMIFA Clocking Diagram PLL Controller LPSC EMIFA SYSCLK3 0 DIV4P5 CLK 1 CFGCHIP3[EMA_CLKSRC] Table 7-6. SPRUH77A – December 2011 Submit Documentation Feedback Copyright © 2011.6 MHz 100 MHz 66.3. EMIFA Frequencies OSCIN Frequency 25 PLL Multiplier Register Multiplier Setting Frequency 24 600 MHz Post Divider Mode (1) Div2 Div3 Div4 25 18 450 MHz Div2 Div3 Div4 25 16 400 MHz Div2 Div3 Div4 (1) (2) POSTDIV Output Frequency 300 MHz 200 MHz 150 MHz 225 MHz 150 MHz 112.com Peripheral Clocking 7.5. the output of the PLL multiplier should be set to 600 MHz and the EMA_CLK source should be set to PLL0_SYSCLK3 with the PLLDIV3 register set to 3. From these example configurations. The 133 MHz is outside of the supported frequency range for EMIFA and. The EMA_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the System Configuration Module controls whether PLL0_SYSCLK3 or DIV4P5 is selected as the clock source for EMIFA. the following observations can be made: • To achieve the maximum frequency (100 MHz) supported by EMIFA and the typical CPU frequency of 300 MHz. Table 7-6 shows example PLL register settings and the resulting DIV4P5 and PLL0_SYSCLK3 frequencies based on the OSCIN reference clock frequency of 25 MHz.5 MHz 200 MHz 133 MHz 100 MHz DIV4P5 133 MHz (2) 133 MHz (2) 133 MHz (2) 100 MHz 100 MHz 100 MHz 89 MHz 89 MHz 89 MHz PLLDIV3 Register Setting 2 2 1 1 3 2 1 1 0 2 1 1 0 PLL0_SYSCLK3 100 MHz 66. • The frequency of the DIV4P5 clock is fixed at the output frequency of the PLL multiplier block divided by 4. Texas Instruments Incorporated Device Clocking 141 . The EMIFA clock can be sourced from either PLL0_SYSCLK3 or DIV4P5 (see Figure 7-4).3 MHz 112. Selecting the appropriate clock source for EMIFA is determined by the desired clock rate.www.5 MHz 100 MHz See Section 7. The maximum frequency supported by EMIFA is 100 MHz. therefore.2 for explanation of POSTDIV divider modes.3 MHz 75 MHz 75 MHz 56.

com 7. PLL0_SYSCLK7 is driven out on the RMII_MHZ_50_CLK pin. the MII_TXCLK and MII_RXCLK signals must be provided from an external source. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .4 EMAC Clocking The EMAC module sources its peripheral bus interface reference clock from PLL0_SYSCLK4 that is at a fixed ratio of the CPU clock. 142 Device Clocking Copyright © 2011.ti. Table 7-7 shows example PLL register settings and the resulting PLL0_SYSCLK7 frequencies based on the OSCIN reference clock frequency of 25 MHz. the RMII 50 MHz reference clock is sourced either from an external clock on the RMII_MHZ_50_CLK pin or from PLL0_SYSCLK7 (as shown in Figure 7-5). The external clock requirement for EMAC varies with the interface used. EMAC Clocking Diagram On Chip PLL Controller 0 LPSC EMAC SYSCLK4 SYSCLK7 50 MHz Reference Clock PINMUX15[3:0] 1000 0000 3-State 0000 1000 RMII_MHZ_50_CLK Signal NOTE: The SYSCLK7 output clock does not meet the RMII reference clock specification of 50 MHz +/-50 ppm. Figure 7-5. Also. • PINMUX15_3_0 = 8h: enables sourcing of the 50 MHz reference clock from PLL0_SYSCLK7. When the RMII interface is active. The PINMUX15_3_0 bits in the pin multiplexing control 15 register (PINMUX15) of the System Configuration Module control this clock selection: • PINMUX15_3_0 = 0: enables sourcing of the 50 MHz reference clock from an external source on the RMII_MHZ_50_CLK pin.Peripheral Clocking www.3. When the MII interface is active.

Texas Instruments Incorporated 143 .2 for explanation of POSTDIV divider modes.www. SPRUH77A – December 2011 Submit Documentation Feedback Device Clocking Copyright © 2011.ti. Certain PLL configurations do not support a 50 MHz clock on PLL0_SYSCLK7. EMAC Reference Clock Frequencies OSCIN Frequency 25 PLL Multiplier Register Setting 24 Multiplier Frequency 600 MHz Post Divider Mode (1) Div2 Div3 Div4 25 18 450 MHz Div2 Div3 Div4 (1) (2) POSTDIV Output Frequency 300 MHz 200 MHz 150 MHz 225 MHz 150 MHz 112.com Peripheral Clocking Table 7-7.5 MHz PLLDIV7 Register Setting 5 3 2 2 PLL0_SYSCLK7 50 MHz 50 MHz 50 MHz Not Applicable (2) 50 MHz Not Applicable (2) See Section 7.

the uPP transmit clock speed cannot exceed the uPP module clock speed. The uPP subsystem requires a module clock to drive its internal logic and a transmit clock to drive I/O signals in transmit mode. or the externally driven UPP_2xTXCLK pin. uPP Transmit Clock Selection CFGCHIP3.3. Figure 7-6.ASYNC3_CLKSRC bit 0 1 x uPP Transmit Clock Source PLL0_SYSCLK2 PLL1_SYSCLK2 UPP_2xTXCLK pin 144 Device Clocking Copyright © 2011. uPP Clocking Diagram Module Clock PLL0_SYSCLK2 LPSC CFGCHIP3[UPP_TX_CLKSRC] uPP PLL0_SYSCLK2 0 0 PLL1_SYSCLK2 1 1 Transmit Clock CFGCHIP3[ASYNC3_CLKSRC] UPP_2xTXCLK pin Table 7-8. Regardless of the source. Table 7-8 lists the register values that select each of the three possible clock sources. The module clock is always sourced by PLL0_SYSCLK2. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .UPP_TX_CLKSRC bit 0 0 1 CFGCHIP3.ti. The transmit clock source is selected by the UPP_TX_CLKSRC and ASYNC3_CLKSRC bits in the chip configuration 3 register (CFGCHIP3) of the System Configuration Module. The module clock speed must be greater than or equal to the transmit clock speed.5 uPP Clocking Figure 7-6 displays the clock connections for the uPP module.Peripheral Clocking www. PLL1_SYSCLK2.com 7. The transmit clock is sourced by three different clocks: PLL0_SYSCLK2 (default).

and AHCLKXCTL. Internally.com Peripheral Clocking 7. If an external clock is driven into a high-frequency master clock (AHCLKX or AHCLKR).www. When the internal clock source option is selected. AHCLKRCTL.3. The transmit and receive clocks are sourced internally or externally by configuring the McASP clock control registers ACLKRCTL. Texas Instruments Incorporated 145 .ti. McASP Clocking Diagram On Chip CFGCHIP3[ASYNC3_CLKSRC] PLL0_SYSCLK2 PLL1_SYSCLK2 0 LPSC 1 Module Clock McASP0 PLL0_AUXCLK TX/RX Reference Clock Clock Generator Frame Sync Generator ACLKX AHCLKX ACLKR AHCLKR AFSX AFSR SPRUH77A – December 2011 Submit Documentation Feedback Device Clocking Copyright © 2011. the transmit and receive clocks are derived from the PLL0_AUXCLK clock through programmable dividers.6 McASP Clocking As shown in Figure 7-7. the McASP peripheral requires multiple clock sources. the module clock is selected to be either PLL0_SYSCLK2 or PLL1_SYSCLK2 by configuring the ASYNC3_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the System Configuration Module. Figure 7-7. ACLKXCTL. the McASP module allows for a mixed clock mode where the associated lower frequency clock (ACLKX or ACLKR) can be derived from the high-frequency master clock through a programmable divider.

Peripherals Peripherals Contained within Group RTC Peripheral Group RTC Fixed-Frequency Peripherals Peripheral Group Definition Operates off of a dedicated 32 kHz crystal oscillator. if the PLL0 frequency changes. McASP0 McBSPs SPI0 SPI1 I2C1 EMAC uPP VPIF USBs 146 Device Clocking Copyright © 2011. The peripherals can be divided into the following groups. Most synchronous peripherals have internal dividers so they can generate their required clock frequencies.Peripheral Clocking www.7 I/O Domains The I/O domains refer to the frequencies of the peripherals that communicate through device pins.3. Table 7-9. It is not necessarily possible to obtain these frequencies from the on-chip clock generation circuitry.com 7. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . depending upon their clock requirements. Timer64P0/P1 fixed-frequency peripherals have a I2C0 fixed-frequency. They are fed the AUXCLK directly from the oscillator input. as shown in Table 7-9.ti. Source of Peripheral Clock — — — As the name suggests. there are frequency requirements for a peripheral pin interface that are set by an outside standard and must be met. In many cases. MMC/SDs HPI UART0 LCDC GPIO Synchronous Peripherals PLL0_SYSCLK2 PLL0_SYSCLK2 PLL0_SYSCLK2 PLL0_SYSCLK2 PLL0_SYSCLK4 Asynchronous Peripherals eCAPs eHRPWMs UART1/2 Timer64P2/P3 EMIFA SATA DDR2/mDDR ASYNC3 ASYNC3 ASYNC3 ASYNC3 DIV_4P5 or PLL0_SYSCLK3 Peripheral Serial Clock PLL1_SYSCLK1 or PLL1 Direct Output ASYNC3 or Peripheral Serial Clock ASYNC3 or Peripheral Serial Clock PLL0_SYSCLK2 or Peripheral Serial Clock ASYNC3 or Peripheral Serial Clock PLL0_SYSCLK4 or Peripheral Serial Clock PLL0_SYSCLK4 or RMII_MHZ_50_CLK PLL0_SYSCLK2 or Peripheral Serial Clock PLL0_SYSCLK2 or Peripheral Serial Clock USB_REFCLKIN or AUXCLK Synchronous/Asynchronous Peripherals Synchronous/asynchronous peripherals can be run with either internally generated synchronous clocks. so the frequencies must be obtained from external sources and are asynchronous to the CPU frequency by definition. or externally generated asynchronous clocks. The peripheral system clock frequency changes accordingly. Synchronous peripherals have their frequencies derived from the CPU clock frequency. Asynchronous peripherals are not required to operate at a fixed ratio of the CPU clock.

................................................. Texas Instruments Incorporated 147 ..........................................................................2 8................................................................................................. Page 8..... 148 PLL Controllers ......................................................................Chapter 8 SPRUH77A – December 2011 Phase-Locked Loop Controller (PLLC) Topic ...............................................................................3 Introduction ........ 153 SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011.......................1 8....... 148 PLLC Registers ......

PLL0 provides the primary system clock to the device.3. Dn Various other control signals supported are: • PLL multiplier: PLLM • Software-programmable PLL bypass: PLLEN 8. which results in a PLL multiplier of 20×. PLLC0 and PLLC1. …. the system operates in bypass mode by default and the system clock (OSCIN) is provided directly from an input reference clock (square wave or internal oscillator) selected by the CLKMODE bit in PLLCTL. The POSTDIV has a default value of /2. PLL1 operations are software programmable through the PLL controller 1 (PLLC1) registers. 148 Phase-Locked Loop Controller (PLLC) Copyright © 2011. The PLLM defaults to a multiplier value of 13h at power-up.2 PLL Controllers PLL0 and PLL1 share the same internal architecture so they also share the same approach for mode configuration. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . These PLL controllers provide clock signals to most of the components of the device through various clock dividers.ti. PLL0 and PLL1 are powered-down/disabled and must be powered-up by software through the PLLPWRDN bit in their respective PLL control register (PLLCTL). The PLL0 and PLL1 output clocks may be divided-down for slower device operation using the PLL post-divider control register (POSTDIV). Both PLL0 and PLL1 provide the following: • Glitch-free transitions when clock settings are changed • Domain clock alignment • Clock gating • PLL power-down The clock outputs generated by the PLL controllers are: • Domain clocks: PLL0_SYSCLK[1-7] and PLL1_SYSCLK[1-3] • Auxiliary clock (PLL0_AUXCLK) from the PLLC0 reference clock source Dividers that can be used for the PLL controllers are: • Pre-PLL divider: PREDIV • Post-PLL divider: POSTDIV • SYSCLK divider: D1. Figure 8-1 shows the PLLC0 and PLLC1 architecture.com 8. software can switch the device to PLL mode operation (set the PLLEN bit in PLLCTL to 1).1 Introduction This device has two phase-locked loop (PLL) controllers.Introduction www. but may be modified through software (using the RATIO field in POSTDIV) to achieve lower device operation frequencies. The default PLLM and POSTDIV settings produce a 300-MHz PLL output clock when given a 30-MHz clock source. The PLL controller registers are listed in Section 8. Before each PLL completes the power-up and frequency-lock sequence. The PLL0 and PLL1 multipliers are controlled by their respective PLL multiplier control register (PLLM). PLL0 operations are software programmable through the PLL controller 0 (PLLC0) registers. PLL1 provides the reference clocks to various peripherals (including DDR2/mDDR) and may generate clocks that are asynchronous to the PLL0 clocks. After the power-up and frequency-lock sequences are complete. At power-up.

5 OSCDIV PLLC0 OBSCLK (CLKOUT Pin) SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 SYSCLK6 SYSCLK7 PLLC1 OBSCLK OCSEL[OCSRC] PLLCTL[PLLEN] 0 PLL PLLM POSTDIV 1 PLL Controller 1 PLLDIV2 (/2) PLLDIV3 (/3) PLLDIV1 (/1) SYSCLK2 SYSCLK3 SYSCLK1 DDR2/mDDR Internal Clock Source SYSCLK1 SYSCLK2 SYSCLK3 14h 17h 18h 19h OSCDIV PLLC1 OBSCLK OCSEL[OCSRC] SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011.com PLL Controllers Figure 8-1. Texas Instruments Incorporated 149 . PLLC Structure PLLCTL[EXTCLKSRC] PLLCTL[CLKMODE] PLL1_SYSCLK3 1 PLLCTL[PLLEN] 0 Square Wave Crystal 0 1 PREDIV 0 PLLM PLL POSTDIV 1 PLLDIV2 (/2) PLLDIV4 (/4) PLLDIV5 (/3) PLLDIV6 (/1) PLLDIV7 (/6) PLLDIV3 (/3) 0 DIV4.ti.5 1 SYSCLK2 SYSCLK4 SYSCLK5 SYSCLK6 SYSCLK7 SYSCLK3 EMIFA Internal Clock Source PLLDIV1 (/1) SYSCLK1 PLL Controller 0 OSCIN DEEPSLEEP Enable CFGCHIP3[EMA_CLKSRC] AUXCLK 14h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh DIV4.www.

150 Phase-Locked Loop Controller (PLLC) Copyright © 2011. HPI. but can be configured to use a /4. Timer64P2/3. I2C1. USB2. the duty cycle will be 44. but the device must maintain the 1:2:4 clock ratios between the clock domains. SATA.com 8.0 PHY. DDR2/mDDR (bus ports). SPI1 (all these modules use PLL0_SYSCLK2 by default) PLL0 input reference clock (not configured by default) PLL1_SYSCLK3 (4) (1) /3 or disabled No (2) (3) (4) The divide values in PLLC0 for PLL0_SYSCLK1/PLL0_SYSCLK6. PLLCs. McBSPs. When this /4. System PLLC Output Clocks Output Clock PLL0_SYSCLK1 PLL0_SYSCLK2 Used by PLLC0 (1) DSP ARM RAM/ROM. PLLC0 and PLLC1 generate several clocks for use by the various processors and modules. ARM INTC Not used ARM EMAC RMII clock I2C0. Instead. the resulting clock will not have a 50% duty cycle. McASP0 serial clock Observation clock (OBSCLK) source PLLC1 PLL1_SYSCLK1 PLL1_SYSCLK2 (3) Default Ratio (relative to PLLn_SYSCLK1) /1 /2 Fixed Clock Ratio Yes Yes PLL0_SYSCLK3 (2) PLL0_SYSCLK4 /3 /4 No Yes PLL0_SYSCLK5 PLL0_SYSCLK6 PLL0_SYSCLK7 PLL0_AUXCLK PLL0_OBSCLK /3 /1 /6 PLL bypass clock Pin configurable /1 or disabled /2 or disabled No Yes No No No No No DDR2/mDDR PHY ECAPs. GPIO. eHRPWMs.5 divide-down of PLL0_PLLOUT instead of PLL0_SYSCLK3 by programming the EMA_CLKSRC and DIV45PENA bits in the chip configuration 3 register (CFGCHIP3) of the system configuration (SYSCFG) module. RTC.5 value is used. and gating for the device system clocks. See the device datasheet for the maximum operating frequencies.4%. USB2. The PLL0 input clock source can be configured to use PLL1_SYSCLK3 instead of OSCIN by programming the EXTCLKSRC bit in the PLLC0 PLL control register (PLLCTL). multiplier. UART0. Shared RAM. DSP ports.2.5 that can be used for EMIFA clock generation. the reset controller in PLLC0 manages reset propagation through the device. uPP. The PLLOUT stage in PLLC0 and PLLC1 is capable of providing frequencies greater than what the SYSCLK dividers can handle. and PLL0_SYSCLK4 can be changed for power savings. PLL0_SYSCLK2. clock alignment. These reference clocks are summarized in Table 8-1.1. UART1/2. alignment.1 Device Clock Generation The PLL controllers (PLLC0 and PLLC1) manage the clock ratios.ti. PLLC0 supports an additional post-divider value of /4. The EMIFA uses PLL0_SYSCLK3 by default. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . The ASYNC3 modules use PLL0_SYSCLK2 by default. Timer64P0/P1. The PLL1 input clock source will also be OSCIN. and test points. PSCs. Additionally. but all these modules can be configured as a group to use PLL1_SYSCLK2 by programming the ASYNC3_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the system configuration (SYSCFG) module. Table 8-1. LCDC. VPIF. MMC/SDs. Various PLL mode attributes such as pre-division. McASP0. The POSTDIV stage should be programmed to keep the input to the SYSCLK dividers within operating limits. EMAC/MDIO. and post-division are software programmable through the PLL controller registers. EDMA. Some output clock dividers require fixed values so that clock ratios between various device components are maintained regardless of PLL or bypass frequency.PLL Controllers www. USB1. PRU EMIFA System configuration (SYSCFG).0. SPI0.

NOTE: The PLL_MASTER_LOCK bit in CFGCHIP0 and the PLL1_MASTER_LOCK bit in CFGCHIP3 default to unlocked after reset. follow the sequence in Section 8. Write an incorrect key value to the KICK0R and KICK1R registers.1 for information on unlocking the PLL controller registers.2. 2. Clear the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3. • If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0).2. This provides protection from stopping modules when the module clocks are disabled. 8.4. Because the SYSCFG module has its own lock mechanism.2.2. the PLL_MASTER_LOCK bit in the chip configuration 0 register (CFGCHIP0) locks PLLC0. For example. the PLL lock bits can only be modified while in a privileged mode.2.2. as required. the PLL1_MASTER_LOCK bit in the chip configuration 3 register (CFGCHIP3) locks PLLC1. To modify the PLL controller registers. Write the correct key values to KICK0R and KICK1R registers. 5. but the PLLEN bit in PLLCTL is cleared to 0 (bypass mode) and the PLLDIVx registers are reset to default values.2. SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. The PLLs are not powered down after a Warm Reset (RESET). Refer to the appropriate subsection on how to program the PLL clocks: • If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1). 3.2. See Section 8.2.3 to change the PLL multiplier. • When set. the SYSCFG module must be unlocked first by writing to the KICK0R and KICK1R registers before the PLL lock bits can be cleared.2 Steps for Programming the PLLs Note that there is a lock mechanism implemented to protect the PLL controller registers.1 Locking/Unlocking PLL Register Access A lock mechanism is implemented on the device to prevent inadvertent writes to the PLL controller registers. so the following procedure is only required if the PLLs have been locked (set to 1). Like the KICK registers.com PLL Controllers 8. Configure the desired PLL controller register values.2. the watchdog timer that runs on the PLL0_AUXCLK will stop if this PLL clock is unintentionally disabled.2. Note that the PLLs are powered down after a Power-on Reset (POR). follow the sequence in Section 8. The PLL lock bits are located within the system configuration (SYSCFG) module: • When set.2. Set the PLL_MASTER_LOCK bit in CFGCHIP0 and/or the PLL1_MASTER_LOCK bit in CFGCHIP3. Texas Instruments Incorporated 151 . See the System Configuration (SYSCFG) Module chapter for information on privilege type and the KICK0R and KICK1R registers. 4.ti.www. follow the full PLL initialization procedure in Section 8. use the following sequence: 1. • If the PLL is already running at a desired multiplier and only the SYSCLK dividers will be updated. as required.

(d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change). 9.ti. Clear the PLLRST bit in PLLCTL to 0 (resets PLL). 7. (b) For PLL0 only. 8. 3. See the device-specific data manual for PLL lock time. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset).2. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Switch the PLL to bypass mode: (a) Clear the PLLENSRC bit in PLLCTL to 0 (allows PLLEN bit to take effect). 6. Clear the PLLPWRDN bit in PLLCTL to 0 (brings PLL out of power-down mode). program PLLDIVn registers to change the SYSCLKn divide values: (a) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in progress). Switch the PLL to bypass mode: (a) Clear the PLLENSRC bit in PLLCTL to 0 (allows PLLEN bit to take effect). Program the desired multiplier value in PLLM. (b) Program the RATIO field in PLLDIVn. as needed. (d) Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode. 4.PLL Controllers www. Wait for the PLL to lock. 152 Phase-Locked Loop Controller (PLLC) Copyright © 2011. as needed. Program the desired multiplier value in PLLM. Program the POSTDIV. (b) Program the RATIO field in PLLDIVn. 3. (c) Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition). select the clock source by programming the EXTCLKSRC bit in PLLCTL. 5. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset). Clear the PLLRST bit in PLLCTL to 0 (resets PLL). (d) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change). 7. program PLLDIVn registers to change the SYSCLKn divide values: (a) Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in progress). (c) Clear the PLLEN bit in PLLCTL to 0 (PLL in bypass mode).3 Changing PLL Multiplier If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0). Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode). If desired. 2.2. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode). Program the CLKMODE bit in PLLC0 PLLCTL. (d) Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode. (c) Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition). 2. If desired. (b) For PLL0 only. 6.2 Initializing PLL Mode from PLL Power Down If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1). 8. See the device-specific data manual for PLL lock time.2.2. (c) Clear the PLLEN bit in PLLCTL to 0 (PLL in bypass mode).com 8. Wait for the PLL to lock. select the clock source by programming the EXTCLKSRC bit in PLLCTL. perform the following procedure to change the PLL multiplier: 1. 4. perform the following procedure to initialize the PLL: 1. Program the POSTDIV. 5.

PLL Controller 0 (PLLC0) Registers Address 01C1 1000h 01C1 10E4h 01C1 10E8h 01C1 1100h 01C1 1104h 01C1 1110h 01C1 1114h 01C1 1118h 01C1 111Ch 01C1 1120h 01C1 1124h 01C1 1128h 01C1 1138h 01C1 113Ch 01C1 1140h 01C1 1144h 01C1 1148h 01C1 114Ch 01C1 1150h 01C1 1160h 01C1 1164h 01C1 1168h 01C1 116Ch 01C1 11F0h 01C1 11F4h Acronym REVID RSTYPE RSCTRL PLLCTL OCSEL PLLM PREDIV PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV POSTDIV PLLCMD PLLSTAT ALNCTL DCHANGE CKEN CKSTAT SYSTAT PLLDIV4 PLLDIV5 PLLDIV6 PLLDIV7 EMUCNT0 EMUCNT1 Register Description PLLC0 Revision Identification Register PLLC0 Reset Type Status Register PLLC0 Reset Control Register PLLC0 Control Register PLLC0 OBSCLK Select Register PLLC0 PLL Multiplier Control Register PLLC0 Pre-Divider Control Register PLLC0 Divider 1 Register PLLC0 Divider 2 Register PLLC0 Divider 3 Register PLLC0 Oscillator Divider 1 Register PLLC0 PLL Post-Divider Control Register PLLC0 PLL Controller Command Register PLLC0 PLL Controller Status Register PLLC0 Clock Align Control Register PLLC0 PLLDIV Ratio Change Status Register PLLC0 Clock Enable Control Register PLLC0 Clock Status Register PLLC0 SYSCLK Status Register PLLC0 Divider 4 Register PLLC0 Divider 5 Register PLLC0 Divider 6 Register PLLC0 Divider 7 Register PLLC0 Emulation Performance Counter 0 Register PLLC0 Emulation Performance Counter 1 Register Section Section 8.3 Section 8.20 Section 8. Texas Instruments Incorporated Phase-Locked Loop Controller (PLLC) 153 .25 Section 8. 8.3.28 Section 8.2.3.15 Section 8.3.3.3.21 Section 8.3.34 Section 8.7 Section 8.3.3.3.ti.36 Section 8.10 Section 8. perform the following procedure to change the SYSCLK divider values: 1.2.3.30 Section 8.3. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (indicates that no operation is currently in progress).5 Section 8.3.3.3.17 Section 8.3.3.www. Table 8-2.24 Section 8.26 Section 8.com PLLC Registers 8.3 PLLC Registers Table 8-2 lists the memory-mapped registers for the PLLC0 and Table 8-3 lists the memory-mapped registers for the PLLC1. Program the RATIO field in PLLDIVn. Set the GOSET bit in PLLCMD to 1 (initiates a new divider transition).4 Changing SYSCLK Dividers If the PLL is already operating at the desired multiplier mode.3.3.3.18 Section 8. Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of divider change).3.1 Section 8.13 Section 8.37 SPRUH77A – December 2011 Submit Documentation Feedback Copyright © 2011.3. 2.3.4 Section 8.9 Section 8.23 Section 8.11 Section 8.3.32 Section 8.3. 3.19 Section 8. 4.3.

37 8.3.14 Section 8. PLLC0 Revision Identification Register (REVID) 31 REV R-4481 3C00h LEGEND: R = Read only.3.12 Section 8.com Table 8-3.35 Section 8.3.3.3.3.3.3.2 Section 8.36 Section 8. PLLC0 Revision Identification Register (REVID) Field Descriptions Bit 31-0 Field REV Value 4481 3C00h Description Peripheral revision ID for PLLC0.25 Section 8.3.6 Section 8.3.31 Section 8.3.3.PLLC Registers www.3.ti.8 Section 8. 154 Phase-Locked Loop Controller (PLLC) Copyright © 2011.29 Section 8.3.16 Section 8.3.3.1 PLLC0 Revision Identification Register (REVID) The PLLC0 revision identification register (REVID) is shown in Figure 8-2 and described in Table 8-4.27 Section 8.23 Section 8.3. Figure 8-2.3. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .9 Section 8.22 Section 8.33 Section 8.3. -n = value after reset 0 Table 8-4. PLL Controller 1 (PLLC1) Registers Address 01E1 A000h 01E1 A100h 01E1 A104h 01E1 A110h 01E1 A118h 01E1 A11Ch 01E1 A120h 01E1 A124h 01E1 A128h 01E1 A138h 01E1 A13Ch 01E1 A140h 01E1 A144h 01E1 A148h 01E1 A14Ch 01E1 A150h 01E1 A1F0h 01E1 A1F4h Acronym REVID PLLCTL OCSEL PLLM PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV POSTDIV PLLCMD PLLSTAT ALNCTL DCHANGE CKEN CKSTAT SYSTAT EMUCNT0 EMUCNT1 Register Description PLLC1 Revision Identification Register PLLC1 Control Register PLLC1 OBSCLK Select Register PLLC1 PLL Multiplier Control Register PLLC1 Divider 1 Register PLLC1 Divider 2 Register PLLC1 Divider 3 Register PLLC1 Oscillator Divider 1 Register PLLC1 PLL Post-Divider Control Register PLLC1 PLL Controller Command Register PLLC1 PLL Controller Status Register PLLC1 Clock Align Control Register PLLC1 PLLDIV Ratio Change Status Register PLLC1 Clock Enable Control Register PLLC1 Clock Status Register PLLC1 SYSCLK Status Register PLLC1 Emulation Performance Counter 0 Register PLLC1 Emulation Performance Counter 1 Register Section Section 8.24 Section 8.

www. Power on reset. RSTYPE latches the highest priority reset source. PLLC1 Revision Identification Register (REVID) 31 REV R-4481 4400h LEGEND: R = Read only. RSTYPE records the reset source that deasserts last. PLLC1 Revision Identification Register (REVID) Field Descriptions Bit 31-0 Field REV Value 4481 4400h Description Peripheral revision ID for PLLC1. If multiple reset sources are asserted simultaneously. External warm reset. Figure 8-4.3. Figure 8-3. Texas Instruments Incorporated 155 .ti. -n = value after reset 3 2 PLLSWRST R-0 1 XWRST R-0 0 POR R-0 16 Table 8-6. 8. External warm reset was not the last reset to occur. PLL soft reset was not the last reset to occur.3 Reset Type Status Register (RSTYPE) The reset type status register (RSTYPE) latches the cause of the last reset. Reset Type Status Register (RSTYPE) Field Descriptions Bit 31-3 2 Field Reserved PLLSWRST 0 1 1 XWRST 0 1 0 POR 0 1 Value 0 Description Reserved PLL software reset. Power On Reset (POR) was not the last reset to occur. PLL soft was the last reset to occur. RSTYPE is shown in Figure 8-4 and described in Table 8-6.2 PLLC1 Revision Identification Register (REVID) The PLLC1 revision identification register (REVID) is shown in Figure 8-3 and described in Table 8-5.3.com PLLC Registers 8. -n = value after reset 0 Table 8-5. If multiple reset sources are asserted and deasserted simultaneously. External warm reset was the last reset to occur. Power On Reset (POR) was the last reset to occur. SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. Reset Type Status Register (RSTYPE) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only.

In software reset Not in software reset RSCTRL unlock key.PLLC Registers www. Writes are possible only when qualified with a valid key. Before writing to the SWRST bit. Register is locked when read value is 3h. Any write to the register following a successful unlock relocks the register. any other key value is invalid and indicates that the register is locked. RSCTRL is shown in Figure 8-5 and described in Table 8-7. R = Read only.4 PLLC0 Reset Control Register (RSCTRL) The reset control register (RSCTRL) allows the device to perform a software-initiated reset. Register must be unlocked before writing to this bit. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . -n = value after reset 17 16 SWRST R/W-1 0 Table 8-7. RSCTRL unlock key 156 Phase-Locked Loop Controller (PLLC) Copyright © 2011.3.com 8.ti. Key used to enable writes to RSCTRL. the register must be unlocked by writing the key value of 5A69h to the KEY bit field. Register is unlocked when read value is Ch. Figure 8-5. The KEY bit field reads back as Ch when the register is unlocked. Reset Control Register (RSCTRL) 31 Reserved R-0 15 KEY R/W-3h LEGEND: R/W = Read/Write. Reset Control Register (RSCTRL) Field Descriptions Bit 31-17 16 Field Reserved SWRST 0 1 15-0 KEY 0-FFFFh 3h Ch 5A69h Value 0 Description Reserved PLL software reset.

PLL0 is operating. PLL0 reset is asserted. SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. Write the default value when modifying this register. PLL0 mode is enabled. Figure 8-6. Internal oscillator (crystal) Square wave Reserved This bit must be cleared before the PLLEN bit will have any effect. not bypassed. PLL0 reset. Texas Instruments Incorporated 157 .5 PLLC0 Control Register (PLLCTL) The PLLC0 control register (PLLCTL) is shown in Figure 8-6 and described in Table 8-8. PLL0 mode enables.ti. PLL0 reset is not asserted. PLLC0 Control Register (PLLCTL) Field Descriptions Bit 31-10 9 Field Reserved EXTCLKSRC 0 1 8 CLKMODE 0 1 7-6 5 4 3 Reserved PLLENSRC Reserved PLLRST 0 1 2 1 Reserved PLLPWRDN 0 1 0 PLLEN 0 1 0 1 0 1 Value 0 Description Reserved External clock source selection. R = Read only.com PLLC Registers 8. Reference clock selection. PLL0 is in bypass mode. -n = value after reset Table 8-8. PLLC0 Control Register (PLLCTL) 31 Reserved R-0 15 Reserved R-0 7 Reserved R-1 6 5 PLLENSRC R/W-1 4 Reserved R/W-1 3 PLLRST R/W-0 2 Reserved R-0 10 9 EXTCLKSRC R/W-0 1 PLLPWRDN R/W-1 8 CLKMODE R/W-0 0 PLLEN R/W-0 16 LEGEND: R/W = Read/Write. Reserved PLL0 power-down. Use PLL1_SYSCLK3 for the PLL bypass clock. Reserved. PLL0 is powered-down.3. Use OSCIN for the PLL bypass clock.www.

PLLC1 Control Register (PLLCTL) Field Descriptions Bit 31-8 7-6 5 4 3 Field Reserved Reserved PLLENSRC Reserved PLLRST 0 1 2 1 Reserved PLLPWRDN 0 1 0 PLLEN 0 1 0 Value 0 1 0 1 Description Reserved Reserved This bit must be cleared before the PLLEN bit will have any effect. Reserved PLL1 power-down. PLL1 mode enables. R = Read only.PLLC Registers www. Reserved. Figure 8-7.ti.3. -n = value after reset Table 8-9. PLL1 is powered-down.com 8. not bypassed. Write the default value when modifying this register. PLL1 is in bypass mode. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . PLL1 is operating. PLL1 reset. PLLC1 Control Register (PLLCTL) 31 Reserved R-0 15 Reserved R-0 7 Reserved R-1 6 5 PLLENSRC R/W-1 4 Reserved R/W-1 3 PLLRST R/W-0 2 Reserved R-0 1 PLLPWRDN R/W-1 0 PLLEN R/W-0 8 16 LEGEND: R/W = Read/Write. PLL1 reset is asserted. PLL1 reset is not asserted.6 PLLC1 Control Register (PLLCTL) The PLLC1 control register (PLLCTL) is shown in Figure 8-7 and described in Table 8-9. 158 Phase-Locked Loop Controller (PLLC) Copyright © 2011. PLL1 mode is enabled.

PLLC0 OBSCLK Select Register (OCSEL) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write.7 PLLC0 OBSCLK Select Register (OCSEL) The PLLC0 OBSCLK select register (OCSEL) controls which clock is output on the CLKOUT pin so that it may be used for test and debug purposes (in addition to its normal function of being a direct input clock divider). Figure 8-8. The OCSEL is shown in Figure 8-8 and described in Table 8-10. Reserved OSCIN PLL0_SYSCLK1 PLL0_SYSCLK2 PLL0_SYSCLK3 PLL0_SYSCLK4 PLL0_SYSCLK5 PLL0_SYSCLK6 PLL0_SYSCLK7 PLLC1 OBSCLK Disabled 15h-16h Reserved SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011.ti. -n = value after reset 5 4 OCSRC R/W-14h 0 16 Table 8-10.www. Output on CLKOUT pin.3.com PLLC Registers 8. PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions Bit 31-5 4-0 Field Reserved OCSRC Value 0 0-1Fh 0-13h 14h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Description Reserved PLLC0 OBSCLK source. Texas Instruments Incorporated 159 . R = Read only.

-n = value after reset 5 4 OCSRC R/W-14h 0 16 Table 8-11. PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions Bit 31-5 4-0 Field Reserved OCSRC Value 0 0-1Fh 0-13h 14h 17h 18h 19h Description Reserved PLLC1 OBSCLK source. PLLC1 OBSCLK Select Register (OCSEL) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write.PLLC Registers www.8 PLLC1 OBSCLK Select Register (OCSEL) The PLLC1 OBSCLK select register (OCSEL) controls which clock is output on PLLC1 OBSCLK so that it may be used for test and debug purposes (in addition to its normal function of being a direct input clock divider).com 8. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Reserved OSCIN PLL1_SYSCLK1 PLL1_SYSCLK2 PLL1_SYSCLK3 15h-16h Reserved 1A-1Fh Reserved 160 Phase-Locked Loop Controller (PLLC) Copyright © 2011. The OCSEL is shown in Figure 8-9 and described in Table 8-11. Figure 8-9.ti. R = Read only.3.

Multiplier Value = PLLM + 1.www. SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. 8. PLLC0 pre-divider is disabled. RATIO defaults to 0 (PLL pre-divide by 1). PLLC0 Pre-Divider Control Register (PREDIV) 31 Reserved R-0 15 PREDEN R/W-1 14 Reserved R-0 5 4 RATIO R/W-0 0 16 LEGEND: R/W = Read/Write. PLLC0 pre-divider is enabled. Divider Value = RATIO + 1. PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions Bit 31-14 15 Field Reserved PREDEN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved PLLC0 pre-divider enable. -n = value after reset 5 4 PLLM R/W-13h 0 16 Table 8-12. Figure 8-11.com PLLC Registers 8.10 PLLC0 Pre-Divider Control Register (PREDIV) The PLLC0 pre-divider control register (PREDIV) is shown in Figure 8-11 and described in Table 8-13. Figure 8-10. -n = value after reset Table 8-13. The valid range of multiplier values for a given OSCIN is defined by the minimum and maximum frequency limits on the PLL VCO frequency. Texas Instruments Incorporated 161 . See the device-specific data manual for PLL VCO frequency specification limits. R = Read only. PLL Multiplier Control Register (PLLM) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write.9 PLL Multiplier Control Register (PLLM) The PLL multiplier control register (PLLM) is shown in Figure 8-10 and described in Table 8-12.ti. Reserved Divider ratio. PLL Multiplier Control Register (PLLM) Field Descriptions Bit 31-5 4-0 Field Reserved PLLM Value 0 0-1Fh Description Reserved PLL multiplier select.3.3. Clock output from the PREDIV stage is disabled. R = Read only.

RATIO defaults to 0 (PLL divide by 1). Divider 1 is disabled. R = Read only. PLLC1 Divider 1 Register (PLLDIV1) 31 Reserved R-0 15 D1EN R/W-0 14 Reserved R-0 5 4 RATIO R/W-0 0 16 LEGEND: R/W = Read/Write. Divider 1 is enabled. PLLDIV1 is shown in Figure 8-13 and described in Table 8-15. Figure 8-12. Reserved Divider ratio. PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions Bit 31-16 15 Field Reserved D1EN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Divider 1 enable. PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions Bit 31-16 15 Field Reserved D1EN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Divider 1 enable. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .3. 162 Phase-Locked Loop Controller (PLLC) Copyright © 2011. Divider 1 is enabled.3.12 PLLC1 Divider 1 Register (PLLDIV1) The PLLC1 divider 1 register (PLLDIV1) controls the divider for PLL1_SYSCLK1. R = Read only. -n = value after reset Table 8-15. Figure 8-13.ti. PLLDIV1 is shown in Figure 8-12 and described in Table 8-14.PLLC Registers www. Reserved Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1). Divider 1 is disabled. Divider Value = RATIO + 1. -n = value after reset Table 8-14. PLLC0 Divider 1 Register (PLLDIV1) 31 Reserved R-0 15 D1EN R/W-1 14 Reserved R-0 5 4 RATIO R/W-0 0 16 LEGEND: R/W = Read/Write.11 PLLC0 Divider 1 Register (PLLDIV1) The PLLC0 divider 1 register (PLLDIV1) controls the divider for PLL0_SYSCLK1. 8.com 8.

Divider Value = RATIO + 1. PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions Bit 31-16 15 Field Reserved D2EN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Divider 2 enable. PLLC1 Divider 2 Register (PLLDIV2) 31 Reserved R-0 15 D2EN R/W-0 14 Reserved R-0 5 4 RATIO R/W-1 0 16 LEGEND: R/W = Read/Write. Reserved Divider ratio.13 PLLC0 Divider 2 Register (PLLDIV2) The PLLC0 divider 2 register (PLLDIV2) controls the divider for PLL0_SYSCLK2.ti. R = Read only. Divider 2 is disabled.com PLLC Registers 8. -n = value after reset Table 8-16. PLLDIV2 is shown in Figure 8-14 and described in Table 8-16. Divider Value = RATIO + 1.www.3. RATIO defaults to 1 (PLL divide by 2). R = Read only. PLLC0 Divider 2 Register (PLLDIV2) 31 Reserved R-0 15 D2EN R/W-1 14 Reserved R-0 5 4 RATIO R/W-1 0 16 LEGEND: R/W = Read/Write. SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. PLLDIV2 is shown in Figure 8-15 and described in Table 8-17. Divider 2 is enabled. Reserved Divider ratio. RATIO defaults to 1 (PLL divide by 2). Texas Instruments Incorporated 163 . Divider 2 is disabled. Figure 8-15. -n = value after reset Table 8-17. Figure 8-14.14 PLLC1 Divider 2 Register (PLLDIV2) The PLLC1 divider 2 register (PLLDIV2) controls the divider for PLL1_SYSCLK2. 8. PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions Bit 31-16 15 Field Reserved D2EN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Divider 2 enable. Divider 2 is enabled.3.

15 PLLC0 Divider 3 Register (PLLDIV3) The PLLC0 divider 3 register (PLLDIV3) controls the divider for PLL0_SYSCLK3. -n = value after reset Table 8-18.com 8. Reserved Divider ratio. RATIO defaults to 2h (PLL divide by 3). Divider 3 is disabled. Divider Value = RATIO + 1. R = Read only.PLLC Registers www. Figure 8-17. PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions Bit 31-16 15 Field Reserved D3EN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Divider 3 enable. PLLC0 Divider 3 Register (PLLDIV3) 31 Reserved R-0 15 D3EN R/W-1 14 Reserved R-0 5 4 RATIO R/W-2h 0 16 LEGEND: R/W = Read/Write. 8. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .ti. PLLDIV3 is shown in Figure 8-16 and described in Table 8-18.16 PLLC1 Divider 3 Register (PLLDIV3) The PLLC1 divider 3 register (PLLDIV3) controls the divider for PLL1_SYSCLK3. Divider 3 is enabled.3. PLLDIV3 is shown in Figure 8-17 and described in Table 8-19. 164 Phase-Locked Loop Controller (PLLC) Copyright © 2011. R = Read only. PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions Bit 31-16 15 Field Reserved D3EN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Divider 3 enable. Reserved Divider ratio. RATIO defaults to 2h (PLL divide by 3). Divider 3 is disabled. -n = value after reset Table 8-19. PLLC1 Divider 3 Register (PLLDIV3) 31 Reserved R-0 15 D3EN R/W-0 14 Reserved R-0 5 4 RATIO R/W-2h 0 16 LEGEND: R/W = Read/Write. Divider Value = RATIO + 1. Figure 8-16.3. Divider 3 is enabled.

PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions Bit 31-16 15 Field Reserved D5EN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Divider 5 enable.com PLLC Registers 8.3. Divider 4 is enabled.3. Reserved Divider ratio. Divider 5 is disabled. RATIO defaults 2 (PLL divide by 3). RATIO defaults 3 (PLL divide by 4). Figure 8-18.17 PLLC0 Divider 4 Register (PLLDIV4) The PLLC0 divider 4 register (PLLDIV4) controls the divider for PLL0_SYSCLK4. -n = value after reset Table 8-21. Divider 4 is disabled. PLLDIV5 is shown in Figure 8-19 and described in Table 8-21. PLLC0 Divider 4 Register (PLLDIV4) 31 Reserved R-0 15 D4EN R/W-1 14 Reserved R-0 5 4 RATIO R/W-3h 0 16 LEGEND: R/W = Read/Write. PLLDIV4 is shown inFigure 8-18 and described in Table 8-20. Figure 8-19. Divider Value = RATIO + 1. PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions Bit 31-16 15 Field Reserved D4EN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Divider 4 enable. R = Read only. Reserved Divider ratio. Texas Instruments Incorporated 165 .www. Divider Value = RATIO + 1. SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. Divider 5 is enabled.18 PLLC0 Divider 5 Register (PLLDIV5) The PLLC0 divider 5 register (PLLDIV5) controls the divider for PLL0_SYSCLK5. -n = value after reset Table 8-20. PLLC0 Divider 5 Register (PLLDIV5) 31 Reserved R-0 15 D5EN R/W-1 14 Reserved R-0 5 4 RATIO R/W-2h 0 16 LEGEND: R/W = Read/Write.ti. 8. R = Read only.

3.PLLC Registers www. PLLC0 Divider 7 Register (PLLDIV7) 31 Reserved R-0 15 D7EN R/W-1 14 Reserved R-0 5 4 RATIO R/W-5h 0 16 LEGEND: R/W = Read/Write.com 8. PLLDIV7 is shown in Figure 8-21 and described in Table 8-23. Divider Value = RATIO + 1. PLLC0 Divider 6 Register (PLLDIV6) 31 Reserved R-0 15 D6EN R/W-1 14 Reserved R-0 5 4 RATIO R/W-0 0 16 LEGEND: R/W = Read/Write. Divider Value = RATIO + 1. R = Read only. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .3. -n = value after reset Table 8-22. RATIO defaults to 5 (PLL divide by 6).20 PLLC0 Divider 7 Register (PLLDIV7) The PLLC0 divider 7 register (PLLDIV7) controls the divider for PLL0_SYSCLK7. PLLDIV6 is shown in Figure 8-20 and described in Table 8-22. 8. PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions Bit 31-16 15 Field Reserved D7EN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Divider 7 enable. Divider 6 is enabled. Divider 6 is disabled. Reserved Divider ratio. Divider 7 is disabled. Figure 8-20. -n = value after reset Table 8-23. Divider 7 is enabled. Reserved Divider ratio. PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions Bit 31-16 15 Field Reserved D6EN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Divider 6 enable. RATIO defaults to 0 (PLL divide by 1). R = Read only. Figure 8-21.19 PLLC0 Divider 6 Register (PLLDIV6) The PLLC0 divider 6 register (PLLDIV6) controls the divider for PLL0_SYSCLK6. 166 Phase-Locked Loop Controller (PLLC) Copyright © 2011.ti.

Figure 8-23. PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions Bit 31-16 15 Field Reserved OD1EN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Oscillator divider 1 enable. Oscillator divider 1 is disabled.3. For example. R = Read only. -n = value after reset Table 8-25. Reserved Divider ratio. Oscillator divider 1 is enabled. R = Read only.com PLLC Registers 8. PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions Bit 31-16 15 Field Reserved OD1EN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Oscillator divider 1 enable. For PLLC1 OBSCLK to toggle. Oscillator divider 1 is disabled. The OSCDIV is shown in Figure 8-23 and described in Table 8-25. RATIO = 0 means divide by 1. The PLLC0 OBSCLK is connected to the CLKOUT pin. Figure 8-22. PLLC0 Oscillator Divider 1 Register (OSCDIV) 31 Reserved R-0 15 OD1EN R/W-1 14 Reserved R-0 5 4 RATIO R/W-0 0 16 LEGEND: R/W = Read/Write. Divider value = RATIO + 1. Texas Instruments Incorporated 167 . The PLLC1 OBSCLK signal may be selected as the output on the CLKOUT pin.www. Reserved Divider ratio.21 PLLC0 Oscillator Divider 1 Register (OSCDIV) The PLLC0 oscillator divider 1 register (OSCDIV) controls the divider for PLLC0 OBSCLK. Divider value = RATIO + 1.ti. dividing down the clock selected as the PLLC1 OBSCLK source. both the OD1EN bit and the OBSEN bit in the PLLC0 clock enable control register (CKEN) must be set to 1. SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. For example.3. Oscillator divider 1 is enabled. PLLC1 Oscillator Divider 1 Register (OSCDIV) 31 Reserved R-0 15 OD1EN R/W-1 14 Reserved R-0 5 4 RATIO R/W-0 0 16 LEGEND: R/W = Read/Write.22 PLLC1 Oscillator Divider 1 Register (OSCDIV) The PLLC1 oscillator divider 1 register (OSCDIV) controls the divider for PLLC1 OBSCLK. both the OD1EN bit and the OBSEN bit in the PLLC1 clock enable control register (CKEN) must be set to 1. RATIO = 0 means divide by 1. -n = value after reset Table 8-24. 8. For PLLC0 OBSCLK to toggle. The OSCDIV is shown in Figure 8-22 and described in Table 8-24. dividing down the clock selected as the PLLC0 OBSCLK source.

A write of 1 initiates the command. R = Read only. Figure 8-25. but has no effect.3. -n = value after reset 1 0 GOSET R/W0C-0 16 Table 8-27. PLL Controller Command Register (PLLCMD) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write.ti. PLLCMD is shown in Figure 8-25 and described in Table 8-27. -n = value after reset Table 8-26.23 PLL Post-Divider Control Register (POSTDIV) The PLL post-divider control register (POSTDIV) is shown in Figure 8-24 and described in Table 8-26. PLL Post-Divider Control Register (POSTDIV) 31 Reserved R-0 15 POSTDEN R/W-1 14 Reserved R-0 5 4 RATIO R/W-1 0 16 LEGEND: R/W = Read/Write.com 8. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . RATIO defaults to 1 (PLL post-divide by 2). Divider Value = RATIO + 1. 8. a write of 0 clears the bit.PLLC Registers www. Post-divider is disabled. R = Read only.24 PLL Controller Command Register (PLLCMD) The PLL controller command register (PLLCMD) contains the command bit for phase alignment. W0C = Write 0 to clear bit. Reserved Divider ratio.3. Clear bit (no effect) Phase alignment 168 Phase-Locked Loop Controller (PLLC) Copyright © 2011. Post-divider is enabled. PLL Controller Command Register (PLLCMD) Field Descriptions Bit 31-1 0 Field Reserved GOSET 0 1 Value 0 Description Reserved GO bit for phase alignment. Figure 8-24. PLL Post-Divider Control Register (POSTDIV) Field Descriptions Bit 31-16 15 Field Reserved POSTDEN 0 1 14-5 4-0 Reserved RATIO 0 0-1Fh Value 0 Description Reserved Post-divider enable.

SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. No Yes Reserved Status of GO operation. oscillator assumed to be stable. PLL Controller Status Register (PLLSTAT) Field Descriptions Bit 31-3 2 Field Reserved STABLE 0 1 1 0 Reserved GOSTAT 0 1 0 Value 0 Description Reserved OSC counter done. indicates GO operation is in progress. If 1. Texas Instruments Incorporated 169 . this bit should become 1. GO operation is in progress.www.25 PLL Controller Status Register (PLLSTAT) The PLL controller status register (PLLSTAT) is shown in Figure 8-26 and described in Table 8-28.3. Figure 8-26. By the time the device comes out of reset. -n = value after reset 3 2 STABLE R-0 1 Reserved R-0 0 GOSTAT R-0 16 Table 8-28. GO operation is not in progress.com PLLC Registers 8. PLL Controller Status Register (PLLSTAT) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only.ti.

No Yes PLL0_SYSCLK2 needs to be aligned to others selected in this register. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions Bit 31-7 6 Field Reserved ALN7 0 1 5 ALN6 0 1 4 ALN5 0 1 3 ALN4 0 1 2 ALN3 0 1 1 ALN2 0 1 0 ALN1 0 1 Value 3h Description Reserved PLL0_SYSCLK7 needs to be aligned to others selected in this register. R = Read only. Figure 8-27. ALNCTL is shown in Figure 8-27 and described in Table 8-29. No Yes PLL0_SYSCLK1 needs to be aligned to others selected in this register. No Yes PLL0_SYSCLK5 needs to be aligned to others selected in this register.26 PLLC0 Clock Align Control Register (ALNCTL) The PLLC0 clock align control register (ALNCTL) indicates which PLL0_SYSCLKn needs to be aligned for proper device operation.PLLC Registers www.ti. -n = value after reset 7 6 ALN7 R/W-1 5 ALN6 R/W-1 4 ALN5 R/W-1 3 ALN4 R/W-1 2 ALN3 R/W-1 1 ALN2 R/W-1 0 ALN1 R/W-1 16 Table 8-29.3. PLLC0 Clock Align Control Register (ALNCTL) 31 Reserved R-0 15 Reserved R-3h LEGEND: R/W = Read/Write. No Yes 170 Phase-Locked Loop Controller (PLLC) Copyright © 2011. No Yes PLL0_SYSCLK3 needs to be aligned to others selected in this register. No Yes PLL0_SYSCLK4 needs to be aligned to others selected in this register.com 8. No Yes PLL0_SYSCLK6 needs to be aligned to others selected in this register.

Figure 8-28. No Yes PLL1_SYSCLK2 needs to be aligned to others selected in this register. R = Read only.3. PLLC1 Clock Align Control Register (ALNCTL) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write.com PLLC Registers 8. No Yes SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions Bit 31-3 2 Field Reserved ALN3 0 1 1 ALN2 0 1 0 ALN1 0 1 Value 0 Description Reserved PLL1_SYSCLK3 needs to be aligned to others selected in this register.www.27 PLLC1 Clock Align Control Register (ALNCTL) The PLLC1 clock align control register (ALNCTL) indicates which PLL1_SYSCLKn needs to be aligned for proper device operation. No Yes PLL1_SYSCLK1 needs to be aligned to others selected in this register. ALNCTL is shown in Figure 8-28 and described in Table 8-30. Texas Instruments Incorporated 171 .ti. -n = value after reset 3 2 ALN3 R/W-1 1 ALN2 R/W-1 0 ALN1 R/W-1 16 Table 8-30.

PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions Bit 31-7 6 Field Reserved SYS7 0 1 5 SYS6 0 1 4 SYS5 0 1 3 SYS4 0 1 2 SYS3 0 1 1 SYS2 0 1 0 SYS1 0 1 Value 0 Description Reserved PLL0_SYSCLK7 divide ratio is modified. Ratio is not modified. PLL0_SYSCLK6 divide ratio is modified. PLL0_SYSCLK2 divide ratio is modified. Ratio is not modified. Ratio is not modified. Ratio is modified. 172 Phase-Locked Loop Controller (PLLC) Copyright © 2011. Ratio is modified. Ratio is not modified. Ratio is modified. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only. PLL0_SYSCLK4 divide ratio is modified.3. Figure 8-29. DCHANGE is shown in Figure 8-29 and described in Table 8-31.ti. PLL0_SYSCLK3 divide ratio is modified. -n = value after reset 7 6 SYS7 R-0 5 SYS6 R-0 4 SYS5 R-0 3 SYS4 R-0 2 SYS3 R-0 1 SYS2 R-0 0 SYS1 R-0 16 Table 8-31.PLLC Registers www. PLL0_SYSCLK5 divide ratio is modified.com 8. PLL0_SYSCLK1 divide ratio is modified. Ratio is not modified. Ratio is modified. Ratio is modified. Ratio is modified. Ratio is modified. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Ratio is not modified.28 PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) The PLLC0 PLLDIV ratio change status register (DCHANGE) indicates if the PLL0_SYSCLKn divide ratio has been modified. Ratio is not modified.

Figure 8-30.3.29 PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) The PLLC1 PLLDIV ratio change status register (DCHANGE) indicates if the PLL1_SYSCLKn divide ratio has been modified. DCHANGE is shown in Figure 8-30 and described in Table 8-32. PLL1_SYSCLK1 divide ratio is modified. SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. PLL1_SYSCLK2 divide ratio is modified. Ratio is not modified. Ratio is not modified. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only. Ratio is modified. Ratio is modified.www.com PLLC Registers 8. -n = value after reset 3 2 SYS3 R-0 1 SYS2 R-0 0 SYS1 R-0 16 Table 8-32.ti. Texas Instruments Incorporated 173 . Ratio is not modified. Ratio is modified. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions Bit 31-3 2 Field Reserved SYS3 0 1 1 SYS2 0 1 0 SYS1 0 1 Value 0 Description Reserved PLL1_SYSCLK3 divide ratio is modified.

PLLC Registers www.31 PLLC1 Clock Enable Control Register (CKEN) The PLLC1 clock enable control register (CKEN) controls the PLLC1 OBSCLK clock. PLLC0 Clock Enable Control Register (CKEN) Field Descriptions Bit 31-2 1 Field Reserved OBSEN 0 1 0 AUXEN 0 1 Value 0 Description Reserved OBSCLK enable. 8. PLLC0 AUXCLK is disabled. Actual PLLC0 OBSCLK status is shown in the PLLC0 clock status register (CKSTAT). Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . CKEN is shown in Figure 8-32 and described in Table 8-34.ti.3. R = Read only.3. PLLC1 Clock Enable Control Register (CKEN) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write. Reserved 174 Phase-Locked Loop Controller (PLLC) Copyright © 2011. both the OBSEN bit and the OD1EN bit in the PLLC1 oscillator divider 1 register (OSCDIV) must be set to 1. AUXCLK enable. both the OBSEN bit and the OD1EN bit in the PLLC0 oscillator divider 1 register (OSCDIV) must be set to 1. R = Read only. Actual PLLC0 AUXCLK status is shown in the PLLC0 clock status register (CKSTAT). -n = value after reset 2 1 OBSEN R/W-1 0 AUXEN R/W-1 16 Table 8-33. PLLC1 OBSCLK is enabled. For PLLC1 OBSCLK to toggle.30 PLLC0 Clock Enable Control Register (CKEN) The PLLC0 clock enable control register (CKEN) controls the PLLC0 OBSCLK and AUXCLK clock. PLLC1 Clock Enable Control Register (CKEN) Field Descriptions Bit 31-2 1 Field Reserved OBSEN 0 1 0 Reserved 0 Value 0 Description Reserved OBSCLK enable. -n = value after reset 2 1 OBSEN R/W-0 0 Reserved R-0 16 Table 8-34. Figure 8-32. Actual PLLC1 OBSCLK status is shown in the PLLC1 clock status register (CKSTAT). PLLC0 AUXCLK is enabled. Figure 8-31. PLLC0 OBSCLK is disabled. For PLLC0 OBSCLK to toggle.com 8. CKEN is shown in Figure 8-31 and described in Table 8-33. PLLC1 OBSCLK is disabled. PLLC0 OBSCLK is enabled. PLLC0 Clock Enable Control Register (CKEN) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write.

PLLC0 Clock Status Register (CKSTAT) Field Descriptions Bit 31-2 1 Field Reserved OBSEN 0 1 0 AUXEN 0 1 Value 0 Description Reserved OBSCLK on status. The PLL0_SYSCLK status is shown in the PLLC0 SYSCLK status register (SYSTAT). CKSTAT is shown in Figure 8-33 and described in Table 8-35.com PLLC Registers 8. PLLC0 AUXCLK is off. Figure 8-33. -n = value after reset 2 1 OBSEN R-1 0 AUXEN R-1 16 Table 8-35.3. SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. PLLC0 AUXCLK is on. PLLC0 OBSCLK is controlled in the PLLC0 oscillator divider 1 register (OSCDIV) by the OBSEN bit in the PLLC0 clock enable control register (CKEN).www.32 PLLC0 Clock Status Register (CKSTAT) The PLLC0 clock status register (CKSTAT) indicates the PLLC0 OBSCLK and AUXCLK on/off status. PLLC0 OBSCLK is off. PLLC0 OBSCLK is on.ti. PLLC0 AUXCLK is controlled by the AUXEN bit in the PLLC0 clock enable control register (CKEN). PLLC0 Clock Status Register (CKSTAT) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only. AUXCLK on status. Texas Instruments Incorporated 175 .

The PLL1_SYSCLK status is shown in the PLLC1 SYSCLK status register (SYSTAT). Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .com 8.ti. PLLC1 OBSCLK is controlled in the PLLC1 oscillator divider 1 register (OSCDIV) by the OBSEN bit in the PLLC1 clock enable control register (CKEN).PLLC Registers www. PLLC1 Clock Status Register (CKSTAT) 31 Reserved R-0 15 Reserved R-2h LEGEND: R = Read only.3. Figure 8-34. PLLC1 OBSCLK is off. PLLC1 OBSCLK is on. CKSTAT is shown in Figure 8-34 and described in Table 8-36. Reserved 176 Phase-Locked Loop Controller (PLLC) Copyright © 2011. -n = value after reset 2 1 OBSEN R-0 0 Reserved R-0 16 Table 8-36.33 PLLC1 Clock Status Register (CKSTAT) The PLLC1 clock status register (CKSTAT) indicates the PLLC1 OBSCLK on/off status. PLLC1 Clock Status Register (CKSTAT) Field Descriptions Bit 31-2 1 Field Reserved OBSEN 0 1 0 Reserved 0 Value 0 Description Reserved OBSCLK on status.

-n = value after reset Table 8-37.34 PLLC0 SYSCLK Status Register (SYSTAT) The PLLC0 SYSCLK status register (SYSTAT) indicates the PLL0_SYSCLKn on/off status. Off On PLL0_SYSCLK5 on status. Off On PLL0_SYSCLK6 on status. Off On PLL0_SYSCLK1 on status.com PLLC Registers 8. PLLC0 SYSCLK Status Register (SYSTAT) 31 Reserved R-1 7 Reserved R-1 6 SYS7ON R-1 5 SYS6ON R-1 4 SYS5ON R-1 3 SYS4ON R-1 2 SYS3ON R-1 1 SYS2ON R-1 0 SYS1ON R-1 8 LEGEND: R/W = Read/Write. PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions Bit 31-7 6 Field Reserved SYS7ON 0 1 5 SYS6ON 0 1 4 SYS5ON 0 1 3 SYS4ON 0 1 2 SYS3ON 0 1 1 SYS2ON 0 1 0 SYS1ON 0 1 Value 3h Description Reserved PLL0_SYSCLK7 on status. Figure 8-35. which depends on the DnEN bit in PLLC0 PLLDIVn.3. SYSTAT is shown in Figure 8-35 and described in Table 8-37. Off On PLL0_SYSCLK4 on status.www. Off On SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. Texas Instruments Incorporated 177 . R = Read only.ti. The actual default is determined by the actual clock on/off status. Off On PLL0_SYSCLK3 on status. Off On PLL0_SYSCLK2 on status.

PLLC Registers www.com 8.3. -n = value after reset 3 2 SYS3ON R-0 1 SYS2ON R-0 0 SYS1ON R-0 8 Table 8-38. Off On PLL1_SYSCLK1 on status. SYSTAT is shown in Figure 8-36 and described in Table 8-38.35 PLLC1 SYSCLK Status Register (SYSTAT) The PLLC1 SYSCLK status register (SYSTAT) indicates the PLL1_SYSCLKn on/off status. PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions Bit 31-3 2 Field Reserved SYS3ON 0 1 1 SYS2ON 0 1 0 SYS1ON 0 1 Value 0 Description Reserved PLL1_SYSCLK3 on status. Figure 8-36. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Off On 178 Phase-Locked Loop Controller (PLLC) Copyright © 2011. Off On PLL1_SYSCLK2 on status. which depends on the DnEN bit in PLLC1 PLLDIVn. R = Read only. The actual default is determined by the actual clock on/off status. PLLC1 SYSCLK Status Register (SYSTAT) 31 Reserved R-0 7 Reserved R-0 LEGEND: R/W = Read/Write.ti.

3.ti. Texas Instruments Incorporated 179 . To start the counter. After the register is started. SPRUH77A – December 2011 Submit Documentation Feedback Phase-Locked Loop Controller (PLLC) Copyright © 2011. a write must be made to EMUCNT0. To start the counter. it can not be stopped except for power on reset. The snapshot version is what is read. -n = value after reset 0 Table 8-39. Figure 8-37.www. The snapshot version is what is read. After the register is started.com PLLC Registers 8.37 Emulation Performance Counter 1 Register (EMUCNT1) The emulation performance counter 1 register (EMUCNT1) is shown in Figure 8-38 and described in Table 8-40. but only used to start the register.36 Emulation Performance Counter 0 Register (EMUCNT0) The emulation performance counter 0 register (EMUCNT0) is shown in Figure 8-37 and described in Table 8-39. It is important to read the EMUCNT0 followed by EMUCNT1 or else the snapshot version may not get updated correctly. When EMUCNT0 is read. it snapshots EMUCNT0 and EMUCNT1. Emulation Performance Counter 1 Register (EMUCNT1) 31 COUNT R-0 LEGEND: R = Read only. Figure 8-38.3. it snapshots EMUCNT0 and EMUCNT1. Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions Bit 31-0 Field COUNT Value 0-FFFF FFFFh Description Counter value for lower 64-bits. This register is not writable. When EMUCNT0 is read. -n = value after reset 0 Table 8-40. it can not be stopped except for power on reset. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions Bit 31-0 Field COUNT Value 0-FFFF FFFFh Description Counter value for upper 64-bits. It counts in a divide-by-4 of the system clock. but only used to start the register. EMUCNT1 is for emulation performance profiling. a write must be made to EMUCNT0. Emulation Performance Counter 0 Register (EMUCNT0) 31 COUNT R-0 LEGEND: R = Read only. 8. EMUCNT0 is for emulation performance profiling. This register is not writable. It is important to read the EMUCNT0 followed by EMUCNT1 or else the snapshot version may not get updated correctly.

Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .180 Phase-Locked Loop Controller (PLLC) Copyright © 2011.

... Page 9................................................................................................................................... Executing State Transitions ....................................................2 9..................................................................................................................................................Chapter 9 SPRUH77A – December 2011 Power and Sleep Controller (PSC) Topic . IcePick Emulation Support in the PSC .............................................. PSC Registers ..........3 9.... Introduction ..........................................................................5 9............ PSC Interrupts ....................6 182 182 187 188 188 191 SPRUH77A – December 2011 Submit Documentation Feedback Power and Sleep Controller (PSC) Copyright © 2011........................................................................1 9....... Power Domain and Module Topology .............4 9............. Texas Instruments Incorporated 181 ............................

clock and reset 9. from a power savings stand point. An LPSC is associated with every module that is controlled by the PSC and provides clock and reset control. However. The module states and terminology are defined in Section 9. The decision to assign an LPSC to a module on a device is primarily based on whether or not disabling the clocks to a module will result in significant power savings. This typically depends on the size and the frequency of operation of the module. All power domains are on when the chip is powered on. Many of the operations of the PSC are transparent to user (software). 182 Power and Sleep Controller (PSC) Copyright © 2011. both PSC modules and all the power domains are powered by the CVDD pins of the device. Each PSC module consists of: • an Always On power domain • an additional pseudo/internal power domain that manages the sleep modes for the RAMs present in the DSP subsystem and the L3 RAM. the power domain they are associated with.1 Introduction The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off. that is. clock and reset operations managed and controlled by the PSC are the focus of this chapter. A PSC module consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs). respectively Each PSC module controls clock states for several on the on chip modules. These modules do not have their module reset/clocks controlled by the PSC module. a state machine for each peripheral/module it controls. Table 9-1 and Table 9-2 lists the set of peripherals/modules that are controlled by the PSC. There are a few modules/peripherals on the device that do not have an LPSC assigned to them. Even though there are 2 PSC modules with 2 power domains each on the device. clock on/off. clock-gating these peripherals does not result in significant power savings. The module level power.2 Power Domain and Module Topology This device includes two PSC modules. the LPSC assignment and the default (power-on reset) module states. controllers and interconnect components. the pseudo/internal power domains. The PSC includes the following features: • Manages chip power-on/off • Provides a software interface to: – Control module clock enable/disable – Control module reset – Control CPU local reset • Manages on-chip RAM sleep modes (for DSP memories and L3 RAM) • Supports IcePick emulation features: power.com 9.2. resets (device level and module level). and I2C0). such as power on and reset control. Timer64P0/P1.ti.Introduction www. the PSC module(s) also provide you with interface to control several important power. See the device-specific data manual for the peripherals available on a given device. There is no provision to remove power externally for the non Always On domains. The GPSC contains memory mapped registers. PSC interrupts. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .2. NOTE: There are no LPSCs for peripherals in the Async2 clock domain (this includes RTC. It is used primarily to provide granular power control for on chip modules (peripherals and CPU). clock and reset operations.

0) USB1 (USB1. BR5. BR6) PRU ARM DSP Power Domain AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) — AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) PD_DSP (PD1) Default Module State SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable Enable Enable — SwRstDisable Enable Enable Enable SwRstDisable SwRstDisable Enable Auto Sleep/ Wake Only — — — — — — — Yes — — Yes Yes Yes — — — Table 9-2. BR2.ti.www.com Power Domain and Module Topology Table 9-1. Power and Sleep Controller (PSC) 183 Copyright © 2011. BR8) SCR1 (BR4) SCR2 (BR3. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .1) GPIO HPI EMAC DDR2/mDDR McASP0 (+ McASP0 FIFO) SATA (1) VPIF SPI1 I2C1 UART1 UART2 McBSP0 (+ McBSP0 FIFO) McBSP1 (+ McBSP1 FIFO) LCDC eHRPWM0/1 MMC/SD1 uPP eCAP0/1/2 EDMA3_1 Transfer Controller 0 Not Used Power Domain AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) — Default Module State SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable SwRstDisable — Auto Sleep/ Wake Only — — — — — — — — — — — — — — — — — — — — — — — Note that the SATA module requires forced state transitions. PSC1 Default Module Configuration LPSC Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22-23 (1) Module Name EDMA3_1 Channel Controller 0 USB0 (USB2. PSC0 Default Module Configuration LPSC Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Module Name EDMA3_0 Channel Controller 0 EDMA3_0 Transfer Controller 0 EDMA3_0 Transfer Controller 1 EMIFA (BR7) SPI0 MMC/SD0 ARM Interrupt Controller ARM RAM/ROM Not Used UART0 SCR0 (BR0. BR1.

PDMODE settings.NEXT and PDCTL1. There is no capability to individually remove voltage/power from the DSP or Shared RAM power domains . This domain is not programmable to OFF state (See details on PDCTL register).PDCTL1. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .PDMODE settings determines the various sleep mode for the on-chip RAM associated with module in the PD1 domain.Power Domain and Module Topology www. PSC1 Default Module Configuration (continued) LPSC Number 24 25 26 27 28 29 30 31 Module Name SCR F0 SCR F1 SCR F2 SCR F6 SCR F7 SCR F8 BR F7 Shared RAM Power Domain AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) AlwaysON (PD0) PD_SHRAM Default Module State Enable Enable Enable Enable Enable Enable Enable Enable Auto Sleep/ Wake Only Yes Yes Yes Yes Yes Yes Yes — 9.2. for both PSC0 and PSC1.com Table 9-2. Furthermore. You should leave both the PDCTL1.ti. Both PD0 and PD1 power domains in PSC0 and PSC1 are powered by the CVDD pins of the device.PDMODE values at default/power on reset values. 184 Power and Sleep Controller (PSC) Copyright © 2011.1 Power Domain States A power domain can only be in one of the two states: ON or OFF. the PD1 power domains. the internal/pseudo power domain can either be in the ON state or OFF state. is always in the ON state when the chip is powered-on. for these power domains the transition from ON to OFF state is further qualified by the PSC0/1. the Always ON domain (or PD0 power domain). for both PSC0 and PSC1. Additionally. The PDCTL1. defined as follows: • ON: power to the domain is on • OFF: power to the domain is off In this device. • On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories • On PSC1 PD1/PD_SHRAM Domain: Controls the sleep state for the 128KB Shared RAM NOTE: Currently programming the PD1 power domain state to OFF is not supported.

Local Reset is useful in cases where the DSP is in enable or disable state.2 Local Reset In addition to module reset. you should program the module state to Disable. For Auto Sleep/Auto Wake Only modules.2. • DSP: When the DSP local reset is asserted the DSP internal memories (L1P. it will transition back to the clock disabled state (automatically sleep) after servicing the internal read/write access request where as in Auto Wake mode. SyncReset. Set the LRST bit in the module control register (MDCTLn) to 1 to de-assert module’s local reset. Texas Instruments Incorporated 185 . The local reset for ARM additionally ensures that any outstanding requests are completed before ARM is reset. For the module to appropriately respond to such external request. If the module clocks need to gated/disabled for power savings. as the DSP module reset would. This does not include the ARM RAM/ROM or ARM interrupt controller module as these exist outside the ARM core. it immediately executes program instructions after reset is de-asserted. the module will permanently transition from the clock disabled to clock enabled state (automatically wake).2. the following modules can be reset using a special local reset that is also a part of the PSC module control for resets. SPRUH77A – December 2011 Submit Documentation Feedback Power and Sleep Controller (PSC) Copyright © 2011. user can use ARM local reset feature. if the software tries to program these modules to Disable. If the CPU is in the enable state. Table 9-1 and Table 9-2 each have a column to indicate whether or not the LPSC configuration for a module is Auto Sleep/Wake Only. that is. L1D and L2) are still accessible. The local reset only resets the DSP CPU core. When the module state is programmed to Disable. The various module states are defined in Table 9-3. 2.2. or SwRstDisable state the power sleep controller ignores these transition requests and transitions the module state to Enable. 9.2. an external event or I/O request cannot enable the clocks. therefore for scenarios where it is needed to just reset the ARM locally but not change the state of clocks. not the rest of DSP subsystem. disabling the clock is not supported and they should be kept in their default “Enable” state. on receiving the first internal read/write access request. where in the module clocks are off/disabled. Auto Sleep or Auto Wake modes.www. including cache etc.com Power Domain and Module Topology 9.ti. 9. and the module reset takes precedence over the local reset. Auto Sleep and Auto Wake states only. Clear the LRST bit in the module control register (MDCTLn) to 0 to assert the module’s local reset. it would need to be reconfigured to the Enable state. Modules that have a “Yes” marked for the Auto Sleep/Wake Only column can be programmed in software to be in Enable. The key difference between the Auto Sleep and Auto Wake states is that once the module is configured in Auto Sleep mode. • ARM: When the ARM local reset is asserted the entire ARM processor is reset .1 Auto Sleep/Wake Only Configurations and Limitation NOTE: Currently no modules should be configured in Auto Sleep or Auto Wake modes.2 Module States The PSC defines several possible states for a module. This various states are essentially a combination of the module reset asserted or de-asserted and module clock on/enabled or off/disabled. SwRstDisable. since when module is in SyncReset or SwRstDisable state the module reset is asserted.2. The procedures for asserting and de-asserting the local reset are as follows (where n corresponds to the module that supports local reset): 1.

Power Domain and Module Topology www.2. similar to the Disable state. without any software intervention. without any software intervention.1 for additional considerations. constraints. After initial power-on.2. software is not expected to initiate this state A module in the SwResetDisable state has its module reset asserted and it has its clock disabled. However this is a special state. Generally. software is not expected to initiate this state A module in the Auto Sleep state also has its module reset de-asserted and its module clock disabled. This device is designed in full static CMOS. When the clock is restarted. The transition from sleep to enabled and back to sleep state has some cycle latency associated with it. This is the normal operational state for a given module A module in the disabled state has its module reset de-asserted and it has its module clock off.com Table 9-3. The transition from sleep to enabled state has some cycle latency associated with it. and after servicing the request it will “automatically” transition into the sleep state (with module reset re de-asserted and module clock disabled). See Section 9. limitations around this mode.ti. constraints. once a module is configured in this state by software. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . it can “automatically” transition to “Enable” state whenever there is an internal read/write request made to it. and will remain in the “Enabled” state from then on (with module reset re de-asserted and module clock on). Generally. similar to the Disable state. A module state in the SyncReset state has its module reset asserted and it has its clock on. However this is a special state.1 for additional considerations. It is not envisioned to use this mode when peripherals are fully operational and moving data. It is not envisioned to use this mode when peripherals are fully operational and moving data. limitations around this mode. the module resumes operating from the stopping point. This state is typically used for disabling a module clock to save power. once a module is configured in this state by software. it retains the module’s state. A module in the Auto Wake state also has its module reset de-asserted and its module clock disabled. See Section 9. so when you stop a module clock. several modules come up in the SwRstDisable state. it will “automatically” transition to “Enable” state whenever there is an internal read/write request made to it.2. SyncReset SwRstDisable Asserted Asserted On Off Auto Sleep De-asserted Off Auto Wake De-asserted Off 186 Power and Sleep Controller (PSC) Copyright © 2011. Module States Module State Enable Disable Module Reset De-asserted De-asserted Module Clock On Off Module State Definition A module in the enable state has its module reset de-asserted and it has its clock on.2.

x is 0 for modules in PD0 (Power Domain 0 or Always On domain) and x is 1 for modules in PD1 (Power Domain 1). Texas Instruments Incorporated 187 .3. 2. 3. 9. Set the GO[x] bit in PTCMD to 1 to initiate the transition(s). there are additional system considerations and constraints that you should be aware of.3. As mentioned in Section 9. 9. To transition the DSP or ARM module state.2. The pseudo/RAM power domains allow internally powering down the state of the RAMs associated with these domains (L1/L2 for PD_DSP in PSC0 and Shared RAM for PD_SHRAM in PSC1) so that these RAMs can run in lower power sleep modes via the power sleep controller. if you want to maintain the memory contents. Set the NEXT bit in MDCTLn to SwRstDisable (0). NOTE: Currently powering down the RAMs via the pseudo/RAM power domain is not supported. NOTE: In the following procedure. therefore. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. the pseudo/RAM power domains are powered down internally. 4. SyncReset (1). NOTE: You may set transitions in multiple NEXT bits in MDCTLn in this step.2 Module State Transitions This section describes the procedure for transitioning the module state (clock and reset control). Auto Sleep (4h) or Auto Wake (5h). Wait for the GOSTAT[x] bit in PTSTAT to clear to 0.3 Executing State Transitions This section describes how to execute the state transitions modules. these domains and the RAM should be left in their default power on state. You are not allowed to change the power domain state to OFF. except for the core(s). SPRUH77A – December 2011 Submit Documentation Feedback Power and Sleep Controller (PSC) Copyright © 2011.com Executing State Transitions 9. Note that some peripherals have special programming requirements and additional recommended steps you must take before you can invoke the PSC module state transition. You must wait for any previously initiated transitions to finish before initiating a new transition. The modules are safely in the new states only after the GOSTAT[x] bit in PTSTAT is cleared to 0.1 Power Domain State Transitions This device consists of two types of domain (in each PSC controller): • Always On domain(s) • pseudo/RAM power domain(s) The Always On power domains are always in the ON state when the chip is powered on. See the individual peripheral user guides for more details. For example. These system considerations and the procedure for transitioning the DSP or ARM module state are described in details in the Power Management chapter. the external memory controller requires that you first place the SDRAM memory in self-refresh mode before you invoke the PSC module state transitions. The procedure for module state transitions is: 1.ti. and in this context powering down does not imply removing the core voltage from pins externally. The following procedure is directly applicable for all modules that are controlled via the PSC (shown in Table 9-1 and Table 9-2).www. Disable (2h). Transitions do not actually take place until you set the GO[x] bit in PTCMD in a later step. Enable (3h). See Table 9-1 and Table 9-2 for power domain associations.

Force Active Block Reset NOTE: When emulation tools remove the above commands. 9. IcePick support only applies to the modules listed in Section 9. 188 Power and Sleep Controller (PSC) Copyright © 2011. therefore.5. the PSC immediately executes a state transition based on the current values in the NEXT bit in PDCTL0 and the NEXT bit in MDCTLn. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .4.ti.5 PSC Interrupts The PSC has an interrupt that is tied to the core interrupt controller.4 IcePick Emulation Support in the PSC The PSC supports IcePick commands that allow IcePick emulation tools to have some control over the state of power domains and modules. Reset Features Assert Reset Wait Reset Reset Descriptions Allows emulation to assert the module’s local reset. Table 9-4. PSC Interrupt Events Interrupt Enable Bits Control Register PDCTLn MDCTLn MDCTLn Enable Bit EMUIHBIE EMUIHBIE EMURSTIE Interrupt Condition Interrupt occurs when the emulation alters the power domain state Interrupt occurs when the emulation alters the module state Interrupt occurs when the emulation tries to alter the module’s local reset The PSC interrupt events only apply when IcePick emulation alters the state of the module from the user-programmed state in the NEXT bit in the MDCTL/PDCTL registers.com 9. 9. IcePick Emulation Commands Power On and Enable Features Inhibit Sleep Force Power Power On and Enable Descriptions Allows emulation to prevent software from transitioning the module out of the enable state. Allows emulation to block software initiated local and module resets.IcePick Emulation Support in the PSC www. as set by software. the PSC interrupt conditions only apply to those modules listed. Allows emulation to keep local reset asserted for an extended period of time after software initiates local reset de-assert. Table 9-5.1 Interrupt Events The PSC interrupt is generated when any of the following events occur: • Power Domain Emulation Event (applies to pseudo/RAM power domain only) • Module State Emulation event • Module Local Reset Emulation event These interrupt events are summarized in Table 9-5 and described in more detail in this section. This IcePick support only applies to the following modules: • DSP [MDCTL15] • ARM [MDCTL14] In particular. Table 9-4 shows IcePick emulation commands recognized by the PSC. Not applicable as AlwaysOn power domain is always on. Allows emulation to force the power domain into an on state. This interrupt is named PSCINT in the interrupt map. Allows emulation to force the module into the enable state. The PSC interrupt is generated when certain IcePick emulation events occur.

Status is reflected in the EMUIHB bit in the module status register (MDSTATn).com PSC Interrupts 9. For details on the ARM interrupt controller.3 Local Reset Emulation Events A local reset emulation event occurs when emulation alters the local reset of a module. the EMUIHBIE and the EMURSTIE bits in MDCTLn (where n is the modules that have IcePick emulation support. a module state emulation event occurs under the following conditions: • When inhibit sleep is asserted by emulation and software attempts to transition the module out of the enable state • When force active is asserted by emulation and module is not already in the enable state 9.5.1. a power domain emulation event occurs under the following conditions: • When inhibit sleep is asserted by emulation and software attempts to transition the module out of the on state • When force power is asserted by emulation and power domain is not already in the on state • When force active is asserted by emulation and power domain is not already in the on state NOTE: Putting the pseudo/RAM power domain associated with the DSP (PD_DSP) to the off state currently is not supported.4). – The P[1] bit in the power error pending register (PERRPR) for the pseudo/RAM power domain associated with DSP memories. a module local reset emulation event occurs under the following conditions: • When assert reset is asserted by emulation although software de-asserted the local reset • When wait reset is asserted by emulation • When block reset is asserted by emulation and software attempts to change the state of local reset 9. Status is reflected in the EMUIHB bit in PDSTATn. – The EMUIHB and the EMURST bits in the module status register for DSP (MDSTAT15).www.2 Interrupt Registers The PSC interrupt enable bits are: the EMUIHBIE bit in PDCTL1 (PSC0). In particular. NOTE: To interrupt the CPU. In particular. SPRUH77A – December 2011 Submit Documentation Feedback Power and Sleep Controller (PSC) Copyright © 2011. • For ARM: – The M[14] bit in the module error pending register 0 (MERRPR0) in PSC0 module.5.1.ti. In particular.5. – The EMUIHB and the EMURST bits in the module status register for ARM (MDSTAT14).1.1 Power Domain Emulation Events A power domain emulation event occurs when emulation alters the state of a power domain (does not apply to the Always On domain). Texas Instruments Incorporated 189 .2 Module State Emulation Events A module state emulation event occurs when emulation alters the state of a module.5. see the ARM Interrupt Controller (AINTC) chapter. The PSC interrupt status bits are: • For DSP: – The M[15] bit in the module error pending register 0 (MERRPR0) in PSC0 module. the power sleep controller interrupt (PSC0_ALLINT and PSC1_ALLINT) must also be enabled appropriately in the ARM interrupt controller. 9. as specified in Section 9. Status is reflected in the EMURST bit in the module status register (MDSTATn).

this bit forces the PSC interrupt logic to re-evaluate event status. the EMUIHBIE and the EMURSTIE bits in MDCTLn to enable the interrupt events that you want. or the bit corresponding to the power domain number in the power error clear register (PERRCR) in PSC0 module. depending on the status bits read in the previous step to determine the event that caused the interrupt. Read the P[n] bit in PERRPR. PSCn_ALLINT must be enabled in the device interrupt controller. if there are still any active interrupt events.6 for a description of the PSC registers. See Section 9. Setting this bit reasserts the PSC interrupt to the device interrupt controller. the M[n] bit in MERRPR1. The PSC interrupt evaluation bit is the ALLEV bit in the INTEVAL register.PSC Interrupts www. (c) Write the M[n] bit in MERRCRn and the P[n] bit in PERRCR to clear corresponding status. enable the interrupt: 1. 190 Power and Sleep Controller (PSC) Copyright © 2011.ti. Enable the power sleep controller interrupt (PSCn_ALLINT) in the device interrupt controller. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . The CPU enters the interrupt service routine (ISR) when it receives the interrupt.com The status bit in MERRPR0 and PERRPR registers is read by software to determine which module or power domain has generated an emulation interrupt and then software can read the corresponding status bits in MDSTAT register or the PDSTATn (PDCTL1 for pseudo/RAM power domain in PSC0) to determine which event caused the interrupt. to determine the source of the interrupt(s). 2. 2. Set the ALLEV bit in the INTEVAL before exiting your PSC interrupt service routine to ensure that you do not miss any PSC interrupts. Set the EMUIHBIE bit in PDCTLn. NOTE: The PSC interrupt is sent to the device interrupt controller when at least one enabled event becomes active. For each active event that you want to service: (a) Read the event status bits in PDSTATn and MDSTATn. (d) Set the ALLEV bit in INTEVAL. When set. (b) Service the interrupt as required by your application. 1. 9. If any events are still active (if any status bits are set) when the ALLEV bit in the INTEVAL is set to 1. To interrupt the CPU. and/or the M[n] bit in MERRPR0. The PSC interrupt can be cleared by writing to bit corresponding to the module number in the module error clear register (MERRCR0). the PSC interrupt is re-asserted to the interrupt controller.5. See the ARM Interrupt Controller (AINTC) chapter for more information on interrupts.3 Interrupt Handling Handle the PSC interrupts as described in the following procedure: First.

6.11 Section 9.13 Section 9.14 Section 9.6.6.6.10 Section 9.16 Section 9. Power and Sleep Controller 1 (PSC1) Registers Address 01E2 7000h 01E2 7018h 01E2 7040h 01E2 7050h 01E2 7060h 01E2 7068h 01E2 7120h 01E2 7128h 01E2 7200h 01E2 7204h 01E2 7300h 01E2 7304h 01E2 7400h 01E2 7404h 01E2 7800h01E2 787Ch 01E2 7A00h01E2 7A7Ch Acronym REVID INTEVAL MERRPR0 MERRCR0 PERRPR PERRCR PTCMD PTSTAT PDSTAT0 PDSTAT1 PDCTL0 PDCTL1 PDCFG0 PDCFG1 MDSTAT0MDSTAT31 MDCTL0MDCTL31 Register Description Revision Identification Register Interrupt Evaluation Register Module Error Pending Register 0 (module 0-31) Module Error Clear Register 0 (module 0-31) Power Error Pending Register Power Error Clear Register Power Domain Transition Command Register Power Domain Transition Status Register Power Domain 0 Status Register Power Domain 1 Status Register Power Domain 0 Control Register Power Domain 1 Control Register Power Domain 0 Configuration Register Power Domain 1 Configuration Register Module Status n Register (modules 0-31) Module Control n Register (modules 0-31) Section Section 9.8 Section 9.15 Section 9.2 Section 9.4 Section 9.17 Section 9.6.14 Section 9.13 Section 9. Texas Instruments Incorporated Power and Sleep Controller (PSC) 191 .1 Section 9.6.6.6.6.6.15 Section 9.6.2 Section 9. Power and Sleep Controller 0 (PSC0) Registers Address 01C1 0000h 01C1 0018h 01C1 0040h 01C1 0050h 01C1 0060h 01C1 0068h 01C1 0120h 01C1 0128h 01C1 0200h 01C1 0204h 01C1 0300h 01C1 0304h 01C1 0400h 01C1 0404h 01C1 0800h01C1 083Ch 01C1 0A00h01C1 0A3Ch Acronym REVID INTEVAL MERRPR0 MERRCR0 PERRPR PERRCR PTCMD PTSTAT PDSTAT0 PDSTAT1 PDCTL0 PDCTL1 PDCFG0 PDCFG1 MDSTAT0MDSTAT15 MDCTL0MDCTL15 Register Description Revision Identification Register Interrupt Evaluation Register Module Error Pending Register 0 (module 0-15) Module Error Clear Register 0 (module 0-15) Power Error Pending Register Power Error Clear Register Power Domain Transition Command Register Power Domain Transition Status Register Power Domain 0 Status Register Power Domain 1 Status Register Power Domain 0 Control Register Power Domain 1 Control Register Power Domain 0 Configuration Register Power Domain 1 Configuration Register Module Status n Register (modules 0-15) Module Control n Register (modules 0-15) Section Section 9.6.6 PSC Registers Table 9-6 lists the memory-mapped registers for the PSC0 and Table 9-7 lists the memory-mapped registers for the PSC1.www.6.9 Section 9.6.6.6.19 SPRUH77A – December 2011 Submit Documentation Feedback Copyright © 2011.6.6.1 Section 9.3 Section 9. Table 9-6.6.6.11 Section 9.18 Table 9-7.6.9 Section 9.7 Section 9.7 Section 9.6.6.6.com PSC Registers 9.6.6.ti.6.5 Section 9.12 Section 9.6.6.12 Section 9.8 Section 9.6.6.10 Section 9.17 Section 9.16 Section 9.6.6 Section 9.

A write of 0 has no effect.com 9. Interrupt Evaluation Register (INTEVAL) Field Descriptions Bit 31-1 0 Field Reserved ALLEV 0 1 Value 0 Description Reserved Evaluate PSC interrupt (PSCn_ALLINT). Figure 9-1.2 Interrupt Evaluation Register (INTEVAL) The interrupt evaluation register (INTEVAL) is shown in Figure 9-2 and described in Table 9-9. 192 Power and Sleep Controller (PSC) Copyright © 2011.6. Interrupt Evaluation Register (INTEVAL) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only. -n = value after reset 1 0 ALLEV W-0 16 Table 9-9. A write of 1 re-evaluates the interrupt condition.6. Revision Identification Register (REVID) Field Descriptions Bit 31-0 Field REV Value 4482 5A00h Description Peripheral revision ID. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .ti. Revision Identification Register (REVID) 31 REV R-4482 5A00h LEGEND: R = Read only. 9. -n = value after reset 0 Table 9-8. Figure 9-2. W= Write only.PSC Registers www.1 Revision Identification Register (REVID) The revision identification register (REVID) is shown in Figure 9-1 and described in Table 9-8.

3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0) The PSC0 module error pending register 0 (MERRPR0) is shown in Figure 9-3 and described in Table 9-10. PSC1 Module Error Pending Register 0 (MERRPR0) 31 Reserved R-0 LEGEND: R = Read only. PSC0 Module Error Pending Register 0 (MERRPR0) 31 Reserved R-0 15 M[15] R-0 14 M[14] R-0 13 Reserved R-0 0 16 LEGEND: R = Read only. See the module status 15 register (MDSTAT15) for the error condition. Module 15 does not have an error condition.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0) The PSC1 module error pending register 0 (MERRPR0) is shown in Figure 9-4. Figure 9-3.www.6. Module interrupt status bit for module 14 (ARM). Reserved 9.6. -n = value after reset Table 9-10. Module 15 has an error condition.com PSC Registers 9. Module 14 has an error condition. Module 14 does not have an error condition. -n = value after reset 0 SPRUH77A – December 2011 Submit Documentation Feedback Power and Sleep Controller (PSC) Copyright © 2011. Texas Instruments Incorporated 193 . PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions Bit 31-16 15 Field Reserved M[15] 0 1 14 M[14] 0 1 13-0 Reserved 0 Value 0 Description Reserved Module interrupt status bit for module 15 (DSP).ti. Figure 9-4. See the module status 14 register (MDSTAT14) for the error condition.

-n = value after reset 0 194 Power and Sleep Controller (PSC) Copyright © 2011.PSC Registers www. W = Write only. A write of 1 clears the M[15] bit in MERRPR0 and the EMUIHB and EMURST bits in MDSTAT15. PSC0 Module Error Clear Register 0 (MERRCR0) 31 Reserved R-0 15 M[15] W-0 14 M[14] W-0 13 Reserved R-0 0 16 LEGEND: R = Read only. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . A write of 0 has no effect. Figure 9-5.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) The PSC0 module error clear register 0 (MERRCR0) is shown in Figure 9-5 and described in Table 9-11. PSC1 Module Error Clear Register 0 (MERRCR0) 31 Reserved R-0 LEGEND: R = Read only.com 9. PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions Bit 31-16 15 Field Reserved M[15] 0 1 14 M[14] 0 1 13-0 Reserved 0 Value 0 Description Reserved Clears the interrupt status bit (M[15]) set in the PSC0 module error pending register 0 (MERRPR0) and the interrupt status bits set in the module status 15 register (MDSTAT15). Clears the interrupt status bit (M[14]) set in the PSC0 module error pending register 0 (MERRPR0) and the interrupt status bits set in the module status 14 register (MDSTAT14).ti. -n = value after reset Table 9-11. A write of 1 clears the M[14] bit in MERRPR0 and the EMUIHB and EMURST bits in MDSTAT14. Reserved 9. Figure 9-6.6. A write of 0 has no effect.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) The PSC1 module error clear register 0 (MERRCR0) is shown in Figure 9-6.6.

-n = value after reset 2 1 P[1] W-0 0 Rsvd R-0 16 Table 9-13.7 Power Error Pending Register (PERRPR) The power error pending register (PERRPR) is shown in Figure 9-7 and described in Table 9-12.6. A write of 0 has no effect. Figure 9-8. Reserved SPRUH77A – December 2011 Submit Documentation Feedback Power and Sleep Controller (PSC) Copyright © 2011.www. See the power domain 1 status register (PDSTAT1) for the error condition. A write of 1 clears the P bit in PERRPR and the interrupt status bits in PDSTAT1. Figure 9-7.6. Reserved 9. W = Write only. Power Error Pending Register (PERRPR) Field Descriptions Bit 31-2 1 Field Reserved P[1] 0 1 0 Reserved 0 Value 0 Description Reserved RAM/Pseudo (PD1) power domain interrupt status. Power Error Clear Register (PERRCR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only.8 Power Error Clear Register (PERRCR) The power error clear register (PERRCR) is shown in Figure 9-8 and described in Table 9-13. Texas Instruments Incorporated 195 . -n = value after reset 2 1 P[1] R-0 0 Rsvd R-0 16 Table 9-12. RAM/Pseudo power domain has an error condition. RAM/Pseudo power domain does not have an error condition.com PSC Registers 9. Power Error Clear Register (PERRCR) Field Descriptions Bit 31-2 1 Field Reserved P[1] 0 1 0 Reserved 0 Value 0 Description Reserved Clears the interrupt status bit (P) set in the power error pending register (PERRPR) and the interrupt status bits set in the power domain 1 status register (PDSTAT1).ti. Power Error Pending Register (PERRPR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only.

com 9.9 Power Domain Transition Command Register (PTCMD) The power domain transition command register (PTCMD) is shown in Figure 9-9 and described in Table 9-14.STATE). If any of the NEXT fields are not matching the corresponding current state (PDSTAT. -n = value after reset 2 1 GO[1] W-0 0 GO[0] W-0 16 Table 9-14.ti. A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including MDCTL. A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain (including PDCTL. If any of the NEXT fields are not matching the corresponding current state (MDSTAT. W = Write only.STATE).6. MDSTAT.NEXT for all the modules residing on this domain).NEXT for all the modules residing on this domain). Power Domain Transition Command Register (PTCMD) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only.PSC Registers www. and MDCTL. Always ON (PD0) power domain GO transition command.STATE. A write of 0 has no effect. Power Domain Transition Command Register (PTCMD) Field Descriptions Bit 31-2 1 Field Reserved GO[1] 0 1 Value 0 Description Reserved RAM/Pseudo (PD1) power domain GO transition command. the PSC will transition those respective domain/modules to the new NEXT state. the PSC will transition those respective domain/modules to the new NEXT state. 0 1 A write of 0 has no effect. 0 GO[0] 196 Power and Sleep Controller (PSC) Copyright © 2011. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Figure 9-9.NEXT for this domain.

either the power domain is transitioning or modules in this power domain are transitioning).com PSC Registers 9. No transition in progress. SPRUH77A – December 2011 Submit Documentation Feedback Power and Sleep Controller (PSC) Copyright © 2011. Always ON (PD0) power domain transition status.ti. Power Domain Transition Status Register (PTSTAT) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only. -n = value after reset 2 1 GOSTAT[1] R-0 0 GOSTAT[0] R-0 16 Table 9-15.www. Always On power domain is transitioning. Texas Instruments Incorporated 197 . Figure 9-10. Modules in Always ON power domain are transitioning. No transition in progress. RAM/Pseudo power domain is transitioning (that is.6. Power Domain Transition Status Register (PTSTAT) Field Descriptions Bit 31-2 1 Field Reserved GOSTAT[1] 0 1 0 GOSTAT[0] 0 1 Value 0 Description Reserved RAM/Pseudo (PD1) power domain transition status.10 Power Domain Transition Status Register (PTSTAT) The power domain transition status register (PTSTAT) is shown in Figure 9-10 and described in Table 9-15 .

11 Power Domain 0 Status Register (PDSTAT0) The power domain 0 status register (PDSTAT0) is shown in Figure 9-11 and described in Table 9-16. Interrupt is not active.6. Power Domain 0 Status Register (PDSTAT0) 31 Reserved R-0 15 Reserved R-0 12 11 EMUIHB R-0 10 Rsvd R-0 9 PORDONE R-0 8 POR R-0 7 Reserved R-0 5 4 STATE R-0 0 16 LEGEND: R = Read only. Power domain is in the on state. Reserved Power Domain Status. Power Domain 0 Status Register (PDSTAT0) Field Descriptions Bit 31-12 11 Field Reserved EMUIHB 0 1 10 9 Reserved PORDONE 0 1 8 POR 0 1 7-5 4-0 Reserved STATE 0 0-1Fh 0 1h 2h-Fh 10h-1Ah 1Bh-1Fh 0 Value 0 Description Reserved Emulation alters domain state. Power domain is in the off state.com 9. Power domain POR is de-asserted. Power domain POR is done.PSC Registers www. Reserved Power_On_Reset (POR) Done status Power domain POR is not done. No emulation altering user-desired power domain states. Emulation alters user-desired power domain state. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Interrupt is active. -n = value after reset Table 9-16. Power domain POR is asserted.ti. Reserved Power domain is in transition. This bit reflects the POR status for this power domain including all modules in the domain. Reserved 198 Power and Sleep Controller (PSC) Copyright © 2011. Power Domain Power_On_Reset (POR) status. Figure 9-11.

Power Domain 1 Status Register (PDSTAT1) Field Descriptions Bit 31-12 11 Field Reserved EMUIHB 0 1 10 9 Reserved PORDONE 0 1 8 POR 0 1 7-5 4-0 Reserved STATE 0 0-1Fh 0 1h 2h-Fh 10h-1Ah 1Bh-1Fh 0 Value 0 Description Reserved Emulation alters domain state. Power domain is in the on state. Reserved Power domain is in transition. Emulation alters user-desired power domain state. This bit reflects the POR status for this power domain including all modules in the domain.com PSC Registers 9. Texas Instruments Incorporated 199 . Power domain is in the off state.www. Reserved Power_On_Reset (POR) Done status Power domain POR is not done. Power Domain Power_On_Reset (POR) status. Power Domain 1 Status Register (PDSTAT1) 31 Reserved R-0 15 Reserved R-0 12 11 EMUIHB R-0 10 Rsvd R-0 9 PORDONE R-0 8 POR R-0 7 Reserved R-0 5 4 STATE R-0 0 16 LEGEND: R = Read only. -n = value after reset Table 9-17. Interrupt is not active.12 Power Domain 1 Status Register (PDSTAT1) The power domain 1 status register (PDSTAT1) is shown in Figure 9-12 and described in Table 9-17. Interrupt is active. Power domain POR is de-asserted. Reserved Power Domain Status.ti. Reserved SPRUH77A – December 2011 Submit Documentation Feedback Power and Sleep Controller (PSC) Copyright © 2011. Power domain POR is asserted. Figure 9-12. Power domain POR is done. No emulation altering user-desired power domain states.6.

Reserved Reserved Power domain next state. Power down mode. Power domain on.ti. Reserved Core on. Power Domain 0 Control Register (PDCTL0) 31 Reserved R-0 15 PDMODE R-Fh 12 11 R-0 10 9 EMUIHBIE R/W-0 8 Rsvd R-1 7 Reserved R-0 24 23 WAKECNT R/W-1Fh 1 0 NEXT R/W-1 16 Reserved LEGEND: R/W = Read/Write. RAM array on. Bits 23-30: GOOD2ACCESS wake delay.6.PSC Registers www. -n = value after reset Table 9-18. Reserved Emulation alters power domain state interrupt enable. 200 Power and Sleep Controller (PSC) Copyright © 2011. Bits 19-16: ON2GOOD wake delay. Disable interrupt. R = Read only. Enable interrupt.com 9.13 Power Domain 0 Control Register (PDCTL0) The power domain 0 control register (PDCTL0) is shown in Figure 9-13 and described in Table 9-18. Power Domain 0 Control Register (PDCTL0) Field Descriptions Bit 31-24 23-16 15-12 Field Reserved WAKECNT PDMODE Value 0 0-FFh 0-Fh 0-Eh Fh 11-10 9 Reserved EMUIHBIE 0 1 8 7-1 0 Reserved Reserved NEXT 0 1 1 0 0 Description Reserved RAM wake count delay value. Power domain off. RAM periphery on. but writes have no effect since internally this power domain always remains in the on state. Figure 9-13. For Always ON power domain this bit is read/write. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Not recommended to change the default value (1Fh).

RAM array off. Reserved Core retention. Power domain on. RAM array off. Core retention. Power Domain 1 Control Register (PDCTL1) Field Descriptions Bit 31-24 23-16 15-12 Field Reserved WAKECNT PDMODE Value 0 0-FFh 0-Fh 0 1h 2h-3h 4h 5h 6h-7h 8h 9h Ah Bh Ch-Eh Fh 11-10 9 Reserved EMUIHBIE 0 1 8 7-1 0 Reserved Reserved NEXT 0 1 1 0 0 Description Reserved RAM wake count delay value. Reserved Core on. RAM periphery on. RAM periphery off (deep sleep). Power domain off. Not recommended to change the default value (1Fh). Power down mode. -n = value after reset Table 9-19.14 Power Domain 1 Control Register (PDCTL1) The power domain 1 control register (PDCTL1) is shown in Figure 9-14 and described in Table 9-19. Figure 9-14. RAM periphery on.com PSC Registers 9. RAM periphery off (deep sleep). RAM periphery off (deep sleep). Enable interrupt. Disable interrupt.ti. RAM periphery off. SPRUH77A – December 2011 Submit Documentation Feedback Power and Sleep Controller (PSC) Copyright © 2011. Bits 19-16: ON2GOOD wake delay. Core off. Core on. Reserved Core on. RAM array retention. RAM periphery off (light sleep). RAM array on. R = Read only. RAM array retention. Core on. RAM periphery off. RAM array retention.6. Reserved Reserved User-desired power domain next state. Bits 23-30: GOOD2ACCESS wake delay. Texas Instruments Incorporated 201 . Core off. RAM periphery off. Reserved Emulation alters power domain state interrupt enable.www. RAM array retention. Power Domain 1 Control Register (PDCTL1) 31 Reserved R-0 15 PDMODE R-Fh 12 11 R-0 10 9 EMUIHBIE R/W-0 8 Rsvd R-1 7 Reserved R-0 24 23 WAKECNT R/W-1Fh 1 0 NEXT R/W-1 16 Reserved LEGEND: R/W = Read/Write. Core on. RAM array off. RAM array retention.

PSC Registers www.6.NEXT bit is not locked.com 9. Always ON power domain.NEXT lock. Power Domain 0 Configuration Register (PDCFG0) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only. 202 Power and Sleep Controller (PSC) Copyright © 2011. Figure 9-15. Not an Always ON power domain. -n = value after reset 4 3 PD_LOCK R-1 2 ICEPICK R-1 1 R-0 0 R-1 16 RAM_PSM ALWAYSON Table 9-20. Power Domain 0 Configuration Register (PDCFG0) Field Descriptions Bit 31-4 3 Field Reserved PD_LOCK 0 1 2 ICEPICK 0 1 1 RAM_PSM 0 1 0 ALWAYSON 0 1 Value 0 Description Reserved PDCTL. Always ON power domain. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .15 Power Domain 0 Configuration Register (PDCFG0) The power domain 0 configuration register (PDCFG0) is shown in Figure 9-15 and described in Table 9-20. Not present Present RAM power domain. IcePick support. PDCTL. Not a RAM power domain.ti. PDCTL. For Always ON power domain this bit is a don't care.NEXT bit is locked and cannot be changed in software. RAM power domain.

6. PDCTL. Always ON power domain. Not a RAM power domain. Not an Always ON power domain.www. PDCTL. IcePick support. Always ON power domain. RAM power domain. For Always ON power domain this bit is a don't care.16 Power Domain 1 Configuration Register (PDCFG1) The power domain 1 configuration register (PDCFG1) is shown in Figure 9-16 and described in Table 9-21. Not present Present RAM power domain.NEXT lock.ti. Power Domain 1 Configuration Register (PDCFG1) Field Descriptions Bit 31-4 3 Field Reserved PD_LOCK 0 1 2 ICEPICK 0 1 1 RAM_PSM 0 1 0 ALWAYSON 0 1 Value 0 Description Reserved PDCTL. SPRUH77A – December 2011 Submit Documentation Feedback Power and Sleep Controller (PSC) Copyright © 2011.com PSC Registers 9. -n = value after reset 4 3 PD_LOCK R-1 2 ICEPICK R-1 1 R-0 0 R-1 16 RAM_PSM ALWAYSON Table 9-21. Texas Instruments Incorporated 203 .NEXT bit is locked and cannot be changed in software. Power Domain 1 Configuration Register (PDCFG1) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only. Figure 9-16.NEXT bit is not locked.

you must set the EMURSTIE bit in the module control 14 register (MDCTL14) and the module control 15 register (MDCTL15). This field is 1 for all other modules. This bit applies to ARM module (module 14) and DSP module (module 15). This bit applies to ARM module (module 14) and DSP module (module 15). If you desire to generate a PSCINT upon this event. 0 1 No emulation altering user-desired module reset state. 0 1 8 LRST 0 1 7-6 5-0 Reserved STATE 0 0-3Fh 0 1h 2h 3h 4h-3Fh 204 Local reset is not done. If you desire to generate a PSCINT upon this event. Reflects actual state of module reset. This bit applies to ARM module (module 14) and DSP module (module 15). Local reset is done.ti. Module Status n Register (MDSTATn) Field Descriptions Bit 31-18 17 Field Reserved EMUIHB 0 1 Value 0 Description Reserved Emulation alters module state. -n = value after reset Table 9-22. No emulation altering user-desired module state programmed in the NEXT bit in the module control 14 register (MDCTL14) and the module control 15 register (MDCTL15). Software is responsible for checking if local reset is done before accessing this module. This bit applies to ARM module (module 14) and DSP module (module 15). Figure 9-17. Emulation altered user-desired module reset state. you must set the EMUIHBIE bit in MDCTL14 and MDCTL15. Reserved Module reset status.com 9. Module Status n Register (MDSTATn) 31 Reserved R-0 15 Reserved R-0 13 12 MCKOUT R-0 11 Rsvd R-1 10 MRST R-0 9 LRSTDONE R-1 8 LRST R-1 7 R-0 6 5 STATE R-0 18 17 EMUIHB R-0 16 EMURST R-0 0 Reserved LEGEND: R = Read only. Emulation altered user-desired state programmed in the NEXT bit in MDCTL14 and MDCTL15. Module clock is on.17 Module Status n Register (MDSTATn) The module status n register (MDSTATn) is shown in Figure 9-17 and described in Table 9-22. Module local reset status. Module reset is de-asserted. Emulation alters module reset. 0 1 11 10 Reserved MRST 0 1 9 LRSTDONE 1 Module clock is off. Shows status of module clock. This field is 0 for all other modules.PSC Registers www. Texas Instruments Incorporated . Local reset is asserted. Module reset is asserted. This field is 0 for all other modules. Local reset done. SwRstDisable state SyncReset state Disable state Enable state Indicates transition SPRUH77A – December 2011 Submit Documentation Feedback 16 EMURST 15-13 12 Reserved MCKOUT 0 Power and Sleep Controller (PSC) Copyright © 2011. Reserved Module state status: indicates current module status. Reserved Module clock output status.6. Local reset is de-asserted.

ignoring and bypassing all the clock stop request handshakes managed by the PSC to change the state of the clocks to the module. Module local reset control.www. Reserved Interrupt enable for emulation alters module state. Enable interrupt. Note: It is not recommended to use the FORCE bit to disable the module clock.com PSC Registers 9.ti. Force is enabled. SwRstDisable state SyncReset state Disable state Enable state SPRUH77A – December 2011 Submit Documentation Feedback Power and Sleep Controller (PSC) Copyright © 2011. PSC0 Module Control n Register (MDCTLn) Field Descriptions Bit 31 Field FORCE Value Description Force enable. Assert local reset De-assert local reset Reserved Module next state. This bit applies to ARM module (module 14) and DSP module (module 15). Texas Instruments Incorporated 205 . Disable interrupt. R = Read only. Interrupt enable for emulation alters reset.6. Figure 9-18. unless specified. Disable interrupt. This bit applies to ARM module (module 14) and DSP module (module 15). This bit forces the module state programmed in the NEXT bit in the module control 14 register (MDCTL14) and the module control 15 register (MDCTL15).18 PSC0 Module Control n Register (modules 0-15) (MDCTLn) The PSC0 module control n register (MDCTLn) is shown in Figure 9-18 and described in Table 9-23. This bit applies to ARM module (module 14) and DSP module (module 15). 0 1 30-11 10 Reserved EMUIHBIE 0 1 9 EMURSTIE 0 1 8 LRST 0 1 7-3 2-0 Reserved NEXT 0 0-3h 0 1h 2h 3h 0 Force is disabled. -n = value after reset Table 9-23. Enable interrupt. PSC0 Module Control n Register (MDCTLn) 31 FORCE R/W-0 15 Reserved R-0 11 10 EMUIHBIE R/W-0 9 EMURSTIE R/W-0 30 Reserved R-0 8 LRST R/W-0 7 Reserved R-0 3 2 NEXT R/W-0 0 16 LEGEND: R/W = Read/Write.

Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . R = Read only. Force is enabled. Note: It is not recommended to use the FORCE bit to disable the module clock.ti.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn) The PSC1 module control n register (MDCTLn) is shown in Figure 9-19 and described in Table 9-24.PSC Registers www. PSC1 Module Control n Register (MDCTLn) Field Descriptions Bit 31 Field FORCE Value Description Force enable. 0 1 30-3 2-0 Reserved NEXT 0 0-3h 0 1h 2h 3h Force is disabled. This bit forces the module state programmed in the NEXT bit in the module control 14 register (MDCTL14) and the module control 15 register (MDCTL15). ignoring and bypassing all the clock stop request handshakes managed by the PSC to change the state of the clocks to the module. -n = value after reset 30 Reserved R-0 3 2 NEXT R/W-0 0 16 Table 9-24. PSC1 Module Control n Register (MDCTLn) 31 FORCE R/W-0 15 Reserved R-0 LEGEND: R/W = Read/Write.com 9. Figure 9-19. Reserved Module next state. SwRstDisable state SyncReset state Disable state Enable state 206 Power and Sleep Controller (PSC) Copyright © 2011. unless specified.6.

................... ARM Sleep Mode Management ................................................................. Deep Sleep Mode ...................................................1 10............................5 10...................................7 10....... Texas Instruments Incorporated 207 ..........................................................4 10........ Power Consumption Overview ....................................................................3 10. Dynamic Voltage and Frequency Scaling (DVFS) ... Page 10..........8 10........ Introduction ........................ Features ............................11 208 208 208 209 210 211 214 216 217 218 222 SPRUH77A – December 2011 Submit Documentation Feedback Power Management Copyright © 2011............... RTC-Only Mode .... Clock Management ......................................................................................... DSP Sleep Mode Management ...........10 10...9 10...... Additional Peripheral Power Management Considerations ................................................................................................ PSC and PLLC Overview ..............................................................6 10..................2 10......................................Chapter 10 SPRUH77A – December 2011 Power Management Topic ..........................................................................................................................................................................................................................................................

thus. Leakage current is dependent mostly on the manufacturing process used. on the battery life. as the name suggests. Similarly. This chapter discusses the various power management features. It can be shown as: Pstatic = f(leakage current) It is essentially a function of the “leakage”. Leakage current is unavoidable while power is applied and scales roughly with the operating junction temperatures. 10.Introduction www. For detailed information on the PLLC0 and PLLC1. lower power consumption results in more optimal and efficient designs from cost. The dynamic power is defined by: Pdynamic = Capacitance × Voltage2 × Frequency From the above formula. analog circuits changing states.com 10. and manage the frequency scaling operations for the device. see the Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter. so the voltage of operations has significant impact on overall power consumption and. For detailed information on the PSC. busses.2 Power Consumption Overview Power consumed by semiconductor devices has two components: dynamic and static. 10. or the power consumed by the logic when it is not switching or is not performing any work.ti. etc. the two PLL controllers (PLLC0 and PLLC1) play an important role in device and module clock generation. or the load capacitances on the switching I/O pins. when the performance requirements are not that high and the device can be operated at a corresponding lower frequency.3 PSC and PLLC Overview The power and sleep controller (PSC) module plays an important role in managing the enabling/disabling of the clocks to the core and various peripheral modules. In the formula. the size of the die. is independent of the switching frequency of the logic. Leakage power can only be avoided by removing power completely from a device or subsystem. Dynamic power can be reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to complete the required operation in the required timeline or to run at a clock setting until the work is complete and then drastically reduce the clock frequency or cut off the clocks until additional work must be performed. Together these modules play a significant role in managing the clocks from a power management feature standpoint. and I/O switching). 208 Power Management Copyright © 2011. The static power. The static power consumption plays a significant role in the Standby Modes (when the application is not running and in a dormant state) and plays an important role in the battery life for portable applications. The PSC provides a granular support to turn on/off clocks on a module by module basis. and energy perspectives. This device has several means of managing the power consumption. For several applications and target markets. Additionally. etc.1 Introduction Power management is an important aspect for most embedded applications. that is. the dynamic power scales with the clock frequency (device/module frequency for core operations and switching frequency for I/O). there may be a specific power budget and requirements to minimize power consumption for both power supply sizing and battery life considerations. the dynamic power varies with the voltage squared. see the Power and Sleep Controller (PSC) chapter. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . The capacitance is the capacitance of the switching nodes. Dynamic power can be reduced by scaling the operating voltage. design. This can be shown as: Ptotal = Pdynamic + Pstatic The dynamic power is the power consumed to perform work when the device is in active modes (clocks applied.

ti. Features Reduces the dynamic power consumption.0 I/O power consumption when not in use. Reduces the dynamic power consumption of the core. Minimizes the SATA I/O power consumption when not in use. low standby-power consumption modes. Power Management Features Power Management PLL bypass and power-down Module clock ON Description Clock Management Both PLLs can be powered-down and run in bypass mode when not in use. The operating voltage and frequency of the device can be dynamically scaled to meet the requirements of the application. Clock management also allows you to slow down the clocks. Allows memory to retain its contents while the rest of the system is powered down. The DSP CPU can be put in sleep (IDLE) mode. Peripheral I/O Power Management USB PHY power-down DDR2/mDDR self-refresh mode Minimizes the USB2. Reduces the dynamic power consumption. Core Sleep Management ARM subsystem sleep modes DSP subsystem sleep mode The ARM CPU can be put in sleep mode. the DSP subsystem clock can be completely gated when not in use. This device uses the state-of-the-art 65 nm process. Reduces the I/O leakage power. Reduces the dynamic power consumption of the core and I/O (if any free running I/O clocks). Texas Instruments Incorporated Power Management 209 . thereby. The deep sleep function can be controlled externally through the DEESLEEP pin or internally through the RTC_ALARM pin.4 Features This device has several means of managing power consumption. mDDR and DDR2 can be clock gated to reduce the dynamic power consumption or the entire device can be powered down to reduce the static power consumption. as detailed in the subsequent sections. Table 10-1. Additionally. There are several features in design as well as user driven software control to reduce dynamic power consumption. providing high-performance transistors with relatively less leakage current and. SATA PHY power-down LVCMOS I/O buffer receiver disable Internal pull-up and pull-down resistor control The SATA PHY can be placed in standby mode. LVCMOS I/O buffer receivers are disabled.com Features 10. Voltage Management RTC-only mode Allows removing power from all core and I/O supply and just have the real-time clock (RTC) running. which reduces both clock tree and module power by basically disabling the clocks when the modules are not being used. The USB2. SPRUH77A – December 2011 Submit Documentation Feedback Copyright © 2011. Module clocks can be turned on/off without requiring reconfiguring the registers. The on-chip power and sleep controller (PSC) module provides granular software controlled module level clock gating. Dynamic Voltage and Frequency Scaling Dynamic Voltage and Frequency Scaling (DVFS) Deep Sleep Mode Reduces the dynamic power consumption of the core and I/O as well as standby power System/Device Sleep Management Reduces the dynamic power consumption of the core and I/O.www. All internal clocks of the device can be turned on/off at the OSCIN level. to reduce the dynamic power. which provides a good balance on power and performance. Table 10-1 describes the power management features. Reduces the dynamic and static power for standby modes that require only the RTC to be functional.0 PHY can be powered-down. the ARM subsystem clock can be completely gated when not in use. Additionally. Minimizes the I/O power consumption. The internal pull-ups and pull-downs are enabled/disabled by groups. The design features (not under user control) include a power optimized clock tree design to reduce overall clock tree power consumption and automatic clock gating in several modules when the logic in the modules is not active.

the module resumes operating from the stopping point. in order to reduce the module's dynamic/switching power consumption down to zero. the access may not occur. which scales linearly with frequency. The PSC provides some protection against such erroneous conditions by monitoring the internal bus activity to ensure there are no accesses to the module from the internal bus.2 Module Clock Frequency Scaling Module clock frequency is scalable by programming the PLL multiply and divide parameters.Clock Management www. and it can potentially result in unexpected behavior. Additionally. before allowing module’s internal clock to be gated. This device is designed in full static CMOS. In this state. the module's state is preserved and retained.4. 10. some modules might also have internal clock dividers. However. The Phase-Locked Loop Controller (PLLC) chapter describes how to program the PLL0 and PLL1 frequency and the frequency constraints. it is still recommended that software must ensure that all of the transactions to the module are finished prior to disabling the clocks.7. special consideration must be given to DSP/ARM clock on/off.5 Clock Management 10.com 10. The Device Clocking chapter details the clocking structure of the device.1 Module Clock ON/OFF The module clock on/off feature allows software to disable clocks to module individually. the module reset is not asserted and only the module clock is turned off.5. when a module clock stops. If a module's clock(s) is stopped while being accessed. it does not affect static power consumption of the module or the device. but reduces overall dynamic power consumption when modules are not active. The power and sleep controller (PSC) module controls module clock gating. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . thus. when the logic is not active. Furthermore. When the clock is restarted. The procedure to turn the core clock on/off is further described in Section 10. 210 Power Management Copyright © 2011. The procedure to turn module clocks on/off using the PSC is described in the Power and Sleep Controller (PSC) chapter.5. Additionally some peripherals implement additional power saving features by automatically shutting of clock to components within the module. NOTE: Stopping clocks to a module only affects dynamic power consumption. NOTE: To preserve the state of the module. the module state in the PSC must be set to Disable. This is transparent to you. Reducing the clock frequency reduces the dynamic/switching power consumption.ti.

#0. When the PLL controller is placed in bypass mode. The OSCIN frequency is typically. #0. c7. Texas Instruments Incorporated 211 . When the wait-for-interrupt mode is enabled. the bypass clock is always OSCIN.5. the PLL retains its frequency lock. it will remain in this state until an interrupt request (IRQ/FIQ) occurs. • Enable the WFI mode using the following CP15 instruction: – MCR p15. • The ARM’s PC jumps to the IRQ/FIQ vector and you must handle the interrupt in an interrupt service routine (ISR). <Rd>. an external interrupt) that you plan to use as the wake-up interrupt to exit from the WFI mode. NOTE: To enable the WFI mode. c0. an external interrupt). 10. c0.3 PLL Bypass and Power Down You can bypass each PLL in this device. the ARM needs to be in supervisor mode.www. However. r3. the bypass clock is selected from either the PLL reference clock (OSCIN) or PLL1_SYSCLK3. The Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter describe PLL bypass and PLL power down. This can lower the overall dynamic power consumption. up to 50 MHz. You can enable the WFI mode via the CP15 register #7 using the following instruction: • MCR p15.arm.com/help/index. The following sequence exemplifies how to enter the WFI mode: • Enable any interrupt (for example. For PLLC1. SPRUH77A – December 2011 Submit Documentation Feedback Power Management Copyright © 2011.jsp. You can also power-down the PLL when bypassing it to minimize the overall power consumed by the PLL module. For PLLC0. trigger any enabled interrupt (for example. which is linearly proportional to the frequency. Exit the ISR and continue normal program execution starting from the instruction immediately following the instruction that enabled the WFI mode. keeping the PLL locked consumes power. This is a feature for dynamic power management of the ARM processor itself. GPIO or watchdog timer) must not be disabled. #4 Once the ARM module transitions into the WFI mode.6 ARM Sleep Mode Management 10.com ARM Sleep Mode Management 10. The advantage of bypassing the PLL without powering it down is that you do not have to incur the PLL lock time when switching back to a normal operating level. at most.1 ARM Wait-For-Interrupt Sleep Mode The ARM module can be put into a low-power state using a special sleep mode called wait-for-interrupt (WFI).ti.6. it does not impact the static power. Bypassing the PLL sends a bypass clock instead of the PLL VCO output (PLLOUT) to the system clocks of the PLLC. You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low maintenance levels without using the PLL during periods of very low system activity. c7. #4 The following sequence describes the procedure to wake-up from the WFI mode: • To wake-up from the WFI mode. downloadable from http://infocenter. For more information on this sleep mode. the core is completely inactive and only resumes operation after receiving an interrupt. This allows you to switch between bypass mode and PLL mode without having to wait for the PLL to relock. NOTE: The ARM interrupt controller (AINTC) and the module sourcing the wake-up interrupt (for example. see the ARM926EJ-S Technical Reference Manual (TRM). or the device will never wake up. all internal clocks within the ARM9 module are shut off.

The GOSTAT[0] bit transitions to 0 when the ARM executes the wait-for-interrupt instruction from inside its interrupt service routine (ISR). The following sequence should be executed by the ARM within the ARM Clock Stop Request interrupt ISR: 1. (a) Initiate the ARM clock off sequence by issuing the ARM clock stop command (PSC DISABLE Command) to the ARM subsystem by writing a 2h to the NEXT bit field in the ARM local power sleep controller (LPSC) module control register (PSC0.ti.ARM Sleep Mode Management www. 3. one of the CHIPSIG interrupts controlled by the chip signal register (CHIPSIG) in the System Configuration (SYSCFG) Module chapter—CHIPSIG[0]. etc. The DSP must check for the completion of all transactions initiated by it and the peripherals controls by the DSP to the ARM resources.MDSTAT14) indicating the ARM clock stop sequence completion (STATE: Disable). 3.). ARM module clock off sequence: 1.MDCTL14).2 ARM Clock OFF The software must be structured such that no peripheral is allowed to access the ARM resources before disabling the clocks to the ARM subsystem. Execute the wait-for-interrupt (WFI) ARM instruction. 2. Check for completion of all ARM master requests (the ARM polls transfer completion statuses of all Master peripherals).PTSTAT) for power transition sequence completion. 212 Power Management Copyright © 2011. CHIPSIG[1]. CFG and DMA port operations.6. Enable the interrupt to be used as the “wake-up” interrupt (for example. This generates the ARMCLKSTOPREQ interrupt to the ARM. ARM interrupt # 90) enabled and the associated interrupt service routine (ISR) set up before the DSP initiates the following ARM clock shutdown procedure. The ARM must check for the completion of all its master peripheral initiated requests (that is. The DSP stops all masters from accessing the ARM and ARM memory.PTCMD) to start the state transition sequence for the ARM module. (d) Check (poll for 2h) the STATE bit field in the ARM LPSC module status register (PSC0. if the transfer completion status is not implemented). Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . The DSP polls all masters for write-completion status (or wait n number of cycles. (c) Check (poll for 0) the GOSTAT[0] bit in the power domain transition status register (PSC0. The ARM must have the ARM Clock Stop Request interrupt (ARMCLKSTOPREQ.) that will be used to wake-up the ARM during the ARM clock-on sequence.com 10. (b) Write a 1 to the GO[0] bit (ARM subsystem is part of the PD_ALWAYSON domain) in the power domain transition command register (PSC0. etc. 2.

the DSP side software is responsible for enabling the clock and releasing the reset to the ARM at power-on reset. Wait for the GOSTAT[0] bit in the power domain transition status register (PSC0. The domain is only safely in the new state after the GOSTAT[0] bit is cleared to 0. Wait for the STATE bit field in the ARM LPSC module status register (PSC0. Write a 3h to the NEXT bit in the ARM local power sleep controller (LPSC) module control register (PSC0. You must wait for the power domain to finish any previously initiated transitions before initiating a new transition. For the DSP to wake the ARM if transitioning from the Disable state. SPRUH77A – December 2011 Submit Documentation Feedback Power Management Copyright © 2011.PTSTAT for power transition sequence completion. This example assumes that the ARM enabled this interrupt before entering its wait-for-interrupt sleep mode state. NOTE: This only applies if you are transitioning from the Disable state. a wake-up interrupt must be triggered in order to wake the ARM (to exit the wait-for-interrupt mode). Check (poll for 0) the GOSTAT[0] bit in PSC0.6. the following clock on sequence is applicable only when it is required to wake-up the ARM. Perform the following sequence for the DSP to enable clocks to the ARM: 1. 2. therefore.com ARM Sleep Mode Management 10. Write a 1 to the GO[0] bit (ARM subsystem is part of the PD_ALWAYSON domain) in the power domain transition command register (PSC0. 4. 5.MDSTAT14) to change to 3h.3 ARM Subsystem Clock ON The ARM module defaults to the SwRstDisable state.ti.MDCTL14) to prepare the ARM module for an enable transition. 3. If previously in the Disable state. The module is only safely in the new state after the STATE bit field changes to reflect the new state.PTSTAT) to clear to 0.www. Texas Instruments Incorporated 213 . trigger an ARM interrupt that has previously been configured as a wake-up interrupt. If the DSP has put the ARM in the clock off/Disable state.PTCMD) to start the state transition sequence for the ARM module.

10. then you can choose to disable the clock to the DSP using the PSC. For information on the IDLE instruction. see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5).3 C674x Megamodule Sleep Mode The IDLE instruction is used as part of the procedure for shutting down the entire C674x megamodule. Additional power saving can be achieved by stopping the clock sourced (PLL output) to the C674x megamodule by programming the power and sleep controller (PSC) module to place the megamodule in the Disable state. For information on the PDC module. The ARM is responsible for programming the PSC to disable the clock going to the C674x megamodule at the root level (stopping PLL0_SYSCLK1 at the PLL output).7 DSP Sleep Mode Management 10. If additional power saving is desired (more then just power savings obtained by using the power down controller). as compared to just executing the IDLE instruction to put only the CPU in idle mode. because the DSP will not be able to complete the PSC programming sequence if its clock source is gated in the middle of the process.7.4 C674x Megamodule Clock ON/OFF The C674x megamodule can clock gate its own components to save power.2 C674x DSP CPU Sleep Mode The DSP CPU can be put in a low-power state by executing the IDLE instruction. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . The DSP cannot perform this programming task on its own.7.7. In shutting down the entire C674x megamodule. The ARM is also responsible for programming the PSC to enable the C674x megamodule.7. see the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8). see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5). the PDC can internally clock gate off the following components of the megamodule and internal memories of the DSP subsystem: • C674x CPU • Level 1 Program Memory Controller (PMC) • Level 1 Data Memory Controller (DMC) • Level 2 Unified Memory Controller (UMC) • Extended Memory Controller (EMC) • L1P Memory • L1D Memory • L2 Memory Putting the entire C674x megamodule into the low-power sleep mode is typically more useful and saves a lot more power. 10. For information on putting the C674x megamodule in the low-power mode using the PDC. by the power-down controller (PDC) module.com 10. this enables saving additional clock tree power (for the path from the PLL to the megamodule boundary).ti.DSP Sleep Mode Management www. By clock gating the megamodule at the root. 214 Power Management Copyright © 2011. 10.1 DSP Sleep Modes The C674x megamodule has an internal power down controller (PDC) module that provides additional power management features in addition to clock management control provided by the device-level power and sleep controller (PSC) module.

EDMA. (a) Initiate the DSP clock off sequence by issuing the DSP clock stop command (PSC DISABLE Command) to the DSP subsystem by writing a 2h to the NEXT bit field in the DSP local power sleep controller (LPSC) module control register (PSC0. 3. The ARM stops all masters from accessing the DSP and DSP memory.1 C674x Megamodule Clock OFF The software must be structured such that no peripheral is allowed to access the DSP resources before disabling the DSP clocks. 3.MDCTL15). The DSP must have the power-down controller interrupt PDC_INT (DSP interrupt #118) enabled and the PDC interrupt service routine (ISR) set up before the ARM initiates the following DSP clock shutdown procedure. 2. 1.7. The GOSTAT[1] bit transitions to 0 when the DSP executes the IDLE instruction from inside its interrupt service routine (ISR). cache operations. This generates the PDC_INT interrupt to the DSP. one of the CHIPSIG interrupts controlled by the chip signal register (CHIPSIG) in the System Configuration (SYSCFG) Module chapter—CHIPSIG[2]. or CHIPSIG[4]/NMI interrupt) that will be used to wake-up the DSP during the DSP clock-on sequence. 4. SPRUH77A – December 2011 Submit Documentation Feedback Power Management Copyright © 2011. if the transfer completion status is not implemented). Write a 0001 5555h to PDCCMD. Texas Instruments Incorporated 215 . 2. Check for completion of all DSP master requests (the DSP polls transfer completion statuses of all Master peripherals).com DSP Sleep Mode Management 10.MDSTAT15) indicating the DSP clock stop sequence completion (STATE: Disable). MDMA. Enable the interrupt to be used as “wake-up” interrupt (for example. (b) Write a 1 to the GO[1] bit (DSP subsystem is part of the PD_DSP domain) in the power domain transition command register (PSC0. CHIPSIG[3].www. (c) Check (poll for 0) the GOSTAT[1] bit in the power domain transition status register (PSC0.PTSTAT) for power transition sequence completion. Execute the IDLE instruction. The ARM polls all masters for write-completion status (or wait n number of cycles. The DSP must check for the completion of all its master peripheral initiated requests (that is.PTCMD) to start the state transition sequence for the DSP module.4. (d) Check (poll for 2h) the STATE bit field in the DSP LPSC module status register (PSC0. The ARM must check for the completion of all transactions initiated by it and the peripherals controls by it to the DSP resources.ti.). The following sequence should be executed by the DSP within the PDC interrupt ISR: 1. IDMA. etc. NOTE: The power-down command register (PDCCMD) in the power-down controller (PDC) can only be written while the DSP is in Supervisor mode.

Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . as voltage from the rest of the core and I/O logic can be completely removed. therefore. the RTC_ALARM pin is not available as an option for use as a control to signal an external power supply to reapply power to the rest of the device.8 RTC-Only Mode In real-time clock (RTC)-only mode.7. You must wait for the power domain to finish any previously initiated transitions before initiating a new transition.RTC-Only Mode www.PTSTAT) to clear to 0. For the ARM to wake the DSP if transitioning from the Disable state. the RTC is powered on and the rest of the device is completely powered off (all supplies except the RTC supply are removed). Mobile DDR and DDR2 contents can be preserved through the use of self-refresh (see Section 10.PTSTAT for power transition sequence completion. Check (poll for 0) the GOSTAT[1] bit in PSC0. except for the RTC core logic supply (RTC_CVDD). This clock on sequence is only required to wake-up the DSP. NOTE: To put the device in RTC-only mode. the RTC is fully functional and keeps track of date. eliminating most of the active and static power of the device. etc. for example. First. a wake-up interrupt must be triggered in order to wake the DSP. only the RTC register contents are preserved. 2. and seconds. However.2 C674x Megamodule Clock ON The C674x megamodule defaults to the Enable state. This example assumes that the DSP enabled this interrupt before entering its IDLE state. there is no software control sequence. hours.4. interrupt vectors. except for what is consumed by the RTC module. 216 Power Management Copyright © 2011. all other internal memory and register contents are lost. reinitialize internal registers. and the following sequence is typically not needed. If previously in the Disable state. You can put the device in the RTC-only mode by removing the power supply from all core and I/O logic. 10. minutes. setup cache memory configurations. In this mode. During wake up. See the DSP Subsystem chapter for more information on DSP interrupts.MDCTL15) to prepare the DSP module for an enable transition. In this mode. Some limitations apply in the RTC-only mode. Wait for the GOSTAT[1] bit in the power domain transition status register (PSC0. 5. running at 32 kHz. if the ARM put the DSP in a clock off state.MDSTAT15) to change to 3h.10. in RTC-only mode. 4. Write a 1 to the GO[1] bit (DSP subsystem is part of the PD_DSP domain) in the power domain transition command register (PSC0. software must be in place to restore the context of the device. The domain is only safely in the new state after the GOSTAT[1] bit is cleared to 0. 3. all power sequencing requirements described in the device-specific data manual must be followed.2). trigger a DSP interrupt that has previously been configured as a wake-up interrupt. The module is only safely in the new state after the STATE bit field changes to reflect the new state.ti. Write a 3h to the NEXT bit field in the DSP local power sleep controller (LPSC) module control register (PSC0.PTCMD) to start the state transition sequence for the DSP module. the overall power consumption would be significantly lower. Wait for the STATE bit field in the DSP LPSC module status register (PSC0. NOTE: This only applies if you are transitioning from the Disable state. Perform the following sequence for the ARM to enable clocks to the DSP: 1. Second. the DSP subsystem clock is on.com 10. This is because the RTC_ALARM pin is powered by the I/O supply that is powered down in RTC-only mode.

See the Device Clocking chapter for information on the clock architecture of the device and see the Phase-Locked Loop Controller (PLLC) chapter for information on the PLL controllers. is composed of a voltage and frequency pair. The PLL0_AUXCLK is derived from OSCIN. 10.com Dynamic Voltage and Frequency Scaling (DVFS) 10. By intelligently switching these elements to their optimal operating points. You determine the optimal OPP for a given task and then switch to that OPP to save power. Bypassing the PLL sends a bypass clock instead of the PLL VCO output (PLLOUT) to the system clock dividers of the PLL controller. When applying DVFS.). the SYSCLK frequency will depend solely on the divider ratios used. it is possible to minimize the power consumption of the device for a given task. A few things must be noted when changing the various internal frequencies of the device: • Changing the SYSCLK frequency The PLL_VCO (PLLOUT) frequency can be programmed through a PLL multiplier.www. the PLLC0 bypass clock can be set to PLL1_SYSCLK3. Each step. Changing the SYSCLK frequency through the dividers is faster as there is no need to reprogram the PLL.1 Frequency Scaling Considerations The operating frequency of the device is controlled through its two PLL controllers (PLLC0 and PLLC1). For PLLC0 the bypass clock is selected from either the PLL reference clock (OSCIN) or PLL1_SYSCLK3. process. This selection is made through the EXTCLKSRC bit in the PLLCTL register of PLLC0. For reasons related to the device (clock architecture. Texas Instruments Incorporated 217 . up to 50 MHZ. However. a processor or system always runs at the lowest OPP that meets the performance requirement at a given time. etc.9. • PLLC0 bypass clock When switching the PLL multiplier. A series of dividers divide PLLOUT to generate the various device SYSCLKs. You can use the OSCIN bypass mode to reduce the core and module clock frequencies to very low maintenance levels without using the PLL during periods of very low system activity. See your device data manual for a list of the OPPs supported by the device. the frequency corresponds to the maximum frequency allowed at a voltage. Care should be taken to ensure that these fixed ratios are maintained. This reduces the total power consumption of the device while still meeting task requirements. When changing the PLL multiplier. When changing the divider ratios it is not required to put the PLL controller in bypass mode. • Peripheral immunity from CPU clock frequency changes Peripherals that are clocked by the PLL0_AUXCLK are immune to changes in the PLL0 frequency. the voltage corresponds to the minimum voltage allowed for a frequency. or reciprocally. DVFS requires control over the clock frequency and the operating voltage of the device elements. For an OPP. For PLLC1. Through a series of multipliers and dividers you can change the frequencies of various clocks throughout the device. SPRUH77A – December 2011 Submit Documentation Feedback Power Management Copyright © 2011. you must put the PLL controller in bypass mode while the PLL multiplier value is modified and a lock on the new frequency is reached. To change the SYSCLK frequency you can change the PLL multiplier or you can change the SYSCLK divider ratio. the PLL controller must be placed in bypass mode. It may be desirable for the bypass clock to not revert to OSCIN in some situations to preserved bandwidth during frequency scaling transitions. see the Device Clocking chapter. For this reason. Peripherals in the ASYNC3 domain are clocked off from either PLL1_SYSCLK2 or PLL0_SYSCLK2. • SYSCLK domain fixed ratios Certain SYSCLK domains need to operate at a fixed ratio with respect to the CPU clock. or operating performance point (OPP). the bypass clock is always OSCIN. The DVFS technique uses dynamic selection of the optimal frequency and voltage to allow a task to be performed in the required amount of time. The OSCIN frequency is typically.ti.9 Dynamic Voltage and Frequency Scaling (DVFS) Dynamic voltage and frequency scaling (DVFS) consists of minimizing the idle time of the system. not over a continuum of voltage and frequency values. For additional details. at most. The lock time is given in the device data manual. DVFS is used only for a few discrete steps.

I2C ports on the device can be used to communicate with external power management chips. the program may continue from where it left off with minimal overhead involved.ti. See the device data manual for ramp rate specifications. 7. 10.11.3). The DEEPSLEEP pin can be driven by an external controller or it can be driven internally by the real-time clock (RTC).10. the maximum operating frequency changes. The USB2. upon recovery. 4.0 (USB0) PHY should be disabled. if this interface is used and internal clocks are selected (see Section 10. 5.11.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up 10. 10. When peripherals are immune to changes in the CPU clock frequency. 6. The external controller should drive the DEEPSLEEP pin high (not in Deep Sleep). The RTC method allows for automatic wake-up at a programmed time. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . their internal clock dividers do not have to be adjusted for changes in their input clock frequencies. Configure the DEEPSLEEP pin as input-only using the PINMUX0_31_28 bits in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter. The SATA PHY should be disabled (see Section 10. 2. The Deep Sleep mode is initiated when the DEEPSLEEP pin is driven low. The USB1. 218 Power Management Copyright © 2011. The device wakes up from Deep Sleep mode when the DEEPSLEEP pin is driven high. For this reason.2 Voltage Scaling Considerations The operating voltage of the device must be totally controlled through mechanisms outside the device.com Furthermore. PLL0_SYSCLK2 must always be /2 of the CPU clock frequency. activate the self-refresh mode and gate the clocks to the DDR2/mDDR memory controller. NOTE: Due to pin multiplexing. if this interface is used and internal clocks are selected (see Section 10. PLL/PLLC0 and PLL/PLLC1 should be placed in bypass mode (clear the PLLEN bit in the PLL control register (PLLCTL) of each PLLC to 0). the DEEPSLEEP pin can only be driven by an external controller or its internal real-time clock (RTC). Care must be taken such that the maximum operating frequency supported at the new voltage is not violated. you can configure the ASYNC3 domain to be clocked from PLL1_SYSCLK2. To preserve DDR2/mDDR memory contents.10 Deep Sleep Mode This device supports a Deep Sleep mode where all device clocks are stopped and the on-chip oscillator is shut down to save power.9.10. Registers and memory contents are preserved.11. A few things must be noted when changing the operating voltage of the device: • Voltage ramp rate: The ramp rate of the operating voltage must be observed during operating performance point (OPP) transitions. 3.Deep Sleep Mode www. The DEEPSLEEP pin cannot be driven by both an external controller and its internal real-time clock at the same time. 10. PLL/PLLC0 and PLL/PLLC1 should be powered down (set the PLLPWRDN bit in PLLCTL of each PLLC to 1).1 Entering Deep Sleep Mode Use the following procedure to enter the Deep Sleep mode if an external signal is used to wake-up the device: 1.1.1 (USB1) PHY should be disabled. it is recommended to change the operating frequency before switching the operating voltage.1). To keep these peripherals immune from changes in PLL0 frequency (such as when the CPU frequency is modified). thus. • Switching to a lower voltage: When switching to a lower voltage. You can use partial array self-refresh (PASR) for additional power savings for mDDR memory.1). PLL1 is mainly used to clock the DDR2/mDDR memory controller. 8.

see the DDR2/mDDR Memory Controller chapter. To preserve DDR2/mDDR memory contents.1. 8. Set the SLEEPENABLE bit in DEEPSLEEP to 1. if this interface is used and internal clocks are selected (see Section 10. 10.10.10.com Deep Sleep Mode 9. 6. if this interface is used and internal clocks are selected (see Section 10. 11. For more details on the clock stop procedure of the DDR2/mDDR memory controller. This bit is set once the device is woken up from Deep Sleep mode. At minimum. and 7-10 of the PLL initialization procedure must be followed.10. The pin is driven low since the alarm has not yet occurred. the Deep Sleep logic releases the clock to the device and sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration (SYSCFG) Module chapter. Configure the desired states to the peripherals and enable as required.1 Entering Deep Sleep Mode Use the following procedure to enter the Deep Sleep state if the RTC is used to wake-up the device: 1.3).2.1 (USB1) PHY should be disabled. 12. This count determines the delay before the Deep Sleep logic releases the clocks to the device during wake up (allowing the oscillator to stabilize). steps 3.11. PLL/PLLC0 and PLL/PLLC1 should be placed in bypass mode (clear the PLLEN bit in the PLL control register (PLLCTL) of each PLLC to 0). 3.ti. 5. and then take the DDR2/mDDR out of self-refresh mode. Texas Instruments Incorporated 219 . 3. PLL/PLLC0 and PLL/PLLC1 should be powered down (set the PLLPWRDN bit in PLLCTL of each PLLC to 1). Configure the DEEPSLEEP/RTC_ALARM pin to output RTC_ALARM using the PINMUX0_31_28 bits in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter.2. 7.2. 2. 4. You can use partial array self-refresh (PASR) for additional power savings for mDDR memory. This automatically clears the SLEEPCOMPLETE bit. 4.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up 10. Enable the clocks to the DDR2/mDDR memory controller. it is not necessary to reprogram all the PLL controller registers unless a new setting is desired.1).11. Configure the desired delay in the SLEEPCOUNT bit field in the deep sleep register (DEEPSLEEP) in the System Configuration (SYSCFG) Module chapter. The USB1. Configure the desired wake-up time as an alarm in the RTC. For more details on the clock enable procedure of the DDR2/mDDR memory controller. 5.www. SPRUH77A – December 2011 Submit Documentation Feedback Power Management Copyright © 2011. The external controller drives the DEEPSLEEP pin high. see the DDR2/mDDR Memory Controller chapter.2 Exiting Deep Sleep Mode Use the following procedure to exit the Deep Sleep state if an external signal is used to wake-up the device: 1. 10. Therefore. Initialize the PLL controllers as described in Section 8. When the SLEEPCOUNT delay is complete. Clear the SLEEPENABLE bit in DEEPSLEEP to 0.11. 6.2.1). Begin polling the SLEEPCOMPLETE bit until it is set to 1. The USB2. 4. activate the self-refresh mode and gate the clocks to the DDR2/mDDR memory controller. 2. reset the DDR PHY. Note that the state of the PLL controller registers is preserved during Deep Sleep mode.0 (USB0) PHY should be disabled. The external controller drives the DEEPSLEEP pin low to initiate Deep Sleep mode. The SATA PHY should be disabled (see Section 10. This automatically clears the SLEEPCOMPLETE bit. 10.

The count has reached the number specified in the SLEEPCOUNT bit field and the SLEEPCOMPLETE bit is set. The DEEPSLEEP pin is driven low by either an external device or the RTC_ALARM pin. 220 Power Management Copyright © 2011. 7. 10.ti. This causes the Deep Sleep logic to exit the Deep Sleep mode. and 7-10 of the PLL initialization procedure must be followed. 3. Configure the desired states to the peripherals and enable as required. Initialize the PLL controllers as described in Section 8. and then take the DDR2/mDDR out of self-refresh mode. 4. 6. The PLL controller reference clock is gated. 5.2. This automatically clears the SLEEPCOMPLETE bit. steps 3. the device now enters the Deep Sleep mode since the DEEPSLEEP pin is low. If the device is being clocked by an external source. Note that the state of the PLL controller registers is preserved during Deep Sleep mode. 2. reset the DDR PHY. 4.10.2. Software clears the SLEEPENABLE bit. The on-chip oscillator is disabled. Set the SLEEPENABLE bit in DEEPSLEEP to 1. 10. The PLL reference clock is enabled and the Deep Sleep mode ends.10. Also. This count determines the delay before the Deep Sleep logic releases the clocks to the device during wake up (allowing the oscillator to stabilize).com 9.2.Deep Sleep Mode www. This automatically clears the SLEEPCOMPLETE bit. 10. Clear the SLEEPENABLE bit in DEEPSLEEP to 0.2. see the DDR2/mDDR Memory Controller chapter. Enable the clocks to the DDR2/mDDR memory controller.3 Deep Sleep Sequence Figure 10-1 illustrates the Deep Sleep sequence: 1. Therefore. 4. 8. The Deep Sleep counter beings counting valid clock cycles. the Deep Sleep logic releases the clock to the device and sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration (SYSCFG) Module chapter. For more details on the clock stop procedure of the DDR2/mDDR memory controller. see the DDR2/mDDR Memory Controller chapter. 6. When the SLEEPCOUNT delay is complete. The SLEEPCOMPLETE bit is automatically cleared. Configure the desired delay in the SLEEPCOUNT bit field in the deep sleep register (DEEPSLEEP) in the System Configuration (SYSCFG) Module chapter. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . 5. this clock may stay enabled. the power savings from turning off this clock is minimal. Software sets the SLEEPENABLE bit in the deep sleep register (DEEPSLEEP) in the System Configuration (SYSCFG) Module chapter. At minimum. 2. The RTC alarm occurs and the RTC_ALARM pin is driven high (which is internally connected to the DEEPSLEEP pin). The Deep Sleep mode begins.2 Exiting Deep Sleep Mode Use the following procedure to exit the Deep Sleep state if the RTC is used to wake-up the device: 1. The DEEPSLEEP pin is driven high and the on-chip oscillator is enabled. it is not necessary to reprogram all the PLL controller registers unless a new setting is desired. For more details on the clock enable procedure of the DDR2/mDDR memory controller. 3.

SPRUH77A – December 2011 Submit Documentation Feedback Power Management Copyright © 2011. 2.com Deep Sleep Mode Figure 10-1.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking Entering the Deep Sleep mode stops all of the clocks to the device so it is the responsibility of the software to ensure that all peripheral accesses have been completed and peripheral interfaces appropriately configured for clocks to stop.4. Set the SLEEPENABLE bit in DEEPSLEEP to 1. Software prepares the device for Deep Sleep mode.10. Configure the GP0[8] pin to generate interrupts on the falling edge of the GPIO signal. 6. 3. the SLEEPCOMPLETE bit is automatically cleared.www. An external device drives the GP0[8] pin low.10.1 Entering Deep Sleep Mode The following example sequence can be used to activate the Deep Sleep mode using a handshaking mechanism between your device and an external device: 1. The DEEPSLEEP pin has no effect until software running on the device sets this bit. 5. Clear the SLEEPENABLE bit in the deep sleep register (DEEPSLEEP) in the System Configuration (SYSCFG) Module chapter to 0. Configure the GP0[8]/DEEPSLEEP/RTC_ALARM pin to output GP0[8] using the PINMUX0_31_28 bits in the PINMUX0 register in the System Configuration (SYSCFG) Module chapter. 10. The Deep Sleep mode is immediately started and all device clocks are stopped. When the pin is configured for GPIO functionality. 4. a handshaking mechanism must be in place to give software time to prepare the device for Deep Sleep mode. Deep Sleep Mode Sequence See Note: 1 2 3 4 5 6 7 8 SLEEPENABLE (internal) DEEPSLEEP CLKGATE (internal) PLLC Ref Clk (internal) OSC_GZ (internal) OSCIN SLEEPCOMPLETE (internal) 10.ti. Also. Therefore. The implementation of the handshake mechanism is up to the system designer. before an external controller drives the DEESPLEEP pin. the internal DEEPSLEEP signal is still driven by the value on the pin. Texas Instruments Incorporated 221 .

3.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode The DDR2/mDDR memory controller supports different methods for reducing its power consumption including self-refresh mode.com 10.11. and clock gating.2 Exiting Deep Sleep Mode To exit the Deep Sleep mode. by writing to the USB0PHYPWDN and the USB0OTGPWRDN bits in the Chip Configuration 2 Register (CFGCHIP2) in the System Configuration (SYSCFG) Module chapter. the Deep Sleep logic releases the clock to the device and sets the SLEEPCOMPLETE bit in the deep sleep register (DEEPSLEEP) in the System Configuration (SYSCFG) Module chapter. An external device drives the GP0[8] pin high. the self-refresh state of the memory is ignored. it automatically runs its memory initialization routine. During power-up. The device exits the Deep Sleep mode. follow this sequence: 1.4. and power and sleep controller (PSC).11. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .1 subsystem is used and the 48 MHz clock input is sourced from the USB2. 222 Power Management Copyright © 2011. the receivers can be configured to disable whenever writes are in progress and the receivers are not needed.0 PHY should not be powered down. power-down mode. Self-refresh mode can be used to preserve the contents of DDR2/mDDR memory when the DDR2/mDDR memory controller is clock gated or when the device is placed in RTC-only mode. PLL controller (PLLC). however.Additional Peripheral Power Management Considerations www. When the DDR2/mDDR memory controller is taken out of reset. This hardware sequence cannot be stopped by software running on the device. NOTE: If the USB1.1 USB PHY Power Down Control The USB modules can be clock gated using the PSC. when not in use. In RTC-only mode. the DDR2/mDDR memory controller DLL.11 Additional Peripheral Power Management Considerations This section lists additional power management features and considerations that might be part of other chip-level or peripheral logic. PHY. When the SLEEPCOUNT delay is complete. its self-refresh mode must be enabled before the DDR2/mDDR memory controller clock is turned off. Even if the PHY is active.10. Additionally. and the receivers at the I/O pins can be disabled. NOTE: To preserve the contents of the external memory while the DDR2/mDDR memory controller is clock gated. You can put the USB2.ti. care must be taken to correctly take the DDR2/mDDR out of self-refresh mode. 10. the DDR2/mDDR memory controller defaults to its reset state. Clear the SLEEPENABLE bit in DEEPSLEEP to 0. 2. apart from the features supported by the core. this does not power down/clock gate the PHY logic. in the RTC-only mode. all portions of the device except for the RTC are powered down. including the DDR2/mDDR memory controller. 10.0 PHY and OTG module in the lowest power state. However. 10. then the USB2.0 PHY.

4.3V. 6. After coming back from RTC-only mode. A floating input pin can consume a small amount of I/O leakage current. 2. These internal resistors are generally very weak and their use is intended for pins that are not connected on the board design.11. Before going into RTC-only mode. SPRUH77A – December 2011 Submit Documentation Feedback Power Management Copyright © 2011. This device includes internal pull-up and pull-down resistors that prevent floating input pins.11. For pins that are connected. Program the DDR2/mDDR memory controller following the normal sequence. configure the device to the desired operating state.8V I/Os and low-static current dual-voltage I/Os that operate at either 1. through an external pull-up resistor or by an external device for example. In the event that certain receivers are not used (such as in a low-power state). it is recommended to disable the internal resistor. you must ensure that all input pins are always pulled to a logic-high or a logic-low voltage level. 10. After this sequence. Internal resistors are disabled through the pullup/pulldown enable register (PUPD_ENA) in the System Configuration (SYSCFG) Module chapter.8V or 3. follow these steps: 1. Texas Instruments Incorporated 223 . the DDR2/mDDR memory controller is ready for use. In applications in which the SATA is not used at all.ti. 5. The receivers on the LCVMOS I/Os are enabled and disabled by software (see the RXACTIVE Control Register (RXACTIVE) in the System Configuration (SYSCFG) Module chapter). Enable the self-refresh mode of the DDR2/mDDR memory controller. 10.11. 3. When an input pin is externally driven to a valid logic level.5 Pull-Up/Pull-Down Disable In general.www.com Additional Peripheral Power Management Considerations To correctly take the memory out of self-refresh after coming back from RTC-only mode. external pull-up and pull-down resistors are recommended. they can be disabled to conserve power. disconnect the DDR2/mDDR memory controller CKE output pin from the memory. For more details on the power management features of the DDR2/mDDR memory controller. see the DDR2/mDDR Memory Controller chapter. Opposing an internal pull-up or pull-down resistor can consume a small amount of current. Disable the self-refresh mode of the DDR2/mDDR memory controller. ensure the memory’s CKE input pin continues to be driven low. The I/O leakage current can be greatly multiplied in the case of several floating inputs pins. the power supply to the SATA PHY can be left unconnected. Note that hardware logic is needed to disconnect the CKE output pin from the memory and to drive the memory’s CKE input pin low.3 SATA PHY Power Down The SATA PHY supports a standby power mode that yields significant power reduction during periods in which the PHY is not used. 10. Connect the DDR2/mDDR memory controller CKE output pin to the memory.4 LVCMOS I/O Buffer Receiver Disable This device supports two types of LVCMOS I/Os: 1.

224 Power Management Copyright © 2011. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

................ Protection .......................................................... Introduction ........................................................................1 11... Page 11......... Texas Instruments Incorporated 225 ............................................................................. ARM-DSP Communication Interrupts ......................................................................................................................................................4 11........... Master Priority Control ........................3 11......................................................................................................... SYSCFG Registers ............5 226 226 227 229 229 SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011....Chapter 11 SPRUH77A – December 2011 System Configuration (SYSCFG) Module Topic .......2 11..........................

therefore. downloadable from http://infocenter.2 Protection The SYSCFG module controls several global operations of the device. accessible by the CPU. • Device Identification • Device Configuration – Pin multiplexing control – Device Boot Configuration Status • Master Priority Control – Controls the system priority for all master peripherals (including EDMA3TC) • Emulation Control – Emulation suspend control for peripherals that support the feature • Special Peripheral Status and Control – Locking of PLL control settings – Default burst size configuration for EDMA3 transfer controllers – Event source selection for the eCAP peripheral input capture – McASP0 AMUTEIN selection and clearing of AMUTE – USB PHY Control – Clock source selection for EMIFA and DDR2/mDDR – HPI Control • ARM-DSP Integration – On-chip inter-processor interrupts and status for signaling between ARM and DSP The system configuration module controls several global operations of the device.1 Introduction The system configuration (SYSCFG) module is a system-level module containing status and top level control logic required by the device. The protection mechanism enables accesses to these registers only if certain conditions are met. 11. The registers that can only be accessed in privileged mode are listed in Section 11. The protection mechanisms that are present in the module are: • A special key sequence that needs to be written into a set of registers in the system configuration module. in Supervisor mode.com/help/index. • Several registers in the module are only accessible when the CPU requesting read/write access is in privileged mode. therefore.Introduction www. Several registers in the SYSCFG memory-map can only be accessed when the accessing host (CPU or master peripheral) is operating in privileged mode.1 Privilege Mode Protection The CPU supports two privilege levels: Supervisor and User. and miscellaneous functions and operations. 11.2. The system configuration module consists of a set of memory-mapped status and control registers. See the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8) and the ARM926EJ-S Technical Reference Manual (TRM).com 11. that is. the module supports protection against erroneous and illegal accesses to the registers in its memory-map.5.jsp for details on privilege levels. it has a protection mechanism that prevents spurious and illegal accesses to the registers in its memory map. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . to allow write ability to the rest of registers in the system configuration module.ti. 226 System Configuration (SYSCFG) Module Copyright © 2011.arm. supporting all of the following system features.

Data DSP MDMA DSP CFG Reserved PRU0 PRU1 EDMA3_0_CC0 EDMA3_1_CC0 Reserved EDMA3_0_TC0 .Instruction ARM . Table 11-1.write EDMA3_1_TC0 – read SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Write the key value of 83E7 0B13h to KICK0R. Writing the correct key value to the kick registers unlocks the registers in the SYSCFG memory-map. it is required to follow a special sequence of writes to the Kick registers (KICK0R and KICK1R) with correct key values. The master ID is shown in Table 11-1. EDMA3 transfer controllers.com Master Priority Control 11.2. The SYSCFG module remains unlocked after the unlock sequence. until locked again. masters and slaves. For all peripherals/ports classified as masters on the device. Locking the module is accomplished by writing any value other then the key values to either KICK0R or KICK1R. the SYSCFG module registers are accessible and can be configured as per the application requirements. 11. See the device-specific data manual to determine the masters present on your device. The default priority levels for each bus master is shown in Table 11-2. Write the key value of 95A4 F1E0h to KICK1R. After steps 1 and 2. the following unlock sequence needs to be executed in software: 1. each master request source must have a unique master ID (mstid) associated with it. the priority is programmed in the master priority registers (MSTPRI0-3) in the SYSCFG modules.www. Texas Instruments Incorporated 227 .3 Master Priority Control The on-chip peripherals/modules are essentially divided into two broad categories. and peripherals that do not rely on the CPU or EDMA3 for initiating the data transfer to/from them. To access any registers in the SYSCFG module. DSP.read EDMA3_0_TC1 . In order to determine allowed connection between masters and slave. Each switched central resource (SCR) performs prioritization based on priority level of the master that sends the read/write requests. The Kick registers (KICK0R and KICK1R) can only be accessed in privileged mode (the host needs to be in Supervisor mode). The master peripherals are typically capable of initiating their own read/write data access requests. while the module is unlocked.read EDMA3_0_TC0 . Master IDs Master ID 0 1 2 3 4-7 8 9 10 11 12-15 16 17 18 19 20 Peripheral ARM .2 Kicker Mechanism Protection NOTE: The Kick registers are disabled in silicon revision 2 and later.ti.write EDMA3_0_TC1 . In order to access the SYSCFG registers. Any number of accesses may be performed to the SYSCFG module. Application software is expected to modify these values to obtain the desired performance. 2. this includes the ARM. The SYSCFG registers are always unlocked and writes to the Kick registers have no functional effect.

1 Reserved uPP SATA VPIF DMA0 VPIF DMA1 Reserved LCDC Reserved Table 11-2.com Table 11-1.1 LCDC (4) HPI (1) Default Priority 0 0 0 0 2 2 2 2 4 4 4 4 4 4 4 4 4 5 6 (1) Master Priority Register MSTPRI1 MSTPRI1 MSTPRI1 MSTPRI1 MSTPRI0 MSTPRI0 MSTPRI0 MSTPRI0 MSTPRI0 MSTPRI0 MSTPRI1 MSTPRI1 MSTPRI1 MSTPRI2 MSTPRI2 MSTPRI2 MSTPRI2 MSTPRI2 MSTPRI2 (2) (3) (4) The default priority settings might not be optimal for all applications. and EDMA3_1_TC0 is configurable through fields in the master priority 1 register (MSTPRI1). The priority for DSP MDMA and DSP CFG is controlled by fields in the master priority 0 register (MSTPRI0) and not DSP. not the EDMA3CC QUEPRI register.0 DMA USB1. The master priority should be changed from default based on application specific requirement.0 CFG USB2. therefore. You should reconfigure the LCDC priority to the highest or equal to other high-priority masters in an application to ensure that the throughput/latency requirements for the LCDC are met.Data DSP MDMA (3) DSP CFG (3) SATA uPP EDMA3_1_TC0 (2) VPIF DMA0 VPIF DMA1 EMAC USB2.MDMAARBE. in order to get optimal performance and prioritization for masters moving data that is real time sensitive. SPRUH77A – December 2011 Submit Documentation Feedback Copyright © 2011. LCDC traffic is typically real-time sensitive. the default priority of 5.Instruction ARM .0 CFG USB2. which is lower as compared to the default priority of several masters.0 DMA Reserved HPI EMAC USB1. The priority for EDMA3_0_TC0.Master Priority Control www. Default Master Priority Master PRU0 PRU1 EDMA3_0_TC0 (2) EDMA3_0_TC1 (2) ARM .ti. EDMA3_0_TC1. is not recommended. Texas Instruments Incorporated 228 System Configuration (SYSCFG) Module . Master IDs (continued) Master ID 21 22-33 34 35 36 37 38 39 40-65 66 67 68 69 70-95 96 97-255 Peripheral EDMA3_1_TC0 – write Reserved USB2.PRI (DSP Bandwidth manager module).

4. the ARM may interrupt the DSP when it is ready to have the DSP process some data buffer in shared memory.5.5.5.3 Section 11.2 Section 11.5.1 Section 11. DSP responds to interrupt and reads command in shared memory.5.5. if the interrupts have been appropriately enabled in the processor’s interrupt controller.5 Section 11. For example.4 Section 11.5 SYSCFG Registers Table 11-3 lists the memory-mapped registers for the system configuration module 0 (SYSCFG0) and Table 11-4 lists the memory-mapped registers for the system configuration module 1 (SYSCFG1).5.2 Section 11.5.4 Section 11.5 Section 11.2 Section 11. DSP interrupts ARM upon completion of the task. This is generally used to allow the ARM and the DSP to coordinate.9.10. These tables also indicate whether a particular register can be accessed only when the CPU is in privileged mode.4 ARM-DSP Communication Interrupts The SYSCFG module also has a set of registers to facilitate interprocessor communication.7.6 Section 11. 5.7.4. 11.10. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . A typical sequence.9.5.1 Section 11.www.10.8.com ARM-DSP Communication Interrupts 11.10.3 Section 11.1 Section 11. ARM writes command in shared memory.5.5.8.3 Section 11. often referred to as ARM-DSP communication. System Configuration Module 0 (SYSCFG0) Registers Address 01C1 4000h 01C1 4008h 01C1 400Ch 01C1 4010h 01C1 4014h 01C1 4018h 01C1 4020h 01C1 4038h 01C1 403Ch 01C1 4040h 01C1 4044h 01C1 40E0h 01C1 40E4h 01C1 40E8h 01C1 40ECh 01C1 40F0h 01C1 40F4h 01C1 40F8h 01C1 4110h 01C1 4114h 01C1 4118h 01C1 4120h 01C1 4124h 01C1 4128h 01C1 412Ch 01C1 4130h (1) Acronym REVID DIEIDR0 (1) DIEIDR1 (1) DIEIDR2 (1) Register Description Revision Identification Register Die Identification Register 0 Die Identification Register 1 Die Identification Register 2 Die Identification Register 3 Device Identification Register 0 Boot Configuration Register Kick 0 Register Kick 1 Register Host 0 Configuration Register Host 1 Configuration Register Interrupt Raw Status/Set Register Interrupt Enable Status/Clear Register Interrupt Enable Register Interrupt Enable Clear Register End of Interrupt Register Fault Address Register Fault Status Register Master Priority 0 Register Master Priority 1 Register Master Priority 2 Register Pin Multiplexing Control 0 Register Pin Multiplexing Control 1 Register Pin Multiplexing Control 2 Register Pin Multiplexing Control 3 Register Pin Multiplexing Control 4 Register Access — — — — — Privileged mode Privileged mode Privileged mode Privileged mode — — Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode — Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Section Section 11.10. which in turn can interrupt the other processor.5. 4.1 Section 11.5.5.5. 2. System Configuration (SYSCFG) Module 229 Copyright © 2011.ti.5. Either of the processors can set specific bits in this SYSCFG register.7.5.9.3 Section 11.5.2 Section 11.7. DSP executes a task based on the command.7.5. ARM interrupts DSP.2 Section 11.5.1 Section 11. Table 11-3.5 DIEIDR3 (1) DEVIDR0 BOOTCFG KICK0R KICK1R HOST0CFG HOST1CFG IRAWSTAT IENSTAT IENSET IENCLR EOI FLTADDRR FLTSTAT MSTPRI0 MSTPRI1 MSTPRI2 PINMUX0 PINMUX1 PINMUX2 PINMUX3 PINMUX4 This register is for internal-use only.1 — — — — Section 11.5. 3.2 Section 11. is as follows: 1.5.

5.11 Section 11.15 Section 11.18 Table 11-4.10.17 Section 11.15 Section 11.9 Section 11.5.12 Section 11.11 Section 11.5.14 Section 11.10.5.5.21 Section 11.14 Section 11.com Table 11-3.10.19 Section 11.5.5.18 Section 11.5.10.5.5.13 Section 11.10.5.5.17 Section 11.16 Section 11.13 Section 11. System Configuration Module 0 (SYSCFG0) Registers (continued) Address 01C1 4134h 01C1 4138h 01C1 413Ch 01C1 4140h 01C1 4144h 01C1 4148h 01C1 414Ch 01C1 4150h 01C1 4154h 01C1 4158h 01C1 415Ch 01C1 4160h 01C1 4164h 01C1 4168h 01C1 416Ch 01C1 4170h 01C1 4174h 01C1 4178h 01C1 417Ch 01C1 4180h 01C1 4184h 01C1 4188h 01C1 418Ch Acronym PINMUX5 PINMUX6 PINMUX7 PINMUX8 PINMUX9 PINMUX10 PINMUX11 PINMUX12 PINMUX13 PINMUX14 PINMUX15 PINMUX16 PINMUX17 PINMUX18 PINMUX19 SUSPSRC CHIPSIG CHIPSIG_CLR CFGCHIP0 CFGCHIP1 CFGCHIP2 CFGCHIP3 CFGCHIP4 Register Description Pin Multiplexing Control 5 Register Pin Multiplexing Control 6 Register Pin Multiplexing Control 7 Register Pin Multiplexing Control 8 Register Pin Multiplexing Control 9 Register Pin Multiplexing Control 10 Register Pin Multiplexing Control 11 Register Pin Multiplexing Control 12 Register Pin Multiplexing Control 13 Register Pin Multiplexing Control 14 Register Pin Multiplexing Control 15 Register Pin Multiplexing Control 16 Register Pin Multiplexing Control 17 Register Pin Multiplexing Control 18 Register Pin Multiplexing Control 19 Register Suspend Source Register Chip Signal Register Chip Signal Clear Register Chip Configuration 0 Register Chip Configuration 1 Register Chip Configuration 2 Register Chip Configuration 3 Register Chip Configuration 4 Register Access Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode — — Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Section Section 11.5.23 Section 11.19 Section 11.8 Section 11.20 Section 11.5.5.5.5.10.10.5.5.5.10 Section 11.SYSCFG Registers www.5.7 Section 11.10.5.ti. System Configuration Module 1 (SYSCFG1) Registers Address 01E2 C000h 01E2 C004h 01E2 C008h 01E2 C00Ch 01E2 C010h 01E2 C014h 01E2 C018h Acronym VTPIO_CTL DDR_SLEW DEEPSLEEP PUPD_ENA PUPD_SEL RXACTIVE PWRDN Register Description VTP I/O Control Register DDR Slew Register Deep Sleep Register Pullup/Pulldown Enable Register Pullup/Pulldown Selection Register RXACTIVE Control Register Power Down Control Register Access Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Privileged mode Section Section 11.5.10.16 Section 11.10.22 Section 11.12 Section 11.20 Section 11.5.5.5.5.10.5.10. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .25 230 System Configuration (SYSCFG) Module Copyright © 2011.5.6 Section 11.10.24 Section 11.5.10.10.

-n = value after reset 0 Table 11-6. SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. The REVID is shown in Figure 11-1 and described in Table 11-5. Revision Identification Register (REVID) Field Descriptions Bit 31-0 Field REV Value 4E84 0102h Description Revision ID. The DEVIDR0 is shown in Figure 11-2 and described in Table 11-6.1 Revision Identification Register (REVID) The revision identification register (REVID) provides the revision information for the SYSCFG module. Figure 11-1. 11.com SYSCFG Registers 11. Figure 11-2.5. Device Identification Register 0 (DEVIDR0) 31 DEVID0 R-1B7D 102Fh LEGEND: R = Read only.2 Device Identification Register 0 (DEVIDR0) The device identification register 0 (DEVIDR0) contains a software readable version of the JTAG ID device. -n = value after reset 0 Table 11-5.5. Software can use this register to determine the version of the device on which it is executing.ti. Revision information for the SYSCFG module. Texas Instruments Incorporated 231 .www. Device Identification Register 0 (DEVIDR0) Field Descriptions Bit 31-0 Field DEVID0 Value 1B7D 102Fh Description Device identification. Revision Identification Register (REVID) 31 REV R-4E84 0102h LEGEND: R = Read only.

Boot Configuration Register (BOOTCFG) 31 Reserved R-0 15 BOOTMODE R-0 LEGEND: R = Read only. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .5.ti. and captured in the boot configuration register (BOOTCFG). -n = value after reset 0 16 Table 11-7.3 Boot Configuration Register (BOOTCFG) The device boot and configuration settings are latched at device reset. This reflects the state of the boot mode pins. Boot Configuration Register (BOOTCFG) Field Descriptions Bit 31-16 15-0 Field Reserved BOOTMODE Value 0 0-FFFFh Description Reserved Boot Mode. See your device-specific data manual and the Boot Considerations chapter for details on boot and configuration settings. 232 System Configuration (SYSCFG) Module Copyright © 2011.SYSCFG Registers www. Figure 11-3. The BOOTCFG is shown in Figure 11-3 and described in Table 11-7.com 11.

The SYSCFG module has a protection mechanism to prevent any spurious writes from changing any of the modules memory-mapped registers.com SYSCFG Registers 11. To allow writing to the registers in the module. Kick 1 Register (KICK1R) 31 KICK0 R/W-0 LEGEND: R/W = Read/Write. It must be written before writing to the kick1 register. Writing any other data value to either of these kick registers will cause the memory mapped registers to be “locked” again and block out any write accesses to registers in the SYSCFG module. Texas Instruments Incorporated 233 .5.5. 11. Writing any other value will lock the other MMRs. At power-on reset.4.www.2 for the exact key values and sequence of steps.4 Kick Registers (KICK0R-KICK1R) NOTE: The kick registers are disabled in silicon revision 2 and later.1 Kick 0 Register (KICK0R) The KICK0R is shown in Figure 11-4 and described in Table 11-8.5. KICK0R must be written before writing to the kick1 register. Kick 1 Register (KICK1R) Field Descriptions Bit 31-0 Field KICK1 Value 0-FFFF FFFFh Description KICK1R allows writing to unlock the kick1 data and the kicker mechanism to write to other MMRs. Kick 0 Register (KICK0R) 31 KICK1 R/W-0 LEGEND: R/W = Read/Write. -n = value after reset 0 Table 11-9. The written data must be 95A4 F1E0h to unlock this register. Once these values are written. then all the registers in the SYSCFG module that are writeable can be written to. Writing any other value will lock the other MMRs.2 Kick 1 Register (KICK1R) The KICK1R is shown in Figure 11-5 and described in Table 11-9. 11. -n = value after reset 0 Table 11-8. it is required to “unlock” the registers by writing to two memory-mapped registers in the SYSCFG module. none of the SYSCFG module registers are writeable (they are readable). See Section 11. Kick 0 Register (KICK0R) Field Descriptions Bit 31-0 Field KICK0 Value 0-FFFF FFFFh Description KICK0R allows writing to unlock the kick0 data.ti. The SYSCFG registers are always unlocked and writes to the kick registers have no functional effect. SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.2.4. with exact data values. Figure 11-4. Figure 11-5. Kick0 and Kick1. The written data must be 83E7 0B13h to unlock this register.

SYSCFG Registers www. Host 0 Configuration Register (HOST0CFG) Field Descriptions Bit 31-1 0 Field Reserved BOOTRDY 0 1 Value 0 Description Reserved ARM boot ready bit allowing ARM to boot. In a typical application. NOTE: In addition to writing to HOST0CFG. Host 0 Configuration Register (HOST0CFG) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write. Figure 11-6.5 Host 0 Configuration Register (HOST0CFG) The ARM subsystem is held in reset when 0 is written to the BOOTRDY bit in the host 0 configuration register (HOST0CFG). 234 System Configuration (SYSCFG) Module Copyright © 2011. By default. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . R = Read only. The HOST0CFG is shown in Figure 11-6 and described in Table 11-10. the ARM subsystem must be enabled via the power and sleep controller (PSC) module. the BOOTRDY bit should not be cleared. -n = value after reset 1 0 BOOTRDY R/W-1 16 Table 11-10.com 11.ti. ARM released from wait in reset mode. the ARM subsystem is in a SwRstDisable state (see the Power and Sleep Controller (PSC) chapter for additional details). ARM held in reset mode.5.

Host 1 Configuration Register (HOST1CFG) Field Descriptions Bit 9-0 Field Reserved Value 0-3F FFFFh 0 Description DSP boot address vector. Reserved 31-10 DSP_ISTP_RST_VAL SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.6 Host 1 Configuration Register (HOST1CFG) The host 1 configuration register (HOST1CFG) provides information on the DSP boot address value at power-on reset. R = Read only. The address field is read/writeable after reset and can be modified to allow execution from an alternate location after a module level or local reset on the DSP. -n = value after reset 10 9 Reserved R-0 0 16 Table 11-11. Host 1 Configuration Register (HOST1CFG) 31 DSP_ISTP_RST_VAL R/W-0070h 15 DSP_ISTP_RST_VAL R/W-0 LEGEND: R/W = Read/Write.ti.5. Figure 11-7. Texas Instruments Incorporated 235 .com SYSCFG Registers 11.www. The boot address defaults to 0070 0000h (DSP ROM) on power-up. The HOST1CFG is shown in Figure 11-7 and described in Table 11-11.

Reading this bit field reflects the raw status of the interrupt before enabling. Protection violation error. Indicates the interrupt is set. interrupt set and clear control. Figure 11-8.com 11. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .SYSCFG Registers www. Indicates the interrupt is not set. Writing 0 has no effect. Indicates the interrupt is set.5. Writing 0 has no effect. This includes enable control.5.1 Interrupt Raw Status/Set Register (IRAWSTAT) The interrupt raw status/set register (IRAWSTAT) shows the interrupt status before enabling the interrupt and allows setting of the interrupt status. Interrupt Raw Status/Set Register (IRAWSTAT) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write. Writing 1 sets the status. Addressing violation error. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions Bit 31-2 1 Field Reserved ADDRERR 0 1 0 PROTERR 0 1 Value 0 Description Reserved. Indicates the interrupt is not set.ti. Reading this bit field reflects the raw status of the interrupt before enabling. and end of interrupt (EOI) control. Writing 1 sets the status. The IRAWSTAT is shown in Figure 11-8 and described in Table 11-12. 236 System Configuration (SYSCFG) Module Copyright © 2011. Always read 0. -n = value after reset 2 1 ADDRERR R/W-0 0 PROTERR R/W-0 16 Table 11-12.7 Interrupt Registers The interrupt registers are a set of registers that provide control for the address and protection violation error interrupt generated by the SYSCFG module when there is an address or protection violation to the module's memory-mapped register address space. R = Read only. 11.7.

The IENSTAT is shown in Figure 11-9 and described in Table 11-13. Indicates the interrupt is not set. Indicates the interrupt is set. Reading this bit field reflects the interrupt enabled status.2 Interrupt Enable Status/Clear Register (IENSTAT) The interrupt enable status/clear register (IENSTAT) shows the status of enabled interrupt and allows clearing of the interrupt status. Writing 0 has no effect. R = Read only. SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Writing 1 clears the status.com SYSCFG Registers 11.5.ti. Figure 11-9. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions Bit 31-2 1 Field Reserved ADDRERR 0 1 0 PROTERR 0 1 Value 0 Description Reserved. Indicates the interrupt is set. Interrupt Enable Status/Clear Register (IENSTAT) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write. Always read 0. Indicates the interrupt is not set. Texas Instruments Incorporated 237 . -n = value after reset 2 1 ADDRERR R/W-0 0 PROTERR R/W-0 16 Table 11-13. Writing 1 clears the status. Protection violation error.7. Reading this bit field reflects the interrupt enabled status. Addressing violation error. Writing 0 has no effect.www.

3 Interrupt Enable Register (IENSET) The interrupt enable register (IENSET) allows setting/enabling the interrupt for address and/or protection violation condition. Writing a 0 has not effect.5. Interrupt Enable Clear Register (IENCLR) Field Descriptions Bit 31-2 1 Field Reserved ADDRERR_CLR 0 1 0 PROTERR_CLR 0 1 Value 0 Description Reserved. It also shows the value of the register (whether or not interrupt is enabled). Writing a 0 has not effect.5.com 11. Writing a 0 has not effect. It also shows the value of the interrupt enable register (IENSET). -n = value after reset 2 1 ADDRERR_EN R/W-0 0 PROTERR_EN R/W-0 16 Table 11-14. Figure 11-10. R = Read only.SYSCFG Registers www. 238 System Configuration (SYSCFG) Module Copyright © 2011. R = Read only.4 Interrupt Enable Clear Register (IENCLR) The interrupt enable clear register (IENCLR) allows clearing/disable the interrupt for address and/or protection violation condition. Writing a 1 enables this interrupt. Writing a 1 enables this interrupt. Always read 0. Interrupt Enable Register (IENSET) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write. Always read 0. Protection violation error. Writing a 1 clears/disables this interrupt. Interrupt Enable Register (IENSET) Field Descriptions Bit 31-2 1 Field Reserved ADDRERR_EN 0 1 0 PROTERR_EN 0 1 Value 0 Description Reserved.7. -n = value after reset 2 1 R/W-0 0 R/W-0 16 ADDRERR_CLR PROTERR_CLR Table 11-15. Addressing violation error. The IENSET is shown in Figure 11-10 and described in Table 11-14.7.ti. The IENCLR is shown in Figure 11-11 and described in Table 11-15. Protection violation error. 11. Writing a 1 clears/disables this interrupt. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Writing a 0 has not effect. Figure 11-11. Addressing violation error. Interrupt Enable Clear Register (IENCLR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write.

-n = value after reset 8 7 EOIVECT W-0 0 16 Table 11-16. Write the interrupt distribution value of the chip.8 Fault Registers The fault registers are a group of registers responsible for capturing the details on the faulty (address/protection violation errors) accesses. Texas Instruments Incorporated 239 . SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Always read 0.1 Fault Address Register (FLTADDRR) The fault address register (FLTADDRR) captures the address of the first transfer that causes the address or memory violation error.5 End of Interrupt Register (EOI) The end of interrupt register (EOI) is used in software to indicate completion of the interrupt servicing of the SYSCFG interrupt (for address/protection violation). this acts as an acknowledgement of completion of the SYSCFG interrupt so that the module can reliably generate the subsequent interrupts. Fault Address Register (FLTADDRR) Field Descriptions Bit 31-0 Field FLTADDR Value 0-FFFF FFFFh Description Fault address for the first fault transfer. EOI vector value.7.www. such as address and type of error.ti.8. End of Interrupt Register (EOI) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only. W = Write only. -n = value after reset 0 Table 11-17. You should write a value of 0 to the EOI register bit 0 after the software has processed the SYSCFG interrupt. The FLTADDRR is shown in Figure 11-13 and described in Table 11-17. 11.com SYSCFG Registers 11. Fault Address Register (FLTADDRR) 31 FLTADDR R-0 LEGEND: R = Read only.5.5. Figure 11-13. The EOI is shown in Figure 11-12 and described in Table 11-16. Figure 11-12. 11.5. End of Interrupt Register (EOI) Field Descriptions Bit 31-8 7-0 Field Reserved EOIVECT Value 0 0-FFh Description Reserved.

details on whether it is a user or supervisor level read/write or execute fault. -n = value after reset Table 11-18. Reserved. Master ID of the first fault transfer. Fault Status Register (FLTSTAT) 31 ID R-0 15 Reserved R-0 13 12 PRIVID R-0 9 8 Reserved R-0 6 5 TYPE R-0 24 23 MSTID R-0 0 16 LEGEND: R = Read only. Fault Status Register (FLTSTAT) Field Descriptions Bit 31-24 23-16 15-13 12-9 8-6 5-0 Field ID MSTID Reserved PRIVID Reserved TYPE 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 10h 11h-1Fh 20h 21h-3Fh Value 0-FFh 0-FFh 0 0-Fh 0 Description Transfer ID of the first fault transfer.SYSCFG Registers www. No transfer fault User execute fault User write fault Reserved User read fault Reserved Supervisor execute fault Reserved Supervisor write fault Reserved Supervisor read fault Reserved 240 System Configuration (SYSCFG) Module Copyright © 2011. Figure 11-14.2 Fault Status Register (FLTSTAT) The fault status register (FLTSTAT) holds/captures additional attributes and status of the first erroneous transaction. Always read 0 Fault type of first fault transfer.ti.5.8. The FLTSTAT is shown in Figure 11-14 and described in Table 11-18.com 11. Reserved. Always read 0 Privilege ID of the first fault transfer. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . This includes things like the master id for the master that caused the address/memory violation error.

www. Always read as 0.5. Reserved. bit = 7h = priority 7 (lowest). Figure 11-15. Bit = 0 = priority 0 (highest). DSP CFG port priority. Always read as 0. Bit = 0 = priority 0 (highest). Reserved. Reserved. Write the default value when modifying this register. Texas Instruments Incorporated 241 . Write the default value when modifying this register. bit = 7h = priority 7 (lowest).9. Reserved.ti. uPP port priority. bit = 7h = priority 7 (lowest). R = Read only. ARM_D port priority. Bit = 0 = priority 0 (highest). Write the default value when modifying this register.com SYSCFG Registers 11. Bit = 0 = priority 0 (highest). Write the default value when modifying this register.5. DSP DMA port priority. Bit = 0 = priority 0 (highest). bit = 7h = priority 7 (lowest). Bit = 0 = priority 0 (highest). Master Priority 0 Register (MSTPRI0) Field Descriptions Bit 31 30-28 27 26-24 23 22-20 19 18-16 15 14-12 11 10-8 7 6-4 3 2-0 Field Reserved Reserved Reserved Reserved Reserved SATA Reserved UPP Reserved DSP_CFG Reserved DSP_MDMA Reserved ARM_D Reserved ARM_I Value 0 4h 0 4h 0 0-7h 0 0-7h 0 0-7h 0 0-7h 0 0-7h 0 0-7h Description Reserved. Reserved. Master Priority 0 Register (MSTPRI0) 31 Rsvd R/W-0 15 Rsvd R/W-0 14 DSP_CFG R/W-2h 30 Reserved R/W-4h 12 28 27 Rsvd R/W-0 11 Rsvd R-0 10 DSP_MDMA R/W-2h 26 Reserved R/W-4h 8 24 23 Rsvd R/W-0 7 Rsvd R-0 6 ARM_D R/W-2h 22 SATA R/W-4h 4 20 19 Rsvd R/W-0 3 Rsvd R-0 2 ARM_I R/W-2h 18 UPP R/W-4h 0 16 LEGEND: R/W = Read/Write. bit = 7h = priority 7 (lowest).9 Master Priority Registers (MSTPRI0-MSTPRI2) 11. bit = 7h = priority 7 (lowest). SATA port priority. Reserved. Write the default value when modifying this register. Write the default value when modifying this register. Reserved. SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Write the default value when modifying this register. ARM_I port priority. Reserved. -n = value after reset Table 11-19. Always read as 0. Reserved.1 Master Priority 0 Register (MSTPRI0) The master priority 0 register (MSTPRI0) is shown in Figure 11-15 and described in Table 11-19.

ti. bit = 7h = priority 7 (lowest). Bit = 0 = priority 0 (highest). Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . EDMA3_0_TC1 port priority. Bit = 0 = priority 0 (highest). Always read as 0. bit = 7h = priority 7 (lowest). Master Priority 1 Register (MSTPRI1) 31 Rsvd R/W-0 15 Rsvd R/W-0 14 EDMA30TC1 R/W-0 30 VPIF_DMA_1 R/W-4h 12 28 27 Rsvd R/W-0 11 Rsvd R-0 10 EDMA30TC0 R/W-0 26 VPIF_DMA_0 R/W-4h 8 24 23 Rsvd R/W-0 7 Rsvd R-0 6 PRU1 R/W-0 22 Reserved R/W-4h 4 20 19 Rsvd R/W-0 3 Rsvd R-0 2 PRU0 R/W-0 18 EDMA31TC0 R/W-4h 0 16 LEGEND: R/W = Read/Write. Always read as 0.9. Bit = 0 = priority 0 (highest). Write the default value when modifying this register. Reserved. bit = 7h = priority 7 (lowest). Bit = 0 = priority 0 (highest). VPIF DMA1 port priority. bit = 7h = priority 7 (lowest). bit = 7h = priority 7 (lowest). bit = 7h = priority 7 (lowest).2 Master Priority 1 Register (MSTPRI1) The master priority 1 register (MSTPRI1) is shown in Figure 11-16 and described in Table 11-20. Write the default value when modifying this register. Bit = 0 = priority 0 (highest). -n = value after reset Table 11-20. Always read as 0. Write the default value when modifying this register. bit = 7h = priority 7 (lowest). R = Read only. Write the default value when modifying this register. Master Priority 1 Register (MSTPRI1) Field Descriptions Bit 31 30-28 27 26-24 23 22-20 19 18-16 15 14-12 11 10-8 7 6-4 3 2-0 Field Reserved VPIF_DMA_1 Reserved VPIF_DMA_0 Reserved Reserved Reserved EDMA31TC0 Reserved EDMA30TC1 Reserved EDMA30TC0 Reserved PRU1 Reserved PRU0 Value 0 0-7h 0 0-7h 0 4h 0 0-7h 0 0-7h 0 0-7h 0 0-7h 0 0-7h Description Reserved. Bit = 0 = priority 0 (highest). Reserved. EDMA3_1_TC0 port priority. 242 System Configuration (SYSCFG) Module Copyright © 2011. EDMA3_0_TC0 port priority.com 11. VPIF DMA0 port priority.5. Figure 11-16. PRU0 port priority. PRU1 port priority. Reserved. Reserved. Write the default value when modifying this register. Bit = 0 = priority 0 (highest).SYSCFG Registers www. Reserved. Reserved. Reserved. Reserved. Write the default value when modifying this register.

Master Priority 2 Register (MSTPRI2) Field Descriptions Bit 31 30-28 27 26-24 23 22-20 19 18-16 15 14-12 11 10-8 7 6-4 3 2-0 Field Reserved LCDC Reserved USB1 Reserved UHPI Reserved Reserved Reserved USB0CDMA Reserved USB0CFG Reserved Reserved Reserved EMAC Value 0 0-7h 0 0-7h 0 0-7h 0 0 0 0-7h 0 0-7h 0 0 0 0-7h Description Reserved. Bit = 0 = priority 0 (highest).www. Write the default value when modifying this register. Reserved. Bit = 0 = priority 0 (highest). Bit = 0 = priority 0 (highest). Write the default value when modifying this register. Write the default value when modifying this register. bit = 7h = priority 7 (lowest). Write the default value when modifying this register. Write the default value when modifying this register. Write the default value to all bits when modifying this register. Master Priority 2 Register (MSTPRI2) 31 Rsvd R/W-0 15 Rsvd R/W-0 14 USB0CDMA R/W-4h 30 LCDC R/W-5h 12 28 27 Rsvd R/W-0 11 Rsvd R/W-0 10 USB0CFG R/W-4h 26 USB1 R/W-4h 8 24 23 Rsvd R/W-0 7 Rsvd R/W-0 6 Reserved R/W-0 22 UHPI R/W-6h 4 20 19 Rsvd R/W-0 3 Rsvd R/W-0 2 EMAC R/W-4h 18 Reserved R/W-0 0 16 LEGEND: R/W = Read/Write. Reserved. -n = value after reset Table 11-21. Reserved. Write the default value when modifying this register.3 Master Priority 2 Register (MSTPRI2) The master priority 2 register (MSTPRI2) is shown in Figure 11-17 and described in Table 11-21. Bit = 0 = priority 0 (highest). Figure 11-17. Reserved. bit = 7h = priority 7 (lowest). Bit = 0 = priority 0 (highest). Write the default value to all bits when modifying this register. bit = 7h = priority 7 (lowest). EMAC port priority. LCDC port priority. Reserved. Reserved. Write the default value to all bits when modifying this register.9. USB0 (USB2.0) CDMA port priority. USB0 (USB2. Write the default value when modifying this register. Texas Instruments Incorporated 243 .com SYSCFG Registers 11.0) CFG port priority. bit = 7h = priority 7 (lowest).ti. Reserved. bit = 7h = priority 7 (lowest).1) port priority. Bit = 0 = priority 0 (highest). Reserved. bit = 7h = priority 7 (lowest). SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.5. USB1 (USB1. Reserved. HPI port priority.

pin multiplexing can be controlled on a pin by pin basis. TMS320C6742/6/8 Pin Multiplexing Utility Application Report (SPRAB63). This is done by the pin multiplexing registers (PINMUX0-PINMUX19). Pin Multiplexing Control 0 Register (PINMUX0) 31 PINMUX0_31_28 R/W-0 15 PINMUX0_15_12 R/W-0 12 11 PINMUX0_11_8 R/W-0 28 27 PINMUX0_27_24 R/W-0 8 7 PINMUX0_7_4 R/W-0 24 23 PINMUX0_23_20 R/W-0 4 3 PINMUX0_3_0 R/W-0 20 19 PINMUX0_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write. O = Output.10.1 Pin Multiplexing Control 0 Register (PINMUX0) Figure 11-18. -n = value after reset Table 11-22.SYSCFG Registers www. Each pin that is multiplexed with several different functions has a corresponding 4-bit field in PINMUXn.5. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions Bit 31-28 Field PINMUX0_31_28 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX0_27_24 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh (1) Value Description RTC_ALARM/UART2_CTS/GP0[8]/DEEPSLEEP Control Selects Function DEEPSLEEP Reserved Selects Function RTC_ALARM Reserved Selects Function UART2_CTS Reserved Selects Function GP0[8] Reserved AMUTE/PRU0_R30[16]/UART2_RTS/GP0[9]/PRU0_R31[16] Control Selects Function PRU0_R31[16] Selects Function AMUTE Selects Function PRU0_R30[16] Reserved Selects Function UART2_RTS Reserved Selects Function GP0[9] Reserved Type I X O X I X I/O X I I/O O X O X I/O X (1) I = Input. On the device.ti. the PINMUX registers have no effect on input from a pin. Pin multiplexing selects which of several peripheral pin functions control the pins I/O buffer output data and output enable values only. I/O = Bidirectional. Hardware does not attempt to ensure that the proper pin multiplexing is selected for the peripherals or that interface mode is being used.com 11.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19) Extensive use of pin multiplexing is used to accommodate the large number of peripheral functions in the smallest possible package. Access to the pin multiplexing utility is available in OMAP-L132/L138. 11. X = Undefined 244 System Configuration (SYSCFG) Module Copyright © 2011. Detailed information about the pin multiplexing and control is covered in the device-specific data manual.5. Note that the input from each pin is always routed to all of the peripherals that share the pin.

ti.com SYSCFG Registers Table 11-22. Texas Instruments Incorporated 245 .www. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions (continued) Bit 23-20 Field PINMUX0_23_20 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 19-16 PINMUX0_19_16 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 15-12 PINMUX0_15_12 0 1h 2h-7h 8h 9h-Fh 11-8 PINMUX0_11_8 0 1h 2h-7h 8h 9h-Fh 7-4 PINMUX0_7_4 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX0_3_0 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh Value Description AHCLKX/USB_REFCLKIN/UART1_CTS/GP0[10]/PRU0_R31[17] Control Selects Function PRU0_R31[17] Selects Function AHCLKX Selects Function USB_REFCLKIN Reserved Selects Function UART1_CTS Reserved Selects Function GP0[10] Reserved AHCLKR/PRU0_R30[18]/UART1_RTS/GP0[11]/PRU0_R31[18] Control Selects Function PRU0_R31[18] Selects Function AHCLKR Selects Function PRU0_R30[18] Reserved Selects Function UART1_RTS Reserved Selects Function GP0[11] Reserved AFSX/GP0[12]/PRU0_R31[19] Control Selects Function PRU0_R31[19] Selects Function AFSX Reserved Selects Function GP0[12] Reserved AFSR/GP0[13]/PRU0_R31[20] Control Selects Function PRU0_R31[20] Selects Function AFSR Reserved Selects Function GP0[13] Reserved ACLKX/PRU0_R30[19]/GP0[14]/PRU0_R31[21] Control Selects Function PRU0_R31[21] Selects Function ACLKX Reserved Selects Function PRU0_R30[19] Reserved Selects Function GP0[14] Reserved ACLKR/PRU0_R30[20]/GP0[15]/PRU0_R31[22] Control Selects Function PRU0_R31[22] Selects Function ACLKR Reserved Selects Function PRU0_R30[20] Reserved Selects Function GP0[15] Reserved I I/O X O X I/O X I I/O X O X I/O X I I/O X I/O X I I/O X I/O X I I/O O X O X I/O X I I/O I X I X I/O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.

2 Pin Multiplexing Control 1 Register (PINMUX1) Figure 11-19. Selects Function AXR10 Selects Function DR1 Reserved Selects Function GP0[2] Reserved AXR11/FSX1/GP0[3] Control Pin is 3-stated.10. I/O = Bidirectional. Selects Function AXR11 Selects Function FSX1 Reserved Selects Function GP0[3] Reserved Z I/O I/O X I/O X Z I/O I X I/O X Z I/O O X I/O X I I/O I X I/O X I/O X Type (1) (1) I = Input. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions Bit 31-28 Field PINMUX1_31_28 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX1_27_24 0 1h 2h 3h-7h 8h 9h-Fh 23-20 PINMUX1_23_20 0 1h 2h 3h-7h 8h 9h-Fh 19-16 PINMUX1_19_16 0 1h 2h 3h-7h 8h 9h-Fh Value Description AXR8/CLKS1/ECAP1_APWM1/GP0[0]/PRU0_R31[8] Control Selects Function PRU0_R31[8] Selects Function AXR8 Selects Function CLKS1 Reserved Selects Function ECAP1_APWM1 Reserved Selects Function GP0[0] Reserved AXR9/DX1/GP0[1] Control Pin is 3-stated.SYSCFG Registers www.5. Texas Instruments Incorporated 246 SPRUH77A – December 2011 Submit Documentation Feedback . Z = High-impedance state System Configuration (SYSCFG) Module Copyright © 2011. O = Output.ti. X = Undefined. Pin Multiplexing Control 1 Register (PINMUX1) 31 PINMUX1_31_28 R/W-0 15 PINMUX1_15_12 R/W-0 12 11 PINMUX1_11_8 R/W-0 28 27 PINMUX1_27_24 R/W-0 8 7 PINMUX1_7_4 R/W-0 24 23 PINMUX1_23_20 R/W-0 4 3 PINMUX1_3_0 R/W-0 20 19 PINMUX1_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write. -n = value after reset Table 11-23.com 11. Selects Function AXR9 Selects Function DX1 Reserved Selects Function GP0[1] Reserved AXR10/DR1/GP0[2] Control Pin is 3-stated.

ti. Selects Function AXR12 Selects Function FSR1 Reserved Selects Function GP0[4] Reserved AXR13/CLKX1/GP0[5] Control Pin is 3-stated.www. Selects Function AXR13 Selects Function CLKX1 Reserved Selects Function GP0[5] Reserved AXR14/CLKR1/GP0[6] Control Pin is 3-stated.com SYSCFG Registers Table 11-23. Texas Instruments Incorporated 247 . Selects Function AXR15 Selects Function EPWM0TZ[0] Reserved Selects Function ECAP2_APWM2 Reserved Selects Function GP0[7] Reserved Z I/O I X I/O X I/O X Z I/O I/O X I/O X Z I/O I/O X I/O X Z I/O I/O X I/O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions (continued) Bit 15-12 Field PINMUX1_15_12 0 1h 2h 3h-7h 8h 9h-Fh 11-8 PINMUX1_11_8 0 1h 2h 3h-7h 8h 9h-Fh 7-4 PINMUX1_7_4 0 1h 2h 3h-7h 8h 9h-Fh 3-0 PINMUX1_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description AXR12/FSR1/GP0[4] Control Pin is 3-stated. Selects Function AXR14 Selects Function CLKR1 Reserved Selects Function GP0[6] Reserved AXR15/EPWM0TZ[0]/ECAP2_APWM2/GP0[7] Control Pin is 3-stated.

com 11. -n = value after reset Table 11-24. O = Output.3 Pin Multiplexing Control 2 Register (PINMUX2) Figure 11-20. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . X = Undefined.10. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions Bit 31-28 Field PINMUX2_31_28 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX2_27_24 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 23-20 PINMUX2_23_20 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh (1) Value Description AXR0/ECAP0_APWM0/GP8[7]/MII_TXD[0]/CLKS0 Control Selects Function CLKS0 Selects Function AXR0 Selects Function ECAP0_APWM0 Reserved Selects Function GP8[7] Reserved Selects Function MII_TXD[0] Reserved AXR1/DX0/GP1[9]/MII_TXD[1] Control Pin is 3-stated.5. I/O = Bidirectional. Selects Function AXR2 Selects Function DR0 Reserved Selects Function GP1[10] Reserved Selects Function MII_TXD[2] Reserved Type I I/O I/O X I/O X O X Z I/O O X I/O X O X Z I/O I X I/O X O X (1) I = Input. Pin Multiplexing Control 2 Register (PINMUX2) 31 PINMUX2_31_28 R/W-0 15 PINMUX2_15_12 R/W-0 12 11 PINMUX2_11_8 R/W-0 28 27 PINMUX2_27_24 R/W-0 8 7 PINMUX2_7_4 R/W-0 24 23 PINMUX2_23_20 R/W-0 4 3 PINMUX2_3_0 R/W-0 20 19 PINMUX2_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write. Z = High-impedance state 248 System Configuration (SYSCFG) Module Copyright © 2011.ti. Selects Function AXR1 Selects Function DX0 Reserved Selects Function GP1[9] Reserved Selects Function MII_TXD[1] Reserved AXR2/DR0/GP1[10]/MII_TXD[2] Control Pin is 3-stated.SYSCFG Registers www.

Selects Function AXR4 Selects Function FSR0 Reserved Selects Function GP1[12] Reserved Selects Function MII_COL Reserved AXR5/CLKX0/GP1[13]/MII_TXCLK Control Pin is 3-stated.www. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions (continued) Bit 19-16 Field PINMUX2_19_16 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 15-12 PINMUX2_15_12 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 11-8 PINMUX2_11_8 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX2_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX2_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description AXR3/FSX0/GP1[11]/MII_TXD[3] Control Pin is 3-stated. Selects Function AXR3 Selects Function FSX0 Reserved Selects Function GP1[11] Reserved Selects Function MII_TXD[3] Reserved AXR4/FSR0/GP1[12]/MII_COL Control Pin is 3-stated. Texas Instruments Incorporated 249 .com SYSCFG Registers Table 11-24.ti. Selects Function AXR5 Selects Function CLKX0 Reserved Selects Function GP1[13] Reserved Selects Function MII_TXCLK Reserved AXR6/CLKR0/GP1[14]/MII_TXEN/PRU0_R31[6] Control Selects Function PRU0_R31[6] Selects Function AXR6 Selects Function CLKR0 Reserved Selects Function GP1[14] Reserved Selects Function MII_TXEN Reserved AXR7/EPWM1TZ[0]/PRU0_R30[17]/GP1[15]/PRU0_R31[7] Control Selects Function PRU0_R31[7] Selects Function AXR7 Selects Function EPWM1TZ[0] Reserved Selects Function PRU0_R30[17] Reserved Selects Function GP1[15] Reserved I I/O I X O X I/O X I I/O I/O X I/O X O X Z I/O I/O X I/O X I X Z I/O I/O X I/O X I X Z I/O I/O X I/O X O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.

Selects Function SPI0_SCS[4] Selects Function UART0_TXD Reserved Selects Function GP8[3] Reserved Selects Function MII_RXD[2] Reserved Type I I/O O X I/O X I X I I/O I X I/O X I X Z I/O O X I/O X I X (1) I = Input.SYSCFG Registers www. -n = value after reset Table 11-25.com 11. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions Bit 31-28 Field PINMUX3_31_28 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX3_27_24 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 23-20 PINMUX3_23_20 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh (1) Value Description SPI0_SCS[2]/UART0_RTS/GP8[1]/MII_RXD[0]/SATA_CP_DET Control Selects Function SATA_CP_DET Selects Function SPI0_SCS[2] Selects Function UART0_RTS Reserved Selects Function GP8[1] Reserved Selects Function MII_RXD[0] Reserved SPI0_SCS[3]/UART0_CTS/GP8[2]/MII_RXD[1]/SATA_MP_SWITCH Control Selects Function SATA_MP_SWITCH Selects Function SPI0_SCS[3] Selects Function UART0_CTS Reserved Selects Function GP8[2] Reserved Selects Function MII_RXD[1] Reserved SPI0_SCS[4]/UART0_TXD/GP8[3]/MII_RXD[2] Control Pin is 3-stated. Z = High-impedance state 250 System Configuration (SYSCFG) Module Copyright © 2011. X = Undefined. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .ti. Pin Multiplexing Control 3 Register (PINMUX3) 31 PINMUX3_31_28 R/W-0 15 PINMUX3_15_12 R/W-0 12 11 PINMUX3_11_8 R/W-0 28 27 PINMUX3_27_24 R/W-0 8 7 PINMUX3_7_4 R/W-0 24 23 PINMUX3_23_20 R/W-0 4 3 PINMUX3_3_0 R/W-0 20 19 PINMUX3_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write.5. I/O = Bidirectional.4 Pin Multiplexing Control 3 Register (PINMUX3) Figure 11-21.10. O = Output.

Selects Function SPI0_SOMI Selects Function EPWMSYNCI Reserved Selects Function GP8[6] Reserved Selects Function MII_RXER Reserved SPI0_ENA/EPWM0B/PRU0_R30[6]/MII_RXDV Control Pin is 3-stated.com SYSCFG Registers Table 11-25. Selects Function SPI0_SCS[5] Selects Function UART0_RXD Reserved Selects Function GP8[4] Reserved Selects Function MII_RXD[3] Reserved SPI0_SIMO/EPWMSYNCO/GP8[5]/MII_CRS Control Pin is 3-stated. Selects Function SPI0_SIMO Selects Function EPWMSYNCO Reserved Selects Function GP8[5] Reserved Selects Function MII_CRS Reserved SPI0_SOMI/EPWMSYNCI/GP8[6]/MII_RXER Control Pin is 3-stated.www.ti. Texas Instruments Incorporated 251 . Selects Function SPI0_ENA Selects Function EPWM0B Reserved Selects Function PRU0_R30[6] Reserved Selects Function MII_RXDV Reserved SPI0_CLK/EPWM0A/GP1[8]/MII_RXCLK Control Pin is 3-stated. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions (continued) Bit 19-16 Field PINMUX3_19_16 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 15-12 PINMUX3_15_12 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 11-8 PINMUX3_11_8 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX3_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX3_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description SPI0_SCS[5]/UART0_RXD/GP8[4]/MII_RXD[3] Control Pin is 3-stated. Selects Function SPI0_CLK Selects Function EPWM0A Reserved Selects Function GP1[8] Reserved Selects Function MII_RXCLK Reserved Z I/O I/O X I/O X I X Z I/O I/O X O X I X Z I/O I X I/O X I X Z I/O O X I/O X I X Z I/O I X I/O X I X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.

Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions Bit 31-28 Field PINMUX4_31_28 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX4_27_24 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 23-20 PINMUX4_23_20 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description SP1_SCS[2]/UART1_TXD/SATA_CP_POD/GP1[0] Control Pin is 3-stated.5 Pin Multiplexing Control 4 Register (PINMUX4) Figure 11-22.10. X = Undefined. Texas Instruments Incorporated 252 SPRUH77A – December 2011 Submit Documentation Feedback .5. Selects Function SPI1_SCS[4] Selects Function UART2_TXD Reserved Selects Function I2C1_SDA Reserved Selects Function GP1[2] Reserved Z I/O O X I/O X I/O X Z I/O I X O X I/O X Z I/O O X O X I/O X Type (1) (1) I = Input. Selects Function SPI1_SCS[3] Selects Function UART1_RXD Reserved Selects Function SATA_LED Reserved Selects Function GP1[1] Reserved SPI1_SCS[4]/UART2_TXD/I2C1_SDA/GP1[2] Control Pin is 3-stated. O = Output. Pin Multiplexing Control 4 Register (PINMUX4) 31 PINMUX4_31_28 R/W-0 15 PINMUX4_15_12 R/W-0 12 11 PINMUX4_11_8 R/W-0 28 27 PINMUX4_27_24 R/W-0 8 7 PINMUX4_7_4 R/W-0 24 23 PINMUX4_23_20 R/W-0 4 3 PINMUX4_3_0 R/W-0 20 19 PINMUX4_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write.ti. I/O = Bidirectional. Z = High-impedance state System Configuration (SYSCFG) Module Copyright © 2011. Selects Function SP1_SCS[2] Selects Function UART1_TXD Reserved Selects Function SATA_CP_POD Reserved Selects Function GP1[0] Reserved SPI1_SCS[3]/UART1_RXD/SATA_LED/GP1[1] Control Pin is 3-stated.com 11.SYSCFG Registers www. -n = value after reset Table 11-26.

Selects Function SPI1_SCS[5] Selects Function UART2_RXD Reserved Selects Function I2C1_SCL Reserved Selects Function GP1[3] Reserved SPI1_SCS[6]/I2C0_SDA/TM64P3_OUT12/GP1[4] Control Pin is 3-stated. Selects Function SPI1_SCS[7] Selects Function I2C0_SCL Reserved Selects Function TM64P2_OUT12 Reserved Selects Function GP1[5] Reserved SPI0_SCS[0]/TM64P1_OUT12/GP1[6]/MDIO_D/TM64P1_IN12 Control Selects Function TM64P1_IN12 Selects Function SPI0_SCS[0] Selects Function TM64P1_OUT12 Reserved Selects Function GP1[6] Reserved Selects Function MDIO_D Reserved SPI0_SCS[1]/TM64P0_OUT12/GP1[7]/MDIO_CLK/TM64P0_IN12 Control Selects Function TM64P0_IN12 Selects Function SPI0_SCS[1] Selects Function TM64P0_OUT12 Reserved Selects Function GP1[7] Reserved Selects Function MDIO_CLK Reserved I I/O O X I/O X O X I I/O O X I/O X I/O X Z I/O I/O X O X I/O X Z I/O I/O X O X I/O X Z I/O I X I/O X I/O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.www.ti. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions (continued) Bit 19-16 Field PINMUX4_19_16 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 15-12 PINMUX4_15_12 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 11-8 PINMUX4_11_8 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX4_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX4_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description SPI1_SCS[5]/UART2_RXD/I2C1_SCL/GP1[3] Control Pin is 3-stated.com SYSCFG Registers Table 11-26. Selects Function SPI1_SCS[6] Selects Function I2C0_SDA Reserved Selects Function TM64P3_OUT12 Reserved Selects Function GP1[4] Reserved SPI1_SCS[7]/I2C0_SCL/TM64P2_OUT12/GP1[5] Control Pin is 3-stated. Texas Instruments Incorporated 253 .

Texas Instruments Incorporated 254 SPRUH77A – December 2011 Submit Documentation Feedback .SYSCFG Registers www.5. X = Undefined. O = Output. Selects Function EMA_BA[0] Reserved Selects Function GP2[8] Reserved EMA_BA[1]/GP2[9] Control Pin is 3-stated. -n = value after reset Table 11-27.ti. Z = High-impedance state System Configuration (SYSCFG) Module Copyright © 2011.com 11. I/O = Bidirectional. Selects Function SPI1_SOMI Reserved Selects Function GP2[11] Reserved SPI1_ENA/GP2[12] Control Pin is 3-stated. Pin Multiplexing Control 5 Register (PINMUX5) 31 PINMUX5_31_28 R/W-0 15 PINMUX5_15_12 R/W-0 12 11 PINMUX5_11_8 R/W-0 28 27 PINMUX5_27_24 R/W-0 8 7 PINMUX5_7_4 R/W-0 24 23 PINMUX5_23_20 R/W-0 4 3 PINMUX5_3_0 R/W-0 20 19 PINMUX5_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write.10. Selects Function SPI1_SIMO Reserved Selects Function GP2[10] Reserved SPI1_SOMI/GP2[11] Control Pin is 3-stated. Selects Function SPI1_ENA Reserved Selects Function GP2[12] Reserved Z I/O X I/O X Z I/O X I/O X Z I/O X I/O X Z O X I/O X Z O X I/O X Type (1) (1) I = Input. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions Bit 31-28 Field PINMUX5_31_28 0 1h 2h-7h 8h 9h-Fh 27-24 PINMUX5_27_24 0 1h 2h-7h 8h 9h-Fh 23-20 PINMUX5_23_20 0 1h 2h-7h 8h 9h-Fh 19-16 PINMUX5_19_16 0 1h 2h-7h 8h 9h-Fh 15-12 PINMUX5_15_12 0 1h 2h-7h 8h 9h-Fh Value Description EMA_BA[0]/GP2[8] Control Pin is 3-stated.6 Pin Multiplexing Control 5 Register (PINMUX5) Figure 11-23. Selects Function EMA_BA[1] Reserved Selects Function GP2[9] Reserved SPI1_SIMO/GP2[10] Control Pin is 3-stated.

Selects Function SPI1_CLK Reserved Selects Function GP2[13] Reserved SPI1_SCS[0]/EPWM1B/PRU0_R30[7]/GP2[14]/TM64P3_IN12 Control Selects Function TM64P3_IN12 Selects Function SPI1_SCS[0] Selects Function EPWM1B Reserved Selects Function PRU0_R30[7] Reserved Selects Function GP2[14] Reserved SPI1_SCS[1]/EPWM1A/PRU0_R30[8]/GP2[15]/TM64P2_IN12 Control Selects Function TM64P2_IN12 Selects Function SPI1_SCS[1] Selects Function EPWM1A Reserved Selects Function PRU0_R30[8] Reserved Selects Function GP2[15] Reserved I I/O I/O X O X I/O X I I/O I/O X O X I/O X Z I/O X I/O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.www.com SYSCFG Registers Table 11-27.ti. Texas Instruments Incorporated 255 . Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions (continued) Bit 11-8 Field PINMUX5_11_8 0 1h 2h-7h 8h 9h-Fh 7-4 PINMUX5_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX5_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description SPI1_CLK/GP2[13] Control Pin is 3-stated.

7 Pin Multiplexing Control 6 Register (PINMUX6) Figure 11-24.5. Z = High-impedance state 256 System Configuration (SYSCFG) Module Copyright © 2011. Selects Function EMA_CS[0] Reserved Selects Function GP2[0] Reserved EMA_WAIT[1]/PRU0_R30[1]/GP2[1]/PRU0_R31[1] Control Selects Function PRU0_R31[1] Selects Function EMA_WAIT[1] Reserved Selects Function PRU0_R30[1] Reserved Selects Function GP2[1] Reserved EMA_WE_DQM[1]/GP2[2] Control Pin is 3-stated. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions Bit 31-28 Field PINMUX6_31_28 0 1h 2h-7h 8h 9h-Fh 27-24 PINMUX6_27_24 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh 23-20 PINMUX6_23_20 0 1h 2h-7h 8h 9h-Fh 19-16 PINMUX6_19_16 0 1h 2h-7h 8h 9h-Fh 15-12 PINMUX6_15_12 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh (1) Value Description EMA_CS[0]/GP2[0] Control Pin is 3-stated. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . O = Output. -n = value after reset Table 11-28. Pin Multiplexing Control 6 Register (PINMUX6) 31 PINMUX6_31_28 R/W-0 15 PINMUX6_15_12 R/W-0 12 11 PINMUX6_11_8 R/W-0 28 27 PINMUX6_27_24 R/W-0 8 7 PINMUX6_7_4 R/W-0 24 23 PINMUX6_23_20 R/W-0 4 3 PINMUX6_3_0 R/W-0 20 19 PINMUX6_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write.ti.10. I/O = Bidirectional.com 11. Selects Function EMA_WE_DQM[1] Reserved Selects Function GP2[2] Reserved EMA_WE_DQM[0]/GP2[3] Control Pin is 3-stated.SYSCFG Registers www. Selects Function EMA_WE_DQM[0] Reserved Selects Function GP2[3] Reserved EMA_CAS/PRU0_R30[2]/GP2[4]/PRU0_R31[2] Control Selects Function PRU0_R31[2] Selects Function EMA_CAS Reserved Selects Function PRU0_R30[2] Reserved Selects Function GP2[4] Reserved Type Z O X I/O X I I X O X I/O X Z O X I/O X Z O X I/O X I O X O X I/O X (1) I = Input. X = Undefined.

ti.www. Texas Instruments Incorporated 257 . Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions (continued) Bit 11-8 Field PINMUX6_11_8 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX6_7_4 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX6_3_0 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh Value Description EMA_RAS/PRU0_R30[3]/GP2[5]/PRU0_R31[3] Control Selects Function PRU0_R31[3] Selects Function EMA_RAS Reserved Selects Function PRU0_R30[3] Reserved Selects Function GP2[5] Reserved EMA_SDCKE/PRU0_R30[4]/GP2[6]/PRU0_R31[4] Control Selects Function PRU0_R31[4] Selects Function EMA_SDCKE Reserved Selects Function PRU0_R30[4] Reserved Selects Function GP2[6] Reserved EMA_CLK/PRU0_R30[5]/GP2[7]/PRU0_R31[5] Control Selects Function PRU0_R31[5] Selects Function EMA_CLK Reserved Selects Function PRU0_R30[5] Reserved Selects Function GP2[7] Reserved I O X O X I/O X I O X O X I/O X I O X O X I/O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.com SYSCFG Registers Table 11-28.

10. I/O = Bidirectional. O = Output. X = Undefined.SYSCFG Registers www. Z = High-impedance state System Configuration (SYSCFG) Module Copyright © 2011. -n = value after reset Table 11-29. Selects Function EMA_CS[5] Reserved Selects Function GP3[12] Reserved Z O X I/O X Z O X I/O X Z O X I/O X Z O X I/O X I I X O X I/O X Type (1) (1) I = Input. Pin Multiplexing Control 7 Register (PINMUX7) 31 PINMUX7_31_28 R/W-0 15 PINMUX7_15_12 R/W-0 12 11 PINMUX7_11_8 R/W-0 28 27 PINMUX7_27_24 R/W-0 8 7 PINMUX7_7_4 R/W-0 24 23 PINMUX7_23_20 R/W-0 4 3 PINMUX7_3_0 R/W-0 20 19 PINMUX7_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write.8 Pin Multiplexing Control 7 Register (PINMUX7) Figure 11-25.ti. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions Bit 31-28 Field PINMUX7_31_28 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX7_27_24 0 1h 2h-7h 8h 9h-Fh 23-20 PINMUX7_23_20 0 1h 2h-7h 8h 9h-Fh 19-16 PINMUX7_19_16 0 1h 2h-7h 8h 9h-Fh 15-12 PINMUX7_15_12 0 1h 2h-7h 8h 9h-Fh Value Description EMA_WAIT[0]/PRU0_R30[0]/GP3[8]/PRU0_R31[0] Control Selects Function PRU0_R31[0] Selects Function EMA_WAIT[0] Reserved Selects Function PRU0_R30[0] Reserved Selects Function GP3[8] Reserved EMA_A_RW/GP3[9] Control Pin is 3-stated. Selects Function EMA_A_RW Reserved Selects Function GP3[9] Reserved EMA_OE/GP3[10] Control Pin is 3-stated. Selects Function EMA_WE Reserved Selects Function GP3[11] Reserved EMA_CS[5]/GP3[12] Control Pin is 3-stated.com 11. Selects Function EMA_OE Reserved Selects Function GP3[10] Reserved EMA_WE/GP3[11] Control Pin is 3-stated.5. Texas Instruments Incorporated 258 SPRUH77A – December 2011 Submit Documentation Feedback .

ti. Selects Function EMA_CS[4] Reserved Selects Function GP3[13] Reserved EMA_CS[3]/GP3[14] Control Pin is 3-stated. Selects Function EMA_CS[3] Reserved Selects Function GP3[14] Reserved EMA_CS[2]/GP3[15] Control Pin is 3-stated. Texas Instruments Incorporated 259 . Selects Function EMA_CS[2] Reserved Selects Function GP3[15] Reserved Z O X I/O X Z O X I/O X Z O X I/O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.com SYSCFG Registers Table 11-29.www. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions (continued) Bit 11-8 Field PINMUX7_11_8 0 1h 2h-7h 8h 9h-Fh 7-4 PINMUX7_7_4 0 1h 2h-7h 8h 9h-Fh 3-0 PINMUX7_3_0 0 1h 2h-7h 8h 9h-Fh Value Description EMA_CS[4]/GP3[13] Control Pin is 3-stated.

com 11. Selects Function EMA_D[11] Reserved Selects Function GP3[3] Reserved EMA_D[12]/GP3[4] Control Pin is 3-stated. O = Output. Selects Function EMA_D[12] Reserved Selects Function GP3[4] Reserved Z I/O X I/O X Z I/O X I/O X Z I/O X I/O X Z I/O X I/O X Z I/O X I/O X Type (1) (1) I = Input.10. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions Bit 31-28 Field PINMUX8_31_28 0 1h 2h-7h 8h 9h-Fh 27-24 PINMUX8_27_24 0 1h 2h-7h 8h 9h-Fh 23-20 PINMUX8_23_20 0 1h 2h-7h 8h 9h-Fh 19-16 PINMUX8_19_16 0 1h 2h-7h 8h 9h-Fh 15-12 PINMUX8_15_12 0 1h 2h-7h 8h 9h-Fh Value Description EMA_D[8]/GP3[0] Control Pin is 3-stated.ti. Selects Function EMA_D[8] Reserved Selects Function GP3[0] Reserved EMA_D[9]/GP3[1] Control Pin is 3-stated. Selects Function EMA_D[10] Reserved Selects Function GP3[2] Reserved EMA_D[11]/GP3[3] Control Pin is 3-stated. I/O = Bidirectional. Pin Multiplexing Control 8 Register (PINMUX8) 31 PINMUX8_31_28 R/W-0 15 PINMUX8_15_12 R/W-0 12 11 PINMUX8_11_8 R/W-0 28 27 PINMUX8_27_24 R/W-0 8 7 PINMUX8_7_4 R/W-0 24 23 PINMUX8_23_20 R/W-0 4 3 PINMUX8_3_0 R/W-0 20 19 PINMUX8_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write. -n = value after reset Table 11-30.9 Pin Multiplexing Control 8 Register (PINMUX8) Figure 11-26. Selects Function EMA_D[9] Reserved Selects Function GP3[1] Reserved EMA_D[10]/GP3[2] Control Pin is 3-stated. Texas Instruments Incorporated 260 SPRUH77A – December 2011 Submit Documentation Feedback . X = Undefined.5.SYSCFG Registers www. Z = High-impedance state System Configuration (SYSCFG) Module Copyright © 2011.

Selects Function EMA_D[13] Reserved Selects Function GP3[5] Reserved EMA_D[14]/GP3[6] Control Pin is 3-stated. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions (continued) Bit 11-8 Field PINMUX8_11_8 0 1h 2h-7h 8h 9h-Fh 7-4 PINMUX8_7_4 0 1h 2h-7h 8h 9h-Fh 3-0 PINMUX8_3_0 0 1h 2h-7h 8h 9h-Fh Value Description EMA_D[13]/GP3[5] Control Pin is 3-stated.ti. Selects Function EMA_D[15] Reserved Selects Function GP3[7] Reserved Z I/O X I/O X Z I/O X I/O X Z I/O X I/O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.www.com SYSCFG Registers Table 11-30. Selects Function EMA_D[14] Reserved Selects Function GP3[6] Reserved EMA_D[15]/GP3[7] Control Pin is 3-stated. Texas Instruments Incorporated 261 .

Selects Function EMA_D[1] Reserved Selects Function GP4[9] Reserved EMA_D[2]/GP4[10] Control Pin is 3-stated. I/O = Bidirectional.10 Pin Multiplexing Control 9 Register (PINMUX9) Figure 11-27. X = Undefined. O = Output.10. Pin Multiplexing Control 9 Register (PINMUX9) 31 PINMUX9_31_28 R/W-0 15 PINMUX9_15_12 R/W-0 12 11 PINMUX9_11_8 R/W-0 28 27 PINMUX9_27_24 R/W-0 8 7 PINMUX9_7_4 R/W-0 24 23 PINMUX9_23_20 R/W-0 4 3 PINMUX9_3_0 R/W-0 20 19 PINMUX9_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write. Selects Function EMA_D[0] Reserved Selects Function GP4[8] Reserved EMA_D[1]/GP4[9] Control Pin is 3-stated. Z = High-impedance state System Configuration (SYSCFG) Module Copyright © 2011. Selects Function EMA_D[3] Reserved Selects Function GP4[11] Reserved EMA_D[4]/GP4[12] Control Pin is 3-stated.5.SYSCFG Registers www. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions Bit 31-28 Field PINMUX9_31_28 0 1h 2h-7h 8h 9h-Fh 27-24 PINMUX9_27_24 0 1h 2h-7h 8h 9h-Fh 23-20 PINMUX9_23_20 0 1h 2h-7h 8h 9h-Fh 19-16 PINMUX9_19_16 0 1h 2h-7h 8h 9h-Fh 15-12 PINMUX9_15_12 0 1h 2h-7h 8h 9h-Fh Value Description EMA_D[0]/GP4[8] Control Pin is 3-stated. Selects Function EMA_D[2] Reserved Selects Function GP4[10] Reserved EMA_D[3]/GP4[11] Control Pin is 3-stated. Selects Function EMA_D[4] Reserved Selects Function GP4[12] Reserved Z I/O X I/O X Z I/O X I/O X Z I/O X I/O X Z I/O X I/O X Z I/O X I/O X Type (1) (1) I = Input.com 11. Texas Instruments Incorporated 262 SPRUH77A – December 2011 Submit Documentation Feedback . -n = value after reset Table 11-31.ti.

com SYSCFG Registers Table 11-31.www. Selects Function EMA_D[6] Reserved Selects Function GP4[14] Reserved EMA_D[7]/GP4[15] Control Pin is 3-stated. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions (continued) Bit 11-8 Field PINMUX9_11_8 0 1h 2h-7h 8h 9h-Fh 7-4 PINMUX9_7_4 0 1h 2h-7h 8h 9h-Fh 3-0 PINMUX9_3_0 0 1h 2h-7h 8h 9h-Fh Value Description EMA_D[5]/GP4[13] Control Pin is 3-stated. Selects Function EMA_D[7] Reserved Selects Function GP4[15] Reserved Z I/O X I/O X Z I/O X I/O X Z I/O X I/O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Texas Instruments Incorporated 263 .ti. Selects Function EMA_D[5] Reserved Selects Function GP4[13] Reserved EMA_D[6]/GP4[14] Control Pin is 3-stated.

ti. -n = value after reset Table 11-32. Selects Function EMA_A[16] Selects Function MMCSD0_DAT[5] Reserved Selects Function PRU1_R30[24] Reserved Selects Function GP4[0] Reserved EMA_A[17]/MMCSD0_DAT[4]/PRU1_R30[25]/GP4[1] Control Pin is 3-stated. O = Output.5. Selects Function EMA_A[17] Selects Function MMCSD0_DAT[4] Reserved Selects Function PRU1_R30[25] Reserved Selects Function GP4[1] Reserved EMA_A[18]/MMCSD0_DAT[3]/PRU1_R30[26]/GP4[2] Control Pin is 3-stated. X = Undefined. I/O = Bidirectional. Pin Multiplexing Control 10 Register (PINMUX10) 31 PINMUX10_31_28 R/W-0 15 PINMUX10_15_12 R/W-0 12 11 PINMUX10_11_8 R/W-0 28 27 PINMUX10_27_24 R/W-0 8 7 PINMUX10_7_4 R/W-0 24 23 PINMUX10_23_20 R/W-0 4 3 PINMUX10_3_0 R/W-0 20 19 PINMUX10_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write. Selects Function EMA_A[18] Selects Function MMCSD0_DAT[3] Reserved Selects Function PRU1_R30[26] Reserved Selects Function GP4[2] Reserved Type Z O I/O X O X I/O X Z O I/O X O X I/O X Z O I/O X O X I/O X (1) I = Input.11 Pin Multiplexing Control 10 Register (PINMUX10) Figure 11-28. Z = High-impedance state 264 System Configuration (SYSCFG) Module Copyright © 2011.com 11. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .SYSCFG Registers www.10. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions Bit 31-28 Field PINMUX10_31_28 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX10_27_24 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 23-20 PINMUX10_23_20 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh (1) Value Description EMA_A[16]/MMCSD0_DAT[5]/PRU1_R30[24]/GP4[0] Control Pin is 3-stated.

com SYSCFG Registers Table 11-32. Selects Function EMA_A[20] Selects Function MMCSD0_DAT[1] Reserved Selects Function PRU1_R30[28] Reserved Selects Function GP4[4] Reserved EMA_A[21]/MMCSD0_DAT[0]/PRU1_R30[29]/GP4[5] Control Pin is 3-stated.ti. Selects Function EMA_A[19] Selects Function MMCSD0_DAT[2] Reserved Selects Function PRU1_R30[27] Reserved Selects Function GP4[3] Reserved EMA_A[20]/MMCSD0_DAT[1]/PRU1_R30[28]/GP4[4] Control Pin is 3-stated. Reserved Selects Function MMCSD0_CLK Reserved Selects Function PRU1_R30[31] Reserved Selects Function GP4[7] Reserved Z X O X O X I/O X Z O I/O X O X I/O X Z O I/O X O X I/O X Z O I/O X O X I/O X Z O I/O X O X I/O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.www. Texas Instruments Incorporated 265 . Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions (continued) Bit 19-16 Field PINMUX10_19_16 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 15-12 PINMUX10_15_12 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 11-8 PINMUX10_11_8 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX10_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX10_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description EMA_A[19]/MMCSD0_DAT[2]/PRU1_R30[27]/GP4[3] Control Pin is 3-stated. Selects Function EMA_A[22] Selects Function MMCSD0_CMD Reserved Selects Function PRU1_R30[30] Reserved Selects Function GP4[6] Reserved MMCSD0_CLK/PRU1_R30[31]/GP4[7] Control Pin is 3-stated. Selects Function EMA_A[21] Selects Function MMCSD0_DAT[0] Reserved Selects Function PRU1_R30[29] Reserved Selects Function GP4[5] Reserved EMA_A[22]/MMCSD0_CMD/PRU1_R30[30]/GP4[6] Control Pin is 3-stated.

-n = value after reset Table 11-33.5. I/O = Bidirectional.ti. Pin Multiplexing Control 11 Register (PINMUX11) 31 PINMUX11_31_28 R/W-0 15 PINMUX11_15_12 R/W-0 12 11 PINMUX11_11_8 R/W-0 28 27 PINMUX11_27_24 R/W-0 8 7 PINMUX11_7_4 R/W-0 24 23 PINMUX11_23_20 R/W-0 4 3 PINMUX11_3_0 R/W-0 20 19 PINMUX11_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .com 11. Selects Function EMA_A[9] Reserved Selects Function PRU1_R30[17] Reserved Selects Function GP5[9] Reserved EMA_A[10]/PRU1_R30[18]/GP5[10]/PRU1_R31[18] Control Selects Function PRU1_R31[18] Selects Function EMA_A[10] Reserved Selects Function PRU1_R30[18] Reserved Selects Function GP5[10] Reserved EMA_A[11]/PRU1_R30[19]/GP5[11]/PRU1_R31[19] Control Selects Function PRU1_R31[19] Selects Function EMA_A[11] Reserved Selects Function PRU1_R30[19] Reserved Selects Function GP5[11] Reserved Type Z O X O X I/O X Z O X O X I/O X I O X O X I/O X I O X O X I/O X (1) I = Input.10.SYSCFG Registers www.12 Pin Multiplexing Control 11 Register (PINMUX11) Figure 11-29. X = Undefined. O = Output. Z = High-impedance state 266 System Configuration (SYSCFG) Module Copyright © 2011. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions Bit 31-28 Field PINMUX11_31_28 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX11_27_24 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh 23-20 PINMUX11_23_20 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh 19-16 PINMUX11_19_16 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh (1) Value Description EMA_A[8]/PRU1_R30[16]/GP5[8] Control Pin is 3-stated. Selects Function EMA_A[8] Reserved Selects Function PRU1_R30[16] Reserved Selects Function GP5[8] Reserved EMA_A[9]/PRU1_R30[17]/GP5[9] Control Pin is 3-stated.

Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions (continued) Bit 15-12 Field PINMUX11_15_12 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh 11-8 PINMUX11_11_8 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX11_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX11_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description EMA_A[12]/PRU1_R30[20]/GP5[12]/PRU1_R31[20] Control Selects Function PRU1_R31[20] Selects Function EMA_A[12] Reserved Selects Function PRU1_R30[20] Reserved Selects Function GP5[12] Reserved EMA_A[13]/PRU0_R30[21]/PRU1_R30[21]/GP5[13]/PRU1_R31[21] Control Selects Function PRU1_R31[21] Selects Function EMA_A[13] Selects Function PRU0_R30[21] Reserved Selects Function PRU1_R30[21] Reserved Selects Function GP5[13] Reserved EMA_A[14]/MMCSD0_DAT[7]/PRU1_R30[22]/GP5[14]/PRU1_R31[22] Control Selects Function PRU1_R31[22] Selects Function EMA_A[14] Selects Function MMCSD0_DAT[7] Reserved Selects Function PRU1_R30[22] Reserved Selects Function GP5[14] Reserved EMA_A[15]/MMCSD0_DAT[6]/PRU1_R30[23]/GP5[15]/PRU1_R31[23] Control Selects Function PRU1_R31[23] Selects Function EMA_A[15] Selects Function MMCSD0_DAT[6] Reserved Selects Function PRU1_R30[23] Reserved Selects Function GP5[15] Reserved I O I/O X O X I/O X I O I/O X O X I/O X I O O X O X I/O X I O X O X I/O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.www. Texas Instruments Incorporated 267 .com SYSCFG Registers Table 11-33.ti.

Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions Bit 31-28 Field PINMUX12_31_28 0 1h 2h-7h 8h 9h-Fh 27-24 PINMUX12_27_24 0 1h 2h-7h 8h 9h-Fh 23-20 PINMUX12_23_20 0 1h 2h-7h 8h 9h-Fh 19-16 PINMUX12_19_16 0 1h 2h-7h 8h 9h-Fh 15-12 PINMUX12_15_12 0 1h 2h-7h 8h 9h-Fh Value Description EMA_A[0]/GP5[0] Control Pin is 3-stated. Texas Instruments Incorporated 268 SPRUH77A – December 2011 Submit Documentation Feedback .5. Z = High-impedance state System Configuration (SYSCFG) Module Copyright © 2011.com 11. Selects Function EMA_A[2] Reserved Selects Function GP5[2] Reserved EMA_A[3]/GP5[3] Control Pin is 3-stated. Pin Multiplexing Control 12 Register (PINMUX12) 31 PINMUX12_31_28 R/W-0 15 PINMUX12_15_12 R/W-0 12 11 PINMUX12_11_8 R/W-0 28 27 PINMUX12_27_24 R/W-0 8 7 PINMUX12_7_4 R/W-0 24 23 PINMUX12_23_20 R/W-0 4 3 PINMUX12_3_0 R/W-0 20 19 PINMUX12_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write. -n = value after reset Table 11-34. I/O = Bidirectional. Selects Function EMA_A[4] Reserved Selects Function GP5[4] Reserved Z O X I/O X Z O X I/O X Z O X I/O X Z O X I/O X Z O X I/O X Type (1) (1) I = Input.ti.SYSCFG Registers www. Selects Function EMA_A[0] Reserved Selects Function GP5[0] Reserved EMA_A[1]/GP5[1] Control Pin is 3-stated. Selects Function EMA_A[3] Reserved Selects Function GP5[3] Reserved EMA_A[4]/GP5[4] Control Pin is 3-stated.10. O = Output. X = Undefined.13 Pin Multiplexing Control 12 Register (PINMUX12) Figure 11-30. Selects Function EMA_A[1] Reserved Selects Function GP5[1] Reserved EMA_A[2]/GP5[2] Control Pin is 3-stated.

Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions (continued) Bit 11-8 Field PINMUX12_11_8 0 1h 2h-7h 8h 9h-Fh 7-4 PINMUX12_7_4 0 1h 2h-7h 8h 9h-Fh 3-0 PINMUX12_3_0 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh Value Description EMA_A[5]/GP5[5] Control Pin is 3-stated. Selects Function EMA_A[5] Reserved Selects Function GP5[5] Reserved EMA_A[6]/GP5[6] Control Pin is 3-stated. Texas Instruments Incorporated 269 . Selects Function EMA_A[7] Reserved Selects Function PRU1_R30[15] Reserved Selects Function GP5[7] Reserved Z O X O X I/O X Z O X I/O X Z O X I/O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Selects Function EMA_A[6] Reserved Selects Function GP5[6] Reserved EMA_A[7]/PRU1_R30[15]/GP5[7] Control Pin is 3-stated.ti.www.com SYSCFG Registers Table 11-34.

-n = value after reset Table 11-35. X = Undefined. Selects Function PRU0_R30[28] Selects Function UHPI_HCNTL1 Reserved Selects Function UPP_CHA_START Reserved Selects Function GP6[10] Reserved Type I O I X I/O X I/O X Z O I X I/O X I/O X Z O I X I/O X I/O X (1) I = Input. Z = High-impedance state 270 System Configuration (SYSCFG) Module Copyright © 2011. Selects Function PRU0_R30[27] Selects Function UHPI_HHWIL Reserved Selects Function UPP_CHA_ENABLE Reserved Selects Function GP6[9] Reserved PRU0_R30[28]/UHPI_HCNTL1/UPP_CHA_START/GP6[10] Control Pin is 3-stated.com 11. O = Output.10.5.SYSCFG Registers www.14 Pin Multiplexing Control 13 Register (PINMUX13) Figure 11-31. Pin Multiplexing Control 13 Register (PINMUX13) 31 PINMUX13_31_28 R/W-0 15 PINMUX13_15_12 R/W-0 12 11 PINMUX13_11_8 R/W-0 28 27 PINMUX13_27_24 R/W-0 8 7 PINMUX13_7_4 R/W-0 24 23 PINMUX13_23_20 R/W-0 4 3 PINMUX13_3_0 R/W-0 20 19 PINMUX13_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write.ti. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . I/O = Bidirectional. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions Bit 31-28 Field PINMUX13_31_28 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX13_27_24 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 23-20 PINMUX13_23_20 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh (1) Value Description PRU0_R30[26]/ UHPI_HRW/UPP_CHA_WAIT/GP6[8]/PRU1_R31[17] Control Selects Function PRU1_R31[17] Selects Function PRU0_R30[26] Selects Function UHPI_HRW Reserved Selects Function UPP_CHA_WAIT Reserved Selects Function GP6[8] Reserved PRU0_R30[27]/UHPI_HHWIL/UPP_CHA_ENABLE/GP6[9] Control Pin is 3-stated.

com SYSCFG Registers Table 11-35.www. Selects Function PRU0_R30[31] Selects Function UHPI_HRDY Reserved Selects Function PRU1_R30[12] Reserved Selects Function GP6[13] Reserved CLKOUT/UHPI_HDS2/PRU1_R30[13]/GP6[14] Control Pin is 3-stated. Selects Function CLKOUT Selects Function UHPI_HDS2 Reserved Selects Function PRU1_R30[13] Reserved Selects Function GP6[14] Reserved RESETOUT/UHPI_HAS/PRU1_R30[14]/GP6[15] Control Selects Function RESETOUT Selects Function RESETOUT Selects Function UHPI_HAS Reserved Selects Function PRU1_R30[14] Reserved Selects Function GP6[15] Reserved O O I X O X I/O X Z O I X O X I/O X Z O O X O X I/O X Z O O X O X I/O X Z O I X I/O X I/O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Texas Instruments Incorporated 271 . Selects Function PRU0_R30[29] Selects Function UHPI_HCNTL0 Reserved Selects Function UPP_CHA_CLOCK Reserved Selects Function GP6[11] Reserved PRU0_R30[30]/UHPI_HINT/PRU1_R30[11]/GP6[12] Control Pin is 3-stated. Selects Function PRU0_R30[30] Selects Function UHPI_HINT Reserved Selects Function PRU1_R30[11] Reserved Selects Function GP6[12] Reserved PRU0_R30[31]/UHPI_HRDY/PRU1_R30[12]/GP6[13] Control Pin is 3-stated.ti. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions (continued) Bit 19-16 Field PINMUX13_19_16 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 15-12 PINMUX13_15_12 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 11-8 PINMUX13_11_8 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX13_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX13_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description PRU0_R30[29]/UHPI_HCNTL0/UPP_CHA_CLOCK/GP6[11] Control Pin is 3-stated.

Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .com 11. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions Bit 31-28 Field PINMUX14_31_28 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX14_27_24 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 23-20 PINMUX14_23_20 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh (1) Value Description VP_DIN[2]/UHPI_HD[10]/UPP_D[10]/RMII_RXER/PRU0_R31[24] Control Selects Function PRU0_R31[24] Selects Function VP_DIN[2] Selects Function UHPI_HD[10] Reserved Selects Function UPP_D[10] Reserved Selects Function RMII_RXER Reserved VP_DIN[3]/UHPI_HD[11]/UPP_D[11]/RMII_RXD[0]/PRU0_R31[25] Control Selects Function PRU0_R31[25] Selects Function VP_DIN[3] Selects Function UHPI_HD[11] Reserved Selects Function UPP_D[11] Reserved Selects Function RMII_RXD[0] Reserved VP_DIN[4]/UHPI_HD[12]/UPP_D[12]/RMII_RXD[1]/PRU0_R31[26] Control Selects Function PRU0_R31[26] Selects Function VP_DIN[4] Selects Function UHPI_HD[12] Reserved Selects Function UPP_D[12] Reserved Selects Function RMII_RXD[1] Reserved Type I I I/O X I/O X I X I I I/O X I/O X I X I I I/O X I/O X I X (1) I = Input. I/O = Bidirectional.SYSCFG Registers www.ti.5. -n = value after reset Table 11-36. O = Output. Pin Multiplexing Control 14 Register (PINMUX14) 31 PINMUX14_31_28 R/W-0 15 PINMUX14_15_12 R/W-0 12 11 PINMUX14_11_8 R/W-0 28 27 PINMUX14_27_24 R/W-0 8 7 PINMUX14_7_4 R/W-0 24 23 PINMUX14_23_20 R/W-0 4 3 PINMUX14_3_0 R/W-0 20 19 PINMUX14_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write.10.15 Pin Multiplexing Control 14 Register (PINMUX14) Figure 11-32. X = Undefined 272 System Configuration (SYSCFG) Module Copyright © 2011.

www.com SYSCFG Registers Table 11-36. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions (continued) Bit 19-16 Field PINMUX14_19_16 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 15-12 PINMUX14_15_12 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 11-8 PINMUX14_11_8 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX14_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX14_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description VP_DIN[5]/UHPI_HD[13]/UPP_D[13]/RMII_TXEN/PRU0_R31[27] Control Selects Function PRU0_R31[27] Selects Function VP_DIN[5] Selects Function UHPI_HD[13] Reserved Selects Function UPP_D[13] Reserved Selects Function RMII_TXEN Reserved VP_DIN[6]/UHPI_HD[14]/UPP_D[14]/RMII_TXD[0]/PRU0_R31[28] Control Selects Function PRU0_R31[28] Selects Function VP_DIN[6] Selects Function UHPI_HD[14] Reserved Selects Function UPP_D[14] Reserved Selects Function RMII_TXD[0] Reserved VP_DIN[7]/UHPI_HD[15]/UPP_D[15]/RMII_TXD[1]/PRU0_R31[29] Control Selects Function PRU0_R31[29] Selects Function VP_DIN[7] Selects Function UHPI_HD[15] Reserved Selects Function UPP_D[15] Reserved Selects Function RMII_TXD[1] Reserved VP_CLKIN1/UHPI_HDS1/PRU1_R30[9]/GP6[6]/PRU1_R31[16] Control Selects Function PRU1_R31[16] Selects Function VP_CLKIN1 Selects Function UHPI_HDS1 Reserved Selects Function PRU1_R30[9] Reserved Selects Function GP6[6] Reserved VP_CLKIN0/UHPI_HCS/PRU1_R30[10]/GP6[7]/UPP_2xTXCLK Control Selects Function UPP_2xTXCLK Selects Function VP_CLKIN0 Selects Function UHPI_HCS Reserved Selects Function PRU1_R30[10] Reserved Selects Function GP6[7] Reserved I I I X O X I/O X I I I X O X I/O X I I I/O X I/O X O X I I I/O X I/O X O X I I I/O X I/O X O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Texas Instruments Incorporated 273 .ti.

16 Pin Multiplexing Control 15 Register (PINMUX15) Figure 11-33. X = Undefined 274 System Configuration (SYSCFG) Module Copyright © 2011. Pin Multiplexing Control 15 Register (PINMUX15) 31 PINMUX15_31_28 R/W-0 15 PINMUX15_15_12 R/W-0 12 11 PINMUX15_11_8 R/W-0 28 27 PINMUX15_27_24 R/W-0 8 7 PINMUX15_7_4 R/W-0 24 23 PINMUX15_23_20 R/W-0 4 3 PINMUX15_3_0 R/W-0 20 19 PINMUX15_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write.ti.SYSCFG Registers www. -n = value after reset Table 11-37.com 11. O = Output. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . I/O = Bidirectional. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions Bit 31-28 Field PINMUX15_31_28 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX15_27_24 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 23-20 PINMUX15_23_20 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh (1) Value Description VP_DIN[10]/UHPI_HD[2]/UPP_D[2]/PRU0_R30[10]/PRU0_R31[10] Control Selects Function PRU0_R31[10] Selects Function VP_DIN[10] Selects Function UHPI_HD[2] Reserved Selects Function UPP_D[2] Reserved Selects Function PRU0_R30[10] Reserved VP_DIN[11]/UHPI_HD[3]/UPP_D[3]/PRU0_R30[11]/PRU0_R31[11] Control Selects Function PRU0_R31[11] Selects Function VP_DIN[11] Selects Function UHPI_HD[3] Reserved Selects Function UPP_D[3] Reserved Selects Function PRU0_R30[11] Reserved VP_DIN[12]/UHPI_HD[4]/UPP_D[4]/PRU0_R30[12]/PRU0_R31[12] Control Selects Function PRU0_R31[12] Selects Function VP_DIN[12] Selects Function UHPI_HD[4] Reserved Selects Function UPP_D[4] Reserved Selects Function PRU0_R30[12] Reserved Type I I I/O X I/O X O X I I I/O X I/O X O X I I I/O X I/O X O X (1) I = Input.10.5.

com SYSCFG Registers Table 11-37.www. Texas Instruments Incorporated 275 . Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions (continued) Bit 19-16 Field PINMUX15_19_16 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 15-12 PINMUX15_15_12 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 11-8 PINMUX15_11_8 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX15_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description VP_DIN[13]_FIELD/UHPI_HD[5]/UPP_D[5]/PRU0_R30[13]/PRU0_R31[13] Control Selects Function PRU0_R31[13] Selects Function VP_DIN[13]_FIELD Selects Function UHPI_HD[5] Reserved Selects Function UPP_D[5] Reserved Selects Function PRU0_R30[13] Reserved VP_DIN[14]_HSYNC/UHPI_HD[6]/UPP_D[6]/PRU0_R30[14]/PRU0_R31[14] Control Selects Function PRU0_R31[14] Selects Function VP_DIN[14]_HSYNC Selects Function UHPI_HD[6] Reserved Selects Function UPP_D[6] Reserved Selects Function PRU0_R30[14] Reserved VP_DIN[15]_VSYNC/UHPI_HD[7]/UPP_D[7]/PRU0_R30[15]/PRU0_R31[15] Control Selects Function PRU0_R31[15] Selects Function VP_DIN[15]_VSYNC Selects Function UHPI_HD[7] Reserved Selects Function UPP_D[7] Reserved Selects Function PRU0_R30[15] Reserved VP_DIN[0]/UHPI_HD[8]/UPP_D[8]/RMII_CRS_DV/PRU1_R31[29] Control Selects Function PRU1_R31[29] Selects Function VP_DIN[0] Selects Function UHPI_HD[8] Reserved Selects Function UPP_D[8] Reserved Selects Function RMII_CRS_DV Reserved I I I/O X I/O X I X I I I/O X I/O X O X I I I/O X I/O X O X I I I/O X I/O X O X Type (1) SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.ti.

Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions (continued) Bit 3-0 Field PINMUX15_3_0 0 1h 2h 3h 4h 5h-7h 8h Value Description VP_DIN[1]/UHPI_HD[9]/UPP_D[9]/RMII_MHZ_50_CLK/PRU0_R31[23] Control Selects Function PRU0_R31[23].ti. PLL0_SYSCLK7 is driven out on the RMII_MHZ_50_CLK pin.4 for more information. Reserved I I I/O X I/O X O Type (1) 9h-Fh X 276 System Configuration (SYSCFG) Module Copyright © 2011.com Table 11-37. Enables sourcing of the 50 MHz reference clock from an external source on the RMII_MHZ_50_CLK pin to the EMAC. Selects Function VP_DIN[1] Selects Function UHPI_HD[9] Reserved Selects Function UPP_D[9] Reserved Selects Function RMII_MHZ_50_CLK. Also. Note that the SYSCLK7 output clock does not meet the RMII reference clock specification of 50 MHz +/-50 ppm. See Section 7. Enables sourcing of the 50 MHz reference clock from PLL0_SYSCLK7 to the EMAC.3.SYSCFG Registers www. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

Texas Instruments Incorporated 277 .com SYSCFG Registers 11.17 Pin Multiplexing Control 16 Register (PINMUX16) Figure 11-34. Pin Multiplexing Control 16 Register (PINMUX16) 31 PINMUX16_31_28 R/W-0 15 PINMUX16_15_12 R/W-0 12 11 PINMUX16_11_8 R/W-0 28 27 PINMUX16_27_24 R/W-0 8 7 PINMUX16_7_4 R/W-0 24 23 PINMUX16_23_20 R/W-0 4 3 PINMUX16_3_0 R/W-0 20 19 PINMUX16_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write. X = Undefined SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.ti. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions Bit 31-28 Field PINMUX16_31_28 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX16_27_24 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 23-20 PINMUX16_23_20 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh (1) Value Description VP_DOUT[2]/LCD_D[2]/UPP_XD[10]/GP7[10]/PRU1_R31[10] Control Selects Function PRU1_R31[10] Selects Function VP_DOUT[2] Selects Function LCD_D[2] Reserved Selects Function UPP_XD[10] Reserved Selects Function GP7[10] Reserved VP_DOUT[3]/LCD_D[3]/UPP_XD[11]/GP7[11]/PRU1_R31[11] Control Selects Function PRU1_R31[11] Selects Function VP_DOUT[3] Selects Function LCD_D[3] Reserved Selects Function UPP_XD[11] Reserved Selects Function GP7[11] Reserved VP_DOUT[4]/LCD_D[4]/UPP_XD[12]/GP7[12]/PRU1_R31[12] Control Selects Function PRU1_R31[12] Selects Function VP_DOUT[4] Selects Function LCD_D[4] Reserved Selects Function UPP_XD[12] Reserved Selects Function GP7[12] Reserved Type I O I/O X I/O X I/O X I O I/O X I/O X I/O X I O I/O X I/O X I/O X (1) I = Input. O = Output.www. I/O = Bidirectional.10. -n = value after reset Table 11-38.5.

SYSCFG Registers www.ti. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions (continued) Bit 19-16 Field PINMUX16_19_16 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 15-12 PINMUX16_15_12 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 11-8 PINMUX16_11_8 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX16_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX16_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description VP_DOUT[5]/LCD_D[5]/UPP_XD[13]/GP7[13]/PRU1_R31[13] Control Selects Function PRU1_R31[13] Selects Function VP_DOUT[5] Selects Function LCD_D[5] Reserved Selects Function UPP_XD[13] Reserved Selects Function GP7[13] Reserved VP_DOUT[6]/LCD_D[6]/UPP_XD[14]/GP7[14]/PRU1_R31[14] Control Selects Function PRU1_R31[14] Selects Function VP_DOUT[6] Selects Function LCD_D[6] Reserved Selects Function UPP_XD[14] Reserved Selects Function GP7[14] Reserved VP_DOUT[7]/LCD_D[7]/UPP_XD[15]/GP7[15]/PRU1_R31[15] Control Selects Function PRU1_R31[15] Selects Function VP_DOUT[7] Selects Function LCD_D[7] Reserved Selects Function UPP_XD[15] Reserved Selects Function GP7[15] Reserved VP_DIN[8]/UHPI_HD[0]/UPP_D0/GP6[5]/PRU1_R31[0] Control Selects Function PRU1_R31[0] Selects Function VP_DIN[8] Selects Function UHPI_HD[0] Reserved Selects Function UPP_D[0] Reserved Selects Function GP6[5] Reserved VP_DIN[9]/UHPI_HD[1]/UPP_D[1]/PRU0_R30[9]/PRU0_R31[9] Control Selects Function PRU0_R31[9] Selects Function VP_DIN[9] Selects Function UHPI_HD[1] Reserved Selects Function UPP_D[1] Reserved Selects Function PRU0_R30[9] Reserved I I I/O X I/O X O X I I I/O X I/O X I/O X I O I/O X I/O X I/O X I O I/O X I/O X I/O X I O I/O X I/O X I/O X Type (1) 278 System Configuration (SYSCFG) Module Copyright © 2011.com Table 11-38.

www. X = Undefined SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.10. I/O = Bidirectional. -n = value after reset Table 11-39. Pin Multiplexing Control 17 Register (PINMUX17) 31 PINMUX17_31_28 R/W-0 15 PINMUX17_15_12 R/W-0 12 11 PINMUX17_11_8 R/W-0 28 27 PINMUX17_27_24 R/W-0 8 7 PINMUX17_7_4 R/W-0 24 23 PINMUX17_23_20 R/W-0 4 3 PINMUX17_3_0 R/W-0 20 19 PINMUX17_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write.5. O = Output. Texas Instruments Incorporated 279 .ti.com SYSCFG Registers 11. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions Bit 31-28 Field PINMUX17_31_28 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX17_27_24 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 23-20 PINMUX17_23_20 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh (1) Value Description VP_DOUT[10]/LCD_D[10]/UPP_XD[2]/GP7[2]/BOOT[2] Control Selects Function BOOT[2] Selects Function VP_DOUT[10] Selects Function LCD_D[10] Reserved Selects Function UPP_XD[2] Reserved Selects Function GP7[2] Reserved VP_DOUT[11]/LCD_D[11]/UPP_XD[3]/GP7[3]/BOOT[3] Control Selects Function BOOT[3] Selects Function VP_DOUT[11] Selects Function LCD_D[11] Reserved Selects Function UPP_XD[3] Reserved Selects Function GP7[3] Reserved VP_DOUT[12]/LCD_D[12]/UPP_XD[4]/GP7[4]/BOOT[4] Control Selects Function BOOT[4] Selects Function VP_DOUT[12] Selects Function LCD_D[12] Reserved Selects Function UPP_XD[4] Reserved Selects Function GP7[4] Reserved Type I O I/O X I/O X I/O X I O I/O X I/O X I/O X I O I/O X I/O X I/O X (1) I = Input.18 Pin Multiplexing Control 17 Register (PINMUX17) Figure 11-35.

Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions (continued) Bit 19-16 Field PINMUX17_19_16 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 15-12 PINMUX17_15_12 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 11-8 PINMUX17_11_8 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX17_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX17_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description VP_DOUT[13]/LCD_D[13]/UPP_XD[5]/GP7[5]/BOOT[5] Control Selects Function BOOT[5] Selects Function VP_DOUT[13] Selects Function LCD_D[13] Reserved Selects Function UPP_XD[5] Reserved Selects Function GP7[5] Reserved VP_DOUT[14]/LCD_D[14]/UPP_XD[6]/GP7[6]/BOOT[6] Control Selects Function BOOT[6] Selects Function VP_DOUT[14] Selects Function LCD_D[14] Reserved Selects Function UPP_XD[6] Reserved Selects Function GP7[6] Reserved VP_DOUT[15]/LCD_D[15]/UPP_XD[7]/GP7[7]/BOOT[7] Control Selects Function BOOT[7] Selects Function VP_DOUT[15] Selects Function LCD_D[15] Reserved Selects Function UPP_XD[7] Reserved Selects Function GP7[7] Reserved VP_DOUT[0]/LCD_D[0]/UPP_XD[8]/GP7[8]/PRU1_R31[8] Control Selects Function PRU1_R31[8] Selects Function VP_DOUT[0] Selects Function LCD_D[0] Reserved Selects Function UPP_XD[8] Reserved Selects Function GP7[8] Reserved VP_DOUT[1]/LCD_D[1]/UPP_XD[9]/GP7[9]/PRU1_R31[9] Control Selects Function PRU1_R31[9] Selects Function VP_DOUT[1] Selects Function LCD_D[1] Reserved Selects Function UPP_XD[9] Reserved Selects Function GP7[9] Reserved I O I/O X I/O X I/O X I O I/O X I/O X I/O X I O I/O X I/O X I/O X I O I/O X I/O X I/O X I O I/O X I/O X I/O X Type (1) 280 System Configuration (SYSCFG) Module Copyright © 2011. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .ti.com Table 11-39.SYSCFG Registers www.

O = Output. -n = value after reset Table 11-40.ti.www.com SYSCFG Registers 11.19 Pin Multiplexing Control 18 Register (PINMUX18) Figure 11-36. X = Undefined. Texas Instruments Incorporated 281 . Pin Multiplexing Control 18 Register (PINMUX18) 31 PINMUX18_31_28 R/W-0 15 PINMUX18_15_12 R/W-0 12 11 PINMUX18_11_8 R/W-0 28 27 PINMUX18_27_24 R/W-0 8 7 PINMUX18_7_4 R/W-0 24 23 PINMUX18_23_20 R/W-0 4 3 PINMUX18_3_0 R/W-0 20 19 PINMUX18_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write. I/O = Bidirectional. Selects Function MMCSD1_DAT[7] Selects Function LCD_PCLK Reserved Selects Function PRU1_R30[7] Reserved Selects Function GP8[11] Reserved PRU0_R30[22]/PRU1_R30[8]/UPP_CHB_WAIT/GP8[12]/PRU1_R31[24] Control Selects Function PRU1_R31[24] Selects Function PRU0_R30[22] Selects Function PRU1_R30[8] Reserved Selects Function UPP_CHB_WAIT Reserved Selects Function GP8[12] Reserved Type I I/O O X O X I/O X Z I/O O X O X I/O X I O O X I/O X I/O X (1) I = Input. Z = High-impedance state SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.10.5. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions Bit 31-28 Field PINMUX18_31_28 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 27-24 PINMUX18_27_24 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 23-20 PINMUX18_23_20 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh (1) Value Description MMCSD1_DAT[6]/LCD_MCLK/PRU1_R30[6]/GP8[10]/PRU1_R31[7] Control Selects Function PRU1_R31[7] Selects Function MMCSD1_DAT[6] Selects Function LCD_MCLK Reserved Selects Function PRU1_R30[6] Reserved Selects Function GP8[10] Reserved MMCSD1_DAT[7]/LCD_PCLK/PRU1_R30[7]/GP8[11] Control Pin is 3-stated.

SYSCFG Registers www. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions (continued) Bit 19-16 Field PINMUX18_19_16 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 15-12 PINMUX18_15_12 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 11-8 PINMUX18_11_8 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX18_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX18_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description PRU0_R30[23]/MMCSD1_CMD/UPP_CHB_ENABLE/GP8[13]/PRU1_R31[25] Control Selects Function PRU1_R31[25] Selects Function PRU0_R30[23] Selects Function MMCSD1_CMD Reserved Selects Function UPP_CHB_ENABLE Reserved Selects Function GP8[13] Reserved PRU0_R30[24]/MMCSD1_CLK/UPP_CHB_START/GP8[14]/PRU1_R31[26] Control Selects Function PRU1_R31[26] Selects Function PRU0_R30[24] Selects Function MMCSD1_CLK Reserved Selects Function UPP_CHB_START Reserved Selects Function GP8[14] Reserved PRU0_R30[25]/MMCSD1_DAT[0]/UPP_CHB_CLOCK/GP8[15]/PRU1_R31[27] Control Selects Function PRU1_R31[27] Selects Function PRU0_R30[25] Selects Function MMCSD1_DAT[0] Reserved Selects Function UPP_CHB_CLOCK Reserved Selects Function GP8[15] Reserved VP_DOUT[8]/LCD_D[8]/UPP_XD[0]/GP7[0]/BOOT[0] Control Selects Function BOOT[0] Selects Function VP_DOUT[8] Selects Function LCD_D[8] Reserved Selects Function UPP_XD[0] Reserved Selects Function GP7[0] Reserved VP_DOUT[9]/LCD_D[9]/UPP_XD[1]/GP7[1]/BOOT[1] Control Selects Function BOOT[1] Selects Function VP_DOUT[9] Selects Function LCD_D[9] Reserved Selects Function UPP_XD[1] Reserved Selects Function GP7[1] Reserved I O I/O X I/O X I/O X I O I/O X I/O X I/O X I O I/O X I/O X I/O X I O O X I/O X I/O X I O I/O X I/O X I/O X Type (1) 282 System Configuration (SYSCFG) Module Copyright © 2011.ti. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .com Table 11-40.

Pin Multiplexing Control 19 Register (PINMUX19) 31 PINMUX19_31_28 R/W-0 15 PINMUX19_15_12 R/W-0 12 11 PINMUX19_11_8 R/W-0 28 27 PINMUX19_27_24 R/W-0 8 7 PINMUX19_7_4 R/W-0 24 23 PINMUX19_23_20 R/W-0 4 3 PINMUX19_3_0 R/W-0 20 19 PINMUX19_19_16 R/W-0 0 16 LEGEND: R/W = Read/Write. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions Bit 31-28 Field PINMUX19_31_28 0 1h 2h-7h 8h 9h-Fh 27-24 PINMUX19_27_24 0 1h 2h 3h-7h 8h 9h-Fh 23-20 PINMUX19_23_20 0 1h 2h-3h 4h 5h-7h 8h 9h-Fh 19-16 PINMUX19_19_16 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description RTCK/GP8[0] Control Selects Function RTCK Selects Function RTCK Reserved Selects Function GP8[0] Reserved LCD_AC_ENB_CS/GP6[0]/PRU1_R31[28] Control Selects Function PRU1_R31[28] Reserved Selects Function LCD_AC_ENB_CS Reserved Selects Function GP6[0] Reserved VP_CLKOUT3/PRU1_R30[0]/GP6[1]/PRU1_R31[1] Control Selects Function PRU1_R31[1] Selects Function VP_CLKOUT3 Reserved Selects Function PRU1_R30[0] Reserved Selects Function GP6[1] Reserved VP_CLKIN3/MMCSD1_DAT[1]/PRU1_R30[1]/GP6[2]/PRU1_R31[2] Control Selects Function PRU1_R31[2] Selects Function VP_CLKIN3 Selects Function MMCSD1_DAT[1] Reserved Selects Function PRU1_R30[1] Reserved Selects Function GP6[2] Reserved I I I/O X O X I/O X I O X O X I/O X I X O X I/O X O O X I/O X Type (1) (1) I = Input. O = Output.10.ti. I/O = Bidirectional.5.20 Pin Multiplexing Control 19 Register (PINMUX19) Figure 11-37. -n = value after reset Table 11-41.com SYSCFG Registers 11. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback 283 .www. X = Undefined System Configuration (SYSCFG) Module Copyright © 2011.

com Table 11-41. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions (continued) Bit 15-12 Field PINMUX19_15_12 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 11-8 PINMUX19_11_8 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 7-4 PINMUX19_7_4 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh 3-0 PINMUX19_3_0 0 1h 2h 3h 4h 5h-7h 8h 9h-Fh Value Description VP_CLKOUT2/MMCSD1_DAT[2]/PRU1_R30[2]/GP6[3]/PRU1_R31[3] Control Selects Function PRU1_R31[3] Selects Function VP_CLKOUT2 Selects Function MMCSD1_DAT[2] Reserved Selects Function PRU1_R30[2] Reserved Selects Function GP6[3] Reserved VP_CLKIN2/MMCSD1_DAT[3]/PRU1_R30[3]/GP6[4]/PRU1_R31[4] Control Selects Function PRU1_R31[4] Selects Function VP_CLKIN2 Selects Function MMCSD1_DAT[3] Reserved Selects Function PRU1_R30[3] Reserved Selects Function GP6[4] Reserved MMCSD1_DAT[4]/LCD_VSYNC/PRU1_R30[4]/GP8[8]/PRU1_R31[5] Control Selects Function PRU1_R31[5] Selects Function MMCSD1_DAT[4] Selects Function LCD_VSYNC Reserved Selects Function PRU1_R30[4] Reserved Selects Function GP8[8] Reserved MMCSD1_DAT[5]/LCD_HSYNC/PRU1_R30[5]/GP8[9]/PRU1_R31[6] Control Selects Function PRU1_R31[6] Selects Function MMCSD1_DAT[5] Selects Function LCD_HSYNC Reserved Selects Function PRU1_R30[5] Reserved Selects Function GP8[9] Reserved I I/O O X O X I/O X I I/O O X O X I/O X I I I/O X O X I/O X I O I/O X O X I/O X Type (1) 284 System Configuration (SYSCFG) Module Copyright © 2011.ti. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .SYSCFG Registers www.

ARM is the source of the emulation suspend.11 Suspend Source Register (SUSPSRC) The suspend source register (SUSPSRC) indicates the emulation suspend source for those peripherals that support emulation suspend. etc. The SUSPSRC is shown in Figure 11-38 and described in Table 11-42. You should maintain this register with its default values. -n = value after reset Table 11-42. SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Suspend Source Register (SUSPSRC) 31 Reserved 30 Reserved 29 TIMER64P_2SRC 28 TIMER64P_1SRC 27 TIMER64P_0SRC 26 Reserved 25 Reserved 24 EPWM1SRC R/W-1 23 EPWM0SRC R/W-1 22 SPI1SRC R/W-1 21 SPI0SRC R/W-1 20 UART2SRC R/W-1 19 UART1SRC R/W-1 18 UART0SRC R/W-1 17 I2C1SRC R/W-1 16 I2C0SRC R/W-1 15 Reserved R/W-1 14 VPIFSRC R/W-1 13 SATASRC R/W-1 12 HPISRC R/W-1 11 Reserved R/W-1 10 Reserved R/W-1 9 USB0SRC R/W-1 8 MCBSP1SRC R/W-1 7 MCBSP0SRC R/W-1 6 PRUSRC R/W-1 5 EMACSRC R/W-1 4 UPPSRC R/W-1 3 TIMER64P_3SRC R/W-1 2 ECAP2SRC R/W-1 1 ECAP1SRC R/W-1 0 ECAP0SRC R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 LEGEND: R/W = Read/Write. DSP is the source of the emulation suspend. ARM is the source of the emulation suspend. The flexibility of the device architecture allows either the ARM or the DSP to control the various peripherals (setup registers. A value of 1 (default) for a SUSPSRC bit corresponding to the peripheral.).com SYSCFG Registers 11. Timer0 64 Emulation Suspend Source. so that only those modules receive the suspend signal. DSP is the source of the emulation suspend.5. the device must know which peripherals are associated with the halting processor. Timer1 64 Emulation Suspend Source. DSP is the source of the emulation suspend. ARM is the source of the emulation suspend. indicates that the DSP emulator controls the peripheral's emulation suspend signal. Figure 11-38. DSP is the source of the emulation suspend. Write the default value to all bits when modifying this register. service interrupts. Write the default value to all bits when modifying this register.www. This allows peripherals associated with the other (unhalted) processor to continue normal operation. ARM is the source of the emulation suspend. during an emulation halt. DSP is the source of the emulation suspend. EPWM1 Emulation Suspend Source. EPWM0 Emulation Suspend Source. Suspend Source Register (SUSPSRC) Field Descriptions Bit 31-30 29 Field Reserved TIMER64P_2SRC 0 1 28 TIMER64P_1SRC 0 1 27 TIMER64P_0SRC 0 1 26-25 24 Reserved EPWM1SRC 0 1 23 EPWM0SRC 0 1 22 SPI1SRC 0 1 1 Value 1 Description Reserved. Texas Instruments Incorporated 285 . Timer2 64 Emulation Suspend Source.ti. DSP is the source of the emulation suspend. ARM is the source of the emulation suspend. SPI1 Emulation Suspend Source. ARM is the source of the emulation suspend. Reserved. While this assignment is a matter of software convention.

ARM is the source of the emulation suspend. DSP is the source of the emulation suspend. ARM is the source of the emulation suspend. PRU Emulation Suspend Source. UART2 Emulation Suspend Source. DSP is the source of the emulation suspend. DSP is the source of the emulation suspend. McBSP1 Emulation Suspend Source. ARM is the source of the emulation suspend. DSP is the source of the emulation suspend. DSP is the source of the emulation suspend. I2C0 Emulation Suspend Source. ARM is the source of the emulation suspend. ARM is the source of the emulation suspend. DSP is the source of the emulation suspend. ARM is the source of the emulation suspend. ARM is the source of the emulation suspend. DSP is the source of the emulation suspend. ARM is the source of the emulation suspend. VPIF Emulation Suspend Source. DSP is the source of the emulation suspend. ARM is the source of the emulation suspend. Write the default value to all bits when modifying this register. UART0 Emulation Suspend Source. DSP is the source of the emulation suspend.ti. ARM is the source of the emulation suspend. DSP is the source of the emulation suspend. ARM is the source of the emulation suspend.SYSCFG Registers www. McBSP0 Emulation Suspend Source. HPI Emulation Suspend Source.0) Emulation Suspend Source. Reserved. uPP Emulation Suspend Source. DSP is the source of the emulation suspend. Reserved. UART1 Emulation Suspend Source. DSP is the source of the emulation suspend. USB0 (USB 2. DSP is the source of the emulation suspend. DSP is the source of the emulation suspend. ARM is the source of the emulation suspend. SATA Emulation Suspend Source. EMAC Emulation Suspend Source. DSP is the source of the emulation suspend. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . I2C1 Emulation Suspend Source.com Table 11-42. ARM is the source of the emulation suspend. ARM is the source of the emulation suspend. ARM is the source of the emulation suspend. Suspend Source Register (SUSPSRC) Field Descriptions (continued) Bit 21 Field SPI0SRC 0 1 20 UART2SRC 0 1 19 UART1SRC 0 1 18 UART0SRC 0 1 17 I2C1SRC 0 1 16 I2C0SRC 0 1 15 14 Reserved VPIFSRC 0 1 13 SATASRC 0 1 12 HPISRC 0 1 11-10 9 Reserved USB0SRC 0 1 8 MCBSP1SRC 0 1 7 MCBSP0SRC 0 1 6 PRUSRC 0 1 5 EMACSRC 0 1 4 UPPSRC 0 1 1 1 Value Description SPI0 Emulation Suspend Source. 286 System Configuration (SYSCFG) Module Copyright © 2011. Write the default value to all bits when modifying this register.

ECAP2 Emulation Suspend Source. ARM is the source of the emulation suspend.com SYSCFG Registers Table 11-42. DSP is the source of the emulation suspend. ARM is the source of the emulation suspend. DSP is the source of the emulation suspend. ARM is the source of the emulation suspend.www. SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. ECAP1 Emulation Suspend Source. ARM is the source of the emulation suspend. DSP is the source of the emulation suspend. Texas Instruments Incorporated 287 . Suspend Source Register (SUSPSRC) Field Descriptions (continued) Bit 3 Field TIMER64P_3SRC 0 1 2 ECAP2SRC 0 1 1 ECAP1SRC 0 1 0 ECAP0SRC 0 1 Value Description Timer3 64 Emulation Suspend Source. DSP is the source of the emulation suspend. ECAP0 Emulation Suspend Source.ti.

Writing a 1 to these bits sets the interrupts. No effect Asserts interrupt Asserts SYSCFG_CHIPINT2 interrupt. No effect Asserts interrupt Asserts SYSCFG_CHIPINT0 interrupt. and NMI.ti. The DSP may generate an interrupt to the ARM by setting one of the four CHIPSIG[3-0] bits. Chip Signal Register (CHIPSIG) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write. so that it can be used as debug interrupts. these are additionally mapped to the ARM interrupt controller (AINTC). Figure 11-39. The ARM has access to 3 DSP interrupt events in the DSP interrupt event map: SYSCFG_CHIPINT2. and SYSCFG_CHIPINT3. The CHIPSIG is shown in Figure 11-39 and described in Table 11-43. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . No effect Asserts interrupt Asserts SYSCFG_CHIPINT1 interrupt. R = Read only. No effect Asserts interrupt 288 System Configuration (SYSCFG) Module Copyright © 2011.12 Chip Signal Register (CHIPSIG) The DSP has access to 4 ARM interrupt events in the ARM interrupt map: SYSCFG_CHIPINT0.com 11. Chip Signal Register (CHIPSIG) Field Descriptions Bit 31-5 4 Field Reserved CHIPSIG4 0 1 3 CHIPSIG3 0 1 2 CHIPSIG2 0 1 1 CHIPSIG1 0 1 0 CHIPSIG0 0 1 Value 0 Description Reserved Asserts DSP NMI interrupt. However. in case there is a need to halt both processors simultaneously. No effect Asserts interrupt Asserts SYSCFG_CHIPINT3 interrupt. The ARM may generate an interrupt to the DSP by setting one of the two CHIPSIG[3-2] bits or an NMI interrupt by setting the CHIPSIG[4] bit in the chip signal register (CHIPSIG). -n = value after reset 5 4 R/W-0 3 R/W-0 2 R/W-0 1 R/W-0 0 CHIPSIG0 R/W-0 16 CHIPSIG4 CHIPSIG3 CHIPSIG2 CHIPSIG1 Table 11-43. NOTE: SYSCFG_CHIPINT2 and SYSCFG_CHIPINT3 are essentially for the ARM to interrupt the DSP.5. Reads return the value of these bits and can also be used as status bits. SYSCFG_CHIPINT3. SYSCFG_CHIPINT1.SYSCFG Registers www. SYSCFG_CHIPINT2. writing a 0 has no effect.

the interrupted processor can clear the bits set in CHIPSIG by writing 1 to the corresponding bits in CHIPSIG_CLR. For more information on ARM interrupts. Texas Instruments Incorporated 289 . The other processor may poll the CHIPSIG[n] bit to determine when the interrupted processor has completed the interrupt service. No effect Clears interrupt SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. writing a 0 has no effect.ti.5.www. After servicing the interrupt. No effect Clears interrupt Clears SYSCFG_CHIPINT1 interrupt. No effect Clears interrupt Clears SYSCFG_CHIPINT2 interrupt. -n = value after reset 5 4 R/W-0 3 R/W-0 2 R/W-0 1 R/W-0 0 CHIPSIG0 R/W-0 16 CHIPSIG4 CHIPSIG3 CHIPSIG2 CHIPSIG1 Table 11-44. No effect Clears interrupt Clears SYSCFG_CHIPINT3 interrupt.com SYSCFG Registers 11. see the ARM Interrupt Controller (AINTC) chapter. Chip Signal Clear Register (CHIPSIG_CLR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write. Writing a 1 to a CHIPSIG[n] bit in CHIPSIG_CLR clears the corresponding CHIPSIG[n] bit in CHIPSIG.13 Chip Signal Clear Register (CHIPSIG_CLR) The chip signal clear register (CHIPSIG_CLR) is used to clear the bits set in the chip signal register (CHIPSIG). Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions Bit 31-5 4 Field Reserved CHIPSIG4 0 1 3 CHIPSIG3 0 1 2 CHIPSIG2 0 1 1 CHIPSIG1 0 1 0 CHIPSIG0 0 1 Value 0 Description Reserved Clears DSP NMI interrupt. The CHIPSIG_CLR is shown in Figure 11-40 and described in Table 11-44. No effect Clears interrupt Clears SYSCFG_CHIPINT0 interrupt. For more information on DSP interrupts. Figure 11-40. R = Read only. see the DSP Subsystem chapter.

-n = value after reset 5 4 PLL_MASTER_LOCK R/W-0 3 R/W-0 2 1 R/W-0 0 16 EDMA30TC1DBS EDMA30TC0DBS Table 11-45. EDMA3_0_TC1 Default Burst Size (DBS). it also facilitates preemption at a system level. each master’s priority (configured by the MSTPRI register) is evaluated at burst size boundaries. etc. By default for all transfer controllers. The burst size determines the intra packet efficiency for the EDMA3_0 transfers. the burst size is set to 16 bytes. The CFGCHIP0 is shown in Figure 11-41 and described in Table 11-45. The DBS value can significantly impact the standalone throughput performance depending on the source and destination (bus width/frequency/burst support etc) and the TC FIFO size.com 11. Figure 11-41. 16 bytes 32 bytes 64 bytes Reserved 290 System Configuration (SYSCFG) Module Copyright © 2011.SYSCFG Registers www. Chip Configuration 0 Register (CFGCHIP0) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write. the DBS size configuration should be carefully analyzed to meet the system’s throughput/performance requirements. Chip Configuration 0 Register (CFGCHIP0) Field Descriptions Bit 31-5 4 Field Reserved PLL_MASTER_LOCK 0 1 3-2 EDMA30TC1DBS 0 1h 2h 3h 1-0 EDMA30TC0DBS 0 1h 2h 3h Value 0 Description Reserved. 16 bytes 32 bytes 64 bytes Reserved EDMA3_0_TC0 Default Burst Size (DBS). All PLLC0 MMRs are locked.ti. or 64 bytes. Therefore. 32.5. as all transfer requests are internally broken down by the transfer controller up to DBS size byte chunks and on a system level.14 Chip Configuration 0 Register (CFGCHIP0) The chip configuration 0 register (CFGCHIP0) controls the following functions: • PLL Controller 0 memory-mapped register lock: Used to lock out writes to the PLLC0 memory-mapped registers (MMRs) to prevent any erroneous writes in software to the PLLC0 register space. Additionally. CFGCHIP0 allows configurability of this parameter so that the TC can have a burst size of 16. PLLC0 MMRs are freely accessible. PLLC0 MMRs lock. R = Read only. However. • EDMA3_0 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on the device. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

• eHRPWM Time Base Clock (TBCLK) Synchronization: Allows the software to globally synchronize all enabled eHRPWM modules to the time base clock (TBCLK). the DBS size configuration should be carefully analyzed to meet the system’s throughput/performance requirements. R = Read only. etc. Chip Configuration 1 Register (CFGCHIP1) 31 CAP2SRC R/W-0 15 HPIENA R/W-0 7 Reserved R/W-0 LEGEND: R/W = Read/Write. the burst size is set to 16 bytes. • McASP0 AMUTEIN signal source control: Allows selecting GPIO interrupt from different banks as source for the McASP0 AMUTEIN signal. • EDMA3_1 Transfer Controller Default Burst Size (DBS) Control: This controls the maximum number of bytes issued per read/write command or the burst size for the individual transfer controllers (TCs) on the device.15 Chip Configuration 1 Register (CFGCHIP1) The chip configuration 1 register (CFGCHIP1) controls the following functions: • eCAP0/1/2 event input source: Allows using McASP0 TX/RX events or various EMAC TX/RX threshold. Therefore. However.www.5. it also facilitates preemption at a system level.com SYSCFG Registers 11. • HPI Control: Allows HPIEN bit control that determines whether or not the HPI module has control over the HPI pins (multiplexed with other peripheral pins).ti. Figure 11-42. The CFGCHIP1 is shown in Figure 11-42 and described in Table 11-46. Additionally. 32. It also provides configurability to select whether the host address is a word address or a byte address mode. as all transfer requests are internally broken down by the transfer controller up to DBS size byte chunks and on a system level. pulse. The DBS value can significantly impact the standalone throughput performance depending on the source and destination (bus width/frequency/burst support etc) and the TC FIFO size. -n = value after reset 14 R/W-0 13 27 26 CAP1SRC R/W-0 12 TBCLKSYNC R/W-0 4 3 AMUTESEL0 R/W-0 11 Reserved R/W-0 0 22 21 CAP0SRC R/W-0 17 16 HPIBYTEAD R/W-0 8 EDMA31TC0DBS SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Texas Instruments Incorporated 291 . each master’s priority (configured by the MSTPRI register) is evaluated at burst size boundaries. By default for all transfer controllers. or miscellaneous interrupt events as eCAP event input sources. CFGCHIP1 allows configurability of this parameter so that the TC can have a burst size of 16. or 64 bytes. The burst size determines the intra packet efficiency for the EDMA3_1 transfers.

ti. eCAP2 Pin input McASP0 TX DMA Event McASP0 RX DMA Event Reserved EMAC C0 RX Threshold Pulse Interrupt EMAC C0 RX Pulse Interrupt EMAC C0 TX Pulse Interrupt EMAC C0 Miscellaneous Interrupt EMAC C1 RX Threshold Pulse Interrupt EMAC C1 RX Pulse Interrupt EMAC C1 TX Pulse Interrupt EMAC C1 Miscellaneous Interrupt EMAC C2 RX Threshold Pulse Interrupt EMAC C2 RX Pulse Interrupt EMAC C2 TX Pulse Interrupt EMAC C2 Miscellaneous Interrupt Reserved Selects the eCAP1 module event input. eCAP1 Pin input McASP0 TX DMA Event McASP0 RX DMA Event Reserved EMAC C0 RX Threshold Pulse Interrupt EMAC C0 RX Pulse Interrupt EMAC C0 TX Pulse Interrupt EMAC C0 Miscellaneous Interrupt EMAC C1 RX Threshold Pulse Interrupt EMAC C1 RX Pulse Interrupt EMAC C1 TX Pulse Interrupt EMAC C1 Miscellaneous Interrupt EMAC C2 RX Threshold Pulse Interrupt EMAC C2 RX Pulse Interrupt EMAC C2 TX Pulse Interrupt EMAC C2 Miscellaneous Interrupt Reserved 292 System Configuration (SYSCFG) Module Copyright © 2011.com Table 11-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions Bit 31-27 Field CAP2SRC 0 1h 2h 3h-6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h-1Fh 26-22 CAP1SRC 0 1h 2h 3h-6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h-1Fh Value Description Selects the eCAP2 module event input. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .SYSCFG Registers www.

Time base clock (TBCLK) within each enabled eHRPWM module is stopped. 16 bytes 32 bytes 64 bytes Reserved eHRPWM Module Time Base Clock Synchronization. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions (continued) Bit 21-17 Field CAP0SRC 0 1h 2h 3h-6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h-1Fh 16 HPIBYTEAD 0 1 15 HPIENA 0 1 14-13 EDMA31TC0DBS 0 1h 2h 3h 12 TBCLKSYNC 0 1 Value Description Selects the eCAP0 module event input. All enabled eHRPWM module clocks are started with the first rising edge of TBCLK aligned. HPI is disabled. HPI Enable Bit. Host address is a byte address. the prescaler bits in the TBCTL register of each eHRPWM module must be set identically. Write the default value to all bits when modifying this register. Reserved.ti. GPIO Interrupt from Bank 0 GPIO Interrupt from Bank 1 GPIO Interrupt from Bank 2 GPIO Interrupt from Bank 3 GPIO Interrupt from Bank 4 GPIO Interrupt from Bank 5 GPIO Interrupt from Bank 6 GPIO Interrupt from Bank 7 Reserved 11-4 3-0 Reserved AMUTESEL0 0 SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.www. Selects the source of McASP0 AMUTEIN signal. eCAP0 Pin input McASP0 TX DMA Event McASP0 RX DMA Event Reserved EMAC C0 RX Threshold Pulse Interrupt EMAC C0 RX Pulse Interrupt EMAC C0 TX Pulse Interrupt EMAC C0 Miscellaneous Interrupt EMAC C1 RX Threshold Pulse Interrupt EMAC C1 RX Pulse Interrupt EMAC C1 TX Pulse Interrupt EMAC C1 Miscellaneous Interrupt EMAC C2 RX Threshold Pulse Interrupt EMAC C2 RX Pulse Interrupt EMAC C2 TX Pulse Interrupt EMAC C2 Miscellaneous Interrupt Reserved HPI Byte/Word Address Mode select.com SYSCFG Registers Table 11-46. Allows you to globally synchronize all enabled eHRPWM modules to the time base clock (TBCLK). Host address is a word address. Texas Instruments Incorporated 293 . For perfectly synchronized TBCLKs. 0 1h 2h 3h 4h 5h 6h 7h 8h 9h-Fh Drive McASP0 AMUTEIN signal low. HPI is enabled. EDMA3_1_TC0 Default Burst Size.

USB2. Clock is not present. Clock is present. PHY drive signals to controller based on its comparators for VBUS and ID pins.0 PHY in reset.1 PHY reference clock input mux. Override phy values to force USB host operation with VBUS low.0 PHY reset. and PLL has not locked.0 PHY is disabled and powered down. USB1. -n = value after reset Table 11-47.16 Chip Configuration 2 Register (CFGCHIP2) The chip configuration 2 register (CFGCHIP2) controls the following functions: • USB1.0 PHY reference clock input mux. USB1. PHY is sensing voltage presence on the VBUS pin. 294 System Configuration (SYSCFG) Module Copyright © 2011.0 PHY operation state control.1 PHY reference clock is sourced by output of USB2.5. Status of USB2. Controls clock mux to USB1. USB2.1 PHY reference clock (USB_REFCLKIN) is sourced by an external pin. USB2.1 OHCI • USB2. PHY is not sensing voltage presence on the VBUS pin. Override phy values to force USB host operation. USB2. Override phy values to force USB device operation. No override. Figure 11-43.0 PHY. Chip Configuration 2 Register (CFGCHIP2) 31 Reserved 24 R-0 23 Reserved 18 R-0 17 USB0PHYCLKGD 16 USB0VBUSSENSE R-0 12 11 USB0PHYCLKMUX R-0 8 USB0DATPOL 15 RESET 14 USB0OTGMODE 13 R/W-3h 10 USB0PHYPWDN 9 USB0OTGPWRDN USB1PHYCLKMUX R/W-1 7 USB1SUSPENDM R/W-0 5 4 USB0VBDTCTEN R/W-1 3 R/W-1 R/W-1 R/W-1 0 6 USB0PHY_PLLON USB0SESNDEN USB0REF_FREQ R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write.ti. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .0 OTG PHY The CFGCHIP2 is shown in Figure 11-43 and described in Table 11-47. Not in reset. power is not good.0 PHY reference clock (USB_REFCLKIN) is sourced by an external pin.0 PHY reference clock (AUXCLK) is internally generated from the PLL. USB2. R = Read only. USB2.0 PHY is enabled and is in operating state (normal operation). Chip Configuration 2 Register (CFGCHIP2) Field Descriptions Bit 31-18 17 Field Reserved USB0PHYCLKGD 0 1 16 USB0VBUSSENSE 0 1 15 RESET 0 1 14-13 USB0OTGMODE 0 1h 2h 3h 12 USB1PHYCLKMUX 0 1 11 USB0PHYCLKMUX 0 1 10 USB0PHYPWDN 0 1 Value 0 Description Reserved Status of USB2. USB2. USB2. and PLL has locked. power is good. USB1. USB2.0 PHY.0 OTG subsystem mode.com 11.0 PHY VBUS sense.1.SYSCFG Registers www.

Differential data polarity are not altered (USB_DP is connected to D+ and USB_DM is connected to D-). All VBUS line comparators are disabled. Reserved 12 MHz 24 MHz 48 MHz 19.0 differential data lines polarity selector. allowing or preventing it from stopping the 48 MHz clock during USB SUSPEND. USB2.ti.com SYSCFG Registers Table 11-47. Session End comparator is enabled.0 OTG subsystem (SS) operation state control. Enable USB1. OTG SS is disabled and is powered down.www.1 PHY is unpowered.1 PHY. Texas Instruments Incorporated 295 . Needs to be 0 whenever USB1.2 MHz 38. OTG SS is enabled and is in operating state (normal operation). USB1. Differential data polarities are inverted (USB_DP is connected to D. USB2.1 suspend mode. USB2. Session End comparator is disabled. Drives USB2.and USB_DM is connected to D+).0 PHY reference clock input frequencies.0 PHY. All VBUS line comparators are enabled. USB2.4 MHz 13 MHz 26 MHz 20 MHz 40 MHz Reserved SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions (continued) Bit 9 Field USB0OTGPWRDN 0 1 8 USB0DATPOL 0 1 7 USB1SUSPENDM 0 1 6 USB0PHY_PLLON 0 1 5 USB0SESNDEN 0 1 4 USB0VBDTCTEN 0 1 3-0 USB0REF_FREQ 0 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah-Fh Value Description USB2.0 PHY is allowed to stop the 48 MHz clock during USB SUSPEND.0 Session End comparator enable.0 PHY is prevented from stopping the 48 MHz clock during USB SUSPEND USB2.0 VBUS line comparators enable. USB2.

• ASYNC3 Clock Source Control: Allows control for the source of the ASYNC3 clock. Clock source for uPP 2x transmit clock. All PLLC1 MMRs are locked. Clock driven by PLL0_SYSCLK2. EMAC MII/RMII mode select.SYSCFG Registers www. • DIV4p5 Clock Enable/Disable: The DIV4p5 (/4.ti. • EMIFA Module Clock Source Control: Allows control for the source of the EMIFA module clock. Normal mode Alternate mode 296 System Configuration (SYSCFG) Module Copyright © 2011.5. • uPP Clock Source Control: Allows control for the source of the uPP 2x transmit clock.17 Chip Configuration 3 Register (CFGCHIP3) The chip configuration 3 register (CFGCHIP3) controls the following peripheral/module functions: • EMAC MII/RMII Mode Select. Clock driven by ASYNC3. R = Read only. PLLC1 MMRs lock. • PRU Event Input Select. Write the default value to all bits when modifying this register. Clock driven by PLL1_SYSCLK2. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions Bit 31-16 15-9 8 Field Reserved Reserved RMII_SEL 0 1 7 6 Reserved UPP_TX_CLKSRC 0 1 5 PLL1_MASTER_LOCK 0 1 4 ASYNC3_CLKSRC 0 1 3 PRUEVTSEL 0 1 0 Value 0 7Fh Description Reserved Reserved. -n = value after reset Table 11-48. • PLL Controller 1 memory-mapped register lock: Used to lock out writes to the PLLC1 memory-mapped registers (MMRs) to prevent any erroneous writes in software to the PLLC1 register space. PRU event input select. Write the default value when modifying this register. Clock source for ASYNC3.com 11. Clock driven by external signal. 2xTXCLK. PLLC1 MMRs are freely accessible. Chip Configuration 3 Register (CFGCHIP3) 31 Reserved R-0 15 Reserved R/W-7Fh 7 Reserved 16 9 8 RMII_SEL R/W-1 6 UPP_TX_CLKSRC 5 PLL1_MASTER_LOCK 4 ASYNC3_CLKSRC 3 PRUEVTSEL 2 DIV45PENA 1 EMA_CLKSRC 0 Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write. MII mode RMII mode Reserved.5) hardware clock divider is provided to generate 133 MHz from the 600 MHz PLL clock for use as clocks to the EMIFs. Allows enabling/disabling this clock divider. Figure 11-44. The CFGCHIP3 is shown in Figure 11-44 and described in Table 11-48. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

5. Write the default value when modifying this register. Clears the latched GPIO interrupt for AMUTEIN of McASP0 when set to 1. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions Bit 31-16 15-8 7-1 0 Field Reserved Reserved Reserved AMUTECLR0 0 1 Value 0 FFh 0 Description Reserved Reserved. 11. Chip Configuration 4 Register (CFGCHIP4) 31 Reserved R-0 15 Reserved R/W-FFh LEGEND: R/W = Read/Write. reads always return a value of 0. R = Read only. Clock driven by PLL0_SYSCLK3 Clock driven by DIV4. Divide by 4. Texas Instruments Incorporated 297 . -n = value after reset 8 7 Reserved R/W-0 1 0 AMUTECLR0 R/W-0 16 Table 11-49. The CFGCHIP4 is shown in Figure 11-45 and described in Table 11-49. Clock source for EMIFA clock domain. if it was previously set. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions (continued) Bit 2 Field DIV45PENA 0 1 1 EMA_CLKSRC 0 1 0 Reserved 0 Value Description Controls the fixed DIV4.5 PLL output Reserved.5 is enabled.18 Chip Configuration 4 Register (CFGCHIP4) The chip configuration 4 register (CFGCHIP4) is used for clearing the AMUNTEIN signal for McASP0. Write the default value to all bits when modifying this register. Reserved. Divide by 4.ti.5 is disabled. Write the default value to all bits when modifying this register. Figure 11-45.5 divider in the PLL controller. Writing a 1 causes a single pulse that clears the latched GPIO interrupt for AMUTEIN of McASP0.com SYSCFG Registers Table 11-48. No effect Clears interrupt SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011.www.

The PWRSAVE bit setting is only valid when the POWERDN bit is cleared to 0.com 11. and process information is used to control the IO's output impedance. R = Read only. Connected to pad. Unlock impedance.ti. VTP impedance lock. Reserved. The PWRSAVE bit setting is only valid when the POWERDN bit is cleared to 0. external reference. Turn off power to the external resistor when it is not needed. temperature. VTP I/O Control Register (VTPIO_CTL) Field Descriptions Bit 31-19 18 Field Reserved VREFEN 0 1 17-16 VREFTAP 0 1h-3h 15 READY 0 1 14 IOPWRDN 0 1 13 12-9 8 CLKRZ Reserved PWRSAVE 0 1 7 LOCK 0 1 6 POWERDN 0 1 0 0 Value 0 Description Reserved Internal DDR I/O Vref enable.SYSCFG Registers www. VTP power save mode. The VTPIO_CTL is shown in Figure 11-46 and described in Table 11-50. temperature. and process (VTP).0% of VDDS Reserved VTP Ready status. Enable power down. Write the default value to all bits when modifying this register. VTP power down. Disable power save mode. 298 System Configuration (SYSCFG) Module Copyright © 2011. Lock impedance. Power down the VTP controller.19 VTP I/O Control Register (VTPIO_CTL) The VTP I/O control register (VTPIO_CTL) is used to control the calibration of the DDR2/mDDR memory controller I/Os with respect to voltage. VTP is not ready. VTP clear. The voltage. Lock impedance value so that the VTP controller can be powered down. Disable power down control by the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R). VTP is ready. Figure 11-46. Power down enable for DDR input buffer.5. Enable power save mode. Write 0 to clear VTP flops. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Reserved Selection for internal reference voltage level. -n = value after reset Table 11-50. VTP I/O Control Register (VTPIO_CTL) 31 Reserved R-0 23 Reserved R-0 15 READY R-0 7 LOCK R/W-0 14 IOPWRDN R/W-0 6 POWERDN R/W-1 13 CLKRZ R/W-0 5 D R/W-6h 3 12 Reserved R/W-0 2 F R/W-7h 19 18 VREFEN R/W-0 9 17 VREFTAP R/W-0 8 PWRSAVE R/W-0 0 16 24 LEGEND: R/W = Read/Write. Disable power down. Vref = 50. Enable power down control by the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R).

Reserved Digital filter is enabled. SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Reserved 100% drive strength Reserved Digital filter control bit.com SYSCFG Registers Table 11-50.www. Texas Instruments Incorporated 299 . VTP I/O Control Register (VTPIO_CTL) Field Descriptions (continued) Bit 5-3 Field D 0-5h 6h 7h 2-0 F 0-6h 7h Value Description Drive strength control bit.ti.

Slew rate control is not supported on this device. -n = value after reset Table 11-51. Select LVCMOS when using mDDR. Select SSTL when using DDR2. The DDR_SLEW is shown in Figure 11-47 and described in Table 11-51. LVCMOS Receiver. DDR Slew Register (DDR_SLEW) 31 Reserved R-0 15 Reserved R-0 7 Reserved R-0 6 5 DDR_PDENA R/W-0 4 CMOSEN R/W-0 3 R-0 12 11 R/W-0 2 1 R-0 10 9 R/W-0 0 8 16 ODT_TERMON ODT_TERMOFF DDR_DATASLEW DDR_CMDSLEW LEGEND: R/W = Read/Write. Termination is not supported on this device. Slew rate control is not supported on this device. SSTL Receiver. Disable pull downs when using DDR2.ti. Enable pull downs when using mDDR. Termination is not supported on this device. Reserved Slew rate mode control status for command macro. No termination Reserved Controls Thevenin termination mode while I/O is not in read or write mode. The CMOSEN field configures the DDR I/O cells into an LVCMOS buffer (this makes it mDDR compatible). Selects mDDR LVCMOS RX / SSTL18 differential RX. DDR Slew Register (DDR_SLEW) Field Descriptions Bit 31-12 11-10 Field Reserved ODT_TERMON 0 1h-3h 9-8 ODT_TERMOFF 0 1h-3h 7-6 5 Reserved DDR_PDENA 0 1 4 CMOSEN 0 1 3-2 DDR_DATASLEW 0 1h-3h 1-0 DDR_CMDSLEW 0 1h-3h 0 Value 0 Description Reserved Controls Thevenin termination mode while I/O is in read or write mode. Reserved 300 System Configuration (SYSCFG) Module Copyright © 2011. Slew rate control is off.com 11.5. Figure 11-47. R = Read only. Slew rate control is off. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .20 DDR Slew Register (DDR_SLEW) The DDR slew register (DDR_SLEW) reflects the DDR I/O timing as programmed in the device eFuse. No termination Reserved Reserved Enables pull downs for mDDR mode (should be disabled for DDR2). Pull downs are disabled. Pull downs are enabled.SYSCFG Registers www. Slew rate mode control status for data macro.

21 Deep Sleep Register (DEEPSLEEP) The deep sleep register (DEEPSLEEP) control the Deep Sleep logic. The DEEPSLEEP is shown in Figure 11-48 and described in Table 11-52. Texas Instruments Incorporated 301 . Reserved Deep sleep counter. the software must poll the SLEEPCOMPLETE bit. setting DEEPSLEEP pin low initiates oscillator shut down.com SYSCFG Registers 11.5. 0 1 29-16 15-0 Reserved SLEEPCOUNT 0 0-FFFFh SLEEPCOUNT delay is not complete. Deep sleep mode is enabled. the software should clear the SLEEPENABLE bit and continue operation. when the SLEEPCOMPLETE bit is read as 1. Deep Sleep Register (DEEPSLEEP) 31 SLEEPENABLE R/W-0 15 SLEEPCOUNT R/W-FFFFh LEGEND: R/W = Read/Write. Once the deep sleep process starts. SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. SLEEPCOUNT delay is complete. Deep sleep complete.www. Deep Sleep Register (DEEPSLEEP) Field Descriptions Bit 31 Field SLEEPENABLE 0 1 30 SLEEPCOMPLETE Value Description Deep sleep enable. -n = value after reset 30 SLEEPCOMPLETE R-0 29 Reserved R-0 0 16 Table 11-52. All 16 bits are tied directly to the counter in the Deep Sleep logic. R = Read only. Figure 11-48. Device is in normal operating mode. DEEPSLEEP pin has no effect.ti. See your device-specific data manual and the Boot Considerations chapter for details on boot and configuration settings. Number of cycles to count prior to the oscillator being stable. The software must clear this bit to 0 when the device is awakened from deep sleep.

See your device-specific data manual for pin group information. -n = value after reset 0 Table 11-54. an external pull-up should be used. See your device-specific data manual for pin group information. NOTE: The PUPD_SEL settings are not active until the device is out of reset.22 Pullup/Pulldown Enable Register (PUPD_ENA) The pullup/pulldown enable register (PUPD_ENA) enables the pull-up or pull-down functionality for the pin group n defined in your device-specific data manual. Internal pull-up or pull-down functionality for pin group n is enabled. 302 System Configuration (SYSCFG) Module Copyright © 2011. Internal pull-up functionality for pin group n is enabled. 11. -n = value after reset 0 Table 11-53. Figure 11-49. The PUPD_SEL is shown in Figure 11-50 and described in Table 11-54 and Table 11-55. The internal pull-up or pull-down functionality selection for bit position n in PUPD_ENA is set in the same bit position n of the pullup/pulldown select register (PUPD_SEL). Pullup/Pulldown Enable Register (PUPD_ENA) 31 PUPDENA[n] R/W-FFFF FFFFh LEGEND: R/W = Read/Write.com 11.5. If the application requires a pull-up during reset. Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions Bit 31-0 Field PUPDSEL[n] Value Description Selects between the internal pull-up or pull-down functionality for pin group CP[n]. During reset.23 Pullup/Pulldown Select Register (PUPD_SEL) The pullup/pulldown select register (PUPD_SEL) selects between the pull-up or pull-down functionality for the pin group n defined in your device-specific data manual. The PUPD_ENA is shown in Figure 11-49 and described in Table 11-53. Figure 11-50. The selection for bit position n in PUPD_SEL is only valid when the same bit position n is set in the pullup/pulldown enable register (PUPD_ENA). 0 1 Internal pull-up or pull-down functionality for pin group n is disabled. Pullup/Pulldown Select Register (PUPD_SEL) 31 PUPDSEL[n] R/W-C3FF FFFFh LEGEND: R/W = Read/Write. Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions Bit 31-0 Field PUPDENA[n] Value Description Enables internal pull-up or pull-down functionality for pin group CP[n]. 0 1 Internal pull-down functionality for pin group n is enabled.SYSCFG Registers www.ti. all of the CP[n] pins are pulled down.5. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

Pin Group CP[4] is configured for pull-up by default. Pin Group CP[11] is configured for pull-up by default. SPRUH77A – December 2011 Submit Documentation Feedback System Configuration (SYSCFG) Module Copyright © 2011. Pin Group CP[15] is configured for pull-up by default. Pin Group CP[25] is configured for pull-up by default. Pin Group CP[14] is configured for pull-up by default. Pin Group CP[27] is configured for pull-down by default. Pin Group CP[6] is configured for pull-up by default. Pin Group CP[17] is configured for pull-up by default. Pin Group CP[0] is configured for pull-up by default. Pin Group CP[1] is configured for pull-up by default. Pin Group CP[19] is configured for pull-up by default. Pin Group CP[9] is configured for pull-up by default. Pin Group CP[10] is configured for pull-up by default. Pin Group CP[22] is configured for pull-up by default.www.ti. Pin Group CP[2] is configured for pull-up by default. Pullup/Pulldown Select Register (PUPD_SEL) Default Values Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field PUPDSEL[31] PUPDSEL[30] PUPDSEL[29] PUPDSEL[28] PUPDSEL[27] PUPDSEL[26] PUPDSEL[25] PUPDSEL[24] PUPDSEL[23] PUPDSEL[22] PUPDSEL[21] PUPDSEL[20] PUPDSEL[19] PUPDSEL[18] PUPDSEL[17] PUPDSEL[16] PUPDSEL[15] PUPDSEL[14] PUPDSEL[13] PUPDSEL[12] PUPDSEL[11] PUPDSEL[10] PUPDSEL[9] PUPDSEL[8] PUPDSEL[7] PUPDSEL[6] PUPDSEL[5] PUPDSEL[4] PUPDSEL[3] PUPDSEL[2] PUPDSEL[1] PUPDSEL[0] Default Value 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Description Pin Group CP[31] is configured for pull-up by default.com SYSCFG Registers Table 11-55. Pin Group CP[30] is configured for pull-up by default. Pin Group CP[7] is configured for pull-up by default. Pin Group CP[3] is configured for pull-up by default. Texas Instruments Incorporated 303 . Pin Group CP[16] is configured for pull-up by default. Pin Group CP[26] is configured for pull-down by default. Pin Group CP[13] is configured for pull-up by default. Pin Group CP[12] is configured for pull-up by default. Pin Group CP[5] is configured for pull-up by default. Pin Group CP[23] is configured for pull-up by default. Pin Group CP[29] is configured for pull-down by default. Pin Group CP[24] is configured for pull-up by default. Pin Group CP[20] is configured for pull-up by default. Pin Group CP[8] is configured for pull-up by default. Pin Group CP[21] is configured for pull-up by default. Pin Group CP[18] is configured for pull-up by default. Pin Group CP[28] is configured for pull-down by default.

Power Down Control Register (PWRDN) Field Descriptions Bit 31-1 0 Field Reserved SATACLK_PWRDN 0 1 Value FFFF FFFEh Description Reserved Enables SATA clock receiver. 304 System Configuration (SYSCFG) Module Copyright © 2011. LVCMOS receivers for pin group n are enabled.5. Figure 11-51.com 11. RXACTIVE Control Register (RXACTIVE) Field Descriptions Bit 31-0 Field RXACTIVE[n] 0 1 Value Description Enables the LVCMOS receivers on pin group n. LVCMOS receivers for pin group n are disabled. Power Down Control Register (PWRDN) 31 Reserved R-FFFF FFFEh 15 Reserved R-FFFF FFFEh LEGEND: R/W = Read/Write. -n = value after reset 0 Table 11-56.24 RXACTIVE Control Register (RXACTIVE) The RXACTIVE control register (RXACTIVE) enables or disables the LVCMOS receivers for the pin group n defined in your device-specific data manual. 11. R = Read only. See your device-specific data manual for pin group information. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Power down feature enabled (SATA clock input circuitry is disabled).5. RXACTIVE Control Register (RXACTIVE) 31 RXACTIVE[n] R/W-FFFF FFFFh LEGEND: R/W = Read/Write. Figure 11-52. Receivers should only be disabled if the associated pin group is not being used. The SATA clock receiver should only be disabled if the SATA is not being used. Power down feature disabled (SATA clock input circuitry is enabled).ti.25 Power Down Control Register (PWRDN) The power down control register (PWRDN) enables or disables the SATA clock receiver. -n = value after reset 1 0 SATACLK_PWRDN R/W-1 16 Table 11-57. The RXACTIVE is shown in Figure 11-51 and described in Table 11-56.SYSCFG Registers www. The PWRDN is shown in Figure 11-52 and described in Table 11-57.

..............................................3 12.................................................... AINTC Registers ................. Texas Instruments Incorporated 305 .................................................4 306 306 309 313 SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011......................................................... Page 12.......2 12............................1 12....................................................................................................................................Chapter 12 SPRUH77A – December 2011 ARM Interrupt Controller (AINTC) Topic .............................................................. Introduction .................... AINTC Methodology ................. Interrupt Mapping .................

For interrupts on same channel.2 Interrupt Mapping The AINTC supports up to 101 system interrupts from different peripherals to be mapped to 32 channels inside the AINTC (see Figure 12-1). • Each host interrupt can be enabled and disabled. interrupts on channel-I have higher priority than interrupts on channel-k. Interrupts from channels 0 and 1 are mapped to FIQ ARM interrupt on host side. the higher the priority. Interrupts from channels 2 to 31 are mapped to IRQ ARM interrupt on host side. • Channels 0 and 1 are mapped (hard-wired) to the FIQ ARM interrupt and channels 2-31 are mapped to IRQ ARM interrupt.1 Introduction The ARM interrupt controller (AINTC) is an interface between interrupts coming from different parts of the system (these are referred to as system interrupts in this document).com 12. Multiple interrupts can be mapped to a single channel. The lower the interrupt number. • Hardware prioritization of interrupts. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . ARM9 supports two types of interrupts: FIQ and IRQ (these are referred to as host interrupts in this document).Introduction www. • • • • • • • Any of the 101 system interrupts can be mapped to any of the 32 channels. Figure 12-1. Interrupts from these 32 channels are further mapped to either an ARM FIQ interrupt or an ARM IRQ interrupt. • Each system interrupt can be enabled and disabled. See the ARM926EJ Technical Reference Manual for information about the ARM's FIQ and IRQ interrupts. The AINTC has the following features: • Supports up to 101 system interrupts. 12. For I < k. • Supports up to 32 interrupt channels. and the ARM9 interrupt interface. AINTC Interrupt Mapping Host Interrupt Mapping of Channels AINTC Channel 0 Channel Mapping of System Interrupts Intr 0 Intr 1 FIQ Channel 1 Peripheral A ARM Channel 2 IRQ Intr (n–1) Intr n Peripheral Z Channel m n ≤ 100 m ≤ 31 306 ARM Interrupt Controller (AINTC) Copyright © 2011. • Combining of interrupts from IPs to a single system interrupt. Table 12-1 shows the system interrupt assignments for the AINTC. • Supports two active low debug interrupts. An interrupt should not be mapped to more than one channel. priority is determined by the hardware interrupt number.ti.

Core 1 Miscellaneous Interrupt DDR2 Controller Interrupt GPIO Bank 0 Interrupt GPIO Bank 1 Interrupt GPIO Bank 2 Interrupt GPIO Bank 3 Interrupt GPIO Bank 4 Interrupt SPRUH77A – December 2011 Submit Documentation Feedback Copyright © 2011.Core 1 Receive Interrupt EMAC .www. Texas Instruments Incorporated ARM Interrupt Controller (AINTC) 307 . AINTC System Interrupt Assignments Event 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Interrupt Name COMMTX COMMRX NINT PRU_EVTOUT0 PRU_EVTOUT1 PRU_EVTOUT2 PRU_EVTOUT3 PRU_EVTOUT4 PRU_EVTOUT5 PRU_EVTOUT6 PRU_EVTOUT7 EDMA3_0_CC0_INT0 EDMA3_0_CC0_ERRINT EDMA3_0_TC0_ERRINT EMIFA_INT IIC0_INT MMCSD0_INT0 MMCSD0_INT1 PSC0_ALLINT RTC_IRQS[1:0] SPI0_INT T64P0_TINT12 T64P0_TINT34 T64P1_TINT12 T64P1_TINT34 UART0_INT — PROTERR SYSCFG_CHIPINT0 SYSCFG_CHIPINT1 SYSCFG_CHIPINT2 SYSCFG_CHIPINT3 EDMA3_0_TC1_ERRINT EMAC_C0RXTHRESH EMAC_C0RX EMAC_C0TX EMAC_C0MISC EMAC_C1RXTHRESH EMAC_C1RX EMAC_C1TX EMAC_C1MISC DDR2_MEMERR GPIO_B0INT GPIO_B1INT GPIO_B2INT GPIO_B3INT GPIO_B4INT Source ARM ARM ARM PRUSS Interrupt PRUSS Interrupt PRUSS Interrupt PRUSS Interrupt PRUSS Interrupt PRUSS Interrupt PRUSS Interrupt PRUSS Interrupt EDMA3_0 Channel Controller 0 Shadow Region 0 Transfer Completion Interrupt EDMA3_0 Channel Controller 0 Error Interrupt EDMA3_0 Transfer Controller 0 Error Interrupt EMIFA Interrupt I2C0 interrupt MMCSD0 MMC/SD Interrupt MMCSD0 SDIO Interrupt PSC0 Interrupt RTC Interrupt SPI0 Interrupt Timer64P0 Interrupt (TINT12) Timer64P0 Interrupt (TINT34) Timer64P1 Interrupt (TINT12) Timer64P1 Interrupt (TINT34) UART0 Interrupt Reserved SYSCFG Protection Shared Interrupt SYSCFG CHIPSIG Register SYSCFG CHIPSIG Register SYSCFG CHIPSIG Register SYSCFG CHIPSIG Register EDMA3_0 Transfer Controller 1 Error Interrupt EMAC .Core 0 Miscellaneous Interrupt EMAC .Core 1 Receive Threshold Interrupt EMAC .Core 1 Transmit Interrupt EMAC .Core 0 Transmit Interrupt EMAC .Core 0 Receive Threshold Interrupt EMAC .ti.Core 0 Receive Interrupt EMAC .com Interrupt Mapping Table 12-1.

0) Interrupt USB1 (USB1.Compare Interrupt 5 Timer64P2 .Interrupt Mapping www.Compare Interrupt 3 Timer64P3 .1) OHCI Host Controller Interrupt USB1 (USB1.Compare Interrupt 6 Timer64P3 .Compare Interrupt 5 Timer64P3 .Compare Interrupt 6 Timer64P2 .com Table 12-1. AINTC System Interrupt Assignments (continued) Event 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Interrupt Name GPIO_B5INT GPIO_B6INT GPIO_B7INT GPIO_B8INT IIC1_INT LCDC_INT UART_INT1 MCASP_INT PSC1_ALLINT SPI1_INT UHPI_ARMINT USB0_INT USB1_HCINT USB1_R/WAKEUP UART2_INT — EHRPWM0 EHRPWM0TZ EHRPWM1 EHRPWM1TZ SATA_INT T64P2_ALL ECAP0 ECAP1 ECAP2 MMCSD1_INT0 MMCSD1_INT1 T64P2_CMPINT0 T64P2_CMPINT1 T64P2_CMPINT2 T64P2_CMPINT3 T64P2_CMPINT4 T64P2_CMPINT5 T64P2_CMPINT6 T64P2_CMPINT7 T64P3_CMPINT0 T64P3_CMPINT1 T64P3_CMPINT2 T64P3_CMPINT3 T64P3_CMPINT4 T64P3_CMPINT5 T64P3_CMPINT6 T64P3_CMPINT7 ARMCLKSTOPREQ uPP_ALLINT VPIF_ALLINT EDMA3_1_CC0_INT0 Source GPIO Bank 5 Interrupt GPIO Bank 6 Interrupt GPIO Bank 7 Interrupt GPIO Bank 8 Interrupt I2C1 Interrupt LCD Controller Interrupt UART1 Interrupt McASP0 Combined RX/TX Interrupt PSC1 Interrupt SPI1 Interrupt HPI ARM Interrupt USB0 (USB2.Compare Interrupt 2 Timer64P3 .Compare Interrupt 0 Timer64P2 .Compare Interrupt 4 Timer64P2 .Compare Interrupt 1 Timer64P2 .Compare Interrupt 1 Timer64P3 .Compare Interrupt 0 Timer64P3 .ti.Compare Interrupt 7 PSC0 Interrupt uPP Combined Interrupt VPIF Combined Interrupt EDMA3_1 Channel Controller 0 Shadow Region 0 Transfer Completion Interrupt SPRUH77A – December 2011 Submit Documentation Feedback Copyright © 2011. Texas Instruments Incorporated 308 ARM Interrupt Controller (AINTC) .Compare Interrupt 2 Timer64P2 .1) Remote Wakeup Interrupt UART2 Interrupt Reserved HiResTimer / PWM0 Interrupt HiResTimer / PWM0 Trip Zone Interrupt HiResTimer / PWM1 Interrupt HiResTimer / PWM1 Trip Zone Interrupt SATA Controller Interrupt Timer64P2 Combined Interrupt (TINT12 and TINT34) eCAP0 Interrupt eCAP1 Interrupt eCAP2 Interrupt MMCSD1 MMC/SD Interrupt MMCSD1 SDIO Interrupt Timer64P2 .Compare Interrupt 4 Timer64P3 .Compare Interrupt 7 Timer64P3 .Compare Interrupt 3 Timer64P2 .

and host interfacing. Flow of System Interrupts to Host Status Enabling Processing System Interrupts Prioritization Channel Mapping Vectorization Host Interfacing Host Interrupts Host Int Mapping 12. The channels are used to combine and prioritize system interrupts.1 Interrupt Processing The interrupt processing block does the following tasks: • Synchronization of slower and asynchronous interrupts • Conversion of polarity to active high • Conversion of interrupt type to pulse interrupts After the processing block. The AINTC receives the system interrupts and maps them to internal channels. they are pulse type of interrupts. The following subsections describe each part of the flow. Figure 12-2 illustrates the flow of system interrupts through the functions to the host. These functions are: processing.3. SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011. AINTC System Interrupt Assignments (continued) Event 94 95 96 97 98 99 100 Interrupt Name EDMA3_1_CC0_ERRINT EDMA3_1_TC0_ERRINT T64P3_ALL MCBSP0_RINT MCBSP0_XINT MCBSP1_RINT MCBSP1_XINT Source EDMA3_1 Channel Controller 0 Error Interrupt EDMA3_1 Transfer Controller 0 Error Interrupt Timer64P3 Combined Interrupt (TINT12 and TINT34) McBSP0 Receive Interrupt McBSP0 Transmit Interrupt McBSP1 Receive Interrupt McBSP1 Transmit Interrupt 12. all interrupts will be active-high pulses. prioritization.www.ti. These channels are then mapped onto the host interface that is typically a smaller number of host interrupts or a vector input. channel mapping. Also. debug. status. Figure 12-2. Texas Instruments Incorporated 309 . vectorization. The AINTC encompasses many functions to process the system interrupts and prepare them for the host interface. host interrupt mapping. Interrupts from system side are active high in polarity. System interrupts are generated by the device peripherals. enabling.com AINTC Methodology Table 12-1.3 AINTC Methodology The AINTC module controls the system interrupt mapping to the host interrupt interface.

Individual host interrupts are enabled or disabled from their individual enables and are not overridden by the global enable. 12. Channel for each system interrupt can be set using these registers. Enable system interrupts. When multiple channels are mapped to the same host interrupt. Host interrupt lines (FIQ and IRQ) can be enabled through one of two methods: (a) Set the desired mapped bit(s) in the host interrupt enable register (HIER). the enabled status will always be inactive. or (b) Write the system interrupt index (0-100) to the system interrupt enable indexed set register (EISR) for every system interrupt to enable. 12. Channels 0 and 1 are mapped to FIQ and channels 2-31 are mapped to IRQ. There are two kinds of pending status: raw status and enabled status.ti.2 Interrupt Enabling The AINTC interrupt enable system allows individual interrupts to be enabled or disabled. or (b) Write the host interrupt index (0-1) to the host interrupt enable indexed set register (HIEISR) for every interrupt line to enable. The pending status reflects whether the system interrupt occurred since the last time the status register bit was cleared.3. System interrupts can be individually enabled through one of two methods: (a) Set the desired mapped bit(s) in the system interrupt enable set registers (ESR1-ESR4). Other interrupts can be mapped to any of the channels from 2 to 31. All host interrupts are enabled by setting the ENABLE bit in the global enable register (GER).AINTC Methodology www. there are 26 channel map registers (CMR0-CMR25) for a system of 101 interrupts. The AINTC has a fixed host interrupt mapping scheme. Higher priority interrupts should be mapped to channels 0 and 1.3. The 32 channels from the AINTC are mapped to these two lines. then prioritization is done to select which interrupt is in the highest-priority channel and which should be sent first to the host. which has two lines: FIQ and IRQ. Enable host interrupt lines.3. 3. 12. Status of system interrupt 'N' is indicated by the Nth bit of SECR1-SECR4. Use the following sequence to enable interrupts: 1. When multiple system interrupts are mapped to the same channel their interrupts are ORed together so that when either is active the output is active. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Channel 0 has highest priority and channel 31 has the lowest priority. Since there exists 101 system interrupts. The channel map registers (CMRm) define the channel for each system interrupt.com 12. Channels 2 to 31 are connected to IRQ ARM interrupt. Enabled status is the pending status of the system interrupts with the enable bits active. Raw status is the pending status of the system interrupt without regards to the enable bit for the system interrupt.4 Interrupt Channel Mapping The AINTC has 32 internal channels to which enabled system interrupts can be mapped.3. system interrupts mapped to channels 0 and 1 are propagated as FIQ to the host and system interrupts mapped to channels 2-31 are propagated as IRQ to the host. Enable global host interrupts. When the enable bit is inactive. Thus. The enabled status of system interrupts is captured in system interrupt status enabled/clear registers (SECR1-SECR4). four 32-bit registers are used to capture the enabled status of interrupts. There is one register per 4 system interrupts. 2. 310 ARM Interrupt Controller (AINTC) Copyright © 2011. therefore.5 Host Interrupt Mapping Interrupts The Host is ARM9. Channels are used to group the system interrupts into a smaller number of priorities that can be given to a host interface with a very small number of interrupt inputs. Channels 0 and 1 are connected to FIQ ARM interrupt.3 Interrupt Status Checking The next stage is to capture which system interrupts are pending. Each bit in the status register is individually clearable.

it is necessary to prioritize between all the system interrupts/channels to decide on a single system interrupt to handle.7 Interrupt Nesting If interrupt service routines (ISRs) consume a large number of CPU cycles and may delay the servicing of other interrupts. The nesting level controls which channel and lower priority channels are nested. The AINTC features a prioritization hold mode that is intended to prevent race conditions while servicing interrupts. The host interrupt nesting level registers (HINLR1 and HINLR2) display and control the nesting level for each host interrupt. The second level of prioritization is between the active system interrupts for the prioritized channel.3. The nesting level is the channel (and all of lower priority channels) that are nested out because of a current interrupt. Write to the host interrupt prioritized vector register (HIPVRn) 3. Since multiple interrupts feed into a single channel and multiple channels feed into a single host interrupt. and other host interrupts do not have their nesting affected. based on channel priority: When an interrupt is taken. Write-set the active interrupt index to the host interrupt enable index set register (HIEISR) 5. The AINTC provides hardware to perform this prioritization with a given scheme so that software does not have to do this. The typical usage is to nest on the current interrupt and disable all interrupts of the same or lower priority (or channel). the AINTC can perform a nesting function in its prioritization. based on channel priority: Always nest based on channel priority for each host interrupt individually. equal or lower priority channels will not interrupt the host but may on other host interrupts if programmed. 2. the nesting level is set to its channel priority for just that host interrupt. The global nesting level register (GNLR) allows the checking and setting of the global nesting level across all host interrupts. When enabled. the nesting level is set to its channel priority.ti. This mode is enabled by setting the priority hold mode (PRHOLDMODE) bit in the control register (CR). Then for that host interrupt. Nesting is available in 1 of 3 methods selectable by the NESTMODE bit in the control register (CR): 1. Write to the host interrupt prioritized index register (HIPIRn) 2. then. Write-clear the active interrupt index to the host interrupt enable index clear register (HIEICR) 12.com AINTC Methodology 12. Then the host will only be interrupted from a higher priority interrupt. The system interrupt in vector position 0 has the highest priority and system interrupt 100 has the lowest priority. When the interrupt is completely serviced the nesting level for the host interrupt is returned to its original value. there are no channels disabled due to nesting. The first level of prioritization is between the active channels for a host interrupt. The prioritized system interrupt for each host interrupt line (FIQ and IRQ) can be obtained from the host interrupt prioritized index registers (HIPIR1 and HIPIR2). Texas Instruments Incorporated 311 . The values are frozen until one of the following actions is taken to release the registers: 1. So the first level of prioritization picks the lowest numbered active channel. 2. a read of either the host interrupt prioritized index register (HIPIRn) or the host interrupt prioritized vector register (HIPVRn) will freeze both the HIPIRn and HIPVRn values for the respective host interrupt n.www. So the second level of prioritization picks the lowest vector position active system interrupt. Write-set bit n of the host interrupt enable register (HIER) 4. Nesting for all host interrupts. the nesting level is returned to its original value. When the interrupt is completely serviced. There is one register per host interrupt. Nesting is a method of disabling certain interrupts (usually lower-priority interrupts) when an interrupt is taken so that only those desired interrupts can trigger to the host while it is servicing the current interrupt. From then. Channel 0 has the highest priority and channel 31 has the lowest. Nesting for individual host interrupts. When an interrupt is taken on a host interrupt.3.6 Interrupt Prioritization The next stage of the AINTC is prioritization. that channel priority and all lower priority channels will be disabled from generating host interrupts and only higher priority channels are allowed. When there is no interrupt being serviced. There are two levels of prioritizations: 1. The host interrupt prioritized index register values update dynamically as interrupts arrive at AINTC so care should be taken to avoid register race conditions. SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011.

AINTC Methodology www. Push the active (or desired) interrupt priority value into the nest priority stack. looks up the specific ISR address for that system interrupt. Without vectorization the host would receive the interrupt and enter a general ISR that gets the prioritized system interrupt to service from the AINTC. 8. The vector null address register (VNR) holds the address of the ISR null address. Vectorization is an advanced feature that allows the host to receive an interrupt service routine (ISR) address in addition to just the interrupt status.8 Interrupt Vectorization The next stage of the AINTC is vectorization. This method requires the most software interaction but gives the most flexibility if simple channel based nesting mechanisms are not adequate. 4. This is in case the vector address is executed when there is no pending interrupt so that a Null handler can be in place to just return from the interrupt.ti. 7. 12. Disable the ARM hardware interrupt. a software stack is used to keep track of nest priorities. 312 ARM Interrupt Controller (AINTC) Copyright © 2011. Because higher priority interrupts can preempt lower priority interrupts in this method. interrupts enabled by the new nest priority level will be able to preempt the ISR. Enable the ARM hardware interrupt. 11. 3. 5. the software will disable all the host interrupts. This now allows only the system interrupts that are still enabled to trigger to the host. With vectorization the host can read a register that has the ISR address already calculated and jump to that address immediately. 10. 2. When an interrupt is taken. Unfreeze the host interrupt prioritized index register n (HIPIRn) and the host interrupt prioritized vector register n (HIPVRn). 6. The specific system interrupt ISR address is then calculated as: ISR address = base + (index × size) There is also a special case when there is no interrupt pending and then the ISR address is the ISR Null address. Software manually performs the nesting of interrupts. Discard the most recent priority level in the nest priority stack and restore the previous priority level to HINLRn by setting the OVERRIDE bit. Vectorization uses a base and universal size where all the ISR code is placed in a contiguous memory region with each ISR code a standard size.com 3. Acknowledge and enable the ARM hardware interrupt. When there is a pending interrupt then the ISR address is calculated as exact base + offset for that interrupt number. if the PRHOLDMODE bit in the control register (CR) is set. The recommended approach is the automatic host interrupt nesting method (second method). Execute the ISR at the address stored from step 5. Take the following steps within the ARM hardware interrupt service routine to handle interrupts using host interrupt priority nesting: 1. the vector base register (VBR) is programmed by software to hold the base address of all the ISR code and the vector size register (VSR) is programmed for the size in words between ISR code for each system interrupt. Calculate and store the ISR address for the active interrupt. and then jumps to that address. The base stack value should be initialized to the default nest priority of the application. and then re-enable all the host interrupts. During this step. Clear the system interrupt status by setting the appropriate bit in the system interrupt status enabled/clear register n (SECRn) or by writing the appropriate index to the system interrupt status indexed clear register (SICR). Disable the ARM hardware interrupt. manually update the enables for any or all the system interrupts. For this calculation. 9. When the interrupt is completely serviced the software must reverse the changes to re-enable the nested out system interrupts.3. Clear the OVERRIDE bit in the host interrupt nesting level register n (HINLRn) to expose the priority level of the active interrupt. Write the active (or desired) priority level into HINLRn by setting the OVERRIDE bit. The index number of each system interrupt is used to calculate the final offset. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

com AINTC Registers 12.4.4.21 Section 12.16 Section 12.7 Section 12.10 Interrupt Disabling At any time.5 Section 12.4.28 Section 12.20 Section 12.4.30 SPRUH77A – December 2011 Submit Documentation Feedback Copyright © 2011.3 Section 12. For clearing the status of an interrupt. For disabling an interrupt whose interrupt number is N.25 Section 12.4.4.4 Section 12.4.23 Section 12.4.12 Section 12. 12.17 Section 12.14 Section 12.4.www. 12.4.4.9 Section 12. if any interrupt is not to be propagated to the host.9 Interrupt Status Clearing After servicing the interrupt (after execution of the ISR).11 Section 12. write a 1 to the Nth bit in the system interrupt enable clear registers (ECR1-ECR4).4.4. If a system interrupt status is not cleared. System interrupt N can also be disabled by writing the value N in the system interrupt enable indexed clear register (EICR).4. ARM Interrupt Controller (AINTC) Registers Address FFFE E000h FFFE E004h FFFE E010h FFFE E01Ch FFFE E020h FFFE E024h FFFE E028h FFFE E02Ch FFFE E034h FFFE E038h FFFE E050h FFFE E054h FFFE E058h FFFE E080h FFFE E084h FFFE E200h FFFE E204h FFFE E208h FFFE E20Ch FFFE E280h FFFE E284h FFFE E288h FFFE E28Ch FFFE E300h FFFE E304h FFFE E308h FFFE E30Ch FFFE E380h FFFE E384h FFFE E388h Acronym REVID CR GER GNLR SISR SICR EISR EICR HIEISR HIEICR VBR VSR VNR GPIR GPVR SRSR1 SRSR2 SRSR3 SRSR4 SECR1 SECR2 SECR3 SECR4 ESR1 ESR2 ESR3 ESR4 ECR1 ECR2 ECR3 Register Description Revision Identification Register Control Register Global Enable Register Global Nesting Level Register System Interrupt Status Indexed Set Register System Interrupt Status Indexed Clear Register System Interrupt Enable Indexed Set Register System Interrupt Enable Indexed Clear Register Host Interrupt Enable Indexed Set Register Host Interrupt Enable Indexed Clear Register Vector Base Register Vector Size Register Vector Null Register Global Prioritized Index Register Global Prioritized Vector Register System Interrupt Status Raw/Set Register 1 System Interrupt Status Raw/Set Register 2 System Interrupt Status Raw/Set Register 3 System Interrupt Status Raw/Set Register 4 System Interrupt Status Enabled/Clear Register 1 System Interrupt Status Enabled/Clear Register 2 System Interrupt Status Enabled/Clear Register 3 System Interrupt Status Enabled/Clear Register 4 System Interrupt Enable Set Register 1 System Interrupt Enable Set Register 2 System Interrupt Enable Set Register 3 System Interrupt Enable Set Register 4 System Interrupt Enable Clear Register 1 System Interrupt Enable Clear Register 2 System Interrupt Enable Clear Register 3 Section Section 12.1 Section 12.4.4.2 Section 12.4.4 AINTC Registers Table 12-2 lists the memory-mapped registers for the AINTC.19 Section 12.10 Section 12.3. System interrupt N can also be cleared by writing the value N into the system interrupt status indexed clear register (SICR).27 Section 12.6 Section 12.4. Table 12-2.15 Section 12.4.24 Section 12.4.26 Section 12.4.22 Section 12.29 Section 12.4.18 Section 12.4. whose interrupt number is N.4.8 Section 12.4. interrupt status is to be cleared.3. then that interrupt should be disabled.4.13 Section 12.4. write a 1 to the Nth bit position in the system interrupt status enabled/clear registers (SECR1-SECR4). Texas Instruments Incorporated ARM Interrupt Controller (AINTC) 313 . then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly.4.4.4.ti.

-n = value after reset 0 Table 12-3.36 Section 12.37 Section 12. Revision Identification Register (REVID) 31 REV R-4E82 A900h LEGEND: R = Read only.com Table 12-2.39 12.4. Figure 12-3.4.4.AINTC Registers www. ARM Interrupt Controller (AINTC) Registers (continued) Address FFFE E38Ch FFFE E400h– FFFE E464h FFFE E900h FFFE E904h FFFE F100h FFFE F104h FFFE F500h FFFE F600h FFFE F604h Acronym ECR4 CMR0-CMR25 HIPIR1 HIPIR2 HINLR1 HINLR2 HIER HIPVR1 HIPVR2 Register Description System Interrupt Enable Clear Register 4 Channel Map Registers 0-25 Host Interrupt Prioritized Index Register 1 Host Interrupt Prioritized Index Register 2 Host Interrupt Nesting Level Register 1 Host Interrupt Nesting Level Register 2 Host Interrupt Enable Register Host Interrupt Prioritized Vector Register 1 Host Interrupt Prioritized Vector Register 2 Section Section 12.4.4.33 Section 12.4.4. Revision Identification Register (REVID) Field Descriptions Bit 31-0 Field REV Value 4E82 A900h Description Revision ID of the AINTC.38 Section 12. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .31 Section 12. 314 ARM Interrupt Controller (AINTC) Copyright © 2011.1 Revision Identification Register (REVID) The revision identification register (REVID) is shown in Figure 25-35 and described in Table 12-3.4.35 Section 12.32 Section 12.4.34 Section 12.4.ti.

Nesting mode.4.3. R = Read only.com AINTC Registers 12. Prioritized Index and Vector Address MMRs will hold their value after the first is read.6 for details. Control Register (CR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write. The CR is shown in Figure 12-4 and described in Table 12-4. Texas Instruments Incorporated 315 . See Section 12. No nesting Automatic individual nesting (per host interrupt) Automatic global nesting (over all host interrupts) Manual nesting Reserved SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011. Priority holding enabled. Control Register (CR) Field Descriptions Bit 31-5 4 Field Reserved PRHOLDMODE 0 1 3-2 NESTMODE 0-3h 0 1h 2h 3h 1-0 Reserved 0 Value 0 Description Reserved Enables priority holding mode. Figure 12-4. No priority holding. Prioritized MMRs will continually update.ti. -n = value after reset 5 4 PRHOLDMODE R/W-0 3 R/W-0 2 1 R-0 0 16 NESTMODE Reserved Table 12-4.2 Control Register (CR) The control register (CR) holds global control parameters.www.

Global Nesting Level Register (GNLR) Field Descriptions Bit 31 30-9 8-0 Field OVERRIDE Reserved NESTLVL Value 0-1 0 0-1FFh Description Always read as 0. The GER is shown in Figure 12-5 and described in Table 12-5. R = Read only.com 12. unless the auto_override bit is set.4.ti. Figure 12-5. Global Enable Register (GER) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write. Global Nesting Level Register (GNLR) 31 OVERRIDE R/W-0 15 Reserved R-0 LEGEND: R/W = Read/Write. -n = value after reset 1 0 ENABLE R/W-0 16 Table 12-5. Global Enable Register (GER) Field Descriptions Bit 31-1 0 Field Reserved ENABLE Value 0 0-1 Description Reserved The current global enable value when read. Figure 12-6.4. Writes set the nesting level. Writes of 1 override the automatic nesting and set the NESTLVL to the written data. The GNLR is shown in Figure 12-6 and described in Table 12-6. Writes set the global enable. 12.AINTC Registers www. Individual host interrupts are still enabled or disabled from their individual enables and are not overridden by the global enable. Reserved The current global nesting level (highest channel that is nested). The nesting level is the channel (and all of lower priority) that are nested out because of a current interrupt. R = Read only.4 Global Nesting Level Register (GNLR) The global nesting level register (GNLR) allows the checking and setting of the global nesting level across all host interrupts when automatic global nesting mode is set. 316 ARM Interrupt Controller (AINTC) Copyright © 2011.3 Global Enable Register (GER) The global enable register (GER) enables all the host interrupts. In autonesting mode this value is updated internally. -n = value after reset 9 8 NESTLVL R/W-100h 30 Reserved R-0 0 16 Table 12-6. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

6 System Interrupt Status Indexed Clear Register (SICR) The system interrupt status indexed clear register (SICR) allows clearing the status of an interrupt. -n = value after reset 7 6 INDEX W-0 0 16 Table 12-8. Figure 12-8. This sets the Raw Status Register bit of the given INDEX.ti. Reads return 0.www. SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011. Texas Instruments Incorporated 317 .5 System Interrupt Status Indexed Set Register (SISR) The system interrupt status indexed set register (SISR) allows setting the status of an interrupt. The interrupt to set is the INDEX value written. System Interrupt Status Indexed Clear Register (SICR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only. Reads return 0. W = Write only. System Interrupt Status Indexed Set Register (SISR) Field Descriptions Bit 31-7 6-0 Field Reserved INDEX Value 0 0-7Fh Description Reserved Writes set the status of the interrupt given in the INDEX value. Figure 12-7. -n = value after reset 7 6 INDEX W-0 0 16 Table 12-7.4. The SICR is shown in Figure 12-8 and described in Table 12-8. W = Write only. The interrupt to clear is the INDEX value written.com AINTC Registers 12. 12. System Interrupt Status Indexed Set Register (SISR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only. The SISR is shown in Figure 12-7 and described in Table 12-7. This clears the Raw Status Register bit of the given INDEX. System Interrupt Status Indexed Clear Register (SICR) Field Descriptions Bit 31-7 6-0 Field Reserved INDEX Value 0 0-7Fh Description Reserved Writes clear the status of the interrupt given in the INDEX value.4.

4. 318 ARM Interrupt Controller (AINTC) Copyright © 2011. This clears the Enable Register bit of the given INDEX.4.AINTC Registers www.7 System Interrupt Enable Indexed Set Register (EISR) The system interrupt enable indexed set register (EISR) allows enabling an interrupt.com 12. Reads return 0. The EISR is shown in Figure 12-9 and described in Table 12-9. -n = value after reset 7 6 INDEX W-0 0 16 Table 12-10. Figure 12-10. 12. W = Write only. Figure 12-9. System Interrupt Enable Indexed Set Register (EISR) Field Descriptions Bit 31-7 6-0 Field Reserved INDEX Value 0 0-7Fh Description Reserved Writes set the enable of the interrupt given in the INDEX value. Reads return 0.ti. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . W = Write only. This sets the Enable Register bit of the given INDEX. The EICR is shown in Figure 12-10 and described in Table 12-10. System Interrupt Enable Indexed Set Register (EISR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only. The interrupt to enable is the INDEX value written. System Interrupt Enable Indexed Clear Register (EICR) Field Descriptions Bit 31-7 6-0 Field Reserved INDEX Value 0 0-7Fh Description Reserved Writes clear the enable of the interrupt given in the INDEX value. System Interrupt Enable Indexed Clear Register (EICR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only.8 System Interrupt Enable Indexed Clear Register (EICR) The system interrupt enable indexed clear register (EICR) allows disabling an interrupt. The interrupt to disable is the INDEX value written. -n = value after reset 7 6 INDEX W-0 0 16 Table 12-9.

Writing a 1 sets IRQ. Host Interrupt Enable Indexed Clear Register (HIEICR) Field Descriptions Bit 31-1 0 Field Reserved INDEX 0 1 Value 0 Description Reserved Writes clear the enable of the host interrupt given in the INDEX value. This disables the host interrupt output. Reads return 0. Texas Instruments Incorporated 319 . -n = value after reset 1 0 INDEX W-0 16 Table 12-11.www. Host Interrupt Enable Indexed Clear Register (HIEICR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only. 12. Host Interrupt Enable Indexed Set Register (HEISR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R = Read only.com AINTC Registers 12. The host interrupt to enable is the INDEX value written.ti. SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011. Reads return 0. Writing a 1 clears IRQ. The host interrupt to disable is the INDEX value written. Figure 12-11. Writing a 0 clears FIQ.10 Host Interrupt Enable Indexed Clear Register (HIEICR) The host interrupt enable indexed clear register (HIEICR) allows disabling a host interrupt output.4. Host Interrupt Enable Indexed Set Register (HEISR) Field Descriptions Bit 31-1 0 Field Reserved INDEX 0 1 Value 0 Description Reserved Writes set the enable of the host interrupt given in the INDEX value. Figure 12-12. Writing a 0 sets FIQ. The HIEICR is shown in Figure 12-12 and described in Table 12-12. The HEISR is shown in Figure 12-11 and described in Table 12-11.9 Host Interrupt Enable Indexed Set Register (HIEISR) The host interrupt enable indexed set register (HIEISR) allows enabling a host interrupt output.4. This enables the host interrupt output or triggers the output again if already enabled. W = Write only. -n = value after reset 1 0 INDEX W-0 16 Table 12-12. W = Write only.

4 bytes 8 bytes 16 bytes 32 bytes 64 bytes 5h-FFh .com 12. 320 ARM Interrupt Controller (AINTC) Copyright © 2011. Vector Base Register (VBR) Field Descriptions Bit 31-0 Field BASE Value 0-FFFF FFFFh Description ISR Base Address. The VBR is shown in Figure 12-13 and described in Table 12-13. This is only the sizes to space the calculated vector addresses for the initial ISR targets (the ISR targets could branch off to the full ISR routines).AINTC Registers www.. The VSR is shown in Figure 12-14 and described in Table 12-14. -n = value after reset 8 7 SIZE R/W-0 0 16 Table 12-14.ti. Vector Size Register (VSR) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write.11 Vector Base Register (VBR) The vector base register (VBR) holds the base address of the ISR vector addresses. R = Read only.12 Vector Size Register (VSR) The vector size register (VSR) holds the sizes of the individual ISR routines in the vector table. NOTE: The VSR must be configured even if the desired value is equal to the default value. 12. -n = value after reset 0 Table 12-13. Figure 12-14. Figure 12-13.4. Vector Base Register (VBR) 31 BASE R/W-0 LEGEND: R/W = Read/Write. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback ..4. Vector Size Register (VSR) Field Descriptions Bit 31-8 7-0 Field Reserved SIZE Value 0 0-FFh 0 1h 2h 3h 4h Description Reserved Size of ISR address spaces.

The GPIR is shown in Figure 12-16 and described in Table 12-16. Vector Null Register (VNR) 31 NULL R/W-0 LEGEND: R/W = Read/Write.com AINTC Registers 12. Figure 12-16.4. The VNR is shown in Figure 12-15 and described in Table 12-15. Figure 12-15. Global Prioritized Index Register (GPIR) 31 NONE R-1 15 Reserved R-0 LEGEND: R = Read only. Texas Instruments Incorporated 321 .4.13 Vector Null Register (VNR) The vector null register (VNR) holds the address of the ISR null address that handles no pending interrupts (if accidentally branched to when no interrupts are pending). Reserved The currently highest priority interrupt index pending across all the host interrupts. 12.ti. Global Prioritized Index Register (GPIR) Field Descriptions Bit 31 30-10 9-0 Field NONE Reserved PRI_INDX Value 0-1 0 0-3FFh Description No Interrupt is pending. Vector Null Register (VNR) Field Descriptions Bit 31-0 Field NULL Value 0-FFFF FFFFh Description ISR Null Address. SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011. -n = value after reset 0 Table 12-15.www. Can be used by host to test for a negative value to see if no interrupts are pending.14 Global Prioritized Index Register (GPIR) The global prioritized index register (GPIR) shows the interrupt number of the highest priority interrupt pending across all the host interrupts. -n = value after reset 10 9 PRI_INDX R-0 30 Reserved R-0 0 16 Table 12-16.

AINTC Registers www.16 System Interrupt Status Raw/Set Register 1 (SRSR1) The system interrupt status raw/set register 1 (SRSR1) shows the pending enabled status of the system interrupts 0 to 31. The GPVR is shown in Figure 12-17 and described in Table 12-17. The SRSR1 is shown in Figure 12-18 and described in Table 12-18. Global Prioritized Vector Register (GPVR) 31 ADDR R-0 LEGEND: R = Read only. System Interrupt Status Raw/Set Register 1 (SRSR1) Field Descriptions Bit 31-0 Field RAW_STATUS[n] 0 1 Value Description System interrupt raw status and setting of the system interrupts 0 to 31. -n = value after reset 0 Table 12-18.4. Figure 12-17. Write a 1 in bit position [n] to set the status of the system interrupt n.15 Global Prioritized Vector Register (GPVR) The global prioritized vector register (GPVR) shows the interrupt vector address of the highest priority interrupt pending across all the host interrupts. -n = value after reset 0 Table 12-17. System Interrupt Status Raw/Set Register 1 (SRSR1) 31 RAW_STATUS[n] W-0 LEGEND: W = Write only. There is one bit per system interrupt. Reads return the raw status. Software can write to SRSR1 to set a system interrupt without a hardware trigger. Figure 12-18. Global Prioritized Vector Register (GPVR) Field Descriptions Bit 31-0 Field ADDR Value 0-FFFF FFFFh Description The currently highest priority interrupts vector address across all the host interrupts. 12. 322 ARM Interrupt Controller (AINTC) Copyright © 2011. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Writing a 0 has no effect.4.ti.com 12.

Figure 12-20. SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011. -n = value after reset 0 Table 12-19. The SRSR2 is shown in Figure 12-19 and described in Table 12-19.18 System Interrupt Status Raw/Set Register 3 (SRSR3) The system interrupt status raw/set register 3 (SRSR3) shows the pending enabled status of the system interrupts 64 to 95. Software can write to SRSR2 to set a system interrupt without a hardware trigger. Reads return the raw status. There is one bit per system interrupt. Writing a 0 has no effect.com AINTC Registers 12. System Interrupt Status Raw/Set Register 3 (SRSR3) 31 RAW_STATUS[n] W-0 LEGEND: W = Write only. Write a 1 in bit position [n] to set the status of the system interrupt n + 32. The SRSR3 is shown in Figure 12-20 and described in Table 12-20.17 System Interrupt Status Raw/Set Register 2 (SRSR2) The system interrupt status raw/set register 2 (SRSR2) shows the pending enabled status of the system interrupts 32 to 63. System Interrupt Status Raw/Set Register 2 (SRSR2) 31 RAW_STATUS[n] W-0 LEGEND: W = Write only. System Interrupt Status Raw/Set Register 3 (SRSR3) Field Descriptions Bit 31-0 Field RAW_STATUS[n] 0 1 Value Description System interrupt raw status and setting of the system interrupts 64 to 95. Reads return the raw status. Figure 12-19. -n = value after reset 0 Table 12-20.ti.4. System Interrupt Status Raw/Set Register 2 (SRSR2) Field Descriptions Bit 31-0 Field RAW_STATUS[n] 0 1 Value Description System interrupt raw status and setting of the system interrupts 32 to 63. Write a 1 in bit position [n] to set the status of the system interrupt n + 64. Software can write to SRSR3 to set a system interrupt without a hardware trigger. There is one bit per system interrupt. Writing a 0 has no effect.www.4. Texas Instruments Incorporated 323 . 12.

Reads return the raw status. Write a 1 in bit position [n] to set the status of the system interrupt n + 96. Write a 1 in bit position [n] to clear the status of the system interrupt n.com 12. -n = value after reset 0 Table 12-22. Software can write to SECR1 to clear a system interrupt after it has been serviced. Figure 12-21.4.19 System Interrupt Status Raw/Set Register 4 (SRSR4) The system interrupt status raw/set register 4 (SRSR4) shows the pending enabled status of the system interrupts 96 to 100. There is one bit per system interrupt. The SECR1 is shown in Figure 12-22 and described in Table 12-22. System Interrupt Status Enabled/Clear Register 1 (SECR1) Field Descriptions Bit 31-0 Field ENBL_STATUS[n] 0 1 Value Description System interrupt enabled status and clearing of the system interrupts 0 to 31.ti. System Interrupt Status Enabled/Clear Register 1 (SECR1) 31 ENBL_STATUS[n] W-0 LEGEND: W = Write only. Writing a 0 has no effect. Figure 12-22.4.20 System Interrupt Status Enabled/Clear Register 1 (SECR1) The system interrupt status enabled/clear register 1 (SECR1) shows the pending enabled status of the system interrupts 0 to 31. Writing a 0 has no effect. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Reads return the enabled status (before enabling with the Enable Registers). 12. There is one bit per system interrupt.AINTC Registers www. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. 324 ARM Interrupt Controller (AINTC) Copyright © 2011. The SRSR4 is shown in Figure 12-21 and described in Table 12-21. System Interrupt Status Raw/Set Register 4 (SRSR4) Field Descriptions Bit 31-5 4-0 Field Reserved RAW_STATUS[n] 0 1 Value 0 Description Reserved System interrupt raw status and setting of the system interrupts 96 to 100. System Interrupt Status Raw/Set Register 4 (SRSR4) 31 Reserved R-0 LEGEND: R = Read only. Software can write to SRSR4 to set a system interrupt without a hardware trigger. W = Write only. -n = value after reset 5 4 W-0 0 RAW_STATUS[n] Table 12-21.

System Interrupt Status Enabled/Clear Register 3 (SECR3) Field Descriptions Bit 31-0 Field ENBL_STATUS[n] 0 1 Value Description System interrupt enabled status and clearing of the system interrupts 64 to 95.4. Write a 1 in bit position [n] to clear the status of the system interrupt n + 32. SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011. Software can write to SECR2 to clear a system interrupt after it has been serviced. 12. Write a 1 in bit position [n] to clear the status of the system interrupt n + 64. There is one bit per system interrupt.www.4.com AINTC Registers 12. Software can write to SECR3 to clear a system interrupt after it has been serviced. System Interrupt Status Enabled/Clear Register 3 (SECR3) 31 ENBL_STATUS[n] W-0 LEGEND: W = Write only. Reads return the enabled status (before enabling with the Enable Registers). There is one bit per system interrupt. System Interrupt Status Enabled/Clear Register 2 (SECR2) Field Descriptions Bit 31-0 Field ENBL_STATUS[n] 0 1 Value Description System interrupt enabled status and clearing of the system interrupts 32 to 63.22 System Interrupt Status Enabled/Clear Register 3 (SECR3) The system interrupt status enabled/clear register 3 (SECR3) shows the pending enabled status of the system interrupts 64 to 95. Writing a 0 has no effect. Texas Instruments Incorporated 325 . The SECR2 is shown in Figure 12-23 and described in Table 12-23. Reads return the enabled status (before enabling with the Enable Registers).21 System Interrupt Status Enabled/Clear Register 2 (SECR2) The system interrupt status enabled/clear register 2 (SECR2) shows the pending enabled status of the system interrupts 32 to 63. -n = value after reset 0 Table 12-24. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. Figure 12-24. Writing a 0 has no effect. The SECR3 is shown in Figure 12-24 and described in Table 12-24. Figure 12-23.ti. -n = value after reset 0 Table 12-23. System Interrupt Status Enabled/Clear Register 2 (SECR2) 31 ENBL_STATUS[n] W-0 LEGEND: W = Write only.

326 ARM Interrupt Controller (AINTC) Copyright © 2011. System Interrupt Enable Set Register 1 (ESR1) 31 ENABLE[n] W-0 LEGEND: W = Write only. Read returns the enable value (0 = disabled. Figure 12-26. Reads return the enabled status (before enabling with the Enable Registers). System Interrupt Enable Set Register 1 (ESR1) Field Descriptions Bit 31-0 Field ENABLE[n] 0 1 Value Description System interrupt 0 to 31 enable. Writing a 0 has no effect. System interrupts that are not enabled do not interrupt the host. 12. W = Write only. -n = value after reset 5 4 W-0 0 ENBL_STATUS[n] Table 12-25. -n = value after reset 0 Table 12-26. Software can write to SECR4 to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. Write a 1 in bit position [n] to clear the status of the system interrupt n + 96.4.AINTC Registers www. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . There is one bit per system interrupt.ti. System Interrupt Status Enabled/Clear Register 4 (SECR4) 31 Reserved R-0 LEGEND: R = Read only.4. The ESR1 is shown in Figure 12-26 and described in Table 12-26. Writing a 0 has no effect.23 System Interrupt Status Enabled/Clear Register 4 (SECR4) The system interrupt status enabled/clear register 4 (SECR4) shows the pending enabled status of the system interrupts 96 to 100. 1 = enabled). Figure 12-25. There is one bit per system interrupt. The SECR4 is shown in Figure 12-25 and described in Table 12-25.24 System Interrupt Enable Set Register 1 (ESR1) The system interrupt enable set register 1 (ESR1) enables system interrupts 0 to 31 to trigger outputs.com 12. System Interrupt Status Enabled/Clear Register 4 (SECR4) Field Descriptions Bit 31-5 4-0 Field Reserved ENBL_STATUS[n] 0 1 Value 0 Description Reserved System interrupt enabled status and clearing of the system interrupts 96 to 100. Write a 1 in bit position [n] to set the enable for system interrupt n.

Read returns the enable value (0 = disabled. -n = value after reset 0 Table 12-27. The ESR3 is shown in Figure 12-28 and described in Table 12-28. System Interrupt Enable Set Register 2 (ESR2) Field Descriptions Bit 31-0 Field ENABLE[n] 0 1 Value Description System interrupt 32 to 63 enable. Figure 12-28. 1 = enabled). There is one bit per system interrupt. Figure 12-27. System interrupts that are not enabled do not interrupt the host. There is one bit per system interrupt. System Interrupt Enable Set Register 3 (ESR3) 31 ENABLE[n] W-0 LEGEND: W = Write only. System Interrupt Enable Set Register 3 (ESR3) Field Descriptions Bit 31-0 Field ENABLE[n] 0 1 Value Description System interrupt 64 to 95 enable.4.com AINTC Registers 12. The ESR2 is shown in Figure 12-27 and described in Table 12-27. SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011. Writing a 0 has no effect.4.26 System Interrupt Enable Set Register 3 (ESR3) The system interrupt enable set register 3 (ESR3) enables system interrupts 64 to 95 to trigger outputs. Read returns the enable value (0 = disabled. -n = value after reset 0 Table 12-28.ti.www. 1 = enabled). Writing a 0 has no effect. Write a 1 in bit position [n] to set the enable for system interrupt n + 64. System interrupts that are not enabled do not interrupt the host. Texas Instruments Incorporated 327 . System Interrupt Enable Set Register 2 (ESR2) 31 ENABLE[n] W-0 LEGEND: W = Write only. Write a 1 in bit position [n] to set the enable for system interrupt n + 32.25 System Interrupt Enable Set Register 2 (ESR2) The system interrupt enable set register 2 (ESR2) enables system interrupts 32 to 63 to trigger outputs. 12.

The ESR4 is shown in Figure 12-29 and described in Table 12-29.AINTC Registers www.ti. 1 = enabled). Write a 1 in bit position [n] to set the enable for system interrupt n + 96. 1 = enabled). The ECR1 is shown in Figure 12-30 and described in Table 12-30. System interrupts that are not enabled do not interrupt the host.27 System Interrupt Enable Set Register 4 (ESR4) The system interrupt enable set register 4 (ESR4) enables system interrupts 96 to 100 to trigger outputs. System interrupts that are not enabled do not interrupt the host. System Interrupt Enable Set Register 4 (ESR4) 31 Reserved R-0 LEGEND: R = Read only. -n = value after reset 0 Table 12-30.com 12. 328 ARM Interrupt Controller (AINTC) Copyright © 2011.4. -n = value after reset 5 4 ENABLE[n] W-0 0 Table 12-29. Writing a 0 has no effect. Figure 12-29. There is one bit per system interrupt. Writing a 0 has no effect. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Read returns the enable value (0 = disabled. System Interrupt Enable Clear Register 1 (ECR1) Field Descriptions Bit 31-0 Field DISABLE[n] 0 1 Value Description System interrupt 0 to 31 disable. System Interrupt Enable Clear Register 1 (ECR1) 31 DISABLE[n] W-0 LEGEND: W = Write only. Figure 12-30.28 System Interrupt Enable Clear Register 1 (ECR1) The system interrupt enable clear register 1 (ECR1) disables system interrupts 0 to 31 to map to channels. Write a 1 in bit position [n] to clear the enable for system interrupt n. There is one bit per system interrupt.4. 12. Read returns the enable value (0 = disabled. W = Write only. System Interrupt Enable Set Register 4 (ESR4) Field Descriptions Bit 31-5 4-0 Field Reserved ENABLE[n] 0 1 Value 0 Description Reserved System interrupt 96 to 100 enable.

-n = value after reset 0 Table 12-32. Writing a 0 has no effect. System interrupts that are not enabled do not interrupt the host.30 System Interrupt Enable Clear Register 3 (ECR3) The system interrupt enable clear register 3 (ECR3) disables system interrupts 64 to 95 to map to channels.www. System Interrupt Enable Clear Register 3 (ECR3) Field Descriptions Bit 27-0 Field DISABLE[n] 0 1 Value Description System interrupt 64 to 95 disable. System Interrupt Enable Clear Register 2 (ECR2) 31 DISABLE[n] W-0 LEGEND: W = Write only. -n = value after reset 0 Table 12-31. Texas Instruments Incorporated 329 .29 System Interrupt Enable Clear Register 2 (ECR2) The system interrupt enable clear register 2 (ECR2) disables system interrupts 32 to 63 to map to channels. There is one bit per system interrupt. 12.4.com AINTC Registers 12. System interrupts that are not enabled do not interrupt the host.4. Read returns the enable value (0 = disabled. 1 = enabled). There is one bit per system interrupt. Figure 12-31. The ECR2 is shown in Figure 12-31 and described in Table 12-31. System Interrupt Enable Clear Register 3 (ECR3) 31 DISABLE[n] W-0 LEGEND: W = Write only. 1 = enabled). Read returns the enable value (0 = disabled. Write a 1 in bit position [n] to clear the enable for system interrupt n + 32.ti. SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011. Figure 12-32. The ECR3 is shown in Figure 12-32 and described in Table 12-32. Write a 1 in bit position [n] to clear the enable for system interrupt n + 64. System Interrupt Enable Clear Register 2 (ECR2) Field Descriptions Bit 31-0 Field DISABLE[n] 0 1 Value Description System interrupt 32 to 63 disable. Writing a 0 has no effect.

The CMRn is shown in Figure 12-34 and described in Table 12-34. Write a 1 in bit position [n] to clear the enable for system interrupt n + 96. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Channel Map Registers (CMRn) Field Descriptions Bit 31-24 23-16 15-8 7-0 Field CHNL_NPLUS3 CHNL_NPLUS2 CHNL_NPLUS1 CHNL_N Value 0-FFh 0-FFh 0-FFh 0-FFh Description Sets the host interrupt for channel N + 3. System interrupts that are not enabled do not interrupt the host. Figure 12-33. System Interrupt Enable Clear Register 4 (ECR4) 31 Reserved R-0 LEGEND: R = Read only. 1 = enabled). 12. There is one register per 4 system interrupts. Sets the host interrupt for channel N + 1.31 System Interrupt Enable Clear Register 4 (ECR4) The system interrupt enable clear register 4 (ECR4) disables system interrupts 96 to 100 to map to channels. -n = value after reset 8 7 CHNL_N R/W-0 24 23 CHNL_NPLUS2 R/W-0 0 16 Table 12-34.4. Figure 12-34. Sets the host interrupt for channel N + 2. Writing a 0 has no effect.4.com 12. -n = value after reset 5 4 DISABLE[n] W-0 0 Table 12-33. (N ranges from 0 to 100). System Interrupt Enable Clear Register 4 (ECR4) Field Descriptions Bit 31-5 4-0 Field Reserved DISABLE[n] 0 1 Value 0 Description Reserved System interrupt 96 to 100 disable. Channel Map Registers (CMRn) 31 CHNL_NPLUS3 R/W-0 15 CHNL_NPLUS1 R/W-0 LEGEND: R/W = Read/Write.ti.AINTC Registers www.32 Channel Map Registers (CMR0-CMR25) The channel map registers (CMR0-CMR25) define the channel for each system interrupt. The ECR4 is shown in Figure 12-33 and described in Table 12-33. Sets the channel for the system interrupt N. W = Write only. 330 ARM Interrupt Controller (AINTC) Copyright © 2011. There is one bit per system interrupt. Read returns the enable value (0 = disabled.

Figure 12-36. Host Interrupt Prioritized Index Register 1 (HIPIR1) 31 NONE R-1 15 Reserved R-0 LEGEND: R = Read only. The HIPIR1 is shown in Figure 12-35 and described in Table 12-35. -n = value after reset 10 9 PRI_INDX R-0 30 Reserved R-0 0 16 Table 12-35. -n = value after reset 10 9 PRI_INDX R-0 30 Reserved R-0 0 16 Table 12-36. Host Interrupt Prioritized Index Register 1 (HIPIR1) Field Descriptions Bit 31 30-10 9-0 Field NONE Reserved PRI_INDX Value 0-1 0 0-3FFh Description No Interrupt is pending. Texas Instruments Incorporated 331 .34 Host Interrupt Prioritized Index Register 2 (HIPIR2) The host interrupt prioritized index register 2 (HIPIR2) shows the highest priority current pending interrupt for the IRQ interrupt. Host Interrupt Prioritized Index Register 2 (HIPIR2) Field Descriptions Bit 31 30-10 9-0 Field NONE Reserved PRI_INDX Value 0-1 0 0-3FFh Description No Interrupt is pending.4. Host Interrupt Prioritized Index Register 2 (HIPIR2) 31 NONE R-1 15 Reserved R-0 LEGEND: R = Read only. Figure 12-35. Reserved Interrupt number of the highest priority pending interrupt for IRQ host interrupt. The HIPIR2 is shown in Figure 12-36 and described in Table 12-36. Reserved Interrupt number of the highest priority pending interrupt for FIQ host interrupt. SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011.www. 12.4.com AINTC Registers 12.ti.33 Host Interrupt Prioritized Index Register 1 (HIPIR1) The host interrupt prioritized index register 1 (HIPIR1) shows the highest priority current pending interrupt for the FIQ interrupt.

Host Interrupt Nesting Level Register 2 (HINLR2) Field Descriptions Bit 31 30-9 8-0 Field OVERRIDE Reserved NEST_LVL Value 0-1 0 0-1FFh Description Reads return 0. The HINLR2 is shown in Figure 12-38 and described in Table 12-38. unless the OVERRIDE is set and then the write data is used.com 12. Figure 12-38. Figure 12-37. unless the OVERRIDE is set and then the write data is used. -n = value after reset 9 8 NEST_LVL R/W-100h 30 Reserved R-0 0 16 Table 12-38. Writes of a 1 override the auto updating of the NEST_LVL and use the write data.35 Host Interrupt Nesting Level Register 1 (HINLR1) The host interrupt nesting level register 1 (HINLR1) displays and controls the nesting level for FIQ host interrupt. R = Read only. Writes set the nesting level for the FIQ host interrupt. Writes set the nesting level for the IRQ host interrupt. The nesting level controls which channel and lower priority channels are nested. In auto mode the value is updated internally.AINTC Registers www. Reserved Reads return the current nesting level for the IRQ host interrupt.4. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . The HINLR1 is shown in Figure 12-37 and described in Table 12-37.4. The nesting level controls which channel and lower priority channels are nested. -n = value after reset 9 8 NEST_LVL R/W-100h 30 Reserved R-0 0 16 Table 12-37. Host Interrupt Nesting Level Register 1 (HINLR1) 31 OVERRIDE W-0 15 Reserved R-0 LEGEND: R/W = Read/Write.36 Host Interrupt Nesting Level Register 2 (HINLR2) The host interrupt nesting level register 2 (HINLR2) displays and controls the nesting level for IRQ host interrupt. W = Write only. Host Interrupt Nesting Level Register 2 (HINLR2) 31 OVERRIDE W-0 15 Reserved R-0 LEGEND: R/W = Read/Write.ti. R = Read only. Host Interrupt Nesting Level Register 1 (HINLR1) Field Descriptions Bit 31 30-9 8-0 Field OVERRIDE Reserved NEST_LVL Value 0-1 0 0-1FFh Description Reads return 0. 332 ARM Interrupt Controller (AINTC) Copyright © 2011. 12. W = Write only. Writes of a 1 override the auto updating of the NEST_LVL and use the write data. In auto mode the value is updated internally. Reserved Reads return the current nesting level for the FIQ host interrupt.

www. Enable of FIQ FIQ is disabled.ti. The HIER is shown in Figure 12-39 and described in Table 12-39. Host Interrupt Enable Register (HIER) Field Descriptions Bit 31-2 1 Field Reserved IRQ 0 1 0 FIQ 0 1 Value 0 Description Reserved Enable of IRQ IRQ is disabled. IRQ is enabled.com AINTC Registers 12.4. These bits are updated when writing to the host interrupt enable indexed set register (HIEISR) and the host interrupt disable indexed clear register (HIDISR). FIQ is enabled. Texas Instruments Incorporated 333 . There is one bit per host interrupt. These work separately from the global enables. R = Read only. Figure 12-39. -n = value after reset 2 1 IRQ R/W-0 0 FIQ R/W-0 16 Table 12-39. Host Interrupt Enable Register (HIER) 31 Reserved R-0 15 Reserved R-0 LEGEND: R/W = Read/Write.37 Host Interrupt Enable Register (HIER) The host interrupt enable register (HIER) enables or disables individual host interrupts (FIQ and IRQ). SPRUH77A – December 2011 Submit Documentation Feedback ARM Interrupt Controller (AINTC) Copyright © 2011.

Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .39 Host Interrupt Prioritized Vector Register 2 (HIPVR2) The host interrupt prioritized vector register 2 (HIPVR2) shows the interrupt vector address of the highest priority interrupt pending for IRQ host interrupt. Figure 12-40.4. -n = value after reset 0 Table 12-41. 334 ARM Interrupt Controller (AINTC) Copyright © 2011.38 Host Interrupt Prioritized Vector Register 1 (HIPVR1) The host interrupt prioritized vector register 1 (HIPVR1) shows the interrupt vector address of the highest priority interrupt pending for FIQ host interrupt. Figure 12-41. 12. The HIPVR1 is shown in Figure 12-40 and described in Table 12-40.4. Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions Bit 31-0 Field ADDR Value 0-FFFF FFFFh Description The currently highest priority interrupt vector address across for the IRQ host interrupt. -n = value after reset 0 Table 12-40.ti. Host Interrupt Prioritized Vector Register 2 (HIPVR2) 31 ADDR R-0 LEGEND: R = Read only.com 12. The HIPVR2 is shown in Figure 12-41 and described in Table 12-41. Host Interrupt Prioritized Vector Register 1 (HIPVR1) 31 ADDR R-0 LEGEND: R = Read only. Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions Bit 31-0 Field ADDR Value 0-FFFF FFFFh Description The currently highest priority interrupt vector address across for the FIQ host interrupt.AINTC Registers www.

................................................................ 336 DSP Wake Up ............................................... 337 SPRUH77A – December 2011 Submit Documentation Feedback Boot Considerations Copyright © 2011........ Texas Instruments Incorporated 335 .............2 Introduction .................................................Chapter 13 SPRUH77A – December 2011 Boot Considerations Topic ................................................................................. Page 13.........................................................1 13......

Introduction www. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .com 13. when device reset is deasserted. all boot modes utilize the internal ARM ROM.1 Introduction This device supports a variety of boot modes through an internal ARM ROM bootloader. which is part of the system configuration (SYSCFG) module. therefore.ti. a list of boot pins used. and the complete list of supported boot modes. This device does not support dedicated hardware boot modes. The input states of the BOOT pins are sampled and latched into the BOOTCFG register. Boot mode selection is determined by the values of the BOOT pins. 336 Boot Considerations Copyright © 2011. The following boot modes are supported: • NAND Flash boot – 8-bit NAND – 16-bit NAND • NOR Flash boot – NOR Direct boot (8-bit or 16-bit) – NOR Legacy boot (8-bit or 16-bit) – NOR AIS boot (8-bit or 16-bit) • HPI boot • I2C0/I2C1 boot – EEPROM (Master Mode) – External Host (Slave Mode) • SPI0/SPI1 boot – Serial Flash (Master Mode) – Serial EEPROM (Master Mode) – External Host (Slave Mode) • UART0/1/2 boot – External Host • MMC/SD0 boot See Using the OMAP-L132/L138 Bootloader Application Report (SPRAB41) for more details on the ROM Boot Loader.

the DSP intializes the ARM296 so that it can execute the ARM ROM bootloader. Write a 83E7 0B13h to the KICK0R register in the SYSCFG module.MDCTL15 to release the DSP local reset controlled by the PSC module. Disabling/enabling clocks to the DSP module at any other time can be independently controlled by the PSC module alone. The steps to release the DSP reset by the SYSCFG module (Steps 1-3) are only required at device reset/system reset/warm reset. NOTE: Step 8 can also be combined with Step 4. Upon successful wake up. 4. You can write a 103h to the PSC0. SPRUH77A – December 2011 Submit Documentation Feedback Boot Considerations Copyright © 2011.PTSTAT) for power transition sequence completion.com DSP Wake Up 13. Perform the following steps to wake up the DSP: 1. Guidelines to enable/disable clocks for power management are provided in the Power Management chapter. 6. 2. Write a 1 to the LRST bit in PSC0.MDSTAT15) to change to 3h.2 DSP Wake Up Following deassertion of device reset. Write a 95A4 F1E0h to the KICK1R register in the SYSCFG module. 8. Check (poll for 0) the GOSTAT[1] bit in the power domain transition status register (PSC0. 3.PTCMD) to start the state transition sequence for the DSP module. The least-significant bits of the boot address are fixed at 0. The module is only safely in the new state after the STATE bit field changes to reflect the new state. the ARM places the DSP in a reset and clock gated (SwRstDisable) state that is controlled by the LPSC and the SYSCFG modules.ti. 7. Write the truncated DSP boot address vector to the DSP_ISTP_RST_VAL field in the host 1 configuration register (HOST1CFG) of the SYSCFG module. Write a 3h to the NEXT bit in the DSP local power sleep controller (LPSC) module control register (PSC0. Texas Instruments Incorporated 337 . Write a 1 to the GO[1] bit (DSP subsystem is part of the PD_DSP domain) in the power domain transition command register (PSC0.MDCTL15 in Step 4 to release the DSP local reset and transition it from a SwRstDisable to Enable state.MDCTL15) to prepare the DSP module for an enable transition (to enable the clocks and all transitioning from the SwRstDisable state to Enable state). Wait for the STATE bit field in the DSP LPSC module status register (PSC0. The domain is only safely in the new state after the GOSTAT[1] bit is cleared to 0.www. 5.

338 Boot Considerations Copyright © 2011. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

SPRUH77A – December 2011 Submit Documentation Feedback Programmable Real-Time Unit Subsystem (PRUSS) Copyright © 2011. Texas Instruments Incorporated 339 . • A Switched Central Resource (SCR) for connecting the various internal and external masters to the resources inside the PRUSS. • An interrupt controller (INTC) for handling system interrupt events.Chapter 14 SPRUH77A – December 2011 Programmable Real-Time Unit Subsystem (PRUSS) The Programmable Real-Time Unit Subsystem (PRUSS) consists of: • Two programmable real-time units (PRU0 and PRU1) and their associated memories. The INTC also supports posting events back to the device level host CPU. The PRUSS documentation (peripheral guide) is on the external wiki: Programmable_Realtime_Unit. The PRUs are optimized for performing embedded tasks that require manipulation of packed memory-mapped data structures. handling of system events that have tight realtime constraints and interfacing with systems external to the device. The two PRUs can operate completely independently or in coordination with each other. The PRUs can also work in coordination with the device level host CPU. This is determined by the nature of the program which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available between the two PRUs and the device level host CPU.

340 Programmable Real-Time Unit Subsystem (PRUSS) Copyright © 2011. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .

............................................................................ Introduction ........4 342 344 372 377 SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011.....................................................................................................................................2 15..................... Architecture ......................... Supported Use Cases ............................................................................................................................................ Topic ........................ Texas Instruments Incorporated 341 ................... Page 15......Chapter 15 SPRUH77A – December 2011 DDR2/mDDR Memory Controller This chapter describes the DDR2/mobile DDR (mDDR) memory controller.....3 15..................... Registers ..........1 15.................................

SDR SDRAM.1 Introduction 15. and 2048 • SDRAM auto-initialization • Self-refresh mode • Partial array self-refresh (for mDDR) • Power-down mode • Prioritized refresh • Programmable refresh rate and backlog counter • Programmable timing parameters • Little-endian mode 342 DDR2/mDDR Memory Controller Copyright © 2011. and 5 – mDDR: 2 and 3 • Internal banks: – DDR2: 1.Introduction www. 1024. The DDR2/mDDR memory is the major memory location for program and data storage.1 Purpose of the Peripheral The DDR2/mDDR memory controller is used to interface with JESD79D-2 standard compliant DDR2 SDRAM devices and JESD209 standard mobile DDR (mDDR) SDRAM devices. 15. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . and asynchronous memories are not supported.ti. 4. 3. 512.1. and 8 – mDDR: 1.com 15. and 4 • Burst length: 8 • Burst type: sequential • 1 CS signal • Page sizes: 256. 2.1. 2. Memories types such as DDR1 SDRAM. SBSRAM. 4.2 Features The DDR2/mDDR memory controller supports the following features: • JESD79D-2 standard compliant DDR2 SDRAM • JESD209 standard compliant mobile DDR (mDDR) • Data bus width of 16 bits • CAS latencies: – DDR2: 2.

Texas Instruments Incorporated 343 . Data Paths to DDR2/mDDR Memory Controller CPU Master peripherals EDMA DDR2/mDDR memory controller SCR BUS BUS External DDR2/mDDR SDRAM 15.4 Supported Use Case Statement The DDR2/mDDR memory controller supports JESD79D-2 DDR2 SDRAM memories and the JESD209 mobile DDR (mDDR) SDRAM memories utilizing 16 bits of the DDR2/mDDR memory controller data bus. the on-die terminating resistors of the DDR2/mDDR SDRAM device must be disabled by tying the ODT input pin of the DDR2/mDDR SDRAM to ground. and the CPU can access the DDR2/mDDR memory controller through the switched central resource (SCR). Figure 15-1 displays the general data paths to on-chip peripherals and external DDR2/mDDR SDRAM. SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011.1. EDMA.ti.5 Industry Standard(s) Compliance Statement The DDR2/mDDR memory controller is compliant with the JESD79D-2 DDR2 SDRAM standard and the JESD209 mobile DDR (mDDR) standard with the following exception: • On-Die Termination (ODT). Furthermore.www.3 Functional Block Diagram The DDR2/mDDR memory controller is the main interface to external DDR2/mDDR memory. Master peripherals. Figure 15-1.1. The DDR2/mDDR memory controller does not include any on-die terminating resistors.com Introduction 15. See Section 15.1.3 for more details. 15.

Architecture www. These two clocks operate at a frequency of 2X_CLK/2. if a 138-MHz DDR2/mDDR interface clock (DDR_CLK) is desired.2. VCLK and 2X_CLK (Figure 15-2).2. and many SDRAM timing parameters.2 Architecture This section describes the architecture of the DDR2/mDDR memory controller as well as how it is structured and how it works within the context of the system-on-a-chip. VCLK is a divided-down version of the PLL0 clock.1 Clock Control The DDR2/mDDR memory controller receives two input clocks from internal clock sources. meaning VCLK is clocked at a frequency of PLL0/2. 2X_CLK should be configured to clock at the frequency of the desired data rate. The clock from PLLC1 is not divided before reaching 2X_CLK. CAS latency. DDR2/mDDR Memory Controller Clock Block Diagram DDR_CLK DDR_CLK DDR2 memory controller VCLK /1 2X_CLK PLLC1 /2 PLLC0 344 DDR2/mDDR Memory Controller Copyright © 2011.1 Clock Source VCLK and 2X_CLK are sourced from two independent PLLs (Figure 15-2). DDR_CLK and DDR_CLK are the two output clocks of the DDR2/mDDR memory controller providing the interface clock to the DDR2/mDDR SDRAM memory. or stated similarly. it should operate at twice the frequency of the desired DDR2/mDDR memory clock. 2X_CLK is the PLL1 clock. The DDR2/mDDR memory controller can gluelessly interface to most standard DDR2/mDDR SDRAM devices and supports such features as self-refresh mode and prioritized refresh. it provides flexibility through programmable parameters such as the refresh rate. 15. For example. then PLLC1 must be configured to generate a 276-MHz clock on 2X_CLK. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .1.com 15. VCLK is sourced from PLL controller 0 (PLLC0) and 2X_CLK is sourced from PLL controller 1 (PLLC1). This divider is fixed at 2. Figure 15-2. PLLC1 should be configured to supply 2X_CLK at the desired frequency.ti. In addition.3 provides a detailed example of interfacing the DDR2/mDDR memory controller to a common DDR2/mDDR SDRAM device. Section 15. 15. VCLK is clocked at a fixed divider ratio of PLL0. Also. The following sections include details on how to interface and properly configure the DDR2/mDDR memory controller to perform read and write operations to externally-connected DDR2/mDDR SDRAM devices.

The PLL multiplier is selected by programming registers within PLLC1.2. See Section 15. Figure 15-3. The address bus is 14-bits wide with an additional three bank address pins. The command FIFO. data strobe. The following features are included: • • • • • The maximum data bus is 16-bits wide.16 for proper clock stop procedures. One chip select signal and one clock enable signal. For information on supported clock frequencies.2 Clock Configuration The frequency of 2X_CLK is configured by selecting the appropriate PLL multiplier.1.www.2.2. and read FIFO described in Section 15. Command signals: Row and column address strobe. see the Device Clocking chapter and your device-specific data manual. This clock domain is clocked at the rate of the external DDR2/mDDR memory. NOTE: PLLC1 should be configured and a stable clock present on 2X_CLK before releasing the DDR2/mDDR memory controller from reset. The PLLC1 divider ration is fixed at 1.com Architecture 15.2.3 DDR2/mDDR Memory Controller Internal Clock Domains There are two clock domains within the DDR2/mDDR memory controller. and data mask. From this. DDR2/mDDR Memory Controller Signals DDR_CLK DDR_CLK DDR_CKE DDR2 memory controller DDR_CS DDR_WE DDR_RAS DDR_CAS DDR_DQM[1:0] DDR_DQS[1:0] DDR_BA[2:0] DDR_A[13:0] DDR_D[15:0] DDR_DQGATE0 DDR_DQGATE1 DDR_VREF 50 Ω DDR_ZP SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011. 15. Two differential output clocks driven by internal clock sources.2 Signal Descriptions The DDR2/mDDR memory controller signals are shown in Figure 15-3 and described in Table 15-1. write FIFO. The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped registers. Texas Instruments Incorporated 345 .6 are all on the VCLK domain. VCLK.2. 2X_CLK/2. To conserve power within the DDR2/mDDR memory controller. For information on programming the PLL controllers. see the Phase-Locked Loop Controller (PLLC) chapter.ti. MCLK. 15. write enable strobe.1. and 2X_CLK may be stopped. The two clock domains are driven by VCLK and a divided-down by 2 version of 2X_CLK called MCLK. VCLK drives the interface to the peripheral bus.

Allows altering the contents of the mode register. Data mask: Active high. Route from DDR_DQGATE0 to DDR device and back to DDR_DQGATE1 with same constraints as used for DDR clock and data. Bank select: Output. Mode register set. 346 DDR2/mDDR Memory Controller Copyright © 2011. output mask signal for write data. Inputs the starting column address and begins the read operation. Chip select: Active low. Table 15-3 shows the signal truth table for the DDR2/mDDR SDRAM commands. No operation. The read operation is followed by a precharge. Column address strobe: Active low. Data: Bi-directional data bus. Precharge single command. Strobe Enable: Active high.com Table 15-1. command output. Power-down mode. O = Output. Deactivates (precharges) a single bank. Data strobe: Active high. DDR2/mDDR Memory Controller Signal Descriptions Pin DDR_CLK. Output with write data. Strobe Enable Delay: Loopback signal for timing adjustment (DQS gating). Inputs the starting column address and begins the read operation. The write operation is followed by a precharge.5% tolerance 1/16th watt resistor (49. Tie to ground via 50 ohm . output for write data. Clock enable: Active high. Row address strobe: Active low. command output. bi-directional signals. Extended Mode Register set. Voltage reference input: Voltage reference input for the SSTL_18 I/O buffers. Output drive strength reference: Reference output for drive strength calibration of N and P channel outputs.2. Write enable strobe: Active low. DDR2/mDDR SDRAM Commands Command ACTV DCAB DEAC DESEL EMRS MRS NOP Power Down READ READ with autoprecharge REFR SLFREFR WRT WRT with autoprecharge Function Activates the selected bank and row. Precharge all command. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . pwr = power 15. defining which bank a given command is applied. Table 15-2.9 ohm . Inputs the starting column address and begins the write operation. Device Deselect. Deactivates (precharges) all banks. Inputs the starting column address and begins the write operation.Architecture www. Note even in the case of mDDR an external resistor divider connected to this pin is necessary.3 Protocol Description(s) The DDR2/mDDR memory controller supports the DDR2/mDDR SDRAM commands listed in Table 15-2. command output. Allows altering the contents of the mode register. Address: Address bus.5% tolerance is acceptable). DDR_ZP I/O/Z DDR_VREF (1) pwr Legend: I = input. Input for read data. input with read data.ti. Autorefresh cycle. Self-refresh mode. Z = high impedance. DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RAS DDR_CAS DDR_DQM[1:0] DDR_DQS[1:0] DDR_BA[2:0] DDR_A[13:0] DDR_D[15:0] DDR_DQGATE0 DDR_DQGATE1 Type O/Z O/Z O/Z O/Z O/Z O/Z O/Z I/O/Z O/Z O/Z I/O/Z O/Z I/O/Z (1) Description Clock: Differential clock outputs.

Truth Table for DDR2/mDDR SDRAM Commands DDR2/mDDR SDRAM: DDR2/mDDR memory controller: ACTV DCAB DEAC MRS EMRS READ READ with precharge WRT WRT with precharge REFR SLFREFR entry SLFREFR exit NOP DESEL Power Down entry Power Down exit CKE DDR_CKE Previous Cycles H H H H H H H H H H H L Current Cycle H H H H H H H H H H L H DDR_CS L L L L L L L L L L L H L H H H X X L L H H L L H H L DDR_RAS L L L L L H H H H L L X H H X X H X H DDR_CAS H H H L L L L L L L L X H H X X H X H DDR_WE H L L L L H H L L H H X H H X X H X H DDR_BA[2:0] Bank X Bank BA BA BA BA BA BA X X X X X X X X X X X X OP Code OP Code Column Address Column Address Column Address Column Address X X X X X X X X X X L H L H X X X X X X X X X X DDR_A[13:11.ti. 9:0] DDR_A[10] CS RAS CAS WE BA[2:0] A[13:11.www. Texas Instruments Incorporated 347 .com Architecture Table 15-3. 9:0] A10 Row Address H L SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011.

See Section 15.2.3. Figure 15-4. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . Page information is always invalid before and after a REFR command. Refresh Command DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:0] DDR_BA[2:0] DDR_DQM[1:0] RFR 348 DDR2/mDDR Memory Controller Copyright © 2011. the DDR2/mDDR memory controller begins performing refreshes at a rate defined by the refresh rate (RR) bit in the SDRAM refresh control register (SDRCR). Following the DCAB command.ti.Architecture www. thus. Autorefresh commands may not be disabled within the DDR2/mDDR memory controller. ensuring the deactivation of all CE spaces and banks selected. REFR is automatically preceded by a DCAB command.1 Refresh Mode The DDR2/mDDR memory controller issues refresh commands to the DDR2/mDDR SDRAM memory (Figure 15-4).7 for more details on REFR command scheduling. This type of refresh cycle is often called autorefresh.com 15.2. a refresh cycle always forces a page miss.

DDR2/mDDR SDRAMs also require this cycle prior to a refresh (REFR) and mode set register commands (MRS and EMRS). During a DCAB command. Figure 15-5 shows the timing diagram for a DCAB command.ti.www.com Architecture 15. Texas Instruments Incorporated 349 . DDR_A[10] is driven high to ensure the deactivation of all banks.2. DCAB Command DCAB DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:11.3. Figure 15-5.2 Deactivation (DCAB and DEAC) The precharge all banks command (DCAB) is performed after a reset to the DDR2/mDDR memory controller or following the initialization sequence. 9:0] DDR_A[10] DDR_BA[2:0] DDR_DQM[1:0] SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011.

Figure 15-6 shows the timings diagram for a DEAC command.Architecture www. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .com The DEAC command closes a single bank of memory specified by the bank select signals. 9:0] DDR_A[10] DDR_BA[2:0] DDR_DQM[1:0] 350 DDR2/mDDR Memory Controller Copyright © 2011. DEAC Command DEAC DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:11.ti. Figure 15-6.

ACTV Command DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE ACTV DDR_A[13:0] ROW DDR_BA[2:0] BANK DDR_DQM[1:0] SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011. Texas Instruments Incorporated 351 .3 Activation (ACTV) The DDR2/mDDR memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory. allowing future accesses (reads or writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of DDR_A[13:0] selects the row.com Architecture 15. a delay of tRCD is incurred before a read or write command is issued.www. Figure 15-7. Reads or writes to the currently active row and bank of memory can achieve much higher throughput than reads or writes to random areas because every time a new row is accessed. When the DDR2/mDDR memory controller issues an ACTV command. Figure 15-7 shows an example of an ACTV command.ti.3. The ACTV command opens a row of memory. the ACTV command must be issued and a delay of tRCD incurred.2.

If additional accesses are pending. 4. DDR_CAS drives low.3. Figure 15-8. DDR_WE and DDR_RAS remain high. The DDR2/mDDR memory controller always configures the memory to have an additive latency of 0.2. The READ command initiates a burst read operation to an active row.com 15. depending on the scheduling result. so read latency equals CAS latency. If additional accesses are not pending to the DDR2/mDDR memory controller. Furthermore. DDR2/mDDR READ Command DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE COL DDR_A[13:0] DDR_BA[2:0] BANK DDR_A[10] DDR_DQM[1:0] CAS Latency DDR_D[15:0] D0 D1 D2 D3 D4 D5 D6 D7 DDR_DQS[1:0] 352 DDR2/mDDR Memory Controller Copyright © 2011. The DDR2/mDDR memory controller uses a burst length of 8. During the READ command. Read latency is equal to CAS latency plus additive latency. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .Architecture www. and the bank address is driven on DDR_BA[2:0]. or 5. the DDR2/mDDR memory controller can terminate the read burst and start a new read burst.4 READ Command Figure 15-8 shows the DDR2/mDDR memory controller performing a read burst from DDR2/mDDR SDRAM.ti. 3. Since the default burst size is 8. and has a programmable CAS latency of 2. the DDR2/mDDR memory controller returns 8 pieces of data for every read command. the DDR2/mDDR memory controller does not issue a DAB/DEAC command until page information becomes invalid. the read burst completes and the unneeded data is disregarded. the column address is driven on DDR_A[13:0]. The CAS latency is three cycles in Figure 15-8.

Figure 15-9. the DDR2/mDDR memory controller can: • Mask out the additional data using DDR_DQM outputs • Terminate the write burst and start a new write burst The DDR2/mDDR memory controller does not perform the DEAC command until page information becomes invalid.ti. always.2. a write latency is incurred.com Architecture 15. Figure 15-9 shows the timing for a DDR2 write on the DDR2/mDDR memory controller. Following the WRT command. The use of the DDR_DQM outputs allows byte and halfword writes to be executed. SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011. For DDR2. depending on the scheduling result and the pending commands. If the transfer request is for less than 8 words.www. For mDDR. write latency is always equal to 1 cycle. For mDDR. DDR2/mDDR WRT Command DDR_CLK DDR_CLK Sample Write Latency DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:0] COL DDR_BA[2:0] DDR_A[10] BANK DDR_DQM[1:0] DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8 DDR_D[15:0] D0 D1 D2 D3 D4 D5 D6 D7 DDR_DQS[1:0] NOTE: This diagrams shows write latency for DDR2. write latency is equal to CAS latency minus 1 cycles. All writes have a burst length of 8. write latency is equal to 1 cycle.5 Write (WRT) Command Prior to a WRT command. Texas Instruments Incorporated 353 . the desired bank and row are activated by the ACTV command.3.

These registers control burst type. Only little-endian format is supported. Table 15-4 summarizes the addressable memory ranges on the DDR2/mDDR memory controller.ti.13 for more information. differential strobe etc. The external memory is always right aligned on the data bus.6 Mode Register Set (MRS and EMRS) DDR2/mDDR SDRAM contains mode and extended mode registers that configure the DDR2/mDDR memory for operation.Architecture www. burst length.2.2. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . single-ended strobe. Figure 15-11 shows the byte lanes used on the DDR2/mDDR memory controller. Figure 15-10. Figure 15-10 shows the timing for an MRS and EMRS command. CAS latency. The DDR2/mDDR memory controller programs the mode and extended mode registers of the DDR2/mDDR memory by issuing MRS and EMRS commands.4 Memory Width and Byte Alignment The DDR2/mDDR memory controller supports memory widths of 16 bits.2. See Section 15. When the MRS or EMRS command is executed.3. DLL enable/disable (on DDR2/mDDR device).com 15. Byte Alignment DDR2 memory controller data bus DDR_D[15:8] DDR_D[7:0] 16-bit memory device 354 DDR2/mDDR Memory Controller Copyright © 2011. the value on DDR_BA[2:0] selects the mode register to be written and the data on DDR_A[13:0] is loaded into the register. The DDR2/mDDR memory controller only issues MRS and EMRS commands during the DDR2/mDDR memory controller initialization sequence. DDR2/mDDR MRS and EMRS Command MRS/EMRS DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:0] COL DDR_BA[2:0] BANK 15. Table 15-4. Addressable Memory Ranges Memory Width ×16 Maximum addressable bytes per CS space 512 Mbytes Description Halfword address Figure 15-11.

row. and it uses the logical address to generate a row. 1 bank 2 banks 4 banks 8 banks Defines the page size of each page in the external DDR2/mDDR memory. and bank address bits is determined by the PAGESIZE.5 Address Mapping The memory controller views the DDR2/mDDR SDRAM device as one continuous block of memory. The memory controller receives memory access requests with a 32-bit logical address. ROWSIZE.com Architecture 15. Configuration Register Fields for Address Mapping Bit Field IBANK 0 1h 2h 3h PAGESIZE 0 1h 2h 3h ROWSIZE 0 1h 2h 3h 4h 5h Bit Value Bit Description Defines the number of internal banks in the external DDR2/mDDR memory. Special address mapping is typically used only with mDDR devices using partial array self-refresh. In this case. The memory controller supports two address mapping schemes: normal address mapping and special address mapping. the memory controller operates with special address mapping. column. the number of column and bank address bits is determined by the IBANK and PAGESIZE fields in SDCR. When the internal bank position (IBANKPOS) bit in the SDRAM configuration register (SDCR) is cleared. the memory controller operates with normal address mapping. and IBANK fields.ti. 256 words (requires 8 column address bits) 512 words (requires 9 column address bits) 1024 words (requires 10 column address bits) 2048 words (requires 11 column address bits) Defines the row size of each row in the external DDR2/mDDR memory 512 (requires 9 row address bits) 1024 (requires 10 row address bits) 2048 (requires 11 row address bits) 4096 (requires 12 row address bits) 8192 (requires 13 row address bits) 16384 (requires 14 row address bits) SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011. See Table 15-5 for a descriptions of these bit fields. The ROWSIZE field is in the SDRAM configuration register 2 (SDCR2). The number of row address bits is determined by the number of valid address pins for the device and does not need to be set in a register. and bank address for accessing the DDR2/mDDR SDRAM device. Texas Instruments Incorporated 355 . Table 15-5.www. In this case. the number of column. When IBANKPOS is set to 1.2.

2. and banks into the device memory-map. and bank bits for combinations of IBANK and PAGESIZE values. The DDR2/mDDR memory controller logical address always contains up to 14 row address bits. Table 15-6. thus the DDR2/mDDR memory controller appropriately shifts the address during row and column address selection.ti. Figure 15-12 shows how this address-mapping scheme organizes the DDR2/mDDR SDRAM rows. Note that the DDR2/mDDR memory controller never opens more than one page per bank. column. Logical Address-to-DDR2/mDDR SDRAM Address Map for 16-bit SDRAM SDCR Bit IBANK 0 1 2h 3h 0 1 2h 3h 0 1 2h 3h 0 1 2h 3h PAGESIZE 0 0 0 0 1 1 1 1 2h 2h 2h 2h 3h 3h 3h 3h nrb=14 nrb=14 nbb=3 nrb=14 nbb=2 nrb=14 nrb=14 nbb=1 nrb=14 nbb=3 ncb=11 ncb=11 ncb=11 ncb=11 nrb=14 nbb=2 nrb=14 nrb=14 nbb=1 nrb=14 nbb=3 ncb=10 ncb=10 ncb=10 ncb=10 nrb=14 nbb=2 nrb=14 nrb=14 nbb=1 nrb=14 nbb=3 ncb=9 ncb=9 ncb=9 ncb=9 nrb=14 nbb=2 31 30 29 28 27 26 25 24 23 Logical Address 22 nrb=14 nbb=1 21:15 14 13 12 11 10 9 8:1 ncb=8 ncb=8 ncb=8 ncb=8 0 356 DDR2/mDDR Memory Controller Copyright © 2011. Table 15-6 show how the logical address bits map to the DDR2/mDDR SDRAM row. the DDR2/mDDR memory controller increments the column address as the logical address increments. this process looks as shown in Figure 15-13. This results in the maximum number of open pages when performing a linear access being equal to the number of banks. the DDR2/mDDR memory controller maximizes the number of activated banks for a linear access. whereas the number of column and bank bits are determined by the IBANK and PAGESIZE fields. The same DDR2/mDDR memory controller pins provide the row and column address to the DDR2/mDDR SDRAM.5. By traversing across banks while remaining on the same row/page. source address of the DDR2/mDDR memory controller to the DDR2/mDDR SDRAM row. Note that during a linear access. it moves onto the same page/row in the next bank. To the DDR2/mDDR SDRAM. columns. This movement continues until the same page has been accessed in all banks. and bank address bits. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . The DDR2/mDDR memory controller leaves the active row open until it becomes necessary to close it. When the DDR2/mDDR memory controller reaches a page/row boundary. the IBANK and PAGESIZE fields of SDCR control the mapping of the logical.Architecture www. column.com 15.1 Normal Address Mapping (IBANKPOS = 0) As stated in Table 15-5. This decreases the deactivate-reactivate overhead. Ending the current access is not a condition that forces the active DDR2/mDDR SDRAM row to be closed.

com Architecture Figure 15-12. bank 1 Row 1. bank 2 Row 1. bank 0 Row N. bank 1 Row N. 4 Col. Logical Address-to-DDR2/mDDR SDRAM Address Map Col. 3 Col. Texas Instruments Incorporated 357 . 2 Col. bank 0 Row 1. bank P NOTE: M is number of columns (as determined by PAGESIZE) minus 1. 1 Col. P is number of banks (as determined by IBANK) minus 1.www. SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011. bank P Row N. bank 2 Row 0. and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1. bank P Row 1. bank 1 Row 0. M−1 Col.ti. bank 2 Row N. 0 Col. bank 0 Row 0. M Row 0.

this case is only recommended to be used with Partial Array Self-refresh for mDDR SDRAM where performance may be traded-off for power savings. The memory controller then proceeds to the next bank in the device. row.ti.2 Special Address Mapping (IBANKPOS = 1) When the internal bank position (IBANKPOS) bit is set to 1. the PAGESIZE. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .5. Since. and bank address bits of the SDRAM device. and IBANK. Therefore. and bank address bits for all combinations of PAGESIZE. or 3 Source Address Row Address Number of row bits is defined by ROWSIZE: nrb = 9. in this address mapping scheme. the memory controller proceeds to the next page in the same bank.2. ROWSIZE. and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1. DDR2/mDDR SDRAM Column. P is number of banks (as determined by IBANK) minus 1.Architecture www. Address Mapping Diagram for 16-Bit SDRAM (IBANKPOS = 1) 31 Bank Address Number of bank bits is defined by IBANK nbb = 1. 10. and IBANK fields control the mapping of the logical source address of the memory controller to the column. 10. 11. 13. this scheme is lower in performance than the case when IBANKPOS is cleared to 0. Table 15-7. 9. ROWSIZE. or 11 1 358 DDR2/mDDR Memory Controller Copyright © 2011. the memory controller can keep only one bank open. the effect of the address-mapping scheme is that as the source address increments across an SDRAM page boundary. and Bank Access C C C o o o l l l 0 1 2 3 C o l M Bank 1 Row 0 Row 1 Row 2 Bank 0 Row 0 Row 1 Row 2 C C C o o o l l l 0 1 2 3 C o l M Bank 2 Row 0 Row 1 Row 2 C C C o o o l l l 0 1 2 3 C o l M Bank P Row 0 Row 1 Row 2 C C C o o o l l l 0 1 2 3 C o l M Row N Row N Row N Row N NOTE: M is number of columns (as determined by PAGESIZE) minus 1. 15. This sequence is shown in Figure 15-14 and Figure 15-15. When IBANKPOS is set to 1.com Figure 15-13. 12. or 14 Column Address Number of column bits is defined by PAGESIZE: ncb = 8. Row. 2. row. This movement along the same bank continues until all the pages have been accessed in the same bank. Table 15-7 shows which source address bits map to the SDRAM column.

Texas Instruments Incorporated 359 . bank 1 Row 3. bank 1 Row 2. Address Mapping Diagram (IBANKPOS = 1) Col. P is number of banks (as determined by IBANK) minus 1. SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011. 1 Col. bank P Row N. bank P Row 2. bank 1 Row N. 2 Col. 0 Col. M−1 Col. and N is number of rows (as determined by ROWSIZE) minus 1. bank 0 Row 3.www. bank P NOTE: M is number of columns (as determined by PAGESIZE) minus 1. bank 0 Row N. 4 Col. bank 0 Row 2. bank 1 Row 1. bank 0 Row 1. 3 Col.ti. M Row 1. bank P Row 3.com Architecture Figure 15-14.

and command and data schedulers.com Figure 15-15. P is number of banks (as determined by IBANK) minus 1. Table 15-8. the DDR2/mDDR memory controller makes use of a command FIFO. and N is number of rows (as determined by ROWSIZE) minus 1. Bank Access (IBANKPOS = 1) C C C o o o l l l 0 1 2 3 C o l M Bank 1 Row 0 Row 1 Row 2 Bank 0 Row 0 Row 1 Row 2 C C C o o o l l l 0 1 2 3 C o l M Bank 2 Row 0 Row 1 Row 2 C C C o o o l l l 0 1 2 3 C o l M Bank P Row 0 Row 1 Row 2 C C C o o o l l l 0 1 2 3 C o l M Row N Row N Row N Row N NOTE: M is number of columns (as determined by PAGESIZE) minus 1.Architecture www. Table 15-8 describes the purpose of each FIFO. SDRAM Column. Commands.ti.2.6 DDR2/mDDR Memory Controller Interface To move data efficiently from on-chip resources to external DDR2/mDDR SDRAM memory. Figure 15-16 shows the block diagram of the DDR2/mDDR memory controller FIFOs. a read FIFO. a write FIFO. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . The same peripheral bus is used to write and read data from external memory as well as internal memory-mapped registers. Row. write data. DDR2/mDDR Memory Controller FIFO Description FIFO Command Write Read Description Stores all commands coming from on-chip requestors Stores write data coming from on-chip requestors to memory Stores read data coming from memory to on-chip requestors Depth (64-bit doublewords) 7 11 17 360 DDR2/mDDR Memory Controller Copyright © 2011. 15. and read data arrive at the DDR2/mDDR memory controller parallel to each other.

If multiple commands have the highest priority. Typically. a given master issues commands on a single priority. Next. DDR2/mDDR Memory Controller FIFO Block Diagram Command FIFO Command/Data Scheduler Command to Memory Write FIFO Write Data to Memory Read FIFO Read Data from Memory Registers Command Data 15. Texas Instruments Incorporated 361 . each master may have one command ready for execution. Following this scheduling. EDMA transfer controller read and write ports are different masters. selects reads to rows already open. all of its commands will complete from oldest to newest. The DDR2/mDDR memory controller first reorders commands from each master based on the following rules: • Selects the oldest command (first command in the queue) • Selects a read before a write if: – The read is to a different block address (2048 bytes) than the write – The read has greater or equal priority The second bullet above may be viewed as an exception to the first bullet. then the DDR2/mDDR memory controller selects the oldest command. and command buses while hiding the overhead of opening and closing DDR2/mDDR SDRAM rows. • Selects the highest priority command from pending reads and writes to open rows. with the exception that a read may be advanced ahead of an older. Among all pending writes.com Architecture Figure 15-16.6.2. Command re-ordering takes place within the command FIFO. Advanced Concept The DDR2/mDDR memory controller performs command re-ordering and scheduling in an attempt to achieve efficient transfers with maximum throughput.ti. This means that for an individual master. The goal is to maximize the utilization of the data.www. SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011. the DDR2/mDDR memory controller examines each of the commands selected by the individual masters and performs the following reordering: • Among all pending reads. lower or equal priority write. selects writes to rows already open.1 Command Ordering and Scheduling. address.

6. which is the prevention of certain commands from being processed by the DDR2/mDDR memory controller. 4. To avoid these conditions. 2. Perform a dummy write to the DDR2/mDDR memory controller SDRAM status register. The EDMA peripheral does not need to implement the above workaround.com The DDR2/mDDR memory controller may now have a final read and write command. any read to the same location (or within 2048 bytes) as a previous write will complete in order 15.6. Refresh request resulting from the Refresh Need level of urgency being reached 4. Request to enter self-refresh mode The following results from the above scheduling algorithm: • All writes from a single master will complete in order • All reads from a single master will complete in order • From the same master. and refresh commands to DDR2/mDDR SDRAM memory.ti. when master B attempts to read the software message it may read stale data and therefore receive an incorrect message. write. the DDR2/mDDR memory controller can momentarily raises the priority of the oldest command in the command FIFO after a set number of transfers have been made. See your device-specific data manual for more information. Read request without a higher priority write (selected from above reordering algorithm) 3. Perform the required write. Besides commands received from on-chip resources. The DDR2/mDDR memory controller attempts to delay refresh commands as long as possible to maximize performance while meeting the SDRAM refresh requirements. if master A passes a software message via a buffer in DDR2/mDDR memory and does not wait for indication that the write completes.3 Possible Race Condition A race condition may exist when certain masters write data to the DDR2/mDDR memory controller. Indicate to master B that the data is ready to be read after completion of the read in step 3. 362 DDR2/mDDR Memory Controller Copyright © 2011. Perform a dummy read to the DDR2/mDDR memory controller SDRAM status register.Architecture www. otherwise the write command will be performed first.2. 3. For example. master A must wait for the write completion status from the DDR2/mDDR memory controller before indicating to master B that the data is ready to be read. Write request (selected from above reordering algorithm) 5. Refresh request resulting from Refresh May level of urgency being reached 6. In order to confirm that a write from master A has landed before a read from master B is performed. it must perform the following workaround: 1. the DDR2/mDDR memory controller also issues refresh commands. Refresh request resulting from the Refresh Must level of urgency being reached 2. 15. Command starvation results from the following conditions: • A continuous stream of high-priority read commands can block a low-priority write command • A continuous stream of DDR2/mDDR SDRAM commands to a row in an open bank can block commands to the closed row in the same bank. it adheres to the following rules: 1. The PR_OLD_COUNT bit in the peripheral bus burst priority register (PBBPR) sets the number of the transfers that must be made before the DDR2/mDDR memory controller will raise the priority of the oldest command. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .2 Command Starvation The reordering and scheduling rules listed above may lead to command starvation.2. The completion of the read in step 3 ensures that the previous write was done. If the Read FIFO is not full. If master A does not wait for indication that a write is complete. then the read command will be performed before the write command. The above workaround is required for all other peripherals. As the DDR2/mDDR memory controller issues read.

Whenever the refresh must level of urgency is reached. Refresh Urgency Levels Urgency Level Refresh May Refresh Release Refresh Need Refresh Must Description Backlog count is greater than 0. At this point.com Architecture 15. The SDRAM timing register 2 (SDTIMR2) programs the values of T_SXNR and T_SXRD. While in the self-refresh state. The value of T_CKE is defined in the SDRAM timing register 2 (SDTIMR2). This means the refresh backlog counter records the number of REFR commands the DDR2/mDDR memory controller currently has outstanding. a refresh backlog counter increments by 1. 15. Indicates there is a backlog of REFR commands. Backlog count is greater than 3. returning to the self-refresh state upon completion. SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011. the memory controller will not immediately start executing commands. it reloads with the value of the RR bit. When this backlog counter is greater than 7.8 Self-Refresh Mode Clearing the self refresh/low power (SR_PD) bit to 0 and then setting the low power mode enable (LPMODEN) bit to 1 in the SDRAM refresh control register (SDRCR) . it will wait T_SXNR + 1 clock cycles before issuing non-read/write commands and T_SXRD + 1 clock cycles before issuing read or write commands. Once the interval counter reaches zero. A refresh interval counter is loaded with the value of the RR bit field and decrements by 1 each cycle until it reaches zero. or when the SR_PD bit in SDRCR changed to 1. Backlog count is greater than 7. Backlog count is greater than 11. all open pages of DDR2/mDDR SDRAM are closed and a self-refresh (SLFRFR) command (an autorefresh command with self refresh/low power) is issued. Conversely. Following a REFR command. when the DDR2/mDDR memory controller is not busy it will issue the REFR command.2. or from clearing the SR_PD bit) until T_CKE + 1 cycles have expired since the self-refresh command was issued. before rechecking the refresh urgency level.2. Indicates the level at which enough REFR commands have been performed and the DDR2/mDDR memory controller may service new memory access requests. from clearing the LPMODEN bit.7 Refresh Scheduling The DDR2/mDDR memory controller issues autorefresh (REFR) commands to DDR2/mDDR SDRAM devices at a rate defined in the refresh rate (RR) bit field in the SDRAM refresh control register (SDRCR). if a request for a memory access is received. a separate backlog counter ensures the interval between two REFR commands does not exceed 8× the refresh rate. Indicates the level at which the DDR2/mDDR memory controller should perform a REFR command before servicing new memory access requests. Texas Instruments Incorporated 363 . the DDR2/mDDR memory controller continues normal operation until all outstanding memory access requests have been serviced and the refresh backlog has been cleared.www. Each time the interval counter expires. The memory controller exits the self-refresh state when a memory access is received. Indicates the DDR2/mDDR memory controller should raise the priority level of a REFR command above servicing a new memory access. the DDR2/mDDR memory controller issues four REFR commands before servicing any new memory requests. in which the DDR2/mDDR SDRAM maintains valid data while consuming a minimal amount of power. forces the DDR2/mDDR memory controller to place the external DDR2/mDDR SDRAM in a low-power mode (self refresh).ti. The DDR2/mDDR memory controller issues REFR commands based on the level of urgency. The DDR2/mDDR memory controller will not wake up from the self-refresh state (whether from a memory access request. the DDR2/mDDR memory controller services the memory access request. This backlog counter increments by 1 each time the interval counter expires and resets to zero when the DDR2/mDDR memory controller issues a REFR command. the backlog counter decrements by 1. when the LPMODEN bit in SDRCR is cleared to 0. When the LPMODEN bit is set to 1. the DDR2/mDDR memory controller waits T_RFC cycles. The level of urgency is defined in Table 15-9. each time the DDR2/mDDR memory controller performs a REFR command. The refresh counters do not operate when the DDR2/mDDR memory is in self-refresh mode. defined in the SDRAM timing register 1 (SDTIMR1). In the case of DDR2. after exiting from the self-refresh state. In addition to the refresh counter previously mentioned. Instead. the DDR2/mDDR memory controller issues a REFR command before servicing any new memory access requests. Table 15-9.

The DDR2/mDDR memory controller exits the power-down state when a memory access is received.10 Power-Down Mode Setting the self-refresh/low power (SR_PD) bit and the low-power mode enable (LPMODEN) bit in the SDRAM refresh control register (SDRCR) to 1. The DDR2/mDDR memory controller will not wake-up from the power-down state (whether from a memory access request.ti.2. Configuration Bit Field for Partial Array Self-refresh Bit Field PASR 0 1h 2h 5h 6h Bit Value Bit Description Partial array self refresh. Refresh banks 0. the DDR2/mDDR memory controller services the memory access request. if a request for a memory access is received. 1/2. from reaching a Refresh Must level. the DDR2/mDDR memory controller input clocks (VCLK and 2X_CLK) may be gated off or changed in frequency.com In the case of mDDR. forces the DDR2/mDDR memory controller to place the external DDR2 SDRAM in the power-down mode. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .9 Partial Array Self Refresh for Mobile DDR For additional power savings during self-refresh. 1. or from clearing the SR_PD bit) until T_CKE + 1 cycles have expired since the power-down command was issued. when the LPMODEN bit in SDRCR is cleared to 0.16. The mDDR performs bank interleaving when the internal bank position (IBANKPOS) bit in SDRAM configuration register (SDCR) is cleared to 0. When the LPMODEN bit is asserted.13). 364 DDR2/mDDR Memory Controller Copyright © 2011. The value of T_CKE is defined in the SDRAM timing register 2 (SDTIMR2).1 for a description of the self-refresh programming sequence. when a Refresh Must level is reached. all open pages of DDR2 SDRAM are closed and a Power Down command (same as NOP command but driving DDR_CKE low on the same cycle) is issued. See Section 15.16 for more information describing the proper procedure to follow when shutting down DDR2/mDDR memory controller input clocks. the memory controller will not immediately start executing commands. Use the partial array self-refresh (PASR) bit field in the SDRAM configuration register 2 (SDCR2) to select the amount of memory to refresh during self-refresh. Instead. 2.5. As shown in Table 15-10 you may select either 4. from clearing the LPMODEN bit. Stable clocks must be present before exiting self-refresh mode. Refer to Section 15. returning to the power-down state upon completion. At this point. 15. and 3 Refresh banks 0 and 1 Refresh bank 0 Refresh 1/2 of bank 0 Refresh 1/4 of bank 0 15. The PASR bits are loaded into the extended mode register of the mDDR device. Since the SDRAM banks are only partially refreshed during partial array self-refresh.2. 2.2. or 1/4 bank(s). it will wait T_SXNR+1 clock cycles and then execute auto-refresh command before issuing any other commands.2. after exiting from the self-refresh state. Table 15-10.2. the DDR2/mDDR memory controller continues normal operation until all outstanding memory access requests have been serviced and the refresh backlog has been cleared. or when the SR_PD bit in SDRCR changed to 0. it is the responsibility of software to move critical data into the banks that are to be refreshed during partial array self-refresh. While in the power-down state. The SDRAM timing register 2 (SDTIMR2) programs the value of T_SXNR.2 for more information on IBANKPOS and addressing mapping in general. See Section 15. 1. Once in self-refresh mode.2. during autoinitialization (see Section 15. the partial array self-refresh (PASR) feature of the mDDR allows you to select the amount of memory that will be refreshed during self-refresh. When IBANKPOS is cleared to 0. it is recommended that you set IBANKPOS to 1 to avoid bank interleaving.Architecture www.

Texas Instruments Incorporated 365 . DDR2/mDDR Memory Controller Reset Block Diagram Hard Reset from PLLC0 chip_rst_n DDR2/mDDR memory controller registers DDR PSC mod_g_rst_n State machine SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011.2. The SDRAM timing register 2 (SDTIMR2) programs the values of T_XP. If memory or register accesses are performed while the DDR2/mDDR memory controller is in the reset state. 15. NOTE: Power-down mode is best suited as a power savings mode when SDRAM is being used intermittently and the system requires power savings as well as a short recovery time. The chip_rst_n is a module-level reset that resets both the state machine as well as the DDR2/mDDR memory controller memory-mapped registers. Reset Sources Reset Signal chip_rst_n mod_g_rst_n Reset Source Hardware/device reset Power and sleep controller Figure 15-17. the user's software should not perform memory. while chip_rst_n or mod_g_rst_n are asserted. See Section 15. Table 15-11. chip_rst_n and mod_g_rst_n.ti. Command and data stored in the DDR2/mDDR memory controller FIFOs are lost. it will wait T_XP + 1 clock cycles before issuing commands. as well as register accesses. Following the rising edge of chip_rst_n or mod_g_rst_n. Instead. For detailed information on power management procedures using the PSC.2. see the Power and Sleep Controller (PSC) chapter.com Architecture After exiting from the power-down state.16. Figure 15-17 shows the DDR2/mDDR memory controller reset diagram. which allows soft reset (from PSC or WDT) to reset the module without resetting the configuration registers and reduces the programming overhead for setting up access to the DDR2/mDDR device. The mod_g_rst_n resets the state machine only. You may use self-refresh mode if you desire additional power savings from disabling clocks. If the DDR2/mDDR memory controller is reset independently of other peripherals. it does not reset the controller's registers. other masters may hang.1 for a description of the power-down mode programming sequence. The Power and Sleep Controller (PSC) acts as a master controller for power management for all of the peripherals on the device. the DDR2/mDDR memory controller will drive DDR_CKE high and then not immediately start executing commands. the DDR2/mDDR memory controller immediately begins its initialization sequence. Table 15-11 describes the different methods for asserting each reset signal.11 Reset Considerations The DDR2/mDDR memory controller has two reset signals.www.

DDREN = 1. The DDR2/mDDR memory controller performs an initialization sequence under the following conditions: • Following reset (rising edge of chip_rst_n or mod_g_rst_n) • Following a write to the DDRDRIVE. Calibrating the output impedance of the IO will also reduce the power consumption of the DDR2/mDDR memory controller. and the register values for mDDR are described in Table 15-14 and Table 15-15. Set these bits as follows for DDR2: SDRAMEN = 1.com 15. the DDR2/mDDR memory controller immediately begins the initialization sequence. burst length. MSDRAMEN = 1. DDREN = 1.2.13 Auto-Initialization Sequence The DDR2/mDDR SDRAM contains mode and extended mode registers that configure the DDR2/mDDR memory for operation. CAS latency. This feature allows the DDR2/mDDR memory controller to tune the output impedance of the IO to match that of the PCB board. the memory controller performs an autorefresh cycle. At the end of the initialization sequence. DLL enable/disable (on the DDR2/mDDR device). DDR2EN = 1.0% tolerance. 0. The DDR2/mDDR reference design requires the reference resistor to be a 50 ohm. However. The calibration is performed with respect to voltage. The DDR2 initialization sequence performed by the DDR2/mDDR memory controller is compliant with the JESD79D-2 specification and the mDDR initialization sequence is compliant with the JESD209 specification. DDR2EN = 0. IBANK. The SDRAMEN. 15. MSDRAMEN. enable the VTP input clock and then perform the VTP calibration sequence again. 366 DDR2/mDDR Memory Controller Copyright © 2011. Under this condition. when the initialization sequence is initiated by a write to the two least-significant bytes in SDCR. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . NOTE: VTP IO calibration must be performed following device power up and device reset.2.ti. The VTP calibration process is described in the DDR2/mDDR initialization sequence in Section 15.13. accesses to the DDR2/mDDR memory controller will not complete. When a reset occurs. 1/16th watt resistor (49. The extended mode registers 2 and 3 are configured with a value of 0h. DDREN.5% tolerance is acceptable). The VTP information obtained from the calibration is used to control the output impedance of the IO. Set these bits as follow for mDDR: SDRAMEN = 1. The impedance of the output IO is selected by the value of a reference resistor connected to pin DDR_ZP. and process (VTP). 5.Architecture www. MSDRAMEN = 0. If the DDR2/mDDR memory controller is reset via the Power and Sleep Controller (PSC) and the VTP input clock is disabled. single-ended strobe.2. temperature. Control of the output impedance of the IO is an important feature because impedance matching reduces reflections.9 ohm. The register values for DDR2 are described in Table 15-12 and Table 15-13. the memory controller issues MRS and EMRS commands that configure the DDR2/mobile DDR SDRAM mode register and extended mode register 1. To re-enable accesses to the DDR2/mDDR memory controller. or PAGESIZE bit fields in the SDRAM configuration register (SDCR) During the initialization sequence. and DDR2EN bits in the SDRAM configuration register (SDCR) determine if the DDR2/mDDR memory controller will perform a DDR2 or mobile DDR initialization sequence. data and commands stored in the DDR2/mDDR memory controller FIFOs will not be lost and the DDR2/mDDR memory controller will ensure read and write commands are completed before starting the initialization sequence. creating a cleaner board design. commands and data stored in the DDR2/mDDR memory controller FIFOs will be lost. These registers control burst type. differential strobe. leaving the memory controller in an idle state with all banks deactivated. etc. CL. The VTP IO control register (VTPIO_CTL) is written to begin the calibration process.1.12 VTP IO Buffer Calibration The DDR2/mDDR memory controller is able to control the impedance of the output IO. The DDR2/mDDR memory controller programs the mode and extended mode registers of the DDR2/mDDR memory by issuing MRS and EMRS commands during the initialization sequence.

com Architecture Table 15-12. Exit OCD calibration Cleared to 0 to select 75 ohms. Value of 2. 3. 4. This feature is not supported because the DDR_ODT signal is not pinned out.ti. Out of reset Normal mode Value of 2. Value of 0 or 1 is programmed based on value of DDRDRIVE0 bit in SDRAM configuration register (SDCR). 5. This feature is not supported because the DDR_ODT signal is not pinned out. Sequential Value of 8 DDR_A[3] DDR_A[2:0] 0 3h 3 2:0 Burst Type Burst Length SPRUH77A – December 2011 Submit Documentation Feedback Copyright © 2011. Texas Instruments Incorporated DDR2/mDDR Memory Controller 367 .www. 3. or 6 is programmed based on value of the T_WR bit in the SDRAM timing register 1 (SDTIMR1 ). or 5 is programmed based on value of the CL bit in the SDRAM configuration register (SDCR). Sequential Value of 8 DDR_A[8] DDR_A[7] DDR_A[6:4] 0 0 CL bit 8 7 6:4 DLL Reset Mode: Test or Normal CAS Latency DDR_A[3] DDR_A[2:0] 0 3h 3 2:0 Burst Type Burst Length Table 15-13. DLL enable DDR_A[5:3] DDR_A[2] 0 1 5:3 2 Additive Latency ODT Value (Rtt) DDR_A[1] DDRDRIVE[0] 1 Output Driver Impedance DDR_A[0] 0 0 DLL enable Table 15-14. DDR2 SDRAM Configuration by MRS Command Memory Controller Address Bus DDR_A[12] DDR_A[11:9] DDR2/mDDR SDRAM Register Bit 12 11:9 DDR2/mDDR SDRAM Field Power Down Exit Write Recovery Value 0 t_WR Function Selection Fast exit Write recovery from autoprecharge. Mobile DDR SDRAM Configuration by MRS Command Memory Controller Address Bus DDR_A[11:7] DDR_A[6:4] mDDR SDRAM Register Bit 11:7 6:4 Value 0 CL bit mDDR SDRAM Field Operating mode CAS Latency Function Selection Normal operating mode Value of 2 or 3 is programmed based on value of CL bit in SDRAM configuration register (SDCR). 4. DDR2 SDRAM Configuration by EMRS(1) Command Memory Controller Address Bus DDR_A[12] DDR_A[11] DDR_A[10] DDR_A[9:7] DDR_A[6] DDR2/mDDR SDRAM Register Bit 12 11 10 9:7 6 DDR2/mDDR SDRAM Field Output Buffer Enable RDQS Enable DQS enable OCD Calibration Program ODT Value (Rtt) Value 0 0 1 0 0 Function Selection Output buffer enable RDQS disable Disables differential DQS signaling. 0 cycles of additive latency Set to 1 to select 75 ohms.

see the Phase-Locked Loop Controller (PLLC) chapter. Program Power and Sleep Controller (PSC) to enable the DDR2/mDDR memory controller clock. For mDDR only. (ii) Clear CLKRZ bit and wait at least 1 VTP clock cycle (clock cycle wait can be achieved by performing a read-modify-write of VTPIO_CTL in the next step).com Table 15-15. (b) For mDDR. Configure the DDR slew register (DDR_SLEW): (a) For DDR2. Program the SDRAM timing register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) to the desired values to meet the memory data sheet specification. clear DDR_PDENA and CMOSEN bits. Value of 0 Value of 0.Architecture www. 5.13. (b) Clear LOCK bit in VTPIO_CTL. Program PLLC1 registers to start the PLL1_SYSCLK1 (that drives 2X_CLK). 5. 3. (iii) Set CLKRZ bit. 8. 11. (d) Poll READY bit in VTPIO_CTL until it changes to 1. 10. Program SDCR to the desired value with BOOTUNLOCK bit cleared to 0 and TIMUNLOCK bit set to 1 (unlocked). (b) Set PWRDNEN bit to allow the input receivers to power down when they are idle. All of the following steps may be done with a single register write to DRPYC1R: (a) Set EXT_STRBEN bit to select external DQS strobe gating. 1. DDR_A[4:3] DDR_A[2:0] 0 PASR bits 4:3 2:0 Temperature Compensated Self Refresh Partial Array Self Refresh 15. 1. or 6 is programmed based on value of PASR bits in SDRAM configuration register 2 (SDCR2). Perform VTP IO calibration: (a) Clear POWERDN bit in the VTP IO control register (VTPIO_CTL).ti. VTP is locked and dynamic calibration is disabled. 9. program the SDRAM configuration register 2 (SDCR2) to the desired value. (c) Pulse CLKRZ bit in VTPIO_CTL: (i) Set CLKRZ bit and wait at least 1 VTP clock cycle (clock cycle wait can be achieved by performing a read-modify-write of VTPIO_CTL in the next step). Before releasing the DDR2/mDDR memory controller from reset. Set IOPWRDN bit in VTPIO_CTL to allow the input receivers to save power when the PWRDNEN bit in the DDR PHY control register 1 (DRPYC1R) is set. Configure DRPYC1R. Clear TIMUNLOCK bit (locked) in SDCR. the clocks to the module must be turned on. (f) Set POWERDN bit in VTPIO_CTL to save power. the DDR2/mDDR memory controller is held in reset with the internal clocks to the module gated off. For information on programming PLLC1. Mobile DDR SDRAM Configuration by EMRS(1) Command Memory Controller Address Bus DDR_A[11:7] DDR_A[6:5] mDDR SDRAM Register Bit 11:7 6:5 Value 0 DDRDRIVE[1:0] mDDR SDRAM Field Operating Mode Output Driver Impedance Function Selection Normal operating mode Value of 0. Set the BOOTUNLOCK bit (unlocked) in the SDRAM configuration register (SDCR). or 3 is programmed based on value of DDRDRIVE[1:0] bits in SDRAM configuration register (SDCR). set the DDR_PDENA and CMOSEN bits. 2. (e) Set LOCK bit in VTPIO_CTL. 2. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback . 368 DDR2/mDDR Memory Controller Copyright © 2011.2. Perform the following steps when turning the clocks on and initializing the module: 1. 2. 6. 4.1 Initializing Following Device Power Up or Reset Following device power up or reset. (c) Program RL bit value to meet the memory data sheet specification. 7.

(d) Program RR refresh rate value to meet the memory data sheet specification. (b) Set MCLKSTOPEN bit to enable MCLK stopping. The DDR2/mDDR memory controller will then treat the request as a linear incrementing request. Data read and write requests may be made directly by masters and by the DMA. however. linear incrementing and cache line wrap. 15.com Architecture 12. Program the Power and Sleep Controller (PSC) to re-enable the DDR2/mDDR memory controller.15 DMA Event Support The DDR2/mDDR memory controller is a DMA slave peripheral and therefore does not generate DMA events.2. (c) Clear SR_PD bit to select self-refresh. The optimal value should be determined based on system considerations.14 Interrupt Support The DDR2/mDDR memory controller supports two addressing modes. 14. Program the SDRAM refresh control register (SDRCR). This interrupt is called the line trap interrupt and is the only interrupt the DDR2/mDDR memory controller supports. This is necessary for the next two steps. All of the following steps may be done with a single register write to SDRCR: (a) Set LPMODEN bit to enable self-refresh. 15. This is necessary for the next two steps. Upon receipt of an access request for an unsupported addressing mode. 15. Texas Instruments Incorporated 369 . Program the Power and Sleep Controller (PSC) to reset (SyncReset) the DDR2/mDDR memory controller. 13. This interrupt is mapped to the CPU and is multiplexed with RTCINT. NOTE: Some memory data sheet timing values such as those programmed into the SDRAM timing register 1 (SDTIMR1) and SDRAM timing register 2 (SDTIMR2) may need to be relaxed in order to compensate for signal delays introduced by board layout.2. SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011. Configure the peripheral bus burst priority register (PBBPR) to a value lower than the default value of FFh.ti. 16. a value of 20h or 30h is sufficient for typical applications. A lower value reduces the likelihood of prolonged command starvation for accesses made from different master/peripherals to mDDR/DDR2 memory. the DDR2/mDDR memory controller generates an interrupt by setting the LT bit in the interrupt raw register (IRR). This is necessary for the next two steps. Clear LPMODEN and MCLKSTOPEN bits in SDRCR to disable self-refresh.www. It is an active-high interrupt and is enabled by the LTMSET bit in the interrupt mask set register (IMSR).

These functions are controlled through the DDR2/mDDR memory controller. For detailed information on power management procedures using the PSC.ti. the DDR2/mDDR memory controller must place the DDR2/mDDR SDRAM memory in self-refresh mode.10) • Disabling the DDR PHY to reduce power The DDR2/mDDR memory controller supports low-power modes where the DLL internal to the PHY and the receivers at the I/O pins can be disabled. to re-enable the clocks follow the clock stop procedure in each respective subsection in reverse order. Figure 15-18. the DDR2/mDDR memory controller clock provided by PLLC1 must not be turned off because this may result in data corruption. and PLLC1. Texas Instruments Incorporated SPRUH77A – December 2011 Submit Documentation Feedback .2.Architecture www. the receivers can be configured to disable whenever writes are in progress and the receivers are not needed.com 15. The input clocks are turned off outside of the DDR2/mDDR memory controller through the use of the Power and Sleep Controller (PSC) and the PLL controller 1 (PLLC1). DDR2/mDDR Memory Controller Power Sleep Controller Diagram CLKSTOP_REQ CLKSTOP_ACK PLL0_SYSCLK2/2 DDR PST MODCLK MODRST LRST VCLKSTOP_REQ VCLKSTOP_ACK DDR2/mDDR memory VCLK controller chip_rst_n mod_g_rst_n 2X_CLK PLLC1 /1 370 DDR2/mDDR Memory Controller Copyright © 2011. Before gating clocks off.2. Once the clocks are stopped. See the following subsections for the proper procedures to follow when stopping the DDR2/mDDR memory controller clocks. • Gating input clocks to the module off Gating input clocks off to the DDR2/mDDR memory controller achieves higher power savings when compared to the power savings of self-refresh mode and power-down mode.16 Power Management Power dissipation from the DDR2/mDDR memory controller may be managed by the following methods: • Self-refresh mode (see Section 15. see the Power and Sleep Controller (PSC) chapter. PSC. If the external memory requires a continuous clock. Figure 15-18 shows the connections between the DDR2/mDDR memory controller.8) • Power-down mode (see Section 15. Even if the PHY is active.2.

16. DDR_CLK. This enables the DDR2/mDDR memory controller to shut off the MCLK.2. 5. To 1. This resets the DDR2/mDDR memory controller PHY.ti. SPRUH77A – December 2011 Submit Documentation Feedback DDR2/mDDR Memory Controller Copyright © 2011. The DDR2/mDDR memory controller will complete any outstanding accesses and backlogged refresh cycles and then place the external DDR2/mDDR memory in self-refresh mode. 5.12 for information on VTP IO calibration. program the PSC to enable VCLK. 2. the DLL will wake up and lock. and DDR_CLK should be gated off. Clear the MCLKSTOPEN bit in SDRCR to 0. The procedure for clock gating is described in the following steps. Texas Instruments Incorporated 371 . all DDR2/mDDR memory accesses are not possible until the clocks are reenabled. Clear the LPMODEN bit in the DDR2 SDRAM refresh control register (SDRCR) to 0.1 DDR2/mDDR Memory Controller Clock Stop Procedure NOTE: If a data access occurs to the DDR2/mDDR memory after completing steps 1-4. use only for self-refresh mode (see notes in this section). To achieve maximum power savings VCLK. A bus lock-up condition will occur if the emulation