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VHDL

Lecture 8

Convert binary to integer


function BIN2INT (B: BIT_VECTOR) return INTEGER is variable RESULT: INTEGER; begin RESULT := 0; for N in B'RANGE loop RESULT := RESULT * 2; if B(N) = '1' then RESULT := RESULT + 1; end loop; return RESULT; end BIN2INT;

Convert binary to integer


function BIN2INT (B: BIT_VECTOR) return INTEGER is variable RESULT: INTEGER; begin RESULT := 0; for N in B'RANGE loop RESULT := RESULT * 2; if B(N) = '1' then RESULT := RESULT + 1; end loop; return RESULT; end BIN2INT;

Convert binary to integer


function BIN2INT (B: BIT_VECTOR) return INTEGER is variable RESULT: INTEGER; begin RESULT := 0; for N in B'RANGE loop RESULT := RESULT * 2; if B(N) = '1' then RESULT := RESULT + 1; end loop; return RESULT; end BIN2INT;

Convert binary to integer


function BIN2INT (B: BIT_VECTOR) return INTEGER is variable RESULT: INTEGER := 0; begin RESULT := 0; for N in B'RANGE loop RESULT := RESULT * 2; if B(N) = '1' then RESULT := RESULT + 1; end loop; return RESULT; end BIN2INT;

Convert binary to integer


function BIN2INT (B: BIT_VECTOR) return INTEGER is variable RESULT: INTEGER := 0; begin RESULT := 0; for N in B'RANGE loop RESULT := RESULT * 2; if B(N) = '1' then RESULT := RESULT + 1; end loop; return RESULT; end BIN2INT;

Convert binary to integer


function BIN2INT (B: BIT_VECTOR) return INTEGER is variable RESULT: INTEGER := 0; begin for N in B'RANGE loop RESULT := RESULT * 2; if B(N) = '1' then RESULT := RESULT + 1; end loop; return RESULT; end BIN2INT;

Convert binary to integer


function BIN2INT (B: BIT_VECTOR) return INTEGER is variable RESULT: INTEGER := 0; begin for N in B'RANGE loop RESULT := RESULT * 2; if B(N) = '1' then RESULT := RESULT + 1; end loop; return RESULT; end BIN2INT;

Convert binary to integer


function BIN2INT (B: BIT_VECTOR) return INTEGER is variable RESULT: INTEGER := 0; begin for N in B'RANGE loop RESULT := RESULT * 2; if B(N) = '1' then RESULT := RESULT + 1; end loop; return RESULT; end BIN2INT;

Convert binary to integer


function BIN2INT (B: BIT_VECTOR) return INTEGER is variable RESULT: INTEGER := 0; begin for N in B'RANGE loop RESULT := RESULT * 2; if B(N) = '1' then RESULT := RESULT + 1; end loop; return RESULT; end BIN2INT;

Convert binary to integer


function BIN2INT (B: BIT_VECTOR) return INTEGER is variable RESULT: INTEGER := 0; begin for N in B'RANGE loop RESULT := RESULT * 2; if B(N) = '1' then RESULT := RESULT + 1; end loop; return RESULT; end BIN2INT;

Simple 4-bit barrel shifter


SHIFT FUNCTION OUTPUT 00 01 10 11 Reset Left shift Right shift No shift 0000 B3B2B1B0 -> B2B1B00 B3B2B1B0 -> 0B3B2B1 B3B2B1B0 -> B3B2B1B0 entity BARREL is port ( B: BIT_VECTOR (3 downto 0); S: BIT_VECTOR (1 downto 0); Y: BIT_VECTOR (3 downto 0)); end entity;

architecture BEHAVE of BARREL is begin process (B, S) begin case S is when "00" => Y <= "0000"; when "01" => Y <= B(2) & B(1) & B(0) & '0'; when "10" => Y <= '0' & B(3) & B(2) & B(1); when others => null; end case; end process; end BEHAVE;

Simple 4-bit barrel shifter


SHIFT FUNCTION OUTPUT 00 01 10 11 Reset Left shift Right shift No shift 0000 B3B2B1B0 -> B2B1B00 B3B2B1B0 -> 0B3B2B1 B3B2B1B0 -> B3B2B1B0 entity BARREL is port ( B: BIT_VECTOR (3 downto 0); S: BIT_VECTOR (1 downto 0); Y: BIT_VECTOR (3 downto 0)); end entity;

architecture BEHAVE of BARREL is begin process (B, S) begin case S is when "00" => Y <= "0000"; when "01" => Y <= B(2) & B(1) & B(0) & '0'; when "10" => Y <= '0' & B(3) & B(2) & B(1); when others => null; end case; end process; end BEHAVE;

Simple 4-bit barrel shifter


SHIFT FUNCTION OUTPUT 00 01 10 11 Reset Left shift Right shift No shift 0000 B3B2B1B0 -> B2B1B00 B3B2B1B0 -> 0B3B2B1 B3B2B1B0 -> B3B2B1B0 entity BARREL is port ( B: BIT_VECTOR (3 downto 0); S: BIT_VECTOR (1 downto 0); Y: BIT_VECTOR (3 downto 0)); end entity;

architecture BEHAVE of BARREL is begin process (B, S) begin case S is when "00" => Y <= "0000"; when "01" => Y <= B(2) & B(1) & B(0) & '0'; when "10" => Y <= '0' & B(3) & B(2) & B(1); when others => null; end case; end process; end BEHAVE;

Simple 4-bit barrel shifter


SHIFT FUNCTION OUTPUT 00 01 10 11 Reset Left shift Right shift No shift 0000 B3B2B1B0 -> B2B1B00 B3B2B1B0 -> 0B3B2B1 B3B2B1B0 -> B3B2B1B0 entity BARREL is port ( B: BIT_VECTOR (3 downto 0); S: BIT_VECTOR (1 downto 0); Y: BIT_VECTOR (3 downto 0)); end entity;

architecture BEHAVE of BARREL is begin process (B, S) begin case S is when "00" => Y <= "0000"; when "01" => Y <= B(2) & B(1) & B(0) & '0'; when "10" => Y <= '0' & B(3) & B(2) & B(1); when others => null; end case; end process; end BEHAVE;

Simple 4-bit barrel shifter


SHIFT FUNCTION OUTPUT 00 01 10 11 Reset Left shift Right shift No shift 0000 B3B2B1B0 -> B2B1B00 B3B2B1B0 -> 0B3B2B1 B3B2B1B0 -> B3B2B1B0 entity BARREL is port ( B: BIT_VECTOR (3 downto 0); S: BIT_VECTOR (1 downto 0); Y: BIT_VECTOR (3 downto 0)); end entity;

architecture BEHAVE of BARREL is begin process (B, S) begin case S is when "00" => Y <= "0000"; when "01" => Y <= B(2) & B(1) & B(0) & '0'; when "10" => Y <= '0' & B(3) & B(2) & B(1); when others => null; end case; end process; end BEHAVE;

Simple 4-bit barrel shifter


SHIFT FUNCTION OUTPUT 00 01 10 11 Reset Left shift Right shift No shift 0000 B3B2B1B0 -> B2B1B00 B3B2B1B0 -> 0B3B2B1 B3B2B1B0 -> B3B2B1B0 entity BARREL is port ( B: BIT_VECTOR (3 downto 0); S: BIT_VECTOR (1 downto 0); Y: BIT_VECTOR (3 downto 0)); end entity;

architecture BEHAVE of BARREL is begin process (B, S) begin case S is when "00" => Y <= "0000"; when "01" => Y <= B(2) & B(1) & B(0) & '0'; when "10" => Y <= '0' & B(3) & B(2) & B(1); when others => null; end case; end process; end BEHAVE;

Simple 4-bit barrel shifter


SHIFT FUNCTION OUTPUT 00 01 10 11 Reset Left shift Right shift No shift 0000 B3B2B1B0 -> B2B1B00 B3B2B1B0 -> 0B3B2B1 B3B2B1B0 -> B3B2B1B0 entity BARREL is port ( B: BIT_VECTOR (3 downto 0); S: BIT_VECTOR (1 downto 0); Y: BIT_VECTOR (3 downto 0)); end entity;

architecture BEHAVE of BARREL is begin process (B, S) begin case S is when "00" => Y <= "0000"; when "01" => Y <= B(2) & B(1) & B(0) & '0'; when "10" => Y <= '0' & B(3) & B(2) & B(1); when others => null; end case; end process; end BEHAVE;

Simple 4-bit barrel shifter


SHIFT FUNCTION OUTPUT 00 01 10 11 Reset Left shift Right shift No shift 0000 B3B2B1B0 -> B2B1B00 B3B2B1B0 -> 0B3B2B1 B3B2B1B0 -> B3B2B1B0 entity BARREL is port ( B: BIT_VECTOR (3 downto 0); S: BIT_VECTOR (1 downto 0); Y: BIT_VECTOR (3 downto 0)); end entity;

architecture BEHAVE of BARREL is begin process (B, S) begin case S is when "00" => Y <= "0000"; when "01" => Y <= B(2) & B(1) & B(0) & '0'; when "10" => Y <= '0' & B(3) & B(2) & B(1); when others => null; end case; end process; end BEHAVE;

Exercise: Attempt same circuit using structural architecture.

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


entity FA_FILE_TB is end entity; architecture MYARCH of FA_FILE_TB is component FA port (A, B, C: in STD_LOGIC; CY, S: out STD_LOGIC); end component; signal A, B, C, CY, S: STD_LOGIC; file INFILE: TEXT OPEN READ_MODE is "INPUTS.DAT"; file OUTFILE: TEXT OPEN WRITE_MODE is "OUTPUTS.DAT"; begin DUT: FA port map (A, B, C, CY, S);

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


process variable INLINE, OUTLINE: LINE; variable INA, INB, INC: STD_LOGIC; variable OUTCY, OUTS: STD_LOGIC; begin while not ENDFILE(INFILE) loop READLINE(INFILE, INLINE); READ(INLINE, INA); READ(INLINE, INB); READ(INLINE, INC); A <= INA; B <= INB; C <= INC;

Full adder test bench (file)


wait for 5 ns -- propagation delay OUTCY <= CY; OUTS <= S; WRITE(OUTLINE, OUTCY); WRITE(OUTLINE, OUTS); WRITELINE(OUTFILE, OUTLINE); end loop; wait; end process;

end MYARCH;

Full adder test bench (file)


wait for 5 ns -- propagation delay OUTCY <= CY; OUTS <= S; WRITE(OUTLINE, OUTCY); WRITE(OUTLINE, OUTS); WRITELINE(OUTFILE, OUTLINE); end loop; wait; end process;

end MYARCH;

Full adder test bench (file)


wait for 5 ns -- propagation delay OUTCY <= CY; OUTS <= S; WRITE(OUTLINE, OUTCY); WRITE(OUTLINE, OUTS); WRITELINE(OUTFILE, OUTLINE); end loop; wait; end process;

end MYARCH;

Full adder test bench (file)


wait for 5 ns -- propagation delay OUTCY <= CY; OUTS <= S; WRITE(OUTLINE, OUTCY); WRITE(OUTLINE, OUTS); WRITELINE(OUTFILE, OUTLINE); end loop; wait; end process;

end MYARCH;

Full adder test bench (file)


wait for 5 ns -- propagation delay OUTCY <= CY; OUTS <= S; WRITE(OUTLINE, OUTCY); WRITE(OUTLINE, OUTS); WRITELINE(OUTFILE, OUTLINE); end loop; wait; end process;

end MYARCH;

Full adder test bench (file)


wait for 5 ns -- propagation delay OUTCY <= CY; OUTS <= S; WRITE(OUTLINE, OUTCY); WRITE(OUTLINE, OUTS); WRITELINE(OUTFILE, OUTLINE); end loop; wait; end process;

end MYARCH;

Full adder test bench (file)


wait for 5 ns -- propagation delay OUTCY <= CY; OUTS <= S; WRITE(OUTLINE, OUTCY); WRITE(OUTLINE, OUTS); WRITELINE(OUTFILE, OUTLINE); end loop; wait; end process;

end MYARCH;

Full adder test bench (file)


wait for 5 ns -- propagation delay OUTCY <= CY; OUTS <= S; WRITE(OUTLINE, OUTCY); WRITE(OUTLINE, OUTS); WRITELINE(OUTFILE, OUTLINE); end loop; wait; end process;

end MYARCH;

Full adder test bench (file)


wait for 5 ns -- propagation delay OUTCY <= CY; OUTS <= S; WRITE(OUTLINE, OUTCY); WRITE(OUTLINE, OUTS); WRITELINE(OUTFILE, OUTLINE); end loop; wait; end process;

end MYARCH;