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ASIC DESIGN FLOW ASSIGNMENT 1

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Brief about ASIC Design flow. Specifications structural and functional verification description RTL resign gate level net list physical implementation-floor planning ,placement ,routing GDSII file used to fabricate the ASIC by using simulation tools

2) What is RTL Design. How it is different from non-RTL in terms of verilog coading.

implemented using logic representation (Boolean Expressions), finite state machines, Combinatorial, Sequential Logic, Schematics etc.... This step is called Logic Design / RTL design . description
3) what is RTL verification .What is the tool that used to Rtl verification. Ans :- checking functionality of the RTL design by using the HDL laungage wheather our code is meeting structural /functional description.VHDL or veri log HDL tools are used to RTL verification.

4) Do you know gate level verification? Transistor level verification? RTL verification? What is difference between them?

5) What is difference between functional verification & formal verification?

6) What is Synthesis? What are inputs needed for Synthesis?

7) What does logical library contain? How does impact Synthesis flow? {For Ex: If Logical lib is changed, what are the results that it could effect. Like timing? area? }

why? 16) What if I do not have create_clock in constraints file while synthesis? How does it effect? 17)What is the difference between flat & hierarchical synthesis? 18) What is timing budgeting? Do we do budgeting while synthesis? 19) What is input delay & output delay on IO ports in hierarchical flow? How does they calculated? 20) What is a multi cycle path? When do we use it? . what is the impact we have? If No. can we do synthesis? If Yes.8) Do we need physical libs for synthesis? 9) What are tools available in market for synthesis? 10) What is a false path? How do we define in DC? 11) What is a critical path? 12) If timing after synthesis is having timing violations (setup & hold) can we go forward to Physical Design? Is there any possibility that timing will be met in PD even it is not in Synthesis? What are the possible situations? 13) What are timing constraints? What are major constraints? Why do we need to have constraints? 14) If we do not provide any constraints while synthesis.