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Assignment-2: VLSI Circuit Simulation

Date: 28.09.2013 Submission Date: 28.10.2013 (Submission beyond the deadline will be discouraged through appropriate means.)

Until and unless specified otherwise, the following simulation problems need to be done in Tanner EDA tool environment. Show simulation results wherever, you find to be appropriate.

Try to answer the following questions in your own words as far as practicable. 1. Simulate the drain and gate I-V characteristics of an n-channel MOS transistor using L=0.25 m and W=1 m. The drain and the gate voltages should be varied between 0 to 2.5V. 2. Repeat problem 1 for a p-channel MOS transistor of same dimension. 3. Study the variations of ON current, OFF current and Sub-threshold slope of an n-channel MOS transistor and a p-channel MOS transistor with the channel length L, keeping the channel width constant and then with channel width, keeping the length constant. 4. What is the model files used for the above simulation and what level of device models have been used. 5. Simulate a CMOS inverter with channel length of the transistors equal to 0.25 m. Assume the W/L ratio of the n-channel MOS transistor to be 2, find out through repeated simulation what should be the aspect ratio of the p-channel MOS transistor to get the switching voltage equal to half of the supply voltage. 6. For the CMOS inverter circuit drawn previously, extract the various propagation delay times using a unit step function as the input. Assume the input rise time to be 1ns. Repeat the problem for rise time to be 2ns, 4ns and 8ns. Make a comparison graph between the various delay parameters and rise time of the input. 7. Draw and implement a full adder circuit and show its functionality for both sum and carry through simulation results.