Synthesis and Timing Verification Manual By Dr.

Ahmet Bindal Computer Engineering Department San Jose State University

ac_shell -gui Launch BuildGates® Synthesis tool. Under the UNIX terminal, type ac_shell –gui, it will launch the BuildGates® Synthesis tool. Example: ac_shell -gui

source (TCL script) source is command in TCL script to compile a TCL source code. setup.tcl proc setup {} { set_global echo_commands true set_global fanout_load_limit 12 read_alf /apps/cadence/bg40/lib/lca500k.alf read_update_library /apps/cadence/bg40/lib/lca500k.wireload3 set_global target_technology lca500kv } Example: ac_shell> source setup.tcl To run the script: ac_shell> setup

set_global The set_global command sets the global variables of ac_shell. These variables are independent of the design, but affect the overall run procedure and the ac_shell policies on various global matters, for example, the Verilog module naming style, message verbosity level, slew limit, and line length in reports. Example: ac_shell> set_global target_technology lca500kv To set the fanout load limit (maximum value) on the output ports of a top level module. Fanout load limits are only used to enforce the design rule checks; they do not affect timing analysis. Setting port capacitance limit affects timing analysis. Example: ac_shell> set_global fanout_load_limit 12

Or For specific fanout limit for an individual output, use set_fanout_load_limit follow by a number value. Example: ac_shell> set_fanout_load_limit 12 [find -port -output sum_out] This is to set the ac_shell to show all the commands as they are execute in the script. Example: ac_shell> set_global echo_commands true

read_alf read_alf command is used to read an ALF library into the database before synthesis. Example: ac_shell> read_alf /apps/cadence/bg40/lib/lca500k.alf

read_library_update Includes various cell-specific information related to layout and wire loading, operating conditions to the existing technology library. Example: ac_shell> read_library_update /apps/cadence/bg40/lib/lca500k.wireload3

read_verilog Reads in Verilog RTL files to ac_shell. read_verilog can read in one file or multiple files. Example: ac_shell> read_verilog my_design.v Read in the multiple files and the files are located in the local directory. Each filename is separate by a space after the command. Example: ac_shell> read_verilog my_design.v mux.v full_adder.v ff.v Read in the file or files in a remote directory. Example: ac_shell> read_verilog {bg40/vlog/design.v bg40/vlog/mux.v}

Example: ac_shell> do_build_generic Builds a generic netlist for all modules in the design hierarchy. If there are multiple top-level modules in the design hierarchy. Example: ac_shell> set_top_timing_module <module_name> . The optimization commands operate on the module (and its hierarchy) set by the top timing module. All the constraints are set with reference to the module specified as the top timing module. If -all is specified. gate-level netlist consisting of technology-independent logic gates. The command performs constant propagation.do_build_generic Transforms the design read in by the commands read_verilog into a hierarchical. using components from the Ambit Synthesis Technology Library (ATL) and Extended ATL (XATL). loop unrolling. Example: ac_shell> set top “module_name” ac_shell> set_top_timing_module $top This example is without using the TCL shell variable to execute the command. Selects the named module as the top of the design hierarchy and as the default top timing module. Example: ac_shell> do_build_generic –module module_name set_top_timing_module Identifies the module to be used by subsequent commands as a context for setting timing constraints. and logic mapping. the -all or -module option must be specified. the first module returned by [find -top *] is selected as the top of the design hierarchy and as the default top timing module.modules in the hierarchy. lifetime analysis. Example: ac_shell> do_build_generic –all Builds a generic netlist for the named module and all sub.

All searches for design objects are started in this module. Single Clock in a system: Example: ac_shell> set_clock ideal_clock –period 10 –lead 3 –trail 8 Or Example: ac_shell> set_clock ideal_clock –period 10 -waveform {3 8} Note1: In this example. For purely combinational design. period. Design objects referenced by subsequent commands can be found relative to this module. there is no defined positive or negative edge. An ideal clock must be defined as a global reference signal for all the data signals in the design. module_name is used as the root (top level module) of the hierarchy. and position of the leading edge and trailing edge. In a multiphase clock system. Figure 1 T=0 T = 10 T=8 T = 20 Trailing edge Ideal_clock T=3 Leading Edge . a positive edge clock is shown. In a singleclock design. several set_clock commands are used to define each phase of the clock. The ideal clock is defined by its name. only one set_clock command is used. If design objects are referenced hierarchically. an ideal clock (or any clock) definition is not necessary. but it can be a negative edge clock.set_current_module Sets the module represented by module_name as the current module. In figure 1. Example: ac_shell> set_current_module <module_name> set_clock set clock clock_name {[-period period] | [-waveform {lead_time trail_time}]} Defines an ideal clock signal. Note2: The ideal_clock is the name of your ideal clock.

This command is usually right after the command set_clock Example: ac_shell> set_clock ideal_clock –period 10 -waveform {3 8} ac_shell> set_clock_root –clock ideal_clock –neg clk . Figure 2 T =0 T = 10 T = 20 T = 30 T = 40 Ideal_clock1 Ideal_clock2 Ideal_clock3 set_clock_root set_clock_root -clock ideal_clock_name [-pos | -neg] list_of_pins Assigns a polarity to a previously (set_clock) specified ideal clock and associates a list of clock pins or ports with the ideal clock signal. set_clock command doesn’t define positive or negative edge of the clock.Multiple Clock in a System: Example: ac_shell> set_clock ideal_clock1 –period 10 –lead 0 –trail 5 ac_shell> set_clock ideal_clock2 –period 20 –lead 8 –trail 18 ac_shell> set_clock ideal_clock3 –period 20 –lead 5 –trail 9 Or Example: ac_shell> set_clock ideal_clock1 –period 10 waveform {0 5} ac_shell> set_clock ideal_clock2 –period 20 waveform {8 18} ac_shell> set_clock ideal_clock3 –period 20 waveform {5 9} Note: All the clocks in figure 2 are drawn with the positive edge.

clk2 and clk3. Figure 3 T =0 T =5 T = 10 T =8 T = 15 T = 20 T = 25 Trailing edge clk T =3 Leading Edge Example: ac_shell> set_clock ideal_clock1 –period 10 waveform {0 5} ac_shell> set_clock ideal_clock2 –period 20 waveform {8 18} ac_shell> set_clock ideal_clock3 –period 20 waveform {5 9} ac_shell> set_clock_root ideal_clock1 –pos clk1 ac_shell> set_clock_root ideal_clock2 –neg clk2 ac_shell> set_clock_root ideal_clock3 –pos clk3 Note: In this example. the clock in figure is negative edge because of the option –neg.Note: clk is the actual clock name of the module of the design. Figure 4 T =0 T = 10 T = 20 T = 30 clk1 clk2 clk3 . clk1. the design has three clocks. This example.

-dont_modify Filter for all objects types. -modules Searches for modules. -nets Searches only for net object types. It returns the object name for all other object types. -inputs Filters for -pin and -port. Returns only input pins or ports. The design objects are found in the design database using global style pattern matching. net. ports. Returns only objects that are blackboxes. -cellrefs Searches for cell references. and instance pins. It returns the complete path of the nets. Pattern matching and regular expressions may be used to find many objects. Returns only clock pins or ports. Multiple wildcard matching in a name is permitted. Returns objects with dont_modify flag set. -full_path_name Returns the complete path name of the object. -instances Searches only for instances. and techlibs. Returns only bus components. ports. This option will work with any object type including cells. modules. -exclude namelist Will not return objects specified by namelist. instances. . -name_list Specifies the names of the objects to search. Refer to set_dont_modify. unless -regexp option is used.find find [-blackboxes] [-alias_only] [-bus] [-cellrefs] [-clocks] [-dont_modify] [-exact] [-exclude] [-full_path_name] [-glob | -regexp] [-hierarchical] [-inputs] [-instances] [-modules] [-nets] [-nocase] [-noclocks] [-of_cell_type cell_name] [-of_lib_type lib_name] [-of_pin_type { data | clock | output | reset | set }] [-outputs] [-pins] [-ports] [-registers] [-sop] [-techlib] [-top] [-scalar] name_list Finds various design objects and prepares the list for other ac_shell commands. -hierarchical Searches the complete database hierarchically from current module. -bus Filter for nets. -clocks Filter for -pins and -ports. not the object_id. instances. -exact Searches only for exact name matches. pins. and the instance pins from the current module. -blackboxes Filter for -cellref and -instances.

-regexp Performs pattern matching using regular expression rules instead of glob style pattern matching by default. -ports Searches only for ports. It returns the respective pins for the sequential elements. It is a useful in searching for the VHDL modules. Returns only sequential instances.insensitive search is performed. which can be *. -of_pin_type { data | clock | output | reset | set } This is a filter for -pin. -registers Filter for -instances. -top Filter for -module. -sop Filter for -cellref and -instances. ports. -techlib Searches for technology libraries.techlibs switches to specify. ? Matches any single character. Returns objects which are sum-ofproducts (SOP) logic. In this example. -noclocks Filter for -pins and -ports. Returns only the top level module. -outputs Filter for -pins and -ports. The equalent to the script is like assign all output to a variable all_outputs.-nocase Use this switch in conjunction with the -module or the . Returns only output pins or ports. -of_cell_type cell_name Filter for -instances. Returns only the scalar components and filters out the bus components. Example: [find –port –input –noclocks “*”] The following example is written in a TCL script to find all the output whenever the script was call upon. Useful in the cases where there is a name collision between a scalar and bus component. It determines whether a case. and instance pins. The following symbols are used for wildcard matching: * Matches 0 or more occurrence of any character. The script name is all_outputs. multi-cycle paths) across reused modules.c] Matches a or b or c. -pins Searches only for instance pins. find all the inputs of the top module and except the clock. [a. . Returns only the instances of cell_name. This option allows you to apply path exceptions (false paths.b. -scalar Filter for nets. Returns only nonclock pins or ports.

This input path delay models the delay from an external register to an input port of the module. -lead and -fall options have the same meaning.5 -fall [all_inputs] Figure 5 T =0 T =5 T =3 T = 10 T =8 T = 15 T = 20 T = 25 Trailing edge clk Leading Edge input Setup time = 0.Example: proc all_outputs {} { find –port –output “*”} set_input_delay set_input_delay [-early | -late] [-rise | -fall] [-clock clock_name] [-lead | -trail] [-worst_case] float port_or_pin_list Sets input path delay values on input ports (or internal input pins).5 Note: Because the ideal clock ‘clk’ is a negative edge clock. . Example: ac_shell> set_input_delay -clock clk -late 9.

including data setup time for the external register. only the network latency needs to be given for those clocks. If the external register is a latch. then the external delay is considered to apply to both early and late times. If both -late and -early options are omitted. it overrides the set_clock_insertion_delay specification. And if it is given. external_delay Specifies the external delay. The default is the asynchronous (@) clock. A generated clock cannot be used with this option.set_external_delay set_external_delay [-rise | -fall] [-late | -early] [-sig | -ref] [-lead | -trail] [-clock clock_name] [-arrival float] [-worst_case] external_delay port_or_pin_list External delay requirements specify the required time that the output ports must be stable. the default is lead. If both -lead and -trail options are omitted. The -arrival option is an archaic method of specifying latency for the clock network for the fictitious flops connected to the output ports. -lead | -trail Specifies that the leading or trailing edge of the clock waveform controls the external register. With the set_clock_insertion_delay. -clock clock_name Specifies the ideal clock signal which is controlling the external register. which requires you to calculate the clock reference time plus latency along the clock path. -arrival float Specifies the actual arrival time of the edge of the clock waveform that is being used to determine the external delay. The -arrival option is still available though. It is used to set the absolute clock arrival time for those flops. This is used if the arrival time of the capturing clock signal is different than the arrival time of the corresponding edge of the ideal (or generated) clock. This option is similar to specifying the actual clock arrival time using the set_clock_insertion_delay command in relation to the ideal (or generated) clock signal defined by the set_clock (or set_generated_clock) command. This constraint considers the timing requirement of the configuration of the output port and the connection to the register input of the external block. . the controlling edge is the capturing edge. So you do not need to do any arithmetic. -early | -late Specifies that the constraint refers to the early (data hold/clock setup) or late (data setup/clock hold) times.

Example: ac_shell> set_external_delay –clock clk_sys 5 out_1 set_drive_resistance set_drive_resistance -clock clk_name [-lead | -trail | -pos | -neg] [-rise | -fall] [-early | -late] [-slew_res slew_res_value] [-slew_intrinsic slew_intrinsic_value] value port_list It provides a simpler version of the set_drive_cell command. If both -rise and -fall options are omitted. It is used only for timing analysis. all outgoing signals from the pin are blocked. The default edge option is -lead. . and it can be used in many situations where the drive resistance can be specified. It is used to specify the drive resistance of a cell. If neither option is given. -worst_case Takes the worst-case delay when multiple external delays for the same clock are specified. -lead | -trail | -pos | -neg Indicates that the signal at the specified port must be recognized as a data signal with the specified association (lead or trail) with respect to the specified clock clock_name.port_or_pin_list Specifies the list of output or bidirectional ports or pins. successive external delays on the same clock overwrite previously asserted values. the external delay applies to both the edges at the output port. It computes an offset to the arrival time of an input and also changes the slew time used to compute the delay of the cell on the sink of the net. -rise | -fall Specifies that the external delay refers to the rising edge or falling edge at the output port. -early | -late Specifies that the drive resistance should be applied to the early arrival time (data hold time) or late arrival time (data setup time) for timing analysis. When an external delay is asserted on an internal circuit pin (one that is not an output port). Without this option. the default is -sig. The RC constant is the capacitance (C) seen at the input port multiplied by the drive resistance (R). It does not affect the electrical properties of the design. Adding the RC constant to the specified arrival time at the input port modifies the arrival time at the input port. -clock clk_name The name of the clock. The RC value is used as the slew value for the delay calculation of the next cell. -sig | -ref Determines whether the external delay assertion is being applied on a data path (-sig) or a clock network (-ref).

technology mapping. -rise | -fall Specifies that the drive resistance is applicable to only the rising edge or the falling edge transition at the input port. assuming cap is the capacitance at this port: slew = slew_intrinsic_value + slew_res_value * cap -slew_res slew_res_value Specifies the value of resistance used in the slew computation at the input port of the module. port_list List of ports for which drive resistance is specified. timing-driven optimization. logic optimization will include some or all of the following: unification. -pos and -neg specify that the slew time should be applied to an actual clock that has positive or negative polarity with respect to the ideal clock waveform. buffering of multi-port nets. If neither rise nor fall options are specified then the resistance is applied to both transitions at the input port. Depending upon the state of the design database. -slew_intrinsic slew_intrinsic_value Specifies the intrinsic value of slew used in the slew computation at the input port of the module. The default polarity is -pos. and design-rule fixing. structuring. The slew value at the input port of the module is computed as follows. Example: ac_shell> set_drive_resistance 0 [all_inputs] do_optimize It performs logic optimization on the current module as specified with the set_current_module command. Example: ac_shell> do_optimize report_timing report_timing [-clock_from clk_signame_list] [-clock_to clk_signame_list] [-edge_from {lead | trail}] [-edge_to {lead | trail}] [-rise] [-fall] [-early | -late] [-max_slack float] [-min_slack float] [-max_paths integer | -max_points npoint] [-nworst integer] [{-from | -from_rise | -from_fall} pin_list] [{-through | -through_rise | -through_fall} pin_list] [{-to | -to_rise | -to_fall} pin_list] [-bidi_input_from | -bidi_output_from] [-bidi_input_to | -bidi_output_to] [-bidi_input_through | -bidi_output_through] [-unconstrained [-delay_limit float]] [-check_clocks] [-latch] [-path_group groupname_list] .For a clock signal. constant propagation. value Resistance value. redundancy removal.

data paths and all the other clock paths (for example. -bidi_input_to | -bidi_output_to Specifies that the bidirectional pins in the -to/-to_rise/ -to_fall pin list refer to the input or output part of the bidirectional pins. By default (without -clknet_too option). Note: If the clock_gating_regardless_of_downstream_logic global is set to true. . instead of the standard timing to data endpoints. -check_clocks Enables reports generated based on timing paths on the clock network. get_module_worst_slack does not consider clock networks at all. A clock path ending at D pin of a register is considered a data path by default because the global clock_gating_regardless_of_downstream_logic is false by default. This report includes clock paths that end at the reference end of a check or a clock gating end point. For default value.[-false_path_analysis {static | robust}] [-justify] [-true] [-tclfile tclfile_name] [-gcffile gcffile_name] [-hdl_sim_file hdlfile_name] [-spice_output filename [-spice_power_node power_rail_voltage_name_list]] [-net] [-unique_pins] [path_type {end | summary | full | full_clock}] [-check_type {setup | hold | pulse_width | clock_period | clock_gating_setup | clock_gating_hold | clock_gating_pulse_width | recovery | removal | clock_separation | skew | no_change_setup | no_change_hold}] [-format column_list] [-tcl_list] [{> | >>} filename] Valid columns are: addition arc arrival bottle cell clkordata clkordatapin delay delay_ast direction dont_modify_instance dont_modify_net edge eslack fanin fanout fpin from_edge hpin instance instance_location load lslack net phase pin pinload pin_location required slack slew stolen to_edge tpin wireload wlmodel -bidi_input_from | -bidi_output_from Specifies that the bidirectional pins in the -from/-from_rise/ from_fall pin list refer to the input or output part of the bidirectional pins. clock path ending at D pin of a register) are reported. For default value. -bidi_input_through | -bidi_output_through Specifies that the bidirectional pins in the -through/ -through_rise/through_fall pin list refer to the input or output part of the bidirectional pins. see Bidirectional Pin Defaults. By default. For default value. see Bidirectional Pin Defaults. the report_timing slack results without -check_clocks option may not match the slack numbers from get_module_worst_slack without -clknet_too option. see Bidirectional Pin Defaults.

For late paths (-late option) reports only those paths with path delay more than the delay limit. See Examples for some sample reports. clock_period. . This option cannot be used with the -unconstrained or -early |-late options. The supported check types are: setup. The -late and -early options in report_timing are meant for the data path. -edge_from {lead | trail} Enables reports generated based on source clock edge. Reports only those paths whose source clocks are the clock signals in clk_signame_list. hold. BuildGates will check late data against early clock in the -late option. removal. pulse_width. -early | -late The timing report is generated for early paths (data hold checks/ clock setup checks) or late paths (data setup checks/clock hold checks). Default is both. clock_separation. Default is both. clock_gating_hold. the -early option reports the worst slack path between the pulsewidth check and the setup check. -edge_to {lead | trail} Enables reports generated based on target clock edge. clock_gating_pulse_width. For clock signals.-check_type check_type Reports only the paths which end at the specified timing check. The default is -late. Reports only those paths whose target clocks are the clock signals in clk_signame_list. reports only those paths with path delay less than the delay limit. skew. recovery. Specifying report_timing with the -late option (the default) will report the worst slack path between the pulsewidth check and the hold check. either leading or trailing. and early data against late clock in the -early option. no_change_setup. -clock_from clk_signame_list Enables reports generated based on source clock waveform(s). Similarly. either leading or trailing. no_change_hold. not the clock path. For early paths (-early option). -delay_limit float Specifies the path delay limit for unconstrained paths (-unconstrained option). -clock_to clk_signame_list Enables reports generated based on target clock waveform(s). there is another timing criteria called the PulseWidth Check in the report. clock_gating_setup. The -delay_limit option can only be used in conjunction with the unconstrained option.

0 -max_paths 1000 Note: This still limits the report to 1000 paths. The endpoint limitation can be adjusted to a reasonable number.-from | -from_rise | -from_fall pin_list Reports paths starting from the pin(s) specified by the pin_list. you can report all violating endpoints by using: -max_slack 0. You can generate a timing report containing any path with greater than the specified slack by using the -max_paths option. -max_paths integer Reports the specified number of worst paths in the design. . it reports worst path to each endpoint by default. Use the -nworst option to report all the checks at an end point or use the -check_type option to report a specific check. The -nworst option cannot be used with the -max_paths option. Typically. The paths are always sorted based on slack. The -max_paths option cannot be used with the -max_points option. The -max_points option cannot be used with the -max_paths option. The path limitation can be adjusted to a reasonable number. This is the most frequently used report. For example. A negative value for slack indicates a timing violation. Note: This option combined with the -through and -to options provides a method for specifying particular paths in the design. -max_points integer Reports the worst path it finds to each endpoint up to the number specified by the -max_points option. The default is one worst path. The default is to show worst path to one endpoint. only the worst path to each endpoint is reported. -min_slack float Reports only those paths whose slack is greater than the value of float. regardless of the endpoint. but can be time consuming if a large number of paths are requested. -nworst integer Specifies the number of paths to be enumerated for each endpoint. Using from_rise (or -from_fall) specifies that the rising (or falling) edge of the signals on the pins in pin_list are the start of the paths. The -max_slack option limits the report to paths that fall into the specified range. A positive slack value indicates that timing was met. This is useful. If -path_type end option is specified. to report all paths with slack greater than 2ns: -min_slack 2. -max_slack float Reports only those paths with slack equal to or less than the value of float are reported. The -max_slack option cannot be used with the -unconstrained option. The -min_slack option cannot be used with the -unconstrained option.0 -max_points 1000 Note: This still limits the report to 1000 endpoints. By default.

the path is always reported as an unconstrained path. the path is either false or does not exist structurally. If no constrained or unconstrained path is found. The pin_list is a logical OR function. If no paths are found.-path_group groupname_list Reports only paths contained in the groups specified in groupname_list. Note: An asynchronous signal is applied to all the unconstrained primary inputs during this mode. . The paths that do not belong to any user-specified path group belong to the default path group named default. -to | -to_rise | -to_fall pin_list Reports paths leading to the pin(s) specified by the pin_list. -rise | -fall Reports the path with the specified edge on the endpoint. Note: The -min_slack and -max_slack options cannot be specified with the -unconstrained option. there may be unconstrained paths or false paths or the path may not exist. Using -through_rise (or through_fall) specifies that the paths go through the rising (or falling) edge of the signals on the pins in pin_list. separate -through statements are needed. -unconstrained Reports only the unconstrained paths (paths with no slack). there may be constrained paths or false paths or the path may not exist. You can report paths belonging to the default path group by using path_group default. Any number of -through pins can be specified. Each signal arriving at the path end node which does not have a matching required time. If no constrained path is found. If an endpoint is specified using -to_rise (or -to_fall) option. -through | -through_rise | -through_fall pin_list Reports paths that pass through the pin(s) specified by the pin_list. Only one list of -to pins can be specified per report. If there is an asynchronous signal (specified with '@' clock) arriving at the path end node. the rise (or -fall) option is ignored and paths with edge specified by to_rise (or -to_fall) are reported. To force the report to pass through multiple pins. The resulting path may pass through any of the pins in the -through pin_list. Using to_rise (or -to_fall) specifies that the rising (or falling) edge of the signals on the pins in pin_list are at the end of the paths. See -delay_limit option described below. See for the conditions under which a path is reported as constrained or unconstrained. results in an unconstrained path. The report_timing command without -unconstrained option reports only constrained paths. Pins in the pin_list can be either pins on the design boundary (ports) or pins on an instance.

with the false_path_analysis option. This option suppresses multiple paths that differ only because of transition polarity or conditional arcs. After report_timing the global is automatically reset back to its previous mode. Unless the -true option is used to disable printing of false paths. Only one path (the worst) is reported for unique set of pins. The -latch option cannot be used with the -max_paths. Only the worst path is reported for each end point. a false path is indicated in the report as shown in this example: Path 1: FALSE PATH -gcffile gcffilename Generates a General Constraint Format (GCF) file. These backend tools will not consider the timing on the false paths while doing placement and routing. see Identifying and Eliminating False Paths in the Timing Analysis for BuildGates Synthesis and Cadence Physically Knowledgeable Synthesis (PKS) manual. Options for Reporting False Paths In addition to the analysis that is performed by default. you can use options to perform false path analysis.-unique_pins Reports paths through unique set of pins. Note: This option can only be used with the -false_path_analysis option. gcffilename. or any of the -from* or -through* options. With this option. Note: Using this option may significantly affect runtime and memory usage if the number of paths to be reported is high. For more information. An error message is issued if gcffilename is not specified. either static or robust. -false_path_analysis {static | robust} Determines the status of a path using static (or robust) analysis. For more information. . containing GCF DISABLE constraints which correspond to the false paths identified. -nworst. latch_time_borrow_mode is automatically set to max_borrow. if not already set. see Analyzing Latch-Based Designs in the Timing Analysis for BuildGates Synthesis and Cadence Physically Knowledgeable Synthesis (PKS) manual. You must always specify the analysis type. Use gcffilename to pass the DISABLE constraints (false paths) to backend tools for operations like place and route. The following five options (-false_path_analysis through -gcffile) deal with false path analysis. Option for Latch Analysis Type -latch Reports the paths through latches in maximum time borrow latch mode.

. The sensitization criterion must be specified using the false_path_analysis option.sp. -tclfile tclfilename Generates a Tcl file.sp is the Spice representation of Path 1 in report_timing. Note: This option can only be used with the -false_path_analysis {static | robust} option.sp filename3. If report_timing gives more than one path. Options for Creating Spice Output The following two options are used to generate Spice files. BuildGates appends the suffix . tclfilename. filename2. Note: This option can only be used with the -false_path_analysis option. containing set_false_path commands corresponding to the false paths identified.sp to the given filename. Use the -hdl_sim_file option to pass the result of false path analysis to dynamic simulation tools for the purpose of verifying true paths under sequential operation. This filters out the false paths from the report and next available true paths are reported. -true Displays only identified true paths.-hdl_sim_file hdlfile_name Generates HDL simulation models for combinational TRUE paths. The false paths identified are not printed. Note: This option can only be used with the -false_path_analysis option. Note: This option can only be used with the -false_path_analysis option. -justify Gets one test vector for which the reported paths become true. The HDL simulation models are appended to the file specified by hdlfile_name. The file can be simulated in a Spice simulator for transient analysis of the path waveform.sp corresponds to Path 2 and so on. -spice_output filename Creates output in Spice format for the path reported. You can source tclfilename before running the report_timing command again.sp filename2. This option also displays a test pattern for each true path. An error message is issued if tclfilename is not specified. The Tcl file can also be sourced before performing finer timing optimizations so that the false paths are not optimized. See Generating a Spice Netlist in the Timing Analysis for BuildGates Synthesis and Cadence Physically Knowledgeable Synthesis (PKS) manual for more information. then BuildGates generates more than one output file with the following pattern: filename. filename. In this example.

full Generates a report which displays the full path with accompanying required time and slack calculation. arrival time. When the instance operating voltage value is not specified. This option can only be used in conjunction with the -spice_output option. If the file name is not specified the report is displayed on standard output. without this option. -format column_list Formats the report according to the column_list. required time. If the -unconstrained option is specified. . For example: -format {hpin cell delay required arrival required edge} See Table 7-8 for a list of valid options. The default format for the full path is: {instance arc cell delay arr req} The default net format (with -net option) for the full path is: {hpin edge net cell delay arr req}. By default. and the net delay is added to the following delay. This is the default path type. -net Adds a row for the net arc. The instance-specific operating voltage can be updated using the read_rrf command when rrf file is available. If the reported path is a clock path.-spice_power_node power_rail_voltage_name_list Ties any node whose name is in the list of power rail names to its instance operating voltage. the req column is not displayed. The -format option does not have any impact on this report format. slack. Options for Formatting and Redirecting Reports {> | >>} filename Stores the generated report in the file specified by filename. The -format option cannot be used with the -path_type end or -path_type summary options. and phase. end Generates an end point report for each path consisting of an endpoint. it also reports the full data path. either the full data path or the full clock path is reported depending on the endpoint (data or clock). The file name must be the last argument in the list. This option generates a very fast report. the rail voltage value from the operating conditions will be used. this option also reports the full clock path (Other End Path) in addition to the full data path (Timing Path). This option also separates the cell delay from the wire delay. By default. Note: The -path_type end format is identical to the format produced by the obsolete -summary option. The column_list specifies which columns to display in the timing report and the order in which they appear. full_clock If the path reported ends at a timing check. the net arc is not shown. cause. The report format can be controlled by using the -format option.

The default format. The column is labeled Clock Expected. This is useful for integrating timing with custom Tcl functions and customizing report generation. Note: The -path_type summary format differs from that produced by the obsolete -summary option. The -format option does not have any impact on this report format. cause. If stolen slack at the arc output pin (output of transparent latches) is not zero. summary Generates a summary report for each path consisting of a start point. See path type examples. Clkordatapin Delay Delay_ast . Number of paths in the report that pass through the pin. use -path_type end. Cell name of the given pin's instance. This delay typically comes from cycle addition or clock uncertainty. Arc delay. The arc as described by the from pin. if the -path_type option is not specified is full. slack. and to pin edge. to pin. and phase. The column is labeled Delay Addition. Reports if a delay has been asserted on the arc. Reports whether the given pin expects a clock signal or a data signal. -tcl_list Produces a report in a tcl list. The column is labeled Clock/Data. arrival time. required time. the arc from the rising edge of pin A to the falling edge of pin Z is reported as: A ^->Z v Arc Arrival Bottle Cell Clkordata Arrival time on the pin. To generate a report in the same format as summary. from pin edge.-path_type {end | summary | full | full_clock} The path_type option lets you choose the format of the report by path type. the stolen column is also displayed along with this column. For example. endpoint. Table 7-8 Report Timing--Column List Options Option Addition Description Delay addition on pin. Reports whether the given pin is on a clock path or a data path.

Hierarchical name of the given pin's instance. this column will be blank. Worst late slack at the given pin. Edge on the from. YES appears in the column. Edge on the pin (^=rise. this column will be blank. Otherwise. If it is. the column will be blank. This argument displays the instance column automatically. Phase name on pin. or source. Reports whether the net is dont_modify. Pin name of the given hierarchical pin. If it is. This argument displays the instance column automatically. Total fanin on the net. v=fall). This argument displays the net column automatically. Reports whether the instance is dont_modify. Otherwise. Dont_modify_net Edge Eslack Fanin Fanout Fpin From_edge Hpin Instance Instance_location Load Lslack Net Phase Pin Pinload Pin_location .y) of the instance. Hierarchical name of the net connected to given pin. YES appears in the column. If the design is not placed. If the design is not placed.y) of the pin. Location (x. Total capacitive load from pins on a given pin. the column will be blank. Total capacitive load on a given pin. From or source pin of the arc. Location (x. OUT). Hierarchical pin name. Total fanout on the net. Worst early slack at the given pin. including its own load. pin.Direction Dont_modify_instance Pin direction (IN.

00 kOhm | +--------------------------------------------+ . or sink.Required Slack Slew Stolen Required time on the pin. Propagated slew at the given pin Slack stolen (or the time given to previous stage) at the given pin. Wireload model used to calculate load on the net.30 | | Temperature | 25.00 pF | | resistance unit | 1. To_edge Tpin Wireload Wlmodel Examples >report_timing -to out +--------------------------------------------+ | Report | report_timing | |---------------------+----------------------| | Options | -to out | +---------------------+----------------------+ | Date | 20000120. (only visible on the output of transparent latches.0-eng | | Version | Aug 18 2000 07:33:54 | +---------------------+----------------------+ | Module | top | | Timing | LATE | | Slew Propagation | FAST | | Operating Condition | CTLF_OP_COND | | PVT Mode | worst_case | | Tree Type | worst_case | | Process | 1.00 | | Voltage | 3. pin of the arc. this column is displayed by default. If the slack is not zero and the delay column is specified. or sink. Slack on the pin (this is the same for the entire path). Total capacitive load from the wire on a given pin.) Edge on the to.00 | | time unit | 1.204141 | | Tool | ac_shell | | Release | v4.00 ns | | capacitance unit | 1. To. pin.

39 | -8.25 +--------------------------------------------------------------------+ | Instance | Arc | Cell | Delay | Arrival | Required | | | | | | Time | Time | |---------------+-------------+---------+-------+---------+----------| | | clkC ^ | | | 0.26 | -8.99 | | J_block/zbuf0/A | ^ | J_block/w03 | BUFA | 0.00 = Required Time 0.External Delay 1.05 | -9.Path 1: VIOLATED External Delay Assertion Endpoint: out (^) checked with trailing edge of 'CLK1' Beginpoint: J_block/C_reg/Q (^) triggered by leading edge of 'CLK2' Other End Arrival Time 2.00 | 0.05 | -9.52 | -8.52 | -8.25 | 0.00 | 9.73 | 9.00 | 0.00 + Phase Shift -1.73 | | J_block/u000/A | ^ | J_block/Z | AND2L | 0.25 | 0.99 | | J_block/zbuf0 | A ^ -> Z ^ | BUFA | 0.00 | | J_block/out | ^ | out | J_block | | 9.99 | | J_block/zbuf0/Z | ^ | J_block/w03prime | BUFA | 0.05 | -9.00 .20 | | J_block/C_reg/Q | ^ | J_block/w03 | FD1QA | 0. The format of the report is similar to the first example.Arrival Time 9.13 | 0.0 .20 | | J_block/clkc | ^ | J_block/clkc | J_block | | 0.86 | | J_block/zbuf1 | A ^ -> Z ^ | BUFA | 0.00 | 9.05 | -9.00 | | J_block | out ^ | J_block | | 9.86 | | J_block/zbuf1/A | ^ | J_block/w03prime | BUFA | 0.20 | | J_block/C_reg | CP ^ -> Q ^ | FD1QA | 0.26 | -8.25 | 0.13 | 0.00 | 0.25 = Slack Time -9.52 | -8.21 | 0.00 | 0.21 | 0.13 | 0.26 | -8.25 | 0.73 | | J_block/u000 | A ^ -> Z ^ | AND2L | 8.00 | +------------------------------------------------------------------------------------+ The following displays the worst late path in the design.00 | +--------------------------------------------------------------------+ The following command gives a report similar to the first with the addition of net arc information.73 | 9.00 | | out | ^ | out | top | 0.25 | 0.00 .73 | | J_block/u000/Z | ^ | J_block/out | AND2L | 8.0: report_timing -max_slack -1.00 | | | out ^ | | 0.39 | -8.05 | -9.20 | | J_block | clkc ^ | J_block | | 0. report_timing The following displays the worst late path to each violating endpoint that has a slack less than -1.86 | | J_block/zbuf1/Z | ^ | J_block/Z | BUFA | 0.20 | | J_block/C_reg/CP | ^ | J_block/clkc | FD1QA | 0. >report_timing -to {out[4]} -net +------------------------------------------------------------------------------------+ | Pin | Edge | Net | Cell | Delay | Arrival | Required | | | | | | | Time | Time | |------------------+-------+------------------+---------+-------+---------+----------| | clkC | ^ | clkC | | | 0.13 | 0.25 | 0.39 | -8.

Use the syntax shown in the example. only the 1000 worst paths are reported.The following displays all the late paths that end at port out[2] and that have negative slack up to a maximum of 1000 worst paths. more than one path may exist: report_timing -from i102/Z -to i123/A -max_paths 10 The following enumerates the worst ten paths through the given two pins. The path only has to satisfy one element in a through list. This is similar to using the -from option.0 The following reports the worst late path that starts at in[0] and ends at out[1]. Only the paths between the specified pins are enumerated. or blocks B and C. report_timing -from in[0] -to out[1] The following displays the three worst paths that start at in[1] and end at out[3]. Do not use -through {A B}. but all through lists must be satisfied. more than one path may exist: report_timing -from in[1] -to out[3] -max_paths 3 The following displays the ten worst paths. If there are more than 1000 paths. Similar to report_timing -max_paths 10 -to out[1]. report_timing -through -through A -through B The following reports the worst endpoint and the ten worst paths to that endpoint. report_timing -to out[2] -max_paths 1000 -max_slack 0. if out[1] is the worst endpoint: report_timing -max_points 1 -nworst 10 . report_timing -through i102/Z -through i123/A -max_paths 10 The following reports the ten worst paths through blocks A and C.With reconvergent fanout. With reconvergent fanout. starting at the beginning points in the design and ending at the endpoints. report_timing -through {A/*B/*} -through {C/*} -max_paths 10 The following forces a path through pin A and pin B. The example can be thought of as ((A or B) and C).

18 | 10.181608 | | Tool | ac_shell | | Release | v4.17 | 10.00 ns | | capacitance unit | 1.00 pF | | resistance unit | 1.16 | +--------------------------------------------------+ ac_shell[3]>report_timing -unconstrained -summary +--------------------------------------------+ | Report | report_timing | |---------------------+----------------------| | Options | -unconstrained | | | -summary | +---------------------+----------------------+ | Date | 20010122.17 | | buf1 | A ^ -> Z ^ | BUF8A | 0.07 | 11.00 | | nand1 | B v -> Z ^ | ND2 | 0.00 | | Temperature | 25.09 | | nand4 | A v -> Z ^ | ND2 | 0.181053 | | Tool | ac_shell | | Release | v4.74 | 11.16 | | | O2 ^ | | 0.00 kOhm | +--------------------------------------------+ Path 1:Endpoint: O2 (^) Beginpoint: reg2/Q (v) triggered by trailing edge of 'vclk' +--------------------------------------------------+ | Instance | Arc | Cell | Delay | Arrival | | | | | | Time | |----------+-------------+-------+-------+---------| | | clk1 v | | | 10. ac_shell[6]>report_timing -unconstrained +--------------------------------------------+ | Report | report_timing | |---------------------+----------------------| | Options | -unconstrained | +---------------------+----------------------+ | Date | 20010122.35 | | reg2 | CP ^ -> Q v | FD1 | 0.1-eng | | Version | Jan 22 2001 15:25:02 | +---------------------+----------------------+ | Module | scid | | Timing | LATE | | Slew Propagation | WORST | | Operating Condition | NOM | | PVT Mode | max | | Tree Type | balanced | | Process | 1.The next two examples illustrate the -unconstrained option.00 | 11.00 | | Voltage | 5.00 | | time unit | 1.1-eng | | Version | Jan 22 2001 15:25:02 | +---------------------+----------------------+ | Module | scid | | Timing | LATE | | Slew Propagation | WORST | | Operating Condition | NOM | | PVT Mode | max | | Tree Type | balanced | .

| Process | 1.0 I set_external_delay -clock ck1 1.00 | | Temperature | 25.00 | | Voltage | 5.0 I No set_external_delay constraint on O set_external_delay -clock ck1 1.15 | Unconstrained | | nand1/A v | Unconstrained Path | 0.00 | | time unit | 1.0 I set_external_delay -clock ck2 1.0 O set_input_delay -clock ck1 1.00 kOhm | +--------------------------------------------+ +----------------------------------------------------------+ | Pin | Cause | Arrival | Phase | |-----------+--------------------+---------+---------------| | O2 ^ | Unconstrained Path | 10.70 | vclk P | | reg2/D ^ | Unconstrained Path | 0.00 pF | | resistance unit | 1.0 O o o o • The path from I to O is reported as a constrained path under the following conditions (constraints on I and O): o set_input_delay -clock ck1 1.15 | Unconstrained | | reg4/D v | Unconstrained Path | 0.0 I set_external_delay 1. Figure 7-3 Conditions for Unconstrained and Constrained Paths • The path from I to O is reported as an unconstrained path under the following conditions (constraints on I and O): o o No constraints on either I or O set_input_delay -clock ck1 1.1 O set_input_delay -clock ck1 1.17 | Unconstrained | | reg1/D v | Unconstrained Path | 0.00 ns | | capacitance unit | 1.24 | Unconstrained | | reg3/D ^ | Unconstrained Path | 0.82 | vclk N | | O1 v | Unconstrained Path | 0.0 O No set_input_delay constraint on I set_input_delay 1.0 O o .0 I set_data_required_time -clock ck2 1.00 | Unconstrained | +----------------------------------------------------------+ The following examples refer to Figure 7-3.

90 | 0. The results are given below: +-----------------------------------------------------------------------------+ | Instance tmp_reg of FD1 |-----------------------------------------------------------------------------| | Check | Sig | Ref | Slack | Delay | Adjust | Sig | Ref |------------+-------+-------+-------+---------+---------+----------+---------| | PULSEWIDTH | CP ^ | CP v | 14.05 | 0.00 . report_timing -early shows: Path 1: MET PulseWidth Check with Pin tmp_reg/CP Endpoint: tmp_reg/CP (v) checked with leading edge of 'c1' Beginpoint: c1 (v) triggered by trailing edge of 'c1' Other End Arrival Time 0.00 | c1(D)(P) | c1(C)(P) | SETUP | D ^ | CP ^ | 28.0 I set_data_required_time 1.Arrival Time 0.42 + Phase Shift 0.42 .00 + PulseWidth 0.0 O o set_input_delay 1.0 O set_data_required_time -clock ck2 1.00 | c1(D)(P) | c1(C)(P) | SETUP | D v | CP ^ | 27. First the report_cell_instance_timing command is used to show all of the checks for the instance. Consider the following instance of a flip-flop. report_timing (default -late) shows: Path 1: MET Hold Check with Pin tmp_reg/D Endpoint: tmp_reg/CP (^) checked with leading edge of 'c1' Beginpoint: c1 (^) triggered by leading edge of 'c1' Other End Arrival Time 1.05 + Phase Shift 0.00 | c1(C)(P) | c1(C)(P) | HOLD | D ^ | CP ^ | 1.0 I set_data_required_time -clock ck1 1.05 .00 | c1(D)(P) | c1(C)(P) | HOLD | D v | CP ^ | 1.58 | 0.00 | c1(D)(P) | c1(C)(P) +-----------------------------------------------------------------------------+ | | | | | | | | Since the hold check has worse slack than pulsewidth check.42 | 0.o set_data_arrival_time -clock ck1 1.86 | 0.00 = Required Time 0.0 I set_data_required_time -clock ck2 1.0 I set_input_delay -clock ck2 1.Arrival Time 15.14 | -30.0 O • Two paths from I to O are reported one as a constrained path and the other one as an unconstrained path under the following conditions (constraints on I and O): o set_input_delay -clock ck1 1.00 + Hold 0.07 | 0.00 = Required Time 1.00 | c1(C)(P) | c1(C)(P) | PULSEWIDTH | CP v | CP ^ | 14.93 | 0.37 | -30.1 O This example is intended to help you understand -late and -early reports for clock signals.00 = Slack Time 1.10 | -30.63 | 0.05 And similarly. since pulsewidth check has worse slack than setup check.05 | -0.

00 + Time Borrowed 2.00 | 2.= Slack Time 14.Arrival Time 1.18 | | inv0 | A v -> Z ^ | IV | 0.25 | +------------------------------------------------------------+ >report_timing -through ld1/Q #header deleted Path 1: MET External Delay Assertion Endpoint: O (v) checked with leading edge of 'CK1' Beginpoint: ld1/Q (^) triggered by leading edge of 'CK1' Other End Arrival Time 0.07 | 2.21 + G (^) -> Q (^) Delay 0.00 = Required Time 2. .21 | 2.75 | 3.25 | | ld1 | D ^ | LD1 | 0.82 | 4.18 +-----------------------------------------------------------------------+ | Instance | Arc | Cell | Delay | Time | Arrival | Required | | | | | | Given To | Time | Time | | | | | | Previous | | | | | | | | Stage | | | |----------+------------+-------+-------+----------+---------+----------| | | CK ^ | | | 0. >report_timing #header deleted Path 1: MET Latch Borrowed Time Check with Pin ld1/G Endpoint: ld1/D (^) checked with leading edge of 'CK1' Beginpoint: I (v) triggered by leading edge of 'CK1' Other End Arrival Time 0.00 | 1.00 | 1. see Analyzing Latch-Based Designs in the Timing Analysis for BuildGates Synthesis and Cadence Physically Knowledgeable Synthesis (PKS) manual.00 | 0.82 | 4.00 | 2.93 | | inv1 | A ^ -> Z v | IV | 0.25 .51 + Phase Shift 0.07 | 1.07 = Slack Time 1.00 | +-----------------------------------------------------------------------+ The following command changes the format of the report. Compare the output to that shown in the first example (report_timing -to out).00 + Phase Shift 5.18 +------------------------------------------------------------+ | Instance | Arc | Cell | Delay | Arrival | Required | | | | | | Time | Time | |----------+------------+-------+-------+---------+----------| | | I v | | | 1.00 | | | O v | | 0.00 = Required Time 4.D (^) -> Q (^) Delay 0.00 .07 | 2.Arrival Time 2. For a comparison of reports using max_borrow analysis mode.54 .82 = Slack Time 1.54 | 2.58 The next two examples illustrate the transparent latch reports using the default global setting latch_time_borrow_mode budget.00 | 2.18 | | ld1 | G ^ -> Q ^ | LD1 | 0.00 .07 | 0.00 | 0.External Delay 1.

Note that filename must be the last argument in the list. The numbers in each Cell Area column represent the area in square microns (TLF) and in terms of the number of SITES used (LEF). net area.00 | 0.21 | 0.00 | .25 | +--------------------------------------------------------------------------+ report_area report_area [-summary] [-block] [-hierarchical] [-cells] [{ > | >> } filename] Generates a report on the area of the netlist.05 | | J_block/C_reg | CP ^ -> Q ^ | J_block/w03 | 0.00 | 0.. -summary Area report is presented in summary form. The information contained in the report is dependent on the options used with the command.05 | | J_block | clkc ^ | J_block/clkc | | | 0. The summary information contains name of the current module. If this option is not used.26 | | J_block/zbuf0 | A ^ -> Z ^ | J_block/w03prime | 0. -hierarchical Area report is presented for the entire hierarchy below the current module.68 | .39 | | J_block/zbuf1 | A ^ -> Z ^ | J_block/Z | 0. wire load model used..00 | 0.13 | 0.73 | 9. Source of Area : Timing Library +--------------------------------------------------------------------------+ | Module | Wireload | CellArea | Net Area | Total Area | |-------------+-----------------------+------------+----------+------------| |CSR1KT_viter | TSMC256K_Conservative | 1114025.>report_timing -to out -format {instance arc net load delay arrival} +--------------------------------------------------------------------------+ | Instance | Arc | Net | Load | Delay | Arrival | | | | | | | Time | |---------------+-------------+------------------+-------+-------+---------| | | clkC ^ | clkC | | | 0. .68 | 0. and total area.13 | 0.20 | 8. Source of Area : LEF +--------------------------------------------------------------------------+ | Module | Wireload | Cell Area | Net Area | Total Area | |-------------+-----------------------+------------+----------+------------| |CSR1KT_viter | TSMC256K_Conservative | 656313.00 | 656313. { > | >> } filename Name of the file in which report will be saved.52 | | J_block/u000 | A ^ -> Z ^ | J_block/out | 3. the data is presented only for the current module. cell area.25 | | J_block | out ^ | out | | | 9.00 | 0..25 | | | out ^ | | | 0. You can convert the LEF area units to square microns by multiplying the SITE SIZE X* Y.. The following examples show reports where the area is taken from a TLF (or ALF) file and a LEF file. If filename is not specified.00 | 1114025.00 | 9. the report is displayed on the standard output.

.00 19.rpt and store it under the directory reports. name and count of cells used.00 Example: ac_shell> report_area –hier –cells > reports/area.-cells Area report is presented on every cell (block) in the current module.00 Number of non-combinational instances 0 Number of hierarchal instances Number of blackbox instances Total number of instances Area of combinational cells Area of non-combinational cells Total cell area Number of nets Area of nets Total area 2 0 5 19.00 471 0. If no options are specified. -block Provides a block summary.00 14151. summary report of cumulative design hierarchy.00 0.00 1721 0. then a summary area report will be generated.rpt Note: this example is to generate a area report and print on a file name area. The cell report includes summary report for current module. type of cells used.00 9970. net area and total design area.00 19. area for each cell.00 14151. See the table below. total cell area. Block report for module am Number of combination instances Current Module Cumulative 3 812 438 10 1 1261 4181.

The information contained in the report depends on the options used. filename must be the last argument in the list. -current_module_only Only the violations in the current module are reported. -verbose Reports all design rules for every net and port in the design regardless of whether there were any violations or not. with the current module as the top of the hierarchy. the report is displayed on standard output. {> | >>} filename Specifies the name of the report file. The following a example will generate a violations report name drc_violations and store under the directory reports. Example: ac_shell> report_design_rule_violations > reports/drc_violations Report_hierarchy report_hierarchy [-inst] [-tcl_list] [{> | >>} filename] The report_hierarchy command reports the structural hierarchy as it exists at various stages in the synthesis process. The report uses the following symbols to distinguish hierarchical blocks: b g o Black box module Generic (unmapped) module Optimized module attribute is set for this module -inst x dont_modify m Module contains a mapped view . -ignore_clknet The clock net violations are not reported. The hierarchy reported is always that of the netlist in memory. The worst violations are reported for every violating net. -summary Provides a summary report of the violations on each net (instead of listing all of the violations). -ignore_dont_modify_nets Does not report design rule violations for nets that are set dont_modify. -hierarchical Reports the violations for hierarchical ports. If filename is not specified.report_design_rule_violations report_design_rule_violations [-ignore_clknet] [-current_module_only] [-verbose] [-ignore_dont_modify_nets] [{ > | >> } filename] [-summary][-hierarchical] It generates a report on all the design rule violations in the design.

-equation Writes the verilog output without reference to atl. Modules that are multiply instantiated will include a separate line of output for each instantiation. {> | >>} filename Generated report is stored in the file specified by filename. as shown in the example below. Example: ac_shell> report_hierarchy > reports/hier. If this option is not used. each combinational or tristate cell instance is represented with an equation. or library cells. Note that filename must be the last argument in the list. If the filename is not specified then the report is displayed on standard output. and a simulation model for each sequential cell is written out. -tcl_list Reports the hierarchy in the form of a Tcl list. xatl. use a Tcl variable. To use the output of the Tcl list to generate Tcl code. verilog_file_name Specifies the file in which the Verilog netlist will be saved. Instead.rpt write_verilog write_verilog [-hierarchical] [-equation] verilog_file_name It writes out a netlist stored in the database in Verilog format. -hierarchical Writes the netlist out as a hierarchical netlist. Example: ac_shell> write_verilog -hier netlists/design. The netlist is generated by the do_build_generic command or do_optimize command.vs .Includes the instance name of the module instantiation in the output. such as ACL modules. This to generate a gate-level netlist of the design that was synthesized and store it into the directory netlists. the command writes out a netlist for the current module and any implied hierarchy created by BuildGates Synthesis.

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