This action might not be possible to undo. Are you sure you want to continue?
32 k x 8 Bit Organization
The ON Semiconductor serial SRAM family includes several integrated memory devices including this 256 kb serially accessed Static Random Access Memory, internally organized as 32 k words by 8 bits. The devices are designed and fabricated using ON Semiconductor’s advanced CMOS technology to provide both high−speed performance and low power. The devices operate with a single chip select (CS) input and use a simple Serial Peripheral Interface (SPI) serial bus. A single data in and data out line is used along with a clock to access data within the devices. The N25S818HA devices include a HOLD pin that allows communication to the device to be paused. While paused, input transitions will be ignored. The devices can operate over a wide temperature range of −40°C to +85°C and can be available in several standard package offerings.
http://onsemi.com MARKING DIAGRAMS
TSSOP−8 T SUFFIX CASE 948AL
C114 XXXXYZZ SOIC−8 S SUFFIX CASE 751BD XXXX Y ZZ = Date Code = Assembly Code = Lot Traceability
• • • • •
• • • • • • •
Power Supply Range: 1.7 to 1.95 V Very Low Standby Current: Typical Isb as low as 200 nA Very Low Operating Current: As low as 3 mA Simple Memory Control: Single chip select (CS) Serial input (SI) and serial output (SO) Flexible Operating Modes: Word read and write Page mode (32 word page) Burst mode (full array) Organization: 32 k x 8 bit Self Timed Write Cycles Built−in Write Protection (CS High) HOLD Pin for Pausing Communication High Reliability: Unlimited write cycles Green SOIC and TSSOP These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant
Device N25S818HAS21I N25S818HAT21I N25S818HAS21IT N25S818HAT21IT Package SOIC−8 (Pb−Free) TSSOP−8 (Pb−Free) SOIC−8 (Pb−Free) TSSOP−8 (Pb−Free) Shipping† 100 Units / Tube 100 Units / Tube 3000 / Tape & Reel 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
June, 2012 − Rev. 12
Publication Order Number: N25S818HA/D
com 2 . PIN NAMES Pin Name CS SCK SI SO HOLD NC VCC VSS Pin Function Chip Select Input Serial Clock Input Serial Data Input Serial Data Output Hold Input No Connect Power Ground SCK Clock Circuitry HOLD CS Decode Logic SI Data In Receiver SRAM Array SO Data Out Buffer Figure 2. Pin Connections (Top View) Table 1. Functional Block Diagram http://onsemi.8 Speed (MHz) 16 Package SOIC TSSOP Typical Standby Current 200 nA Read/Write Operating Current 3 mA @ 1 Mhz Table 2. DEVICE OPTIONS Part Number N25S818HAS2 N25S818HAT2 Density 256 Kb Power Supply (V) 1.N25S818HA CS SO NC VSS 1 VCC HOLD SCK SI TSSOP−8 CS SO NC VSS SOIC−8 1 VCC HOLD SCK SI Figure 1.
3 VCC – 0.2 0.8 Unit V V V V V mA mA mA mA mA nA 1. TA = 25°C VIN = 0 V.3 –0.N25S818HA Table 3. IOUT = 0 F = fCLK MAX.3 to VCC + 0. Typical values are measured at Vcc = Vcc Typ. IOUT = 0 F = 10 MHz.5 500 –40 to 125 −40 to +85 260°C.7 x VCC −0. Functional operation above the Recommended Operating Conditions is not implied. VOUT = 0 to VCC F = 1 MHz. These parameters are verified in device characterization and are not 100% tested http://onsemi. f = 1 MHz.5 3 6 10 500 Typ (Note 1) Max 1. f = 1 MHz. OPERATING CHARACTERISTICS (Over Specified Temperature Range) Item Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Current Symbol VCC VIH VIL VOH VOL ILI ILO ICC1 ICC2 ICC3 Standby Current ISB IOH = −0.5 0.4 mA IOL = 1 mA CS = VCC.OUT VCC PD TSTG TA TSOLDER Rating –0.95 VCC + 0.3 0. Table 4. VIN = VSS or VCC 200 Test Conditions 1. Maximum Ratings are stress ratings only.8 V Device Min 1.com 3 . VIN = 0 to VCC CS = VCC. ABSOLUTE MAXIMUM RATINGS Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time Symbol VIN. CAPACITANCE (Note 2) Item Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN = 0 V. TA = 25°C Min Max 7 7 Unit pF pF 2.7 0. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5.5 0. TA = 25°C and are not 100% tested. IOUT = 0 CS = VCC.3 to 4. 10 sec Unit V V mW °C °C °C Stresses exceeding Maximum Ratings may damage the device..
TIMING Item Clock Frequency Clock Rise Time Clock Fall Time Clock High Time Clock Low Time Clock Delay Time CS Setup Time CS Hold Time CS Disable Time SCK to CS Data Setup Time Data Hold Time Output Valid From Clock Low Output Hold Time Output Disable Time HOLD Setup Time HOLD Hold Time HOLD Low to Output High−Z HOLD High to Output Valid Symbol fCLK tR tF tHI tLO tCLD tCSS tCSH tCSD tSCS tSU tHD tV tHO tDIS tHS tHH tHZ tHV 10 10 10 50 0 20 32 32 32 32 50 32 5 10 10 32 Min Max 16 2 2 Units MHz ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns http://onsemi.com 4 .N25S818HA Table 6.1 VCC to 0. TIMING TEST CONDITIONS Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Operating Temperature 0.5 VCC CL = 100 pF −40 to +85°C Table 7.9 VCC 5 ns 0.
Serial Output Timing CS tHS SCK tHH SO n+2 n+1 tHZ SI n+2 n+1 n Don’t Care n n High−Z tHV n tSU n−1 n−1 tHH tHS HOLD Figure 5.com 5 . Serial Input Timing CS tLO SCK tV SO MSB out Don’t Care LSB out tHI tCSH tDIS SI Figure 4. Hold Timing http://onsemi.N25S818HA tCSD CS tR tCSS SCK tSU SI MSB in tHD LSB in tF tCSH tCLD tSCS SO High−Z Figure 3.
If CS is brought high during a program cycle. after the initial word of data is shifted out. the address counter wraps to the address 0000h. If operating in page mode. data and instructions are latched on the rising edge of SCK. This can be continued for the entire array and when the highest address is reached (7FFFh). HOLD must be pulled high while the SCK pin is low. the user can assert the HOLD input and place the device into a Hold mode. this input may be taken low to pause serial communication without resetting the serial sequence. This allows the burst read cycle to be continued indefinitely. Lowering the HOLD input at any time will take to SO output to High−Z. the cycle will complete and then the device will enter standby mode. A high level is required for normal operation. the data stored at the next memory location can be read sequentially by continuing to provide clock pulses. http://onsemi. The device must remain selected during this sequence. the Hold function will not be invoked until the next SCK high to low transition. First. the data stored at that address in memory is shifted out on the SO pin after the output valid time from the clock edge. If SCK is not low. The pin must be brought low while SCK is low for immediate use. Once the device is selected and a serial sequence is started. It may also interface with other non−SPI ports by programming discrete I/O lines to operate the device. after the initial word of data is shifted out. When CS is high. the 8−bit READ instruction is transmitted to the device followed by the 16−bit address with the MSB being a don’t care. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. After releasing the HOLD pin. To resume operations. CONTROL SIGNAL DESCRIPTIONS Signal CS Name Chip Select I/O I Description A low level selects the device and a high level puts the device in standby mode. INSTRUCTION SET Instruction READ WRITE RDSR WRSR Instruction Format 0000 0011 0000 0010 0000 0101 0000 0001 sampled on the first rising edge of SCK after CS goes low. The following table contains the possible instructions and formats. All READ operations are terminated by pulling CS high.N25S818HA Table 8. the data stored at the next memory location on the page can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is read out. At the end of the page. the operation will resume from the point where it was held. the addresses pointer will be wrapped to the 0 word address within the page and the operation can be continuously looped over the 32 words of the same page. The serial SRAM contains an 8−bit instruction register and is accessed via the SI pin. If operating in burst mode. All instructions. Data is transferred out after the falling edge of SCK. SO is high−Z during the Hold time and SI and SCK are inputs are ignored. If the clock line is shared. Data is Table 9. CS must be driven low after power−up prior to any sequence being started. SO is in high−Z. addresses and data are transferred MSB first and LSB last. Receives instructions. Data out is updated on SO after the falling edge of SCK. Synchronizes all activities between the memory and controller.com 6 . Description Read data from memory starting at selected address Write data to memory starting at selected address Read status register Write status register READ Operations The serial SRAM READ is selected by enabling CS low. addresses and data on the rising edge of SCK. After the READ instruction and addresses are sent. All incoming addresses. SCK Serial Clock I SI SO HOLD Serial Data In Serial Data Out Hold I O I Functional Operation Basic Operation The 256 Kb serial SRAM is designed to interface directly with a standard Serial Peripheral Interface (SPI) common on many standard micro−controllers. This can be continued for the entire page length of 32 words long. The CS pin must be low and the HOLD pin must be high for the entire operation.
com 7 . Page and Burst READ Sequence http://onsemi. Word READ Sequence CS 0 SCK Instruction SI 0 0 0 0 0 0 1 1 15 14 16−bit address 13 12 2 1 0 Don’t Care Data Out from ADDR 1 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 ADDR 1 SO High−Z 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Don’t Care Data Out from ADDR 2 7 6 5 4 3 2 1 0 7 Data Out from ADDR 3 6 5 4 3 2 1 0 . 7 Data Out from ADDR n 6 5 4 3 2 1 0 Figure 7..N25S818HA CS 0 SCK Instruction SI 0 0 0 0 0 0 1 1 15 14 16−bit address 13 12 2 1 0 Data Out SO High−Z 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 Figure 6..
additional data words can be written as long as the address requested is sequential on the same page. the data to be stored in memory is shifted in on the SI pin. This can be continued for the entire page length of 32 words long. This can be continued for the entire array and when the highest address is reached (7FFFh).com 8 . If operating in page mode..N25S818HA SI 16−bit address Page address (X) Word address (Y) SO Page X Word Y Page X Word Y+1 Page X Word Y+2 Page X Word 31 Page X Word 0 Page X Word 1 Data Words: sequential. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is written in. at the end of the page the address wraps back to the beginning of the page Figure 8. Page X Page X+1 Page X+1 Word Y+1 Word Y−1 Word Y Figure 9. 21 22 23 24 25 26 27 28 29 30 31 16−bit address 13 12 . The new data will replace data already stored in the memory locations. 2 1 0 7 6 Data In 5 4 3 2 1 0 SO High−Z Figure 10. the addresses pointer will be wrapped to the 0 word address within the CS 0 SCK Instruction SI 0 0 0 0 0 0 1 0 15 14 1 2 3 4 5 6 7 8 9 10 11 page and the operation can be continuously looped over the 32 words of the same page. First. This allows the burst write cycle to be continued indefinitely. at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. If operating in burst mode. the new data will replace data already stored in the memory locations. additional data words can be written to the next sequential memory locations by continuing to provide clock pulses. after the initial word of data is shifted in. At that time.. Simply write the data on SI pin and continue to provide clock pulses... Word WRITE Sequence http://onsemi. After the WRITE instruction and addresses are sent. Page READ Sequence SI 16−bit address Page address (X) Word address (Y) SO Page X Word Y Page X Word Y+1 Data Words: sequential. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. Burst READ Sequence WRITE Operations The serial SRAM WRITE is selected by enabling CS low. the 8−bit WRITE instruction is transmitted to the device followed by the 16−bit address with the MSB being a don’t care. . At the end of the page. after the initial word of data is shifted in.. Page X Word 31 Page X Word 0 Page X Word 1 .. the address increments to the next page and the burst continues. Again. All WRITE operations are terminated by pulling CS high. the address counter wraps to the address 0000h.
Burst WRITE Sequence http://onsemi. Page X Word 31 Page X Word 0 Page X Word 1 . At that time.. SO High−Z Figure 13. the address increments to the next page and the burst continues. 7 Data In to ADDR n 6 5 4 3 2 1 0 High−Z Figure 11..com 9 ... Page and Burst WRITE Sequence Data Words: sequential. Page WRITE Sequence SI 16−bit address Page address (X) Word address (Y) Page X Word Y Page X Word Y+1 . Page X Page X+1 Page X+1 Word Y+1 Word Y−1 Word Y Data Words: sequential. at the end of the page the address wraps back to the beginning of the page SI 16−bit address Page address (X) Word address (Y) SO Page X Word Y Page X Page X Page X Word 31 Page X Word 0 Page X Word 1 Word Y+1 Word Y+2 High−Z Figure 12... at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address.N25S818HA CS 0 SCK Instruction SI 0 0 0 0 0 0 1 0 15 14 16−bit address 13 12 2 1 0 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 ADDR 1 SO High−Z Data In to ADDR 1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Data In to ADDR 2 7 6 5 4 3 2 1 0 7 Data In to ADDR 3 6 5 4 3 2 1 0 .
Several of the register bits must be set to a low ‘0’ if any of the other CS 0 1 2 3 4 5 6 7 bits are written. The device is in low−power standby state with CS = 1. A low level on CS is required to enter an active state. The timing sequence to write to the status register is shown below. WRITE Status Register Sequence Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mode 0 1 0 1 0 = Word Mode (Default) 0 = Page Mode 1 = Burst Mode 1 = Reserved Reserved Must = 0 Reserved Must = 0 Hold Function 0 = Hold (Default) 1 = No Hold Figure 15.N25S818HA WRITE Status Register Instruction (WRSR) This instruction provides the ability to write the status register and select among several operating modes. READ Status Register Instruction (RDSR) Power−Up State The serial SRAM enters a know state at power−up time. SCK 8 9 10 11 12 13 14 15 Instruction SI 0 0 0 0 0 0 0 1 7 6 Status Register Data In 5 4 3 2 1 0 SO High−Z Figure 14. http://onsemi. The register may be read at any time by performing the following timing sequence. Status Register READ Status Register Instruction (RDSR) This instruction provides the ability to read the Status register. followed by the organization of the status register.com 10 . CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Status Register Data Out SO High−Z 7 6 5 4 3 2 1 0 Figure 16.
30 4.50 0.30 NOM MAX 1.30 0. Angles in degrees. 4.05 0.05 0.90 1.50 4.00 6.20 3.40 0.10 6.15 0.90 6.65 BSC 1. L1 END VIEW L http://onsemi.60 0.19 0.4x3 CASE 948AL−01 ISSUE O b SYMBOL A A1 A2 b E1 E c D E E1 e L L1 MIN 0.com 11 .09 2.75 θ e 0º 8º TOP VIEW D A2 A q1 c A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-153.50 0.N25S818HA PACKAGE DIMENSIONS TSSOP8.00 REF 3.80 0.20 0.40 4.
A listing of SCILLC’s product/patent coverage may be accessed at www. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe. any claim of personal injury or death associated with such unintended or unauthorized use. including “Typicals” must be validated for each customer application by customer’s technical experts.25 0. (2) Complies with JEDEC MS-012.00 θ 0º 8º D h A1 A θ c e SIDE VIEW b L END VIEW Notes: (1) All dimensions are in millimeters. or authorized for use as components in systems intended for surgical implant into the body.27 NOM MAX 1. costs.40 MIN 1.N25S818HA PACKAGE DIMENSIONS SOIC 8. SCILLC makes no warranty.33 0.10 0.20 4. All operating parameters.80 1. affiliates. employees. trade secrets.19 4. subsidiaries. SCILLC reserves the right to make changes without further notice to any products herein.onsemi.O. SCILLC is an Equal Opportunity/Affirmative Action Employer. SCILLC does not convey any license under its patent rights nor the rights of others.pdf. or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. intended. SCILLC owns the rights to a number of patents. This literature is subject to all applicable copyright laws and is not for resale in any manner. SCILLC products are not designed.com N. or other applications intended to support or sustain life. Denver.com/site/pdf/Patent−Marking.com/orderlit For additional information.25 5.51 0. nor does SCILLC assume any liability arising out of the application or use of any product or circuit. consequential or incidental damages.onsemi.27 BSC 0.80 3.35 0. and reasonable attorney fees arising out of.com 12 N25S818HA/D . Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application. copyrights. even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. including without limitation special. directly or indirectly. trademarks. and other intellectual property. Angles in degrees. ON Semiconductor and are registered trademarks of Semiconductor Components Industries. LLC (SCILLC). Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 ON Semiconductor Website: www. Box 5163. Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi. and expenses.50 1. Buyer shall indemnify and hold SCILLC and its officers.onsemi. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. please contact your local Sales Representative http://onsemi.com Order Literature: http://www. damages.80 5. representation or guarantee regarding the suitability of its products for any particular purpose.25 0. and specifically disclaims any and all liability. 150 mils CASE 751BD−01 ISSUE O SYMBOL A A1 b c E1 E D E E1 e h L PIN # 1 IDENTIFICATION TOP VIEW 0.75 0. and distributors harmless against all claims.00 6. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.
This action might not be possible to undo. Are you sure you want to continue?
We've moved you to where you read on your other device.
Get the full title to continue reading from where you left off, or restart the preview.