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HW1.VLSI1.soln

HW1.VLSI1.soln

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VLSI Soln
VLSI Soln

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12/07/2013

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HOMEWORK 1 Problems 1-5 carry 5 points each Problem 6 carries 10 points Problem 7 carries 15 points [Partial credit allowed for

correct concepts]

SOLUTIONS
1. Use the laws of Boolean algebra to prove the following identity: x'yz' + xyz' + xyz = yz' + xy (where ' denotes complementation). LHS = x'yz' + xyz' + xyz = x'yz' + xyz' + xyz' + xyz = yz' (x + x') + xy(z' + z) = yz' + xy = RHS. It is okay to start from the RHS as well.

2. Consider a CMOS inverter with the following parameters: Wn=2µm, Wp=4µm, Ln=Lp=0.8µm, K'n=µ n.Coxn=20µA/V2, K'p=µ p.Coxp=10µA/V2, VTn=1V, VTp= -1V, VDD=5V,VSS=GND=0V. Find the value of VM (the inverter threshold) of the above inverter. K' is the process trans-conductance. [Hint: VM is the midpoint voltage on the voltage transfer characteristic, where Vin=Vout.]
Vo

VM

Vi

Vin = Vout happens in the nearly vertical segment of the VTC where both the PMOS and the NMOS transistors are in saturation. ∴equating the saturation drain current equations, we get: (K'n/2).( Wn/ Ln).(Vin - VTn)2 = (K'p/2).( Wp/ Lp).(VDD - Vin - VTn)2

( Wn / Ln). (2. 3. or.0/0. or.5 V Give full credit if students use direct formula from text book.( Lp / Wp)]1/2 [(5 – VM – 1)/(VM – 1)] = [(20/10). [Hint: Construct a truth table with various input combinations and try to find the output for each case.8).or.] VDD IN1 IN2 OUT IN1 IN2 OUT 0 0 0 0 1 1 1 0 1 1 1 0 The above circuit implements the XOR function . [(VDD .0)] 1/2 [(4 – VM )/(VM – 1)] = 1 VM = 2. or.8/4.Vin .VTn)/ Vin .VTn)] = [(K'n/ K'p). Identify the logic function implemented by the following circuit that has 2 inputs IN1 and IN2 and one output OUT.5 The threshold is at 2.(0.

Draw the transistor-level circuit of the following complex gate: OUT = [(a + bc + def)g]' (where ' denotes complementation).4. a b c g d e f OUT d b e c f a g .

Perform a layout simulation by tying the terminals to appropriate power supplies and applying a one-cycle . A common method is to produce an input circuit description or deck. VDD f a b c VSS 6. Green = N-diff. Red = Poly.g. perform a DC analysis to plot the voltage transfer characteristic of the inverter. Feel free to use a reasonable value for VDD (e. read in the deck.. Assign Wn=2µm and Wp=4µm. Assume an output load of 0. and run the simulator].5 pF. do a layout of the above inverter. HSPICE) of your choice. invoke the simulator. Blue = Metal 1. Give full credit for correct analysis output and for any transistor width and voltage and any circuit simulator as long as the input deck is specified properly.g. Using a layout editor of your choice. 5 V) and default values for the other transistor parameters as specified in the default model used by the chosen CAD tool. Make sure that the layout is design-rule correct (for the technology you are using). Lab project. [Hint: A tutorial or example in the manual for the simulator you are using is likely to show an inverter simulation example.. Black cross = contact (via). Draw the transistor-level shematic of an inverter. Using a circuitsimulation tool (e. 7. Use the following color convention: Yellow = P-diff. Do a stick-diagram-based layout of the function f = (a + bc)'.5.

Some evidence of correct functionality of the inverter layout (e. Verify the inverted output for correct results. Lab project. . a plot without the cross-hatched mark that is usually present in case of a DRC violation).. Give full credit for any form of layout with any transistor width as long as the layout is design-rule correct. LVS or circuit extraction and DC analysis or circuit extraction and transient analysis or layout logic simulation.square wave at the input of the inverter. Students should demonstrate some evidence of correct layout (e.g. etc) is necessary to get full credit. Submit layout plot and simulation results..g.

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